JP2019009705A - Amplifier circuit - Google Patents

Abstract

To obtain an amplifier circuit capable of executing a reduction in offset voltage in real time by a simple circuit configuration without using switching operation .SOLUTION: An amplifier circuit includes an output circuit including a first transistor and a second transistor connected in series, an extraction circuit for extracting a voltage, corresponding to an offset current included in an output signal from an output circuit, based on a first gate voltage supplied to a gate terminal of the first transistor and a second gate voltage supplied to a gate terminal of the second transistor, and an adjustment circuit for adjusting the offset current included in the output signal from the output circuit, according to magnitude of a voltage corresponding to the offset current.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an amplifier circuit.

  Conventionally, in the differential amplifier circuit, an output offset voltage may be generated due to mismatch of elements constituting the circuit. For example, when the load resistance of the amplifier circuit is as small as several Ω, when such an offset voltage occurs, a DC current flows constantly and the current consumption increases. Further, when output voltage accuracy is required, such an offset voltage may cause an error. Further, since the offset voltage is generated with a different magnitude for each differential amplifier circuit, it has to be adjusted for each circuit.

In order to solve such problems, techniques for canceling the output offset of the differential amplifier circuit are disclosed in Reference Document 1 and Reference Document 2. Reference 1 describes that the occurrence of an output offset is reduced by performing switching operation by monitoring and accumulating voltage using a capacitor and a switch. Reference 2 describes that a comparator and a DAC circuit are provided, and the occurrence of an output offset is reduced by searching for a DAC setting that minimizes the output offset and performing digital control.
Patent Document 1 JP 2007-228388 A Patent Document 2 JP 2012-156936 A

  However, when a switch is used, noise may occur due to the switching operation. In addition, when a comparator and a DAC circuit are used, a preset operation is executed, so that it becomes difficult to execute real-time offset cancellation. For example, the offset voltage may change with changes in temperature, power supply voltage, etc., and cannot be canceled in response to such a change in offset voltage.

  It is also conceivable to block the propagation of the output offset by inserting a DC cut capacitor in series without using such an offset cancel circuit or the like. However, the differential amplifier circuit amplifies a band of several tens of Hz to several tens of kHz like an audio amplifier and the like, and when the impedance of the next stage is small, a capacitor having a large capacitance value is necessary. The installation area of the capacitor increases as compared with the circuit scale of the differential amplifier circuit.

  In the first aspect of the present invention, an output circuit including a first transistor and a second transistor connected in series, a first gate voltage supplied to the gate terminal of the first transistor, and a gate terminal of the second transistor Based on the supplied second gate voltage, an extraction circuit that extracts a voltage corresponding to the offset current included in the output signal of the output circuit, and an output signal of the output circuit according to the magnitude of the voltage corresponding to the offset current An amplifier circuit is provided that includes an adjustment circuit that adjusts an offset current contained therein.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

An example of the amplifier circuit 100 is shown. 2 shows a configuration example of an amplifier circuit 200 according to the present embodiment. 2 shows a configuration example of an input circuit 110 according to the present embodiment. The 1st modification of the amplifier circuit 200 which concerns on this embodiment is shown. The 2nd modification of the amplifier circuit 200 which concerns on this embodiment is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

FIG. 1 shows an example of the amplifier circuit 100. The amplifier circuit 100 has a differential input amplifier circuit, and outputs an amplified signal obtained by amplifying the input voltage Vi as an output voltage Vo. FIG. 1 shows an example in which an amplifier circuit 100 is connected to a common voltage Vcom via a load 20 and supplies a potential difference between the output voltage Vo and the common voltage Vcom to the load 20. The load 20 may be an element having a resistance component. The common voltage Vcom may be a predetermined voltage. For example, the common voltage Vcom is a voltage V _DD / 2 that is substantially half of the power supply voltage V _DD . The amplifier circuit 100 includes an input terminal 12, an output terminal 14, an input circuit 110, and an output circuit 120.

  The input terminal 12 receives an input voltage Vi. The output terminal 14 outputs an output voltage Vo. The input circuit 110 outputs two single-ended output signals according to the differential input signal. FIG. 1 shows an example in which the positive signal of the differential input signal is Vip and the negative signal is Vin. FIG. 1 shows an example in which the positive signal Vip of the differential input signal is the input voltage Vi. FIG. 1 shows an example in which the first single-ended output signal is Von1, and the second single-ended output signal obtained by level-shifting the first single-ended output signal is Von2.

  The input circuit 110 has an amplifier 112. The amplifier 112 amplifies the differential input signal. The amplifier 112 may include a differential input operational amplifier. Input circuit 110 provides two single-ended output signals to output circuit 120.

The output circuit 120 outputs an output voltage Vo according to two single-ended output signals. The output circuit 120 includes a first transistor 122 and a second transistor 124. The first transistor 122 and the second transistor 124 are connected in series between the power supply V _DD and the reference potential 30. For example, when the first transistor 122 and the second transistor 124 are FETs, the source terminal of the first transistor 122 is connected to the power supply V _DD and the drain terminal is connected to the drain terminal of the second transistor 124. The source terminal of the second transistor 124 is connected to the reference potential 30. The reference potential 30 may be a ground potential, and is 0 V as an example.

  The first single-ended output signal Von1 is supplied to the gate terminal of the first transistor 122, and the second single-ended output signal Von2 is supplied to the gate terminal of the second transistor 124. The first transistor 122 may be a PMOS transistor, and the second transistor 124 may be an NMOS transistor. The output circuit 120 outputs an output voltage Vo from between the first transistor 122 and the second transistor 124. The output voltage Vo is fed back to the input circuit 110 as the negative signal Vin of the differential input signal.

  In other words, the amplifier circuit 100 is controlled so that the output voltage Vo is substantially the same as the input voltage Vi, and operates as a voltage follower. In such an amplifier circuit 100, a steady current hardly flows through the load 20 in an ideal operating state where no offset voltage is generated in the output voltage Vo. However, an offset voltage may be superimposed on the output voltage Vo due to mismatch of elements constituting the circuit, environmental fluctuation, change with time, and the like. In this case, when the common voltage of the input voltage Vi is Vcom, a current corresponding to the offset voltage constantly flows through the load 20, and the power consumption of the amplifier circuit 100 increases. The offset voltage may become an error component of the output voltage Vo of the amplifier circuit 100 and cause a decrease in accuracy.

  When reducing such an offset voltage, the offset voltage differs from one amplifier circuit 100 to another, and therefore circuit constants and the like must be adjusted for each amplifier circuit 100. Further, when the offset voltage is generated with a change over time, a circuit constant or the like must be adjusted with the passage of time. In addition, when the offset voltage is generated due to the environmental change, it may be necessary to adjust the circuit constant or the like in real time according to the environmental change.

  Therefore, the amplifier circuit according to the present embodiment can reduce the offset voltage in real time with a simple circuit configuration without using a switching operation. Such an amplifier circuit will be described next.

  FIG. 2 shows a configuration example of the amplifier circuit 200 according to the present embodiment. In the amplifier circuit 200 according to the present embodiment, the same reference numerals are given to substantially the same operations as those of the amplifier circuit 100 shown in FIG. The amplifier circuit 200 includes an input terminal 12, an output terminal 14, an input circuit 110, an output circuit 120, an extraction circuit 210, and an adjustment circuit 220.

  The input terminal 12, the output terminal 14, the input circuit 110, and the output circuit 120 operate as a voltage follower similarly to the operation described in FIG. That is, an example in which the input circuit 110 and the output circuit 120 shown in FIGS. 1 and 2 constitute a gain stage and operate as a two-stage class AB differential amplifier circuit is shown. In this case, when the common voltage of the input voltage Vi is Vcom and the positive side signal Vip of the differential input signal of the input circuit 110 is equal to the negative side signal Vin (Vip = Vin), ideally the output of the output circuit 120 The voltage Vo substantially coincides with the common voltage Vcom (Vo = Vcom). That is, the direct current flowing through the load 20 becomes zero.

However, in the actual input circuit 110 and output circuit 120, since an offset voltage is generated, Vo = Vcom + Vofs. Here, the offset voltage is Vofs. For example, when the input voltage Vi is a sine wave signal based on the common voltage Vcom, it can be expressed as Vi = Vcom + A · sin (ωt), and the output voltage Vo becomes Vo = Vcom + A · sin (ωt) + Vofs. By such an offset voltage Vofs, an offset current Iofs that is a direct current flows through the load 20. Here, when the resistance value of the load 20 is R ₀ , the offset current Iofs is Vofs / R ₀ . That is, when the resistance value _R0 of the load 20 is decreased, the power consumption is increased.

  The extraction circuit 210 extracts a voltage corresponding to the offset current Iofs included in the output signal of the output circuit 120. The extraction circuit 210 extracts a voltage corresponding to the offset current Iofs based on the first gate voltage supplied to the gate terminal of the first transistor 122 and the second gate voltage supplied to the gate terminal of the second transistor 124.

  Here, when the offset current Iofs is not zero, there is a difference between the direct current flowing through the first transistor 122 that drives the output voltage Vo from the positive side and the direct current flowing through the second transistor 124 that drives from the negative side. Will occur. The extraction circuit 210 extracts a voltage corresponding to such a direct current difference. The extraction circuit 210 includes a third transistor 212, a fourth transistor 214, a first filter 216, and a second filter 218.

  In the third transistor 212, the first gate voltage is supplied to the gate terminal. The third transistor 212 corresponds to the first transistor 122 and is, for example, a PMOS transistor similar to the first transistor 122. The fourth transistor 214 is supplied with the second gate voltage at the gate terminal. The fourth transistor 214 corresponds to the second transistor 124 and is, for example, an NMOS transistor similar to the second transistor 124.

The third transistor 212 and the fourth transistor 214 are connected in series between the power supply V _DD and the reference potential 30. In the third transistor 212 and the fourth transistor 214, for example, the source terminal of the third transistor 212 is connected to the power supply _VDD , and the drain terminal is connected to the drain terminal of the fourth transistor 214. The source terminal of the fourth transistor 214 is connected to the reference potential 30.

  The element size of the third transistor 212 is desirably substantially the same as the element size of the first transistor 122. In this case, it is desirable that the element size of the fourth transistor 214 is substantially the same as the element size of the second transistor 124. That is, it is desirable that the third transistor 212 and the fourth transistor 214 operate as replicas of the first transistor 122 and the second transistor 124.

  In addition, the extraction circuit 210 is configured such that the ratio of the element size of the third transistor 212 to the element size of the first transistor 122 and the ratio of the element size of the fourth transistor 214 to the element size of the second transistor 124 are the same. In addition, the third transistor 212 and the fourth transistor 214 may be formed. As an example, the element size of the third transistor 212 is formed to be about 1/10 of the element size of the first transistor 122, and the element size of the fourth transistor 214 is formed to be about 1/10 of the element size of the second transistor 124. The

  As such, the third transistor 212 and the fourth transistor 214 may operate as scaled replicas of the first transistor 122 and the second transistor 124. The extraction circuit 210 supplies the voltage between the third transistor 212 and the fourth transistor 214 to the adjustment circuit 220.

  The first filter 216 passes a DC component. The first filter 216 is, for example, a low-pass filter that allows the DC component Vcom to pass through the input voltage Vi = Vcom + A · sin (ωt) input to the amplifier circuit 200 and prevents the AC component A · sin (ωt) from passing. Functions as a filter. The first filter 216 is provided between the gate terminal of the first transistor 122 and the gate terminal of the third transistor 212. In other words, the third transistor 212 is supplied with the first gate voltage to the gate terminal via the first filter 216.

  The second filter 218 passes a DC component. The second filter 218 may be substantially the same circuit as the first filter. The second filter 218 is provided between the gate terminal of the second transistor 124 and the gate terminal of the fourth transistor 214. In other words, the fourth transistor 214 is supplied with the second gate voltage to the gate terminal via the second filter 218.

  As described above, the third transistor 212 and the fourth transistor 214 that operate as replicas of the first transistor 122 and the second transistor 124 are supplied with the DC components of the first gate voltage and the second gate voltage as the gate voltage, respectively. Therefore, the third transistor 212 and the fourth transistor 214 can extract and output a voltage corresponding to the offset current Iofs, which is a direct current component, from the output signals of the first transistor 122 and the second transistor 124.

That is, the extraction circuit 210 can extract and compare signals corresponding to direct currents flowing through the first transistor 122 and the second transistor 124, respectively. For example, when the direct current of the first transistor 122 is larger than the direct current of the second transistor 124, the direct current flowing through the third transistor 212 is larger than the direct current flowing through the fourth transistor 214. That is, the voltage output from the extraction circuit 210 becomes closer to the V _DD side as the direct current flowing through the first transistor 122 is larger than the direct current flowing through the second transistor 124.

  For example, when the direct current of the first transistor 122 is smaller than the direct current of the second transistor 124, the direct current flowing through the third transistor 212 is smaller than the direct current flowing through the fourth transistor 214. That is, the voltage output from the extraction circuit 210 becomes closer to the reference potential side as the direct current flowing through the first transistor 122 is smaller than the direct current flowing through the second transistor 124.

When the third transistor 212 and the fourth transistor 214 are formed by transistors having substantially the same shape, and the direct currents flowing through the first transistor 122 and the second transistor 124 are substantially equal, the third transistor 212 and the fourth transistor 214 The direct currents flowing through them are substantially equal. In this case, the voltage output from the extraction circuit 210 is closer to V _DD / 2. As described above, the extraction circuit 210 according to the present embodiment functions as a current converter for direct current flowing through the first transistor 122 and the second transistor 124.

  The adjustment circuit 220 adjusts the offset current Iofs included in the output signal of the output circuit 120 according to the magnitude of the voltage corresponding to the offset current of the extraction circuit 210. The adjustment circuit 220 has a comparison circuit 222 and a reference voltage Vref. The comparison circuit 222 compares the reference voltage Vref with a voltage corresponding to the offset current Iofs. Here, the reference voltage Vref may be a predetermined voltage. The adjustment circuit 220 supplies the comparison result of the comparison circuit 222 to the input circuit 110 as an adjustment signal.

The comparison circuit 222 includes, for example, an amplifier circuit that performs a feedback operation so that the input reference voltage Vref and the voltage match. That is, the comparison circuit 222 functions as a current balancing amplifier. The reference voltage Vref is preferably a voltage that is substantially equal to the voltage that the extraction circuit 210 outputs when the direct currents flowing through the first transistor 122 and the second transistor 124 are substantially equal. As an example, the reference voltage Vref is a voltage that substantially matches V _DD / 2. That is, the adjustment circuit 220 generates an adjustment signal and feeds it back to the input circuit 110 so as to reduce the offset current Iofs.

  Here, the input circuit 110 according to the present embodiment is configured to be able to adjust the offset current Iofs according to the adjustment signal supplied from the adjustment circuit 220. Such an input circuit 110 will be described next.

FIG. 3 shows a configuration example of the input circuit 110 according to the present embodiment. The input circuit 110 outputs two single-ended output signals according to the differential input signal. The input circuit 110 includes a power supply V _DD , a fifth transistor 232, a sixth transistor 234, a seventh transistor 236, an eighth transistor 238, a ninth transistor 242, a current control circuit 250, and a level shift circuit 262.

The fifth transistor 232 and the sixth transistor 234 form a mirror circuit connected to the power supply V _DD . For example, each of the fifth transistor 232 and the sixth transistor 234 has a source terminal connected to the power supply V _DD and a gate terminal connected to the drain terminal of the fifth transistor 232. The fifth transistor 232 and the sixth transistor 234 may be PMOS transistors.

  The seventh transistor 236 and the eighth transistor 238 constitute a differential pair. For example, the drain terminal of the seventh transistor 236 is connected to the drain terminal of the fifth transistor 232, and the drain terminal of the eighth transistor 238 is connected to the drain terminal of the sixth transistor 234. A differential signal is input to the differential pair. For example, the negative signal Vin of the differential input signal is input to the gate terminal of the seventh transistor 236, and the positive signal Vip of the differential input signal is input to the gate terminal of the eighth transistor 238. The seventh transistor 236 and the eighth transistor 238 may be NMOS transistors.

  The ninth transistor 242 is provided between the differential pair and the reference potential 30. For example, the ninth transistor 242 has a drain terminal connected to the source terminals of the seventh transistor 236 and the eighth transistor 238 and a source terminal connected to the reference potential 30. A predetermined bias voltage Vbn is input to the gate terminal of the ninth transistor 242. Here, the bias voltage Vbn may be a substantially constant voltage. The ninth transistor 242 may be an NMOS transistor.

Thus, between the power supply V _DD and the reference potential 30, the fifth transistor 232, the seventh transistor 236, and the ninth transistor 242 are connected in series. In addition, between the power supply V _DD and the reference potential 30, the sixth transistor 234, the eighth transistor 238, and the ninth transistor 242 are connected in series.

  The current control circuit 250 controls the current flowing through the mirror circuit in accordance with the adjustment signal received from the adjustment circuit 220. For example, the current control circuit 250 is provided in one of the fifth transistor 232 and the sixth transistor 234 of the mirror circuit. Current control circuit 250 includes a tenth transistor 252 connected in parallel with one of fifth transistor 232 and sixth transistor 234. FIG. 3 shows an example in which the current control circuit 250 includes a tenth transistor 252 connected in parallel with the sixth transistor 234.

  That is, the tenth transistor 252 has a drain terminal connected to the drain terminal of the sixth transistor 234 and a source terminal connected to the source terminal of the sixth transistor 234. The adjustment signal output from the adjustment circuit 220 is supplied to the gate terminal of the tenth transistor 252. That is, the tenth transistor 252 operates as a variable current source corresponding to the adjustment signal. Thereby, the current control circuit 250 can control the current output from the mirror circuit by adding the current according to the adjustment signal to the current output from the sixth transistor 234. That is, the tenth transistor 252 functions as an offset current Iofs adjustment transistor. The tenth transistor 252 may be a PMOS transistor.

  Further, the current control circuit 250 may be provided in both the fifth transistor 232 and the sixth transistor 234. For example, the current control circuit 250 includes an eleventh transistor 254 connected in parallel with the other of the fifth transistor 232 and the sixth transistor 234. FIG. 3 shows an example in which the current control circuit 250 includes an eleventh transistor 254 connected in parallel with the fifth transistor 232.

  That is, the eleventh transistor 254 has a drain terminal connected to the drain terminal of the fifth transistor 232 and a source terminal connected to the source terminal of the fifth transistor 232. In addition, a predetermined second bias voltage Vbp is supplied to the gate terminal of the eleventh transistor 254. The second bias voltage Vbp may be a substantially constant voltage. That is, the eleventh transistor 254 operates as a constant current source. The eleventh transistor 254 may be a PMOS transistor.

  Thus, the current control circuit 250 can control the current output from the mirror circuit by adding a current corresponding to the second bias voltage Vbp to the current output from the fifth transistor 232. The amount of current flowing through the eleventh transistor 254 is determined in advance in consideration of the size of the differential pair of the seventh transistor 236 and the eighth transistor 238, the generation range and / or the adjustable range of the offset voltage Vofs, and the like. It is desirable that

  For example, when the current amount of the eleventh transistor 254 is larger than the current amount of the tenth transistor 252, the current amount of the seventh transistor 236 is larger than the current amount of the eighth transistor 238. That is, the negative side signal Vin of the differential input signal becomes larger than the positive side signal Vip. Here, since the negative side signal Vin of the differential input signal corresponds to the output voltage Vo of the output circuit 120, the output voltage Vo is increased. For example, since the common voltage of the input voltage Vi is Vcom, the output voltage Vo> Vcom.

  For example, when the current amount of the eleventh transistor 254 is smaller than the current amount of the tenth transistor 252, the current amount of the seventh transistor 236 is smaller than the current amount of the eighth transistor 238. That is, the negative side signal Vin of the differential input signal becomes smaller than the positive side signal Vip. Therefore, for example, since the common voltage of the input voltage Vi is Vcom, the output voltage Vo <Vcom and the output voltage Vo is lowered.

  As described above, the input circuit 110 according to the present embodiment outputs the output of the mirror circuit controlled by the current control circuit 250 as the first single-end output signal Von1. FIG. 3 shows an example in which the first single-ended output signal Von1 is output from between the sixth transistor 234 and the eighth transistor 238.

  The level shift circuit 262 shifts the level of the first single-ended output signal Von1 between the sixth transistor 234 and the eighth transistor 238. In the example of FIG. 3, the level shift circuit 262 generates a signal obtained by shifting the level of the first single-end output signal Von1 to the negative side, and outputs the signal as the second single-end output signal Von2. As described above, the input circuit 110 supplies two single-ended output signals adjusted according to the adjustment signal to the output circuit 120. That is, one first single-ended output signal Von1 is supplied as the first gate voltage to the gate terminal of the first transistor 122, and the other second single-ended output signal Von2 is used as the second gate voltage as the second transistor. 124 is supplied to the gate terminal.

  As described above, the amplifier circuit 200 according to the present embodiment can perform a feedback operation so that the direct currents flowing through the first transistor 122 and the second transistor 124 are matched. As a result, the amplification circuit 200 makes the direct current flowing through the load 20 almost zero, so that the generation of the offset voltage Vofs can be reduced.

  Note that the size of each of the third transistor 212 and the fourth transistor 214 included in the extraction circuit 210 may be scaled to about 1/10 to 1/100 of the size of the first transistor 122 and the second transistor 124. By scaling in this way, the amplifier circuit 200 can reduce the offset voltage Vofs with almost no increase in power consumption. The third transistor 212, the fourth transistor 214, and the comparison circuit 222 are only required to amplify the DC component, and an inexpensive amplifying element having a narrow band can be used.

  The comparison circuit 222 may have non-linearity, and an offset voltage of about several mV to several tens of mV may be generated. In this case, an error corresponding to the offset voltage may occur between the operating point of the first transistor 122 and the second transistor 124 and the operating point of the third transistor 212 and the fourth transistor 214. However, since the third transistor 212 and the fourth transistor 214 operate in a saturation region, even if the drain-source voltage fluctuates from several mV to several tens mV, the influence on the current amount is very small, Since the replica function hardly changes, the offset voltage Vofs of the amplifier circuit 200 hardly fluctuates.

  Therefore, the comparison circuit 222 does not need to use a high-accuracy amplifier with a reduced offset voltage. In other words, the amplifier circuit 200 can execute real-time offset cancellation without using a switch circuit by using an inexpensive and simple extraction circuit 210 and adjustment circuit 220.

  Although the amplifier circuit 200 according to this embodiment has been described by taking the class AB differential amplifier circuit as an example, the present invention is not limited to this. For example, the amplifier circuit 200 may constitute a class A amplifier circuit. The amplifier circuit 200 in this case will be described with reference to FIG.

  FIG. 4 shows a first modification of the amplifier circuit 200 according to this embodiment. In the amplifier circuit 200 according to the first modification, the same reference numerals are given to the same components as those of the amplifier circuit 200 shown in FIGS. 2 and 3, and the description thereof is omitted. The amplifier circuit 200 operates as a voltage follower that drives the load 20, similarly to the amplifier circuit 200 of FIG. 2. The input circuit 110 of the first modified example outputs one single-ended output signal according to the differential input signal. For example, the input circuit 110 may not include the level shift circuit 262 described with reference to FIG.

  Further, in the output circuit 120 of the first modification, the single-ended output signal of the input circuit 110 is supplied to the gate terminal of one of the first transistor 122 and the second transistor 124, and the gate terminal of the other transistor is supplied. A predetermined voltage is supplied. In FIG. 4, a single-ended output signal is supplied to the gate terminal of the first transistor 122 as a first gate voltage, and a predetermined first bias voltage Vbno is supplied to the gate terminal of the second transistor 124 as a second gate voltage. The example supplied is shown. Here, the first bias voltage Vbno may be a substantially constant voltage.

  Further, the extraction circuit 210 and the adjustment circuit 220 of the first modification may be substantially the same as the extraction circuit 210 and the adjustment circuit 220 described in FIG. Note that since the second gate voltage is a substantially constant voltage, the extraction circuit 210 may not include the second filter 218.

  The amplifier circuit 200 according to the first modification described above has the same DC currents flowing through the first transistor 122 and the second transistor 124 as in the operations of the extraction circuit 210 and the adjustment circuit 220 described with reference to FIGS. Feedback operation. Therefore, the amplifier circuit 200 can execute real-time offset cancellation without providing a switch circuit.

  Although the amplifier circuit 200 according to the present embodiment has been described by taking the amplifier circuit having two gain stages of the input circuit 110 and the output circuit 120 as an example, the present invention is not limited to this. For example, the amplifier circuit 200 may have three or more gain stages. Instead of this, the amplifier circuit 200 may have a configuration having one gain stage. The amplifier circuit 200 in this case will be described with reference to FIG.

FIG. 5 shows a second modification of the amplifier circuit 200 according to this embodiment. In the amplifier circuit 200 according to the second modified example, the same reference numerals are given to the substantially same operations as those of the amplifier circuit 200 shown in FIGS. 2, 3, and 4, and the description thereof is omitted. The amplifier circuit 200 operates as a voltage follower that drives the load 20, similarly to the amplifier circuit 200 of FIG. 2. FIG. 5 shows an example in which the amplifier circuit 200 includes the output circuit 120 as a single gain stage. The output circuit 120 of the second modification includes a power supply V _DD , a first transistor 122, a second transistor 124, a twelfth transistor 332, a thirteenth transistor 336, a fourteenth transistor 338, and a current control circuit 250.

The first transistor 122 and the twelfth transistor 332 form a mirror circuit connected to the power supply _VDD . For example, the first transistor 122 and the twelfth transistor 332 have their source terminals connected to the power supply V _DD and their gate terminals connected to the drain terminal of the twelfth transistor 332, respectively. The first transistor 122 and the twelfth transistor 332 may be PMOS transistors.

  The thirteenth transistor 336 and the fourteenth transistor 338 form a differential pair. For example, the drain terminal of the thirteenth transistor 336 is connected to the drain terminal of the twelfth transistor 332, and the drain terminal of the fourteenth transistor 338 is connected to the drain terminal of the first transistor 122. The input voltage Vi is input to the gate terminal of the thirteenth transistor 336, and the gate terminal of the fourteenth transistor 338 is connected to the drain terminal of the fourteenth transistor 338. The drain terminal and gate terminal of the fourteenth transistor 338 are connected to the output terminal 14. The thirteenth transistor 336 and the fourteenth transistor 338 may be NMOS transistors.

  The second transistor 124 is provided between the differential pair and the reference potential 30. For example, the second transistor 124 has a drain terminal connected to the source terminals of the thirteenth transistor 336 and the fourteenth transistor 338 and a source terminal connected to the reference potential 30. A predetermined bias voltage Vbn is input to the gate terminal of the second transistor 124. Here, the bias voltage Vbn may be a substantially constant voltage. The second transistor 124 may be an NMOS transistor.

Thus, between the power supply V _DD and the reference potential 30, the first transistor 122, the fourteenth transistor 338, and the second transistor 124 are connected in series, and the twelfth transistor 332, the thirteenth transistor 336, and the second transistor 124 are connected in series.

  Further, the current control circuit 250 controls the current flowing through the mirror circuit in accordance with the adjustment signal received from the adjustment circuit 220. For example, the current control circuit 250 is provided in one of the first transistor 122 and the twelfth transistor 332 of the mirror circuit. Current control circuit 250 includes a tenth transistor 252 connected in parallel with one of first transistor 122 and twelfth transistor 332. FIG. 5 shows an example in which the current control circuit 250 includes a tenth transistor 252 connected in parallel with the first transistor 122.

  That is, the tenth transistor 252 has a drain terminal connected to the drain terminal of the first transistor 122 and a source terminal connected to the source terminal of the first transistor 122. The adjustment signal output from the adjustment circuit 220 is supplied to the gate terminal of the tenth transistor 252. Thereby, the current control circuit 250 can control the current output from the mirror circuit by adding the current according to the adjustment signal to the current output from the first transistor 122. The tenth transistor 252 may be a PMOS transistor.

  Further, the current control circuit 250 may be provided in both the first transistor 122 and the twelfth transistor 332. For example, the current control circuit 250 includes an eleventh transistor 254 connected in parallel with the other of the first transistor 122 and the twelfth transistor 332. FIG. 5 shows an example in which the current control circuit 250 includes an eleventh transistor 254 connected in parallel with the twelfth transistor 332.

  That is, the eleventh transistor 254 has a drain terminal connected to the drain terminal of the twelfth transistor 332 and a source terminal connected to the source terminal of the twelfth transistor 332. In addition, a predetermined second bias voltage Vbp is supplied to the gate terminal of the eleventh transistor 254. The second bias voltage Vbp may be a substantially constant voltage. That is, the eleventh transistor 254 operates as a constant current source. The eleventh transistor 254 may be a PMOS transistor.

  Thus, the current control circuit 250 can control the current output from the mirror circuit by adding a current corresponding to the second bias voltage Vbp to the current output from the twelfth transistor 332. The amount of current flowing through the eleventh transistor 254 is determined in advance in consideration of the size of the differential pair of the thirteenth transistor 336 and the fourteenth transistor 338, the generation range and / or the adjustable range of the offset voltage Vofs, and the like. It is desirable that

  As described above, the output circuit 120 of the present embodiment uses the output of the mirror circuit controlled by the current control circuit 250 as the output voltage Vo. FIG. 5 shows an example in which the output voltage Vo is output from between the first transistor 122 and the fourteenth transistor 338. Further, the first gate voltage supplied to the gate terminal of the first transistor 122 and the second gate voltage supplied to the gate terminal of the second transistor 124 are supplied to the extraction circuit 210.

  For example, in the third transistor 212, the first gate voltage is supplied to the gate terminal. The fourth transistor 214 is supplied with a predetermined bias voltage Vbn as a second gate voltage to the gate terminal. The extraction circuit 210 and the adjustment circuit 220 of the second modification may be substantially the same as the extraction circuit 210 and the adjustment circuit 220 described in FIG. Note that since the second gate voltage is a substantially constant voltage, the extraction circuit 210 may not include the second filter 218.

  The amplifier circuit 200 according to the second modification described above matches the direct currents flowing through the first transistor 122 and the second transistor 124 in the same manner as the operations of the extraction circuit 210 and the adjustment circuit 220 described with reference to FIGS. Feedback operation. Therefore, the amplifier circuit 200 can execute real-time offset cancellation without providing a switch circuit.

  In the amplifier circuit 200 according to the second modification described above, the second transistor 124 is connected to each of the thirteenth transistor 336 and the fourteenth transistor 338 constituting a differential pair. That is, the current flowing through the second transistor 124 branches and flows to the thirteenth transistor 336 and the fourteenth transistor 338. Therefore, for example, the current flowing through the fourteenth transistor 338 that drives the output voltage Vo from the negative side is approximately ½ of the current flowing through the second transistor 124.

  For example, when the first transistor 122, the second transistor 124, and the twelfth transistor 332 are formed to have substantially the same size, the fourth transistor 214 is formed to have a size that is approximately ½ of the size of the third transistor 212. .

  That is, the extraction circuit 210 of the second modified example includes the ratio of the element size of the third transistor 212 to the element size of the first transistor 122 and the fourth transistor for the element size obtained by halving the element size of the second transistor 124. The third transistor 212 and the fourth transistor 214 may be formed so that the element size ratio of 214 is substantially the same. As a result, the third transistor 212 and the fourth transistor 214 of the extraction circuit 210 can more accurately reflect and compare the direct currents flowing through the first transistor 122 and the fourteenth transistor 338, respectively.

  In the above-described amplifier circuit 200 according to the present embodiment, the example in which the transistor constituting the amplifier circuit is a MOS transistor has been described. However, the present invention is not limited to this. Each transistor may be a bipolar transistor. Further, in the present embodiment, the example in which the amplifier circuit 200 configures the voltage follower has been described. However, the present invention is not limited to this, and an inverting amplifier circuit or another configuration may be used. The differential amplifier circuit may have a fully differential amplification configuration.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

12 input terminal, 14 output terminal, 20 load, 30 reference potential, 100 amplifier circuit, 110 input circuit, 112 amplifier, 120 output circuit, 122 first transistor, 124 second transistor, 200 amplifier circuit, 210 extraction circuit, 212 second 3 transistors, 214 4th transistor, 216 1st filter, 218 2nd filter, 220 adjustment circuit, 222 comparison circuit, 232 5th transistor, 234 6th transistor, 236 7th transistor, 238 8th transistor, 242 9th transistor , 250 Current control circuit, 252 10th transistor, 254 11th transistor, 262 Level shift circuit, 332 12th transistor, 336 13th transistor, 338 14th transistor

Claims (15)

An output circuit including a first transistor and a second transistor connected in series;
Based on the first gate voltage supplied to the gate terminal of the first transistor and the second gate voltage supplied to the gate terminal of the second transistor, a voltage corresponding to the offset current included in the output signal of the output circuit is obtained. An extraction circuit to extract;
An amplifier circuit comprising: an adjustment circuit that adjusts the offset current included in the output signal of the output circuit according to the magnitude of the voltage corresponding to the offset current. The extraction circuit includes:
A third transistor corresponding to the first transistor, wherein the first gate voltage is supplied to a gate terminal;
A fourth transistor corresponding to the second transistor and having the second gate voltage supplied to a gate terminal;
2. The amplifier circuit according to claim 1, wherein the third transistor and the fourth transistor are connected in series, and a voltage between the third transistor and the fourth transistor is a voltage corresponding to the offset current.   3. The amplifier circuit according to claim 2, wherein the third transistor is supplied with the first gate voltage to a gate terminal through a filter circuit that allows a DC component to pass therethrough.   4. The amplifier circuit according to claim 2, wherein the fourth transistor is supplied with the second gate voltage to a gate terminal through a filter circuit that allows a DC component to pass therethrough. 5.   In the extraction circuit, the ratio of the element size of the third transistor to the element size of the first transistor is equal to the ratio of the element size of the fourth transistor to the element size of the second transistor. The amplifier circuit according to any one of claims 2 to 4, wherein the third transistor and the fourth transistor are formed. An input circuit that outputs two single-ended output signals in response to a differential input signal;
A first single-ended output signal of one of the two single-ended output signals is supplied to the gate terminal of the first transistor as the first gate voltage;
The second single-ended output signal of the other of the two single-ended output signals is supplied to the gate terminal of the second transistor as the second gate voltage. Amplification circuit. An input circuit that outputs one single-ended output signal in response to a differential input signal,
The one single-ended output signal is supplied to the gate terminal of the first transistor as the first gate voltage;
6. The amplifier circuit according to claim 1, wherein a predetermined first bias voltage is supplied to the gate terminal of the second transistor as the second gate voltage. 7. The input circuit is
Power supply,
A mirror circuit including a fifth transistor and a sixth transistor respectively connected to the power source;
A differential pair including a seventh transistor and an eighth transistor;
A ninth transistor provided between the differential pair and a reference potential;
Have
Between the power source and the reference potential,
The fifth transistor, the seventh transistor, and the ninth transistor are connected in series;
The sixth transistor, the eighth transistor, and the ninth transistor are connected in series;
The amplification circuit according to claim 6, wherein the mirror circuit is provided with a current control circuit that controls a current flowing through the mirror circuit in one of the fifth transistor and the sixth transistor. The current control circuit includes a tenth transistor connected in parallel with one of the fifth transistor and the sixth transistor;
The amplifier circuit according to claim 8, wherein an adjustment signal output from the adjustment circuit is supplied to a gate terminal of the tenth transistor. The current control circuit includes an eleventh transistor connected in parallel with the other of the fifth transistor and the sixth transistor;
The amplifier circuit according to claim 9, wherein a predetermined second bias voltage is supplied to a gate terminal of the eleventh transistor. The output circuit is
Power supply,
A mirror circuit including the first transistor and the twelfth transistor respectively connected to the power source;
A differential pair including a thirteenth transistor and a fourteenth transistor;
The second transistor provided between the differential pair and a reference potential;
A current control circuit for controlling a current flowing through the mirror circuit in one of the first transistor and the twelfth transistor;
Have
Between the power source and the reference potential,
The first transistor, the fourteenth transistor, and the second transistor are connected in series;
5. The amplifier circuit according to claim 2, wherein the twelfth transistor, the thirteenth transistor, and the second transistor are connected in series.   The extraction circuit includes a ratio of an element size of the third transistor to an element size of the first transistor, and a ratio of an element size of the fourth transistor to an element size obtained by halving the element size of the second transistor. The amplifier circuit according to claim 11, wherein the third transistor and the fourth transistor are formed so as to be the same. The current control circuit includes a tenth transistor connected in parallel with one of the first transistor and the twelfth transistor,
The amplifier circuit according to claim 11 or 12, wherein an adjustment signal output from the adjustment circuit is supplied to a gate terminal of the tenth transistor. The current control circuit includes an eleventh transistor connected in parallel with the other of the first transistor and the twelfth transistor,
The amplifier circuit according to claim 13, wherein a predetermined second bias voltage is supplied to a gate terminal of the eleventh transistor.   The adjustment circuit includes a comparison circuit that compares a predetermined reference voltage with a voltage corresponding to the offset current, and supplies a comparison result of the comparison circuit to the current control circuit as the adjustment signal. Item 15. The amplifier circuit according to any one of Items 9, 10, 13, and 14.

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