JP2019004179A - Substrate processing apparatus - Google Patents

Abstract

To provide a substrate processing apparatus that has a high rate of operation, can perform processing of a substrate correctly and precisely and has a high degree of freedom of structure change.SOLUTION: A substrate processing apparatus comprises: a plurality of processing blocks each including a plurality of units performing a series of continuous processes for applying liquid processing to a substrate and a conveying mechanism between units for conveying the substrates between a plurality of the units; block control sections that are arranged in each of a plurality of processing blocks and control a plurality of the units and the conveying mechanism between the units; and a main conveying mechanism that is controlled by a host controller installed in common with respect to each block control section corresponding to each of a plurality of the processing blocks, and conveys the substrate from or to the processing blocks. Then, the block control sections transfer information with respect to the host controller to independently perform processing.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a substrate processing apparatus including a plurality of units for processing a substrate.

  In a photolithography process in the manufacturing process of a semiconductor device, a developing solution is used to supply a chemical solution such as a resist for forming a coating film on a semiconductor wafer (hereinafter referred to as a wafer), which is a substrate, or to develop the resist. Various treatments such as supplying various liquids and heat treatment are performed. A substrate processing apparatus equipped with a large number of units for performing various types of processing is provided with a control unit (controller), which transmits a control signal to each unit and a substrate transport mechanism that transports a substrate between the units. Is controlling the operation. Patent Document 1 describes a substrate processing apparatus having such a control unit.

  However, it is necessary to stop the operation of the control unit when performing maintenance such as replacement of hardware components constituting the control unit or updating of software configuring the control unit. During the stop, each unit and the substrate transport mechanism cannot operate. Therefore, there is a possibility that the operating rate of the substrate processing apparatus cannot be sufficiently increased. In addition, when the unit is downsized and more units are mounted on the substrate processing apparatus, the load on the control unit is increased, so that the accuracy and accuracy of the operation of the unit cannot be ensured. There is. Further, there is a demand for a substrate processing apparatus that can freely add and remove units and can handle various processes.

JP-A-2005-175310

  The present invention has been made in view of such points, and an object of the present invention is to provide a substrate processing apparatus that has a high operating rate, can perform substrate processing accurately and accurately, and has a high degree of freedom in changing the configuration. That is.

The substrate processing apparatus according to the present invention includes a plurality of units each including a plurality of units that perform a series of continuous processes for performing liquid processing on the substrate, and an inter-unit transport mechanism that transports the substrate between the plurality of units. Processing blocks,
A block controller provided for each of the plurality of processing blocks, for controlling the plurality of units and the inter-unit transport mechanism;
A host control unit provided in common for each block control unit corresponding to each of the plurality of processing blocks;
A main transport mechanism that is controlled by the host controller and carries the substrate in and out of the processing block;
The block control unit is configured to exchange information with the host control unit.

  The substrate processing apparatus of the present invention is provided with a plurality of processing blocks including a plurality of units that perform a series of continuous processing for performing liquid processing on a substrate and an inter-unit transfer mechanism, and is provided corresponding to the processing blocks. The main transfer mechanism controlled by the host control unit that exchanges information with the block control unit carries the substrate into and out of the processing block. Therefore, even if one of the block control units becomes inoperable, the processing block including the other block control units can process the substrate, so that a reduction in the operating rate of the substrate processing apparatus can be suppressed. In addition, since the load on the block control unit can be suppressed as compared with the case where the operation of all the units in the substrate processing apparatus is controlled by one block control unit, even when a relatively large number of units are provided. It is possible to prevent the accuracy and precision of substrate processing in each unit from being lowered. Furthermore, in this substrate processing apparatus, the number of units can be increased or decreased by increasing or decreasing the processing blocks. Since a block control unit is provided for each processing block, fluctuations in loads in the block control unit and the higher-level control unit of processing blocks other than the increased or decreased processing blocks are suppressed by increasing or decreasing the processing blocks. Therefore, in the substrate processing apparatus of the present invention, it is possible to change the configuration by relatively increasing and decreasing the number of units, thereby improving the throughput and meeting various processing requirements.

1 is a plan view of a coating and developing apparatus according to a first embodiment of the present invention. It is a perspective view of the coating and developing apparatus. It is a schematic longitudinal side view of the coating and developing apparatus. It is a schematic longitudinal side view of the coating and developing apparatus. It is a vertical front view of the processing block provided in the said coating and developing apparatus. It is a perspective view of the conveyance mechanism which conveys a wafer to the said process block and a process block. It is a schematic block diagram of the resist film formation unit and liquid processing supply mechanism provided in a processing block. It is explanatory drawing which shows the connection of the block control part provided in the said process block, and a block control part. It is the schematic which shows the conveyance path | route of the wafer in the said application | coating and image development apparatus. It is a schematic perspective view of the application | coating and developing apparatus of 2nd Embodiment. 2 is a plan view of the coating and developing apparatus. FIG. It is a perspective view which shows the modification of the application | coating and developing apparatus of the said 2nd Embodiment.

(First embodiment)
A coating and developing apparatus 1 that is a substrate processing apparatus according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2 are a plan view and a perspective view of the coating and developing apparatus 1, respectively. The coating / developing apparatus 1 is connected to an exposure apparatus A4. By the coating / developing apparatus 1 and the exposure apparatus A4, a resist film is formed on the surface of the wafer W as a substrate, the resist film is exposed, and the resist film is developed. A resist pattern forming system is formed in which a resist pattern is formed on the resist film by sequentially performing the above steps.

  The coating / developing apparatus 1 includes a carrier section A1, a processing section A2, and an interface section A3 arranged in a straight line in the horizontal direction in this order, and an exposure apparatus A4 opposite to the interface section A3. Is connected. Regarding sections A1 to A3, sections arranged adjacent to each other are in contact with each other and are partitioned from each other. For convenience, in the following description, the arrangement direction of the sections A1 to A3 is the front-rear direction, the carrier section A1 side is the front side, and the interface section A3 side is the rear side. Unless otherwise specified, the right side and the left side described later are the right side and the left side when viewed from the front side toward the rear side.

3 and 4 are schematic longitudinal side views of the coating / developing apparatus 1 as viewed from the right side to the left side and from the left side to the right side, and each section will be described with reference to FIGS. 3 and 4. . First, the carrier section A1 will be described. Reference numeral 11 in the drawing denotes a carrier that is transported from the outside of the coating and developing apparatus 1 in a state where a plurality of wafers W are stored. In the figure, reference numeral 12 denotes a mounting table for the carrier 11. In the figure, reference numeral 13 denotes an opening / closing portion that opens and closes a transport port provided on the side wall of the carrier section A1. In the drawing, reference numeral 14 denotes a wafer W transfer mechanism, which is arranged in the horizontal direction so that the wafer W can be transferred between the carrier 11 mounted on the mounting table 12 and transfer units TRS11 and TRS12 described later. A holding body is provided for holding a wafer W that can move, move up and down, rotate about a vertical axis, and move forward and backward.

The delivery units TRS11 and TRS12 are respectively provided on the upper right side and the upper left side on the rear side in the carrier section A1. Each of the transfer sections TRS (described later) provided in the transfer sections TRS11 and TRS12 and the interface section A3 provided in the carrier section A1 includes, for example, a horizontal plate and a plurality of pins protruding upward from the plate. The wafer W is moved up and down on the pins by the lifting and lowering operation of the wafer W transfer mechanism accessing each transfer unit TRS, and the wafer W is transferred between the wafer W transfer mechanisms. be able to.

  Next, the processing section A2 will be described with reference to the schematic longitudinal front view of FIG. The processing section A2 includes processing blocks (cells) B1 to B8. The processing blocks B1, B2, B3, B4 are arranged in a line in this order from the front to the rear on the right side, and the processing blocks B5, B6, B7, B8 are on the left side, from the front to the rear. They are arranged in a line in order. Further, the processing blocks B1 and B5 face left and right, the processing blocks B2 and B6 face left and right, the processing blocks B3 and B7 face left and right, and the processing blocks B4 and B8 face left and right. Each of the processing blocks B <b> 1 to B <b> 8 includes a casing 31, and each casing 31 is partitioned from each other.

  The processing blocks B <b> 1 to B <b> 8 can perform a series of continuous processes including the temperature adjustment of the wafer W, the supply of the processing liquid to the temperature-adjusted wafer W, and the heating process of the wafer W, respectively. , A temperature adjustment unit, a liquid processing unit, and a heating unit. The processing blocks B1 and B2 are blocks having the same configuration. In these processing blocks B1 and B2, a chemical solution (coating solution) for forming an antireflection film is applied to the wafer W as the processing solution. The processing blocks B3 and B4 are blocks having the same configuration. In these processing blocks B3 and B4, a resist, which is a coating solution for forming a resist film, is applied to the wafer W as the processing solution. The processing blocks B5 to B8 are blocks having the same configuration. In these processing blocks B5 to B8, a developing solution is supplied to the wafer W as the processing solution. Note that the processing block for supplying the chemical solution for forming the antireflection film may be represented as “BCT”, the processing block for supplying the resist as “COT”, and the processing block for supplying the developing solution as “DEV”. .

  As a representative of the processing blocks B1 to B8, the COT processing block B3 will be described with reference to the perspective view of FIG. The upper right side of the casing 31 of the COT processing block B3 forms a protruding portion 32 that protrudes upward (see FIG. 2), and on the front side in the protruding portion 32, the transfer portions TRS1 and TRS2 are arranged in the vertical direction. Are provided. The transfer units TRS1 and TRS2 have a role of placing the wafer W between the main transfer mechanism D1 and the inter-unit transfer mechanism 4 described later, and the transfer unit TRS1 is a COT. The loading unit for loading the wafer W into the processing block B3 and the transfer unit TRS2 are loading units for unloading the wafer W from the COT processing block B3. An opening is formed on the left side surface of the protrusion 32 so that the main transport mechanism D1 can access the transfer units TRS1 and TRS2. When this access is not performed, the opening is closed by a shutter. The shutter and the opening are not shown.

  The delivery units TRS1 and TRS2 are configured in the same manner. As a representative example, the transfer unit TRS1 will be described with reference to FIG. 6. The transfer unit TRS1 includes a plurality of circular horizontal plates (only one is shown in FIG. 6) stacked in the vertical direction at intervals. And a plurality of notches are formed on the peripheral edge of each plate. The wafer W is placed on each of the plurality of plates, and the notch of the plate is formed so as to correspond to a later-described claw portion 44B of each transfer mechanism that transfers the wafer W to the transfer portion TRS.

  An inter-unit transfer mechanism 4 that transfers the wafer W between the units in the process block B3 and between the units and the transfer units TRS1 and TRS2 is provided on the right rear side in the process block B3. The inter-unit transport mechanism 4 includes an upright vertical frame-shaped elevating guide 41, an elevating table 42 that elevates vertically along the length direction of the elevating guide 41, and a vertical axis on the elevating table 42. And a holder 44 for the wafer W provided on the rotary table 43 so as to be movable back and forth. The raising / lowering guide 41 is formed so that the holding body 44 can move up and down in a region (hoistway) from the lower end to the protrusion 32 in the housing 31. The holding body 44 has a generally C-shaped holding body main body 44A surrounding the side periphery of the wafer W, and protrudes from the lower end of the holding body main body 44A toward the inside of the holding body main body 44A. A plurality of claw portions 44B that support the portion.

  The transfer of the wafer W between the inter-unit transfer mechanism 4 and the transfer units TRS1 and TRS2 is performed with respect to the plates constituting the transfer units TRS1 and TRS2 in a state where the holding body 44 of the inter-unit transfer mechanism 4 advances the rotary table 43. It is done by moving up and down. At the time of delivery, the holding body main body 44A passes through the outside of the plate and the claw portion 44B passes through the notch of the plate. Note that the transfer of the wafer W between the main transfer mechanism D1 and the transfer units TRS1 and TRS2 described later is performed in the same manner as the transfer of the wafer W between the inter-unit transfer mechanism 4 and the transfer units TRS1 and TRS2. Is called.

  Below the protrusion 32 in the housing 31, temperature adjustment units SCPL <b> 1 to SCPL <b> 3 are stacked in the vertical direction. Each of the temperature adjustment units SCPL1 to SCPL3 is configured in substantially the same manner as the transfer unit TRS1, and can transfer the wafer W to and from the inter-unit transfer mechanism 4. The difference from the transfer unit TRS1 is that the plate of the temperature adjustment unit SCPL is provided with a liquid flow path whose temperature is adjusted by a temperature adjustment mechanism (not shown), and this liquid brings the temperature of the plate to a predetermined temperature. It has been adjusted. By placing the wafer W on this plate, the temperature of the wafer W is adjusted to a predetermined temperature. The temperature adjustment units SCPL1 to SCPL3 adjust the temperature of the wafer W before supplying the resist to the wafer W so that the resist film formed by the resist has a desired film thickness. It has a role to control reliably.

  In the housing 31, heating units 33 to 36 are provided on the left rear side so as to be stacked in the vertical direction. The heating units 33 to 36 have a role of volatilizing the solvent remaining in the resist film and drying the resist film. The heating units 33 to 36 include, for example, a temperature adjustment plate for the wafer W formed similarly to the plate of the temperature adjustment unit SCPL, and a hot plate for heating the mounted wafer W to a desired temperature. A moving mechanism for moving the plate in the horizontal direction between the outer side of the hot plate and the upper side of the hot plate is provided. The hot plate is provided with elevating pins that support the back surface of the wafer W that protrudes and sinks on the hot plate in order to deliver the wafer W between the hot plate and the plate moved on the hot plate. . In addition, the plates of the heating units 33 to 36 are provided with slits through which elevating pins pass when the wafer W is transferred. When the plates of the heating units 33 to 36 are located outside the hot plate, the wafer W is transferred to the plates by the lifting and lowering operation of the holding body 44 of the inter-unit transfer mechanism 4. The hot plate is configured to change its temperature in accordance with a control signal from a block control unit C3 described later.

  A resist film forming unit 5, which is a liquid processing unit, is provided below the above-described temperature adjustment units SCPL1 to SCPL3. Further, a processing liquid supply mechanism 6 is provided on the left side of the temperature adjustment units SCPL1 to SCPL3. Referring to FIG. 7, which is a schematic configuration diagram of the resist film forming unit 5 and the processing liquid supply mechanism 6, the resist film forming unit 5 includes a spin chuck 51 that sucks and holds the center of the back surface of the wafer W, and a wafer W. A nozzle 52 for discharging a resist to the center of the wafer W and a cup 53 surrounding the side periphery of the wafer W in order to prevent the liquid from scattering from the wafer W.

  In the figure, reference numeral 54 denotes a rotation mechanism, which rotates the spin chuck 51 to apply the resist discharged to the center of the surface of the wafer W by spreading it to the peripheral edge by centrifugal force, thereby forming a resist film. The number of rotations of the wafer W by the rotation mechanism 54 is controlled according to a control signal from the block control unit C3. In the figure, reference numeral 55 denotes an elevating pin that pushes up the back surface of the wafer W. In FIG. 6, the resist film forming unit 5 is shown so as to straddle the housing 31 from side to side. However, the spin chuck 51 described above is below the temperature adjustment units SCPL <b> 1 to SCPL <b> 3, that is, inside the housing 31. The wafer W can be transferred between the inter-unit transfer mechanism 4 and the spin chuck 51 via the lift pins 55.

  The wafer W can be transferred by moving the holding body 44 of the inter-unit transfer mechanism 4 up and down with respect to the units and the transfer units TRS1 and TRS2 arranged in this way. That is, the resist film forming unit 5, the temperature adjustment units SCPL <b> 1 to SCPL <b> 3, the heating units 33 to 36, and the transfer units TRS <b> 1 and TRS <b> 2 are arranged along the hoistway of the holder 44.

  Next, the processing liquid supply mechanism 6 will be described with reference to FIG. The processing liquid supply mechanism 6 includes a pipe 61 for supplying a resist to the nozzle 52 of the resist film forming unit 5. The pipe 61 has, for example, a valve V 1, a pump P, and a filter 62 toward the upstream side. A resist storage tank 63 is interposed in this order. The pump P sucks the resist stored in the storage tank 63 and pumps it to the downstream side. The supply state of the pressure-fed resist to the nozzle 52 and the supply stop state are switched by opening and closing the valve V1. That is, the flow rate and supply timing of the resist supplied to the wafer W are controlled by the operations of the pump P and the valve V1. The storage tank 63 is provided with an air vent so that the resist supplied from the upstream side of the storage tank 63 can be stored, but the illustration is omitted.

  Incidentally, for example, a processing liquid supply source 65 is provided outside the processing section A2. The processing liquid supply source 65 is connected to the upstream end of the pipe 64. The downstream side of the pipe 64 is branched, and one downstream end is connected to the storage tank 63 via a valve V <b> 2 included in the processing liquid supply mechanism 6. The other downstream end of the branched pipe 64 will be described later.

  The processing liquid supply source 65 includes a tank that stores a resist as a processing liquid, and a pressure feeding mechanism that pressurizes the tank and feeds the resist to the downstream side of the pipe 64, and the valve V2 is opened. Thus, the resist is supplied to the pump P via the pipes 61 and 64 and the resist is stored in the storage tank 63. After the resist is stored in the storage tank 63, for example, the valve V2 is closed, and the resist stored in the storage tank 63 is supplied to the nozzle 52 as described above. The operations of the valves V and the pumps P of the processing liquid supply mechanism 6 and the resist film forming unit 5 are controlled according to control signals from the block control unit C3. The processing liquid supply mechanism 6 only needs to include at least the pump P because it can supply the nozzle 52 resist.

  In the COT processing block B3, a block control unit C3 is provided so as to straddle between the transfer units TRS1 and TRS2 and the temperature adjustment units SCPL1 to SCPL3 from above the processing liquid supply mechanism 6 (FIG. 6). The block control unit C3 will be described later.

  Subsequently, processing blocks other than the COT processing block B3 will be described focusing on differences from the processing block B3. The configuration of the COT processing block B4 is the same as that of the COT processing block B3 as described above. The storage tank 63 of the processing liquid supply mechanism 6 provided in the processing block B4 is connected to the other downstream end of the pipe 64 of FIG. Is connected. As described above, the resist supply source 65 is shared by the COT processing blocks B3 and B4. Then, the processing liquid supply mechanism 6 of the COT processing block B3 and the processing liquid supply mechanism 6 of the COT processing block B4 use the resist supplied from the resist supply source 65 independently of the resist film forming unit of the processing block B3. 5. The resist film forming unit 5 in the COT processing block B4 can be supplied. That is, the resist film forming unit 5 of the COT processing block B3 and the resist film forming unit 5 of the COT processing block B4 can perform processing by supplying the same kind of processing liquid to the wafer W independently of each other. As will be described later, the number of processing blocks in the coating and developing apparatus 1 can be appropriately increased or decreased. The pipe 64 is detachable from the processing liquid supply source 65 and the storage tank 63 so that the downstream branching number can be replaced with one corresponding to the number of COT processing blocks in the coating and developing apparatus 1.

  The BCT processing blocks B1 and B2 have substantially the same configuration as the processing block B3. The difference from the processing block B3 is that a liquid processing unit is used, and an antireflection film is formed on the wafer W instead of the resist film forming unit 5 described above. For example, an antireflection film forming unit 5 </ b> A for supplying a chemical solution for forming an antireflection film may be provided. Therefore, in the processing liquid supply source 65 connected to each processing liquid supply mechanism 6 provided in the BCT processing blocks B1 and B2, the chemical liquid for forming the antireflection film is stored instead of the resist. The temperature adjustment unit and heating unit provided in the BCT processing blocks B1 and B2 have the same role as the temperature adjustment unit and heating unit of the COT processing blocks B3 and B4.

  Further, the DEV processing blocks B5 to B8 will be described. The difference between the DEV processing blocks B5 to B8 and the COT processing block B3 is that the protruding portion 32 of the housing 31 is formed on the left side, and the inter-unit transport mechanism. 4 is provided at the left rear in the block, the temperature adjustment units SCPL1 to SCPL3, the transfer units TRS1, TRS2, and the spin chuck 51 of the liquid processing unit are provided at the left front in the block, and the processing liquid supply mechanism 6 is blocked. And the heating units 33 to 36 are provided on the right rear side in the block. By arranging each part in this way, the temperature adjustment units SCPL1 to SCPL3, the transfer units TRS1, TRS2, the liquid processing unit, the block control unit C, and the processing liquid supply mechanism 6 are provided symmetrically in the processing section A2. Yes.

  Further, instead of the main transfer mechanism D1, a later-described main transfer mechanism D2 transfers the wafer W to the transfer units TRS1 and TRS2 of the DEV processing blocks B5 to B8. An opening (not shown) that is opened and closed by the shutter in the protrusion 32 of the housing 31 is provided on the right side surface corresponding to the position of the main transport mechanism D2.

  In the DEV processing blocks B5 to B8, as a liquid processing unit, a developing unit 5B for supplying a developing solution to the wafer W and developing the exposed resist film is provided instead of the resist film forming unit 5 described above. Therefore, the developing solution is stored in the processing solution supply source 65 for supplying the processing solution to the DEV processing blocks B5 to B8 instead of the resist. The downstream end of the pipe 64 connected to the processing liquid supply source 65 is branched into four and connected to the processing liquid supply mechanisms 6 of the processing blocks B5 to B8, and the developing units of the processing blocks B5 to B8. In 5B, it is comprised so that a developing solution can be supplied mutually independently.

  The temperature adjustment units SCPL1 to SCPL3 provided in the processing blocks B5 to B8 adjust the temperature of the wafer W before supplying the developing solution to control the reaction between the resist film and the developing solution, and more reliably form a resist pattern having a desired shape. Is provided. The heating units 33 to 38 are provided for performing drying of the wafer W after the development processing and post-exposure baking (PEB) for heating the wafer W after the exposure processing and before the development processing.

  The processing blocks B1 to B8 configured as described above can carry the wafer W independently of each other and perform a series of continuous processes including the temperature adjustment, heating, and liquid processing. In FIG. 1 and the like, the block controllers provided in the processing blocks B1, B2, and B4 to B8 are indicated as C1, C2, and C4 to C8, respectively.

  Next, the main transport mechanisms D1 and D2 provided in the processing section A2 will be described. The main transport mechanism D1 is provided on the left side of the protrusion 32 of the casing 31 on the casing 31 of the processing blocks B1 to B4. The main transport mechanism D1 is configured in substantially the same manner as the inter-unit transport mechanism 4, and the same components as the inter-unit transport mechanism 4 in the main transport mechanism D1 in each drawing are attached to the inter-unit transport mechanism 4. The same reference numerals as those in FIG. The difference from the inter-unit transport mechanism 4 is that the height of the lift guide 41 of the main transport mechanism D1 is smaller than the height of the lift guide 41 of the inter-unit transport mechanism 4, and the lift of the main transport mechanism D1. The guide 41 is connected to a moving mechanism 46 formed over the processing block B1 to B4, and two holding bodies 44 of the main transport mechanism D1 are provided, and are independent of each other on the turntable 43. Is configured to be capable of moving forward and backward.

  By the moving mechanism 46, the lifting guide 41 can move in the front-rear direction in a region extending from the processing block B1 to B4. The holding body 44 of the main transfer mechanism D1 is connected to the wafers W between the transfer units TRS1 and TRS2 of the processing blocks B1 to B4, the transfer unit TRS11 of the carrier section A1, and a transfer unit TRS21 described later in the interface section A3. Can be handed over.

  The main transport mechanism D2 is configured in the same manner as the main transport mechanism D1, and is provided on the right side of the protrusion 32 on the housing 31 of the processing blocks B5 to B8. The moving mechanism 46 of the main transport mechanism D2 It is formed over the block B1 to B4. The raising / lowering guide 41 of the main transport mechanism D2 is movable in the front-rear direction in an area extending from the processing block B5 to B8, and the holding body 44 of the main transport mechanism D2 is a transfer unit TRS1 of the processing blocks B5 to B8. The wafer W can be transferred between TRS2, the transfer section TRS12 of the carrier section A1, and the transfer section TRS22 described later provided in the interface section A3.

  Next, the interface section A3 will be described. The transfer sections TRS21 and TRS23 are stacked and provided above and below the right side of the interface section A3. The transfer sections TRS21 and TRS23 are stacked and provided above and below the left side of the interface section A3. Further, in the interface section A3, for example, transfer mechanisms 21 to 23 for the wafer W are provided. The transfer mechanism 21 transfers the wafer W between the transfer units TRS21 and TRS23, and the transfer mechanism 22 transfers a wafer W holder that can be moved up and down and retracted in order to transfer the wafer W between the transfer units TRS22 and TRS24. I have. The transfer mechanism 23 includes a wafer W holder that can move in the left-right direction, can move up and down, can rotate about the vertical axis, and can move forward and backward in order to transfer the wafer W between the exposure apparatus A4 and the transfer units TRS23 and TRS24. ing. The interface section A3 is provided with a cleaning unit for cleaning the wafer W, a temperature adjustment unit SCPL, and the like in addition to the transfer unit. However, in order to prevent the explanation from becoming complicated, the description and illustration of these units are omitted.

  Next, the upper control unit 100 provided in the coating and developing apparatus 1 and the block control units C1 to C8 will be described with reference to FIG. The host controller 100 and the block controllers C1 to C8 are each a computer. Each block control unit C is connected to each unit provided in the processing block B including the block control unit C, the processing liquid supply mechanism 6, and the inter-unit transport mechanism 4. The host controller 100 is connected to the transport mechanism 14 of the carrier section A1, the transport mechanisms 21 to 23 of the interface section A3, and the main transport mechanisms D1 and D2. Further, the block control units C1 to C8 are connected to the higher order control unit 100. That is, a common higher order control unit 100 is provided for the block control units C1 to C8 provided corresponding to the processing blocks B1 to B8, respectively. As will be described later, in the coating and developing apparatus 1, the processing block B can be increased or decreased freely. For this reason, connection and disconnection between each block control unit C and the upper control unit 100 can be performed freely. It is configured to be able to.

  When each block control unit C can transfer the wafer W to the processing block B including the block control unit C, information indicating that the block control unit C can transfer the wafer W (hereinafter referred to as transfer). And the positional information of the wafer W in the processing block B are transmitted. Supplementing the above transportable information, for example, the block control unit C is under maintenance as described in the section of the background art, is being restarted, or the software or hardware constituting the block control unit C If the block control unit C does not operate normally due to trouble or the like, this transportable information is not output. Further, even when the inter-unit transport mechanism 4 or the unit cannot be used, for example, when the series of processing cannot be performed in the processing block B, this transportable information is not output. Supplementing the position information of the wafer W, for example, it is information indicating which wafer W is located in which unit or transfer unit TRS in the processing block B.

  For each block control unit C to which the above-described transferable information is output, the upper control unit 100 transfers the wafer according to the transfer recipe in the processing block B including the block control unit C and the transfer recipe in the processing block B. The liquid processing unit to which W is conveyed and the processing recipe of the heating unit are transmitted. As described above, information for transferring and processing the wafer W is exchanged between the host control unit 100 and each block control unit C.

  The transfer recipe in the processing block B is specifically data on the transfer path of the wafer W in the processing block B. More specifically, which unit of the unit group in one processing block B is selected. Data in which order the wafers W are transferred. In addition, the processing recipe of the liquid processing unit includes, for example, the supply flow rate of the processing liquid to the wafer W, the timing of supplying the processing liquid, and the rotation speed of the wafer W during the liquid processing. The processing recipe of the heating units 33 to 36 includes, for example, the temperature of the hot plate.

  Each block control unit C is configured such that each unit of the processing block B including the block control unit C, the processing liquid supply mechanism 6 and the inter-unit transport mechanism so that the transport and processing specified by the transport recipe and the processing recipe can be performed. A control signal is output to 4 to control these operations. That is, based on the transfer recipe and processing recipe created for each processing block B1 to B8, the block control units C1 to C8 individually output control signals, whereby the operations of the respective units in the processing blocks B1 to B8 are processed. The blocks B are controlled independently of each other.

  Further, the upper control unit 100 outputs control signals to the main transport mechanisms D1 and D2, the transport mechanism 14 of the carrier section A1, and the transport mechanisms 21 to 23 of the interface section A3, and performs operations of these transport mechanisms. Control. As a result, the wafer W is transferred between the carrier section A1, each processing block B, and the interface section A3 as described later, and a resist pattern is formed on the wafer W. Output of the control signal from the upper control unit 100 to the main transport mechanisms D1 and D2 is performed based on the position information transmitted from each block control unit C. That is, when position information indicating that the wafer W has been placed on the transfer unit TRS2 which is a loading placement unit of the processing block B is output, a control signal is sent to the main transfer mechanisms D1 and D2 so as to receive the wafer W. Is output, and it is found from the position information that the transfer unit TRS1, which is the loading unit of the processing block B that is the transfer destination of the wafer W, is vacant, a control signal is sent so as to transfer the wafer W to the transfer unit TRS1. Is output.

  Each block control unit C and the host control unit 100 each have a program storage unit (not shown). As described above, each program storage unit stores a program in which commands (step groups) are configured to transmit control signals to the respective units of the coating and developing apparatus 1 to control the operations of the respective units. The program is stored in the program storage unit in a state of being stored in a storage medium such as a hard disk, a compact disk, a magnetic optical disk, or a memory card.

  Subsequently, the transfer and processing of the wafer W in the coating and developing apparatus 1 will be described. FIG. 9 shows an outline of the transfer path of the wafer W. First, the upper control unit 100 transmits a transport recipe and a processing recipe to the processing block B to which the above-described transportable information is output. Then, the wafer W in the carrier 11 mounted on the mounting table 12 in the carrier section A1 is transferred to the transfer unit TRS11 by the transfer mechanism 14 in the carrier section A1, and is transferred to the main transfer mechanism D1. Then, the wafer W is transferred to the transfer unit TRS1 of the BCT processing block B1 or B2 by the main transfer mechanism D1. Then, the wafer W is transferred to one of the temperature adjustment units SCPL1 to SCPL3 by the inter-unit transfer mechanism 4 and the temperature is adjusted, and then transferred to the antireflection film forming unit 5A to form an antireflection film. The Thereafter, the wafer W is transported to one of the heating units 33 to 36 and heated, and then transported to the delivery unit TRS2, and is unloaded from the BCT processing block B1 or B2 by the main transport mechanism D1.

  Thereafter, the wafer W is transferred to the transfer part TRS1 of the COT processing block B3 or B4 by the main transfer mechanism D1. Then, the wafer W is transferred to one of the temperature adjustment units SCPL1 to SCPL3 by the inter-unit transfer mechanism 4 and the temperature is adjusted, and then transferred to the resist film forming unit 5 and laminated on the antireflection film. Thus, a resist film is formed. Thereafter, the wafer W is transported to one of the heating units 33 to 36 and heated, and then transported to the transfer unit TRS2, and is unloaded from the COT processing block B3 or B4 by the main transport mechanism D1.

  Subsequently, the wafer W is transferred by the main transfer mechanism D1 to the transfer section TRS21 of the interface section A3, transferred in the order of the transfer mechanism 21 → the transfer section TRS23 → the transfer mechanism 23, and then transferred to the exposure apparatus A4 to be registered. The film is exposed along a predetermined pattern. The exposed wafer W is transferred in the order of the transfer mechanism 23 → the transfer unit TRS24 → the transfer mechanism 21 → the transfer unit TRS22, and is transferred from the interface section A3 by the main transfer mechanism D2.

  Thereafter, the wafer W is transferred by the main transfer mechanism D2 to any one of the transfer units TRS1 among the DEV processing blocks B5 to B8. Then, the wafer W is transferred to any one of the heating units 33 to 36 by the inter-unit transfer mechanism 4 to perform PEB, and then transferred to any one of the temperature adjustment units SCPL1 to SCPL3. After adjustment, the image is conveyed to the developing unit 5. A developing solution is supplied, and the resist film is dissolved along the exposed pattern to form a resist pattern. Thereafter, the wafer W is transferred to one of the heating units 33 to 36 and heated, and then transferred to the transfer unit TRS2. The main transfer mechanism D2 causes the wafer W in the DEV processing blocks B5 to B8 to be transferred. It is unloaded from the loaded processing block B. Thereafter, the wafer W is transferred by the main transfer mechanism D2 in the order of the transfer section TRS12 → the transfer mechanism 14 of the carrier section A1, and returned to the carrier 11.

  In this way, until the wafer W is unloaded from the carrier 11 and returned to the carrier 11, the block control unit C of each processing block B outputs the above-described position information of the wafer W to the host control unit 100, Based on this, the operations of the main transport mechanisms D1 and D2 are controlled. Further, the processing in the liquid processing unit and the heating unit in the processing block B is performed according to the transmitted processing recipe. That is, for the liquid processing unit and the processing liquid supply mechanism 6 connected to the liquid processing unit, the processing liquid supply flow rate, the processing liquid supply timing, and the rotation speed of the wafer W are specified respectively in the processing recipe. In addition, the operation of each valve V and pump P is controlled to perform processing. In the heating units 33 to 36, processing is performed by setting the temperature of the hot plate to the temperature specified in the processing recipe.

  According to the coating / developing apparatus 1 described above, the processing blocks B1 to B8 are provided that perform a series of processes including a liquid process, a temperature adjustment process, and a heating process on the wafer W, respectively. Each processing block B is connected to the host control unit 100, and based on the transfer recipe and the processing recipe transmitted from the host control unit 100, the operation of the units in the processing block B, the processing liquid supply mechanism 6 In order to control the operation and the operation of the inter-unit transport mechanism 4, a block control unit C that outputs a control signal is provided. Therefore, even if one of the block control units C becomes inoperable due to the above-mentioned maintenance or the like, the wafer W is transferred to the block having the same configuration as the block including the block control unit C that has become inoperable. The wafers W can be processed by operating the transfer mechanisms D1 and D2. Accordingly, it is possible to prevent the processing of the wafer W from being disabled in the entire coating and developing apparatus 1 by stopping the operation of one block control unit C. As a result, it is possible to suppress a decrease in the operating rate of the coating and developing apparatus 1.

  Further, according to the coating and developing apparatus 1 described above, as compared with an apparatus configured to control all the units in all the eight processing blocks B and all the inter-unit transport mechanisms 4 by one block control unit C, Since the amount of data transmitted and received with respect to the units of the two block control units C and the inter-unit transport mechanism 4 can be suppressed, the data processing burden of the block control unit C can be suppressed. As a result, it is possible to prevent a delay in data transmission / reception with respect to each unit and the inter-unit transport mechanism 4 and to ensure the accuracy of operation and the accuracy of the operations of the units and the inter-unit transport mechanism 4.

  Further, when the coating and developing apparatus 1 is turned on (at the time of setup), the wafer W can be transferred first from the processing block B to which transferable information is output by the block control unit C among the blocks having the same configuration. . Accordingly, it is possible to prevent the timing until the start of processing of the wafer W from being delayed, so that the above-described apparatus configuration in which the block control unit C is provided for each processing block B is also advantageous from this point.

  In addition, if the block control unit C is provided for each unit, the burden of data transmission / reception in the block control unit C can be further suppressed. It is realistic to control the transfer mechanism for transferring the wafer W between the units and the plurality of units by one block control unit C. In the operation example of the apparatus 1 described above, the resist film forming process and the developing process are performed on the wafer W. For example, one or two of a resist film forming process, an antireflection film forming process, and a developing process are performed. There is a case where the operation which performs only is made. As described above, the block control unit C that controls a unit related to a process that is not performed among the resist film forming process, the antireflection film forming process, and the developing process is stopped, and maintenance can be performed. Considering that it is necessary to control a plurality of units by one block control unit C, as in each processing block B described above, the temperature adjustment process performed in association with this liquid process, It is effective to control the unit that performs the heat treatment with one block control unit.

  Further, in each processing block B, each unit is arranged along the circumferential direction of the hoistway where the holding body 44 of the inter-unit transport mechanism 4 moves up and down as viewed in plan. By arranging the units along the hoistway in this way, the wafer W can be transferred between the units by the rotation and advance / retreat operation of the holding body 44. That is, it is not necessary to move the elevating guide 41 of the inter-unit transport mechanism 4 in the lateral direction for delivery between the units. Therefore, the footprint (occupied floor area) in each processing block B can be suppressed. Further, since each unit is provided by being stacked in the vertical direction (longitudinal direction) along this hoistway, the number of units provided in the processing block B should be increased while the footprint is reliably suppressed. Can do.

  In the above example, one liquid processing unit is provided in one processing block B, but a plurality of liquid processing units may be provided. In that case, for example, like the heating unit and the temperature adjustment unit, the plurality of liquid processing units can be provided so as to be stacked in the vertical direction. Moreover, in order to suppress the influence which the heat of the heating units 33-36 has on a liquid processing unit reliably, in each said processing block B, although a liquid processing unit and a heating unit are not mutually laminated | stacked, these liquid processing units The heating units may be stacked on each other.

  By the way, in the coating and developing apparatus 1 described above, for example, the wafer W may be transported so that only a resist film is formed. In that case, the wafer W is transferred from the carrier section A1 to the COT processing block B3 or B4 by the main transfer mechanism D1 without passing through the BCT processing blocks B1 and B2, and as described above in the COT processing block B3 or B4. Temperature adjustment, resist film formation, and heating are sequentially performed on the wafer W. Thereafter, the wafer W is transferred to the carrier 11 through the main transfer mechanism D1, the transfer section TRS11 of the carrier section A1, and the transfer mechanism 14 in order.

  Further, the wafer W may be transferred so that only development processing is performed. In that case, for example, the wafer W is transferred in the order of the delivery section TRS12 of the carrier section A1, the main transfer mechanism D2, and the DEV processing blocks B5 to B8, and the units in the DEV processing block B are transferred in the above order. Then, the wafer W is processed. Thereafter, the wafer W is returned to the carrier C via the main transfer mechanism D2 and the transfer unit TRS12. Similarly, for example, the wafer W may be transferred to B1 or B2 of the processing blocks B1 to B8 and only the antireflection film may be formed, or only the processing blocks B1 and B3 may be transferred to form the antireflection film. In addition, only the formation of the resist film may be performed. Processing blocks B that are not used can be removed from the processing section A2, or may not be provided from the beginning. Furthermore, a processing block configured in the same manner as the processing blocks B3 and B4 can be added to the coating and developing apparatus 1 to form a resist film with a total of three processing blocks. The throughput of the developing device 1 can be increased. When the processing block B is added in this way, the position of the added block only needs to be able to deliver the wafer W by the main transfer mechanisms D1 and D2, and is, for example, the front side or the rear side of the processing blocks B1 to B8. . Thus, the number of processing blocks can be increased or decreased as appropriate according to the type of processing required and the throughput.

  By the way, adding a unit to the coating and developing apparatus 1 or removing an unnecessary unit can be performed by increasing or decreasing the number of processing blocks. A block control unit C is provided for each processing block, and transmission of a control signal to the increased / decreased unit is performed by the block control unit C in the processing block including the increased / decreased unit. Therefore, the load of the block control unit C included in other processing blocks other than the increased or decreased processing blocks does not fluctuate. Even if the number of units is increased or decreased, the control signal for controlling each unit is output from the block control unit C, and since there is no need to output the control signal from the higher level control unit 100, the load on the higher level control unit 100 is also increased. Does not fluctuate greatly. In this manner, since fluctuations in the loads of the block control unit C and the host control unit 100 of other processing blocks B are suppressed, the number of units in the coating and developing apparatus 1 is increased or decreased by increasing or decreasing the number of processing blocks. Can be performed relatively freely, for example it is possible to provide a very large number of units. Therefore, the coating / developing apparatus 1 has an advantage that throughput can be improved and various processing requirements can be met.

  Further, since the main transport mechanisms D1 and D2 are provided above the processing blocks B1 to B8, when maintenance is performed on the main transport mechanisms D1 and D2, an operator can perform the main transport mechanism from the ceiling side of the clean room. D1 and D2 can be accessed. There is no need to provide other components of the coating and developing apparatus 1 on the main transport mechanisms D1 and D2. That is, since the upper part of the main transport mechanisms D1 and D2 can be opened, a relatively large space is provided between the coating / developing apparatus 1 and the ceiling of the clean room, which facilitates access and maintenance. There is an advantage of becoming. However, the main transport mechanisms D1 and D2 are provided below the processing blocks B1 to B8, and the transfer units TRS1 and TRS2 of each processing block B are also disposed below the processing block B so as to correspond to the main transport mechanisms D1 and D2. The wafer W may be transferred between D1 and D2 and the inter-unit transfer mechanism 4.

(Second Embodiment)
Next, the coating and developing apparatus 7 according to the second embodiment will be described focusing on the differences from the coating and developing apparatus 1 with reference to FIGS. 10 and 11 which are schematic perspective views and plan views, respectively. . The coating and developing device 7 includes a coating film forming unit 7A and a developing unit 7B that are provided on the left and right sides of the coating and forming unit 7A. The coating film forming unit 7A includes a carrier section A1 and a processing section A5. The processing section A5 is different from the processing section A2 of the first embodiment, and the processing block B is only the processing blocks B1 to B4. It has. The processing blocks B1 and B2 of the processing section A5 are provided at the positions where the processing blocks B5 and B6 of the processing section A2 of the first embodiment are provided. Each arrangement of the unit, the processing liquid supply mechanism 6, the block control unit C, and the inter-unit transport mechanism 4 is the same as that of the processing blocks B5 and B6.

  The developing unit 7B includes a carrier section A1, a processing section A6, and an interface section A3. Unlike the processing section A2, the processing section A6 includes only two processing blocks B5 and B6 among the processing blocks B1 to B8, and includes only D2 among the main transport mechanisms D1 and D2. The interface section A3 of the developing unit 7B is connected to the exposure apparatus A4 as in the first embodiment.

  An inter-section transport mechanism 71 is provided between the coating film forming unit 7A and the developing unit 7B. The inter-section transport mechanism 71 is configured in substantially the same manner as the inter-unit transport mechanism 4, and in FIG. 11, the same components as the main transport mechanism D 1 in the inter-section transport mechanism 71 are described in the inter-unit transport mechanism 4. The same reference numerals as those attached are used. The difference is that the inter-section transport mechanism 71 includes a horizontal movement mechanism 47 for moving the lifting guide 41 in the horizontal direction. Furthermore, the left-right direction moving mechanism 47 is connected to the front-rear direction moving mechanism 48 and can move in the front-rear direction.

  The holding body 44 of the inter-section transport mechanism 71 configured in this way includes the processing blocks B3 and B4 of the coating film forming unit 7A, the transfer units TRS1 and TRS2, and the transfer units TRS1 of the processing blocks B5 and B6 of the developing unit 7B. The wafer W can be delivered by accessing the TRS 2. The operation of the inter-section transport mechanism 71 is controlled by the host controller 100. Note that the inter-section transport mechanism 71 is thus provided to the transfer portion TRS on the side surfaces of the protruding portions 32 of the respective casings 31 of the processing blocks B3 and B4 of the coating film forming portion 7A and the processing blocks B5 and B6 of the developing portion 7B. An opening (not shown) for access is provided. For example, the opening is opened and closed by a shutter.

  Hereinafter, an example of the conveyance path of the wafer W in the coating and developing apparatus 7 will be described with reference to FIG. The wafer W delivered from the carrier 11 placed on the carrier section A1 of the coating film forming unit 7A is transferred from the transfer mechanism 14 of the carrier section A1 to the BCT processing block B1 via the transfer unit TRS12 and the main transfer mechanism D2. The antireflection film is formed by being conveyed between the units in the BCT processing blocks B1 and B2 as in the first embodiment. Thereafter, the wafer W is transferred to the COT processing block B3 or B4 through the main transfer mechanism D2, the transfer unit TRS12, the transfer mechanism 14, the transfer unit TRS11, and the main transfer mechanism D1 in this order. Similarly, after the units in the COT processing blocks B3 and B4 are transported to form a resist film, they are transported to the transfer section TRS2 of the COT processing blocks B3 and B4.

  After that, the wafer W is transferred by the inter-section transfer mechanism 71 to the transfer block TRS1 (not shown in FIG. 11 because it is stacked on the TRS2) of the processing block B5 or B6 of the developing unit 7B, and the main transfer mechanism D2. Then, the transfer unit TRS22, the transfer mechanism 22, the transfer unit TRS24 (not shown in FIG. 11 because it is stacked on the TRS22) and the transfer mechanism 23 are transferred to the exposure apparatus A4 in this order. The exposed wafer W is transported into the processing block B5 or B6 through the same path as in the first embodiment, subjected to development processing, and transported to the carrier 11 placed on the carrier section A1 of the developing unit 7B. The The carrier 11 placed on the developing unit 7B may be the carrier 11 that has delivered the wafer W by the coating film forming unit 7A, or a carrier different from the carrier 11 that has delivered the wafer W by the coating film forming unit 7A. 11 may be sufficient.

  Such a coating / developing apparatus 7 also has the same effects as the coating / developing apparatus 1. Further, the transport to the processing blocks B5 and B6 for performing the development processing is performed by the main transport mechanism D2 of the developing unit 7B, thereby reducing the load on the main transport mechanisms D1 and D2 of the coating film forming unit 7A and throughput. Can be improved.

  As shown in FIG. 12, a shelf 81 for temporarily placing the carrier 11 and a transfer mechanism 82 for the carrier 11 may be provided for the coating and developing device 7 described above. The shelf 81 is provided above the mounting table 12 of each carrier section A1 of the coating film forming unit 7A and the developing unit 7B. The transfer mechanism 82 includes a multi-joint arm 83 whose tip is configured to hold the upper portion of the carrier 11, and the multi-joint arm 83 extends to the tip side and the base end side of the arrow in the figure. The folded state is shown respectively. Reference numeral 84 in the drawing is a horizontal movement mechanism that is connected to the base side of the multi-joint arm 83 and moves the multi-joint arm 83 horizontally. With such a transfer mechanism 82, the carrier 11 can be transported between the mounting table 12 and the shelf 81 of each carrier section A1.

  An example of the transport of the carrier 11 will be described. For example, the carrier 11 is transported to the shelf 81 by a transfer mechanism (not shown) separate from the transfer mechanism 82 and waits. Thereafter, the wafer W is transferred to the mounting table 12 of the coating film forming unit 7A by the transfer mechanism 82, and the wafer W stored in the carrier 11 is discharged as described above. Thereafter, the carrier 11 is again transported to the shelf 81 by the transfer mechanism 82 and waited, and then transported to the mounting table 12 of the developing unit 7B, and the discharged wafer W is returned to the carrier 11. The operation of the transfer mechanism 82 is controlled by the host controller 100.

  By the way, the processing performed in the processing block B of each of the above embodiments is not limited to the formation of the antireflection film, the formation of the resist film, and the development processing. For example, as the liquid processing unit in the processing block B described above, a unit for applying a chemical solution for forming a protective film for protecting the resist film instead of the resist film forming unit 5 and the antireflection film forming unit 5A. It may be provided. This protective film is formed on the resist film in order to protect the surface of the resist film from water supplied to the surface of the wafer W in the exposure apparatus A4 when immersion exposure is performed in the exposure apparatus A4, for example. Is done.

  Further, as the liquid processing unit of the processing block B, a cleaning unit for supplying a cleaning liquid to the wafer W and cleaning it may be provided. For example, a liquid processing unit that supplies SPM (mixed liquid of sulfuric acid, hydrogen peroxide, and water) as a cleaning liquid, a liquid processing unit that supplies SC2 (mixed liquid of hydrochloric acid, hydrogen peroxide, and water), and SC1 (ammonia and excess liquid). A liquid processing unit for supplying a mixed liquid of hydrogen oxide and water is provided in one block, and the wafer W is transferred between these liquid processing units. For example, the cleaning liquid is applied to the wafer W in the order of SPM, SC2, SC1. May be performed. In addition, a liquid processing unit for supplying hydrofluoric acid (HF) as a cleaning liquid and a liquid processing unit for supplying SC1 are provided in one block, and the wafer W is transported between these liquid processing units. The cleaning liquid may be supplied in the order of SC1.

  As described above, the continuous series of processes performed in one process block B does not include the heating process and the temperature adjustment process, and only the liquid process may be performed. Furthermore, the apparatus may be configured such that only the above-described cleaning process is performed without performing the coating film forming process and the developing process. That is, the substrate processing apparatus of the present invention is not applied only to the coating and developing apparatus. Further, the liquid processing performed in one processing block may be one type or plural types. Therefore, for example, the antireflection film forming unit 5A and the resist film forming unit 5 are provided in one processing block B. Processing may be performed.

  In each of the above-described embodiments, two or more processing blocks B having the same configuration are provided in the coating and developing apparatus. However, a plurality of processing blocks B having the same configuration may not be provided. For example, the substrate processing apparatus may be configured such that different processes are performed in all of the plurality of processing blocks. Then, the plurality of processing blocks may be transferred in order, or the wafer W may be transferred to only one of the plurality of processing blocks, and each wafer W may be transferred to a different processing block. Thus, different processing may be performed on the wafer W.

  By the way, in each of the above examples, the block control unit C is provided in the processing block B by being included in the housing 31. In other words, the processing block B and the block control unit C are integrally configured such that when the processing block B is moved, the block control unit C is also moved. However, the block control unit C may not be provided in the processing block B. Specifically, the block control unit C may be provided outside the housing 31 separately from the housing 31, that is, the block control unit C may be provided separately from the processing block B. Thus, when the block control unit C is provided separately from the processing block B, the number of units that can be installed in the housing 31 can be increased and the layout of the block control unit C can be freely set. It is advantageous in that it can be performed.

However, since the block control unit C is provided in the processing block B, when the processing block B is increased or decreased with respect to the substrate processing apparatus, the block control unit C is moved together with the processing block B to the substrate processing apparatus. Thus, it can be added or removed, which is advantageous in that the effort of adding and removing can be reduced. The provision of the block control unit C in the processing block B is not limited to the provision of the block control unit C in the housing 31 as described above. For example, on the housing 31 or outside the housing 31 A configuration in which the block control unit C is provided on the side so as to be adjacent to the housing 31 and the housing 31 and the block control unit C can be moved together is also included.

A2 processing sections B1 to B8 Processing blocks C1 to C8 Block control units D1 and D2 Main transfer mechanisms TRS1 and TRS2 Transfer unit W Wafer 1 Coating and developing device 4 Inter-unit transfer mechanism 5 Resist film forming unit 6 Liquid processing supply mechanism 100 Upper level control Part

The substrate processing apparatus according to the present invention includes a plurality of units each including a plurality of units that perform a series of continuous processes for performing liquid processing on the substrate, and an inter-unit transport mechanism that transports the substrate between the plurality of units. Processing blocks,
A block controller provided for each of the plurality of processing blocks, for controlling the plurality of units and the inter-unit transport mechanism;
And a host control section that is provided in common to each of the block control unit corresponding to each of the plurality of processing blocks,
The block control unit is configured to exchange information with the host control unit, and can freely connect and disconnect each block control unit and the host control unit .

Claims (1)

A plurality of processing blocks each including a plurality of units that perform a series of continuous processing to perform liquid processing on a substrate, and an inter-unit transport mechanism that transports the substrate between the plurality of units;
A block controller provided for each of the plurality of processing blocks, for controlling the plurality of units and the inter-unit transport mechanism;
A host control unit provided in common for each block control unit corresponding to each of the plurality of processing blocks;
A main transport mechanism that is controlled by the host controller and carries the substrate in and out of the processing block;
The substrate processing apparatus, wherein the block control unit is configured to exchange information with the host control unit.

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