JP2019004030A5

JP2019004030A5 -

Info

Publication number: JP2019004030A5
Application number: JP2017117072A
Authority: JP
Filing date: 2017-06-14
Publication date: 2019-09-19

Description

上記目的を達成するための請求項１では、ＩＧＢＴ素子（１ａ）を有するＩＧＢＴ領域（１）と、ＦＷＤ素子（２ａ）を有するＦＷＤ領域（２）とが共通の半導体基板（１０）に形成されている半導体装置において、第１導電型のドリフト層（１１）と、ドリフト層上に形成された第２導電型のベース層（１２）と、ベース層の表層部であって、ベース層を挟んでドリフト層から離れた位置に形成され、ドリフト層よりも高不純物濃度とされた第１導電型のエミッタ領域（１６）と、ドリフト層を挟んでベース層と反対側であって、ＩＧＢＴ領域に形成された第２導電型のコレクタ層（２０）と、ドリフト層を挟んでベース層と反対側であって、ＦＷＤ領域に形成され、コレクタ層と隣接する第１導電型のカソード層（２１）と、ベース層と、コレクタ層およびカソード層との間に形成されたＦＳ層（２２）と、を有する半導体基板と、エミッタ領域とドリフト層との間に位置するベース層の表面に配置されたゲート絶縁膜（１４）と、ゲート絶縁膜上に配置されたゲート電極（１５）と、ベース層およびエミッタ領域と電気的に接続される第１電極（１８）と、コレクタ層およびカソード層と電気的に接続される第２電極（２３）と、を備え、ＦＳ層は、コレクタ層およびカソード層から離れて形成されており、ＦＷＤ素子に順方向電流が流れている状態から当該電流を遮断してリカバリ状態となった際、ＦＷＤ素子内の第１キャリアの一部がコレクタ層へと流れることにより、サージピーク電圧を小さくする量の第２キャリアが第２電極からコレクタ層を介してドリフト層に注入されるようにし、カソード層には、コレクタ層と離れた位置に、第２電極と電気的に接続される第２導電型のキャリア注入層（２４）を形成する。 In order to achieve the above object, an IGBT region (1) having an IGBT element (1a) and an FWD region (2) having an FWD element (2a) are formed on a common semiconductor substrate (10). A first conductivity type drift layer (11), a second conductivity type base layer (12) formed on the drift layer, and a surface layer portion of the base layer, sandwiching the base layer The emitter region (16) of the first conductivity type formed at a position away from the drift layer and having a higher impurity concentration than the drift layer, and on the opposite side of the base layer across the drift layer and in the IGBT region The formed second conductivity type collector layer (20) and the first conductivity type cathode layer (21) formed in the FWD region on the opposite side of the base layer across the drift layer and adjacent to the collector layer And the base layer A semiconductor substrate having an FS layer (22) formed between the collector layer and the cathode layer, and a gate insulating film (14) disposed on the surface of the base layer located between the emitter region and the drift layer A gate electrode (15) disposed on the gate insulating film; a first electrode (18) electrically connected to the base layer and the emitter region; and a first electrode electrically connected to the collector layer and the cathode layer. The FS layer is formed apart from the collector layer and the cathode layer, and the current is cut off from the state in which the forward current is flowing through the FWD element to enter the recovery state. At this time, a part of the first carrier in the FWD element flows to the collector layer, so that an amount of the second carrier for reducing the surge peak voltage is injected from the second electrode to the drift layer through the collector layer. Is the way to, the cathode layer, at a position remote from the collector layer to form a second conductivity type carrier injection layer that are connected to the second electrode and the electrically (24).

Claims

In a semiconductor device in which an IGBT region (1) having an IGBT element (1a) and an FWD region (2) having an FWD element (2a) are formed on a common semiconductor substrate (10),
A first conductivity type drift layer (11);
A second conductivity type base layer (12) formed on the drift layer;
A first conductivity type emitter region (16), which is a surface layer portion of the base layer, formed at a position away from the drift layer with the base layer interposed therebetween, and having a higher impurity concentration than the drift layer;
A second conductivity type collector layer (20) formed in the IGBT region on the opposite side of the base layer across the drift layer;
A cathode layer (21) of the first conductivity type formed on the FWD region on the opposite side of the drift layer and adjacent to the collector layer;
The semiconductor substrate comprising the base layer and a field stop layer (22) formed between the collector layer and the cathode layer;
A gate insulating film (14) disposed on a surface of the base layer located between the emitter region and the drift layer;
A gate electrode (15) disposed on the gate insulating film;
A first electrode (18) electrically connected to the base layer and the emitter region;
A second electrode (23) electrically connected to the collector layer and the cathode layer,
The field stop layer is formed away from the collector layer and the cathode layer;
When a forward current flows through the FWD element, the current is cut off and a recovery state is established, so that a part of the first carrier in the FWD element flows to the collector layer, thereby causing a surge peak voltage. Of the second carrier is injected from the second electrode into the drift layer through the collector layer ,
A semiconductor device in which a second conductivity type carrier injection layer (24) electrically connected to the second electrode is formed in the cathode layer at a position away from the collector layer .

The field stop layer is formed at a position where a ratio of a distance (L2) between the field stop layer, the collector layer, and the cathode layer to a thickness (L1) of the semiconductor substrate is less than 21.5%. The semiconductor device according to claim 1.

The field stop layer is formed at a position where a ratio of a distance (L2) between the field stop layer, the collector layer, and the cathode layer to a thickness (L1) of the semiconductor substrate is 2 to 21%. Item 14. The semiconductor device according to Item 1.

The semiconductor device according to claim 1, wherein a plurality of the carrier injection layers are formed.