JP2018523235A5 - - Google Patents

Download PDF

Info

Publication number
JP2018523235A5
JP2018523235A5 JP2018502709A JP2018502709A JP2018523235A5 JP 2018523235 A5 JP2018523235 A5 JP 2018523235A5 JP 2018502709 A JP2018502709 A JP 2018502709A JP 2018502709 A JP2018502709 A JP 2018502709A JP 2018523235 A5 JP2018523235 A5 JP 2018523235A5
Authority
JP
Japan
Prior art keywords
memory
barrier operation
load
executing
data memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2018502709A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018523235A (ja
JP6739513B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2015/041322 external-priority patent/WO2017014752A1/en
Publication of JP2018523235A publication Critical patent/JP2018523235A/ja
Publication of JP2018523235A5 publication Critical patent/JP2018523235A5/ja
Application granted granted Critical
Publication of JP6739513B2 publication Critical patent/JP6739513B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2018502709A 2015-07-21 2015-07-21 Ｄｍｂ操作を伴うロード／ストア操作を使用するロード獲得／ストア解放命令の実装 Active JP6739513B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/041322 WO2017014752A1 (en) 2015-07-21 2015-07-21 Implementation of load acquire/store release instructions using load/store operation with dmb operation

Publications (3)

Publication Number Publication Date
JP2018523235A JP2018523235A (ja) 2018-08-16
JP2018523235A5 true JP2018523235A5 (zh) 2018-11-15
JP6739513B2 JP6739513B2 (ja) 2020-08-12

Family

ID=57835180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018502709A Active JP6739513B2 (ja) 2015-07-21 2015-07-21 Ｄｍｂ操作を伴うロード／ストア操作を使用するロード獲得／ストア解放命令の実装

Country Status (4)

Country Link
EP (1) EP3326059A4 (zh)
JP (1) JP6739513B2 (zh)
CN (2) CN108139903B (zh)
WO (1) WO2017014752A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10606590B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Effective address based load store unit in out of order processors
US10394558B2 (en) 2017-10-06 2019-08-27 International Business Machines Corporation Executing load-store operations without address translation hardware per load-store unit port
US10606591B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10417002B2 (en) 2017-10-06 2019-09-17 International Business Machines Corporation Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
US10572256B2 (en) 2017-10-06 2020-02-25 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US11175924B2 (en) 2017-10-06 2021-11-16 International Business Machines Corporation Load-store unit with partitioned reorder queues with single cam port

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07302200A (ja) * 1994-04-28 1995-11-14 Hewlett Packard Co <Hp> 順次付けロード動作および順序付け記憶動作を強制する命令を有するコンピュータのロード命令方法。
JP2000181891A (ja) * 1998-12-18 2000-06-30 Hitachi Ltd 共有メモリアクセス順序保証方式
US7552317B2 (en) * 2004-05-04 2009-06-23 Sun Microsystems, Inc. Methods and systems for grouping instructions using memory barrier instructions
WO2005121948A1 (en) * 2004-06-02 2005-12-22 Sun Microsystems, Inc. Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor
US7725618B2 (en) * 2004-07-29 2010-05-25 International Business Machines Corporation Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
US8060482B2 (en) * 2006-12-28 2011-11-15 Intel Corporation Efficient and consistent software transactional memory
EP2203828A1 (en) * 2007-10-18 2010-07-07 Nxp B.V. Data processing system with a plurality of processors, cache circuits and a shared memory
GB2461716A (en) * 2008-07-09 2010-01-13 Advanced Risc Mach Ltd Monitoring circuitry for monitoring accesses to addressable locations in data processing apparatus that occur between the start and end events.
US8997103B2 (en) * 2009-09-25 2015-03-31 Nvidia Corporation N-way memory barrier operation coalescing
US8935513B2 (en) * 2012-02-08 2015-01-13 International Business Machines Corporation Processor performance improvement for instruction sequences that include barrier instructions
US9582276B2 (en) * 2012-09-27 2017-02-28 Apple Inc. Processor and method for implementing barrier operation using speculative and architectural color values
US9442755B2 (en) * 2013-03-15 2016-09-13 Nvidia Corporation System and method for hardware scheduling of indexed barriers
US9477599B2 (en) * 2013-08-07 2016-10-25 Advanced Micro Devices, Inc. Write combining cache microarchitecture for synchronization events

Similar Documents

Publication Publication Date Title
JP2018523235A5 (zh)
JP2017535854A5 (zh)
JP2016535373A5 (zh)
JP2015109059A5 (zh)
JP2014500544A5 (zh)
JP2015201216A5 (zh)
JP2015531935A5 (zh)
JP2017516228A5 (zh)
JP2010127719A5 (zh)
JP2016515265A5 (zh)
JP2011054161A5 (zh)
RU2015142983A (ru) Принудительное создание события элемента управления
JP2017528028A5 (zh)
JP2018528515A5 (zh)
JP2014523046A5 (zh)
JP2012224024A5 (zh)
JP2016511470A5 (zh)
JP2015519654A5 (zh)
JP6739513B2 (ja) Ｄｍｂ操作を伴うロード／ストア操作を使用するロード獲得／ストア解放命令の実装
JP2016505972A5 (zh)
JP2017039057A5 (zh)
JP2018502425A5 (zh)
JP2016189201A5 (zh)
EP2863329A8 (en) Establishing physical locality between secure execution environments
JP2015072542A5 (zh)