EP3326059A4 - IMPLEMENTATION OF LOAD / STORAGE RELOCATION INSTRUCTIONS ON THE BASIS OF LOAD / STORE OPERATION WITH DMB OPERATION - Google Patents
IMPLEMENTATION OF LOAD / STORAGE RELOCATION INSTRUCTIONS ON THE BASIS OF LOAD / STORE OPERATION WITH DMB OPERATION Download PDFInfo
- Publication number
- EP3326059A4 EP3326059A4 EP15899072.1A EP15899072A EP3326059A4 EP 3326059 A4 EP3326059 A4 EP 3326059A4 EP 15899072 A EP15899072 A EP 15899072A EP 3326059 A4 EP3326059 A4 EP 3326059A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- load
- store
- implementation
- dmb
- acquire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
- Stored Programmes (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2015/041322 WO2017014752A1 (en) | 2015-07-21 | 2015-07-21 | Implementation of load acquire/store release instructions using load/store operation with dmb operation |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3326059A1 EP3326059A1 (en) | 2018-05-30 |
EP3326059A4 true EP3326059A4 (en) | 2019-04-17 |
Family
ID=57835180
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP15899072.1A Pending EP3326059A4 (en) | 2015-07-21 | 2015-07-21 | IMPLEMENTATION OF LOAD / STORAGE RELOCATION INSTRUCTIONS ON THE BASIS OF LOAD / STORE OPERATION WITH DMB OPERATION |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP3326059A4 (zh) |
JP (1) | JP6739513B2 (zh) |
CN (2) | CN108139903B (zh) |
WO (1) | WO2017014752A1 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10606590B2 (en) | 2017-10-06 | 2020-03-31 | International Business Machines Corporation | Effective address based load store unit in out of order processors |
US10394558B2 (en) | 2017-10-06 | 2019-08-27 | International Business Machines Corporation | Executing load-store operations without address translation hardware per load-store unit port |
US10606591B2 (en) | 2017-10-06 | 2020-03-31 | International Business Machines Corporation | Handling effective address synonyms in a load-store unit that operates without address translation |
US10417002B2 (en) | 2017-10-06 | 2019-09-17 | International Business Machines Corporation | Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses |
US10572256B2 (en) | 2017-10-06 | 2020-02-25 | International Business Machines Corporation | Handling effective address synonyms in a load-store unit that operates without address translation |
US11175924B2 (en) | 2017-10-06 | 2021-11-16 | International Business Machines Corporation | Load-store unit with partitioned reorder queues with single cam port |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0679993A2 (en) * | 1994-04-28 | 1995-11-02 | Hewlett-Packard Company | A computer apparatus having special instructions to force ordered load and store operations |
US20050273583A1 (en) * | 2004-06-02 | 2005-12-08 | Paul Caprioli | Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor |
US20080163220A1 (en) * | 2006-12-28 | 2008-07-03 | Cheng Wang | Efficient and consistent software transactional memory |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000181891A (ja) * | 1998-12-18 | 2000-06-30 | Hitachi Ltd | 共有メモリアクセス順序保証方式 |
US7552317B2 (en) * | 2004-05-04 | 2009-06-23 | Sun Microsystems, Inc. | Methods and systems for grouping instructions using memory barrier instructions |
US7725618B2 (en) * | 2004-07-29 | 2010-05-25 | International Business Machines Corporation | Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment |
EP2203828A1 (en) * | 2007-10-18 | 2010-07-07 | Nxp B.V. | Data processing system with a plurality of processors, cache circuits and a shared memory |
GB2461716A (en) * | 2008-07-09 | 2010-01-13 | Advanced Risc Mach Ltd | Monitoring circuitry for monitoring accesses to addressable locations in data processing apparatus that occur between the start and end events. |
US8997103B2 (en) * | 2009-09-25 | 2015-03-31 | Nvidia Corporation | N-way memory barrier operation coalescing |
US8935513B2 (en) * | 2012-02-08 | 2015-01-13 | International Business Machines Corporation | Processor performance improvement for instruction sequences that include barrier instructions |
US9582276B2 (en) * | 2012-09-27 | 2017-02-28 | Apple Inc. | Processor and method for implementing barrier operation using speculative and architectural color values |
US9442755B2 (en) * | 2013-03-15 | 2016-09-13 | Nvidia Corporation | System and method for hardware scheduling of indexed barriers |
US9477599B2 (en) * | 2013-08-07 | 2016-10-25 | Advanced Micro Devices, Inc. | Write combining cache microarchitecture for synchronization events |
-
2015
- 2015-07-21 CN CN201580082189.6A patent/CN108139903B/zh not_active Expired - Fee Related
- 2015-07-21 CN CN201910999320.5A patent/CN110795150A/zh active Pending
- 2015-07-21 WO PCT/US2015/041322 patent/WO2017014752A1/en unknown
- 2015-07-21 JP JP2018502709A patent/JP6739513B2/ja active Active
- 2015-07-21 EP EP15899072.1A patent/EP3326059A4/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0679993A2 (en) * | 1994-04-28 | 1995-11-02 | Hewlett-Packard Company | A computer apparatus having special instructions to force ordered load and store operations |
US20050273583A1 (en) * | 2004-06-02 | 2005-12-08 | Paul Caprioli | Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor |
US20080163220A1 (en) * | 2006-12-28 | 2008-07-03 | Cheng Wang | Efficient and consistent software transactional memory |
Non-Patent Citations (1)
Title |
---|
See also references of WO2017014752A1 * |
Also Published As
Publication number | Publication date |
---|---|
EP3326059A1 (en) | 2018-05-30 |
JP2018523235A (ja) | 2018-08-16 |
CN108139903B (zh) | 2019-11-15 |
CN110795150A (zh) | 2020-02-14 |
WO2017014752A1 (en) | 2017-01-26 |
CN108139903A (zh) | 2018-06-08 |
JP6739513B2 (ja) | 2020-08-12 |
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Legal Events
Date | Code | Title | Description |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
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17P | Request for examination filed |
Effective date: 20180119 |
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AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
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AX | Request for extension of the european patent |
Extension state: BA ME |
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RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: AMPERE COMPUTING LLC |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: AMPERE COMPUTING LLC |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 20190318 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: G06F 9/30 20180101AFI20190312BHEP |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: EXAMINATION IS IN PROGRESS |
|
17Q | First examination report despatched |
Effective date: 20200713 |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: EXAMINATION IS IN PROGRESS |