JP2018519570A5 - - Google Patents
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- Publication number
- JP2018519570A5 JP2018519570A5 JP2017559370A JP2017559370A JP2018519570A5 JP 2018519570 A5 JP2018519570 A5 JP 2018519570A5 JP 2017559370 A JP2017559370 A JP 2017559370A JP 2017559370 A JP2017559370 A JP 2017559370A JP 2018519570 A5 JP2018519570 A5 JP 2018519570A5
- Authority
- JP
- Japan
- Prior art keywords
- tag
- entry
- order bits
- memory
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000006835 compression Effects 0.000 claims 43
- 238000007906 compression Methods 0.000 claims 43
- 238000000034 method Methods 0.000 claims 8
- 230000004044 response Effects 0.000 claims 2
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/716,947 US9514061B1 (en) | 2015-05-20 | 2015-05-20 | Method and apparatus for cache tag compression |
| US14/716,947 | 2015-05-20 | ||
| PCT/US2016/026664 WO2016186747A1 (en) | 2015-05-20 | 2016-04-08 | Method and apparatus for cache tag compression |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2018519570A JP2018519570A (ja) | 2018-07-19 |
| JP2018519570A5 true JP2018519570A5 (enExample) | 2019-04-25 |
| JP6724043B2 JP6724043B2 (ja) | 2020-07-15 |
Family
ID=55755783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017559370A Active JP6724043B2 (ja) | 2015-05-20 | 2016-04-08 | キャッシュタグ圧縮のための方法および装置 |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US9514061B1 (enExample) |
| EP (1) | EP3298493B1 (enExample) |
| JP (1) | JP6724043B2 (enExample) |
| KR (1) | KR102138697B1 (enExample) |
| CN (1) | CN107735773B (enExample) |
| AU (1) | AU2016265131B2 (enExample) |
| ES (1) | ES2787002T3 (enExample) |
| HU (1) | HUE049200T2 (enExample) |
| TW (1) | TWI698745B (enExample) |
| WO (1) | WO2016186747A1 (enExample) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9996471B2 (en) * | 2016-06-28 | 2018-06-12 | Arm Limited | Cache with compressed data and tag |
| US10387305B2 (en) * | 2016-12-23 | 2019-08-20 | Intel Corporation | Techniques for compression memory coloring |
| US10061698B2 (en) * | 2017-01-31 | 2018-08-28 | Qualcomm Incorporated | Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur |
| US10254961B2 (en) | 2017-02-21 | 2019-04-09 | International Business Machines Corporation | Dynamic load based memory tag management |
| US10229061B2 (en) | 2017-07-14 | 2019-03-12 | International Business Machines Corporation | Method and arrangement for saving cache power |
| GB2566469B (en) * | 2017-09-13 | 2021-03-24 | Advanced Risc Mach Ltd | Cache line statuses |
| US10831669B2 (en) | 2018-12-03 | 2020-11-10 | International Business Machines Corporation | Systems, methods and computer program products using multi-tag storage for efficient data compression in caches |
| US11720495B2 (en) * | 2019-05-24 | 2023-08-08 | Texas Instmments Incorporated | Multi-level cache security |
| US10983915B2 (en) * | 2019-08-19 | 2021-04-20 | Advanced Micro Devices, Inc. | Flexible dictionary sharing for compressed caches |
| US11436144B2 (en) * | 2020-04-10 | 2022-09-06 | Micron Technology, Inc. | Cache memory addressing |
| CN114201265B (zh) * | 2021-12-10 | 2025-09-02 | 北京奕斯伟计算技术股份有限公司 | 支持物理地址大于虚拟地址的虚拟内存管理方法及装置 |
| KR102781288B1 (ko) * | 2022-05-11 | 2025-03-14 | 서울시립대학교 산학협력단 | 명령어를 처리하는 방법 및 이를 위한 프로세서 모듈 |
| KR20250064407A (ko) | 2023-11-02 | 2025-05-09 | 대한민국(방위사업청장) | 안보심리지수 생성방법 및 그 시스템 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9226660D0 (en) * | 1992-12-22 | 1993-02-17 | Assersohn Roy J B | Database system |
| JPH086857A (ja) * | 1994-06-17 | 1996-01-12 | Mitsubishi Electric Corp | キャッシュメモリ |
| US6122709A (en) * | 1997-12-19 | 2000-09-19 | Sun Microsystems, Inc. | Cache with reduced tag information storage |
| US6795897B2 (en) | 2002-05-15 | 2004-09-21 | International Business Machines Corporation | Selective memory controller access path for directory caching |
| US7162669B2 (en) | 2003-06-10 | 2007-01-09 | Hewlett-Packard Development Company, L.P. | Apparatus and method for compressing redundancy information for embedded memories, including cache memories, of integrated circuits |
| US7512750B2 (en) | 2003-12-31 | 2009-03-31 | Intel Corporation | Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information |
| US7277988B2 (en) * | 2004-10-29 | 2007-10-02 | International Business Machines Corporation | System, method and storage medium for providing data caching and data compression in a memory subsystem |
| US8806101B2 (en) * | 2008-12-30 | 2014-08-12 | Intel Corporation | Metaphysical address space for holding lossy metadata in hardware |
| US8627041B2 (en) | 2009-10-09 | 2014-01-07 | Nvidia Corporation | Efficient line and page organization for compression status bit caching |
| US8904111B2 (en) * | 2009-10-20 | 2014-12-02 | The University Of Electro-Communications | Cache memory with CAM and SRAM sub-tags and generation control |
| JP2012003314A (ja) * | 2010-06-14 | 2012-01-05 | Renesas Electronics Corp | キャッシュメモリ装置 |
| US8838897B2 (en) * | 2011-06-29 | 2014-09-16 | New Jersey Institute Of Technology | Replicating tag entries for reliability enhancement in cache tag arrays |
| US9112537B2 (en) * | 2011-12-22 | 2015-08-18 | Intel Corporation | Content-aware caches for reliability |
| US9348762B2 (en) * | 2012-12-19 | 2016-05-24 | Nvidia Corporation | Technique for accessing content-addressable memory |
| US9396122B2 (en) * | 2013-04-19 | 2016-07-19 | Apple Inc. | Cache allocation scheme optimized for browsing applications |
| US9183155B2 (en) * | 2013-09-26 | 2015-11-10 | Andes Technology Corporation | Microprocessor and method for using an instruction loop cache thereof |
| TWI514145B (zh) * | 2013-10-21 | 2015-12-21 | Univ Nat Sun Yat Sen | 可儲存除錯資料的處理器、其快取及控制方法 |
-
2015
- 2015-05-20 US US14/716,947 patent/US9514061B1/en active Active
-
2016
- 2016-04-08 JP JP2017559370A patent/JP6724043B2/ja active Active
- 2016-04-08 AU AU2016265131A patent/AU2016265131B2/en active Active
- 2016-04-08 CN CN201680026963.6A patent/CN107735773B/zh active Active
- 2016-04-08 EP EP16717073.7A patent/EP3298493B1/en active Active
- 2016-04-08 KR KR1020177033433A patent/KR102138697B1/ko active Active
- 2016-04-08 HU HUE16717073A patent/HUE049200T2/hu unknown
- 2016-04-08 ES ES16717073T patent/ES2787002T3/es active Active
- 2016-04-08 WO PCT/US2016/026664 patent/WO2016186747A1/en not_active Ceased
- 2016-04-19 TW TW105112179A patent/TWI698745B/zh active
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