CN107735773B - 用于高速缓冲存储标签压缩的方法及设备 - Google Patents

用于高速缓冲存储标签压缩的方法及设备 Download PDF

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CN107735773B
CN107735773B CN201680026963.6A CN201680026963A CN107735773B CN 107735773 B CN107735773 B CN 107735773B CN 201680026963 A CN201680026963 A CN 201680026963A CN 107735773 B CN107735773 B CN 107735773B
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tag
entry
array
index value
memory
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CN107735773A (zh
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亨利·阿瑟·佩尔兰三世
托马斯·菲利普·施派尔
托马斯·安德鲁·萨托里乌斯
迈克尔·威廉·莫罗
詹姆斯·诺里斯·迪芬德尔费尔
肯尼思·艾伦·多克瑟尔
迈克尔·斯科特·麦克勒瓦伊内
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6032—Way prediction in set-associative cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201680026963.6A 2015-05-20 2016-04-08 用于高速缓冲存储标签压缩的方法及设备 Active CN107735773B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/716,947 US9514061B1 (en) 2015-05-20 2015-05-20 Method and apparatus for cache tag compression
US14/716,947 2015-05-20
PCT/US2016/026664 WO2016186747A1 (en) 2015-05-20 2016-04-08 Method and apparatus for cache tag compression

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CN107735773A CN107735773A (zh) 2018-02-23
CN107735773B true CN107735773B (zh) 2021-02-05

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US (1) US9514061B1 (enExample)
EP (1) EP3298493B1 (enExample)
JP (1) JP6724043B2 (enExample)
KR (1) KR102138697B1 (enExample)
CN (1) CN107735773B (enExample)
AU (1) AU2016265131B2 (enExample)
ES (1) ES2787002T3 (enExample)
HU (1) HUE049200T2 (enExample)
TW (1) TWI698745B (enExample)
WO (1) WO2016186747A1 (enExample)

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US9996471B2 (en) * 2016-06-28 2018-06-12 Arm Limited Cache with compressed data and tag
US10387305B2 (en) * 2016-12-23 2019-08-20 Intel Corporation Techniques for compression memory coloring
US10061698B2 (en) * 2017-01-31 2018-08-28 Qualcomm Incorporated Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur
US10254961B2 (en) 2017-02-21 2019-04-09 International Business Machines Corporation Dynamic load based memory tag management
US10229061B2 (en) 2017-07-14 2019-03-12 International Business Machines Corporation Method and arrangement for saving cache power
GB2566469B (en) * 2017-09-13 2021-03-24 Advanced Risc Mach Ltd Cache line statuses
US10831669B2 (en) 2018-12-03 2020-11-10 International Business Machines Corporation Systems, methods and computer program products using multi-tag storage for efficient data compression in caches
US11720495B2 (en) * 2019-05-24 2023-08-08 Texas Instmments Incorporated Multi-level cache security
US10983915B2 (en) * 2019-08-19 2021-04-20 Advanced Micro Devices, Inc. Flexible dictionary sharing for compressed caches
US11436144B2 (en) * 2020-04-10 2022-09-06 Micron Technology, Inc. Cache memory addressing
CN114201265B (zh) * 2021-12-10 2025-09-02 北京奕斯伟计算技术股份有限公司 支持物理地址大于虚拟地址的虚拟内存管理方法及装置
KR102781288B1 (ko) * 2022-05-11 2025-03-14 서울시립대학교 산학협력단 명령어를 처리하는 방법 및 이를 위한 프로세서 모듈
KR20250064407A (ko) 2023-11-02 2025-05-09 대한민국(방위사업청장) 안보심리지수 생성방법 및 그 시스템

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CN101770429A (zh) * 2008-12-30 2010-07-07 英特尔公司 用于在硬件中保存有损失的元数据的元物理地址空间
CN103885893A (zh) * 2012-12-19 2014-06-25 辉达公司 用于访问内容寻址存储器的技术

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US6122709A (en) * 1997-12-19 2000-09-19 Sun Microsystems, Inc. Cache with reduced tag information storage
US6795897B2 (en) 2002-05-15 2004-09-21 International Business Machines Corporation Selective memory controller access path for directory caching
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US8904111B2 (en) * 2009-10-20 2014-12-02 The University Of Electro-Communications Cache memory with CAM and SRAM sub-tags and generation control
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US7480759B2 (en) * 2004-10-29 2009-01-20 International Business Machines Corporation System, method and storage medium for providing data caching and data compression in a memory subsystem
CN101770429A (zh) * 2008-12-30 2010-07-07 英特尔公司 用于在硬件中保存有损失的元数据的元物理地址空间
CN103885893A (zh) * 2012-12-19 2014-06-25 辉达公司 用于访问内容寻址存储器的技术

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Publication number Publication date
TWI698745B (zh) 2020-07-11
JP2018519570A (ja) 2018-07-19
KR102138697B1 (ko) 2020-07-28
CN107735773A (zh) 2018-02-23
BR112017024623A2 (pt) 2018-07-31
US9514061B1 (en) 2016-12-06
JP6724043B2 (ja) 2020-07-15
HUE049200T2 (hu) 2020-09-28
TW201706853A (zh) 2017-02-16
WO2016186747A1 (en) 2016-11-24
AU2016265131A1 (en) 2017-11-02
EP3298493A1 (en) 2018-03-28
EP3298493B1 (en) 2020-02-12
AU2016265131B2 (en) 2020-09-10
KR20180008507A (ko) 2018-01-24
US20160342530A1 (en) 2016-11-24
ES2787002T3 (es) 2020-10-14

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