JP2018518765A - Independent UART BRK detection - Google Patents

Abstract

A universal asynchronous receiver / transmitter (UART) module is disclosed. The UART module may include a receiver unit that is clocked by a programmable receiver clock configured to sample the incoming data signal and comprises a counter clocked by the receiver clock, the counter being reset, Counting starts on every falling edge of the data signal and triggers the BRK detection signal when the counter reaches a programmable threshold.

Description

(Cross-reference to related applications)
This application claims priority to US Provisional Patent Application No. 62 / 183,006, filed June 22, 2015. The above references are hereby incorporated by reference herein for all purposes.

(Technical field)
The present disclosure relates to serial interfaces, and more particularly to universal asynchronous receiver / transmitter (UART) interfaces with BRK detection.

(background)
UART is well known and commonly used in microcontrollers to provide a communication channel. The UART interface converts parallel data into a serial transmission form. Various types of protocols exist and are used in UART communication as defined by various communication standards such as EIA, RS-232, RS-422, or RS-485. Other protocols such as the LIN protocol also use the same interface configuration as the RS-232 interface.

(wrap up)
There is a need to provide a UART that allows automatic detection of the BRK regardless of when the BRK is received.

  A universal asynchronous receiver / transmitter (UART) module is disclosed. The UART module may include a receiver unit that is clocked by a programmable receiver clock configured to sample the incoming data signal and comprises a counter clocked by the receiver clock, the counter being reset, Counting starts on every falling edge of the data signal and triggers the BRK detection signal when the counter reaches a programmable threshold.

  In various embodiments, a universal asynchronous receiver / transmitter (UART) module is disclosed. The module may include a receiver unit that is clocked by a programmable receiver clock configured to sample the incoming data signal and comprises a counter clocked by the receiver clock, the counter being reset to the data Counting starts on every falling edge of the signal and triggers the BRK detection signal if the counter reaches a programmable threshold.

  In some embodiments, the programmable receiver clock may be coupled to a baud rate generator. In some embodiments, the counter stops counting on the rising edge of the data signal. In the same or an alternative embodiment, the threshold can be programmed to be 11.

  In some embodiments, the receiver unit may include a state machine for controlling the counter. In such an embodiment, the state machine is programmable to operate in different modes of operation. In such embodiments, the interface may also include a first in first out buffer memory that receives a plurality of sampled data.

  In various embodiments, a microprocessor is disclosed. The microprocessor is a universal asynchronous receiver / transmitter (UART) including a receiver unit that is clocked by a programmable receiver clock configured to sample an incoming data signal and includes a counter clocked by the receiver clock. The counter may be reset to start counting on each falling edge of the data signal and trigger the BRK detection signal if the counter reaches a programmable threshold.

  In some embodiments, the programmable receiver clock may be coupled to a baud rate generator. In some embodiments, the counter stops counting on the rising edge of the data signal. In the same or an alternative embodiment, the threshold can be programmed to be 11.

  In some embodiments, the receiver unit may include a state machine for controlling the counter. In such an embodiment, the state machine is programmable to operate in different modes of operation. In such embodiments, the interface may also include a first in first out buffer memory that receives a plurality of sampled data.

  In various embodiments, a method for controlling a universal asynchronous receiver / transmitter (UART) module is disclosed. The method includes clocking a receiver unit with a programmable receiver clock configured to sample an incoming data signal and resetting a counter clocked by the programmable receiver clock, Resetting and starting counting on each falling edge of the data signal, and triggering the BRK detection signal when the counter reaches a programmable threshold.

FIG. 1 illustrates a BRK received by a UART at the start of a byte, according to an embodiment of the present disclosure. FIG. 2 illustrates a BRK received by a UART in the middle of a byte, according to an embodiment of the present disclosure. FIG. 3 illustrates an exemplary known transmitter module of a known universal asynchronous receiver transmitter as implemented in a known microcontroller. FIG. 4 illustrates an exemplary known receiver module of a known universal asynchronous receiver transmitter as implemented in a known microcontroller. FIG. 5 illustrates a receiver unit or any other similar serial interface unit for a UART operable to provide an automatic BRK detector according to an embodiment of the present disclosure.

(Detailed explanation)
Some legacy UARTs used by many microcontrollers do not have special logic to detect break ("BRK") characters. In some embodiments, the BRK is an 8-bit zero with a framing error. FIG. 1 illustrates a BRK 102 received by a UART at the start of a byte 104 according to an embodiment of the present disclosure. The receive line (eg, “RXS”) may go low, after which the start bit stays low for 11 clock cycles, indicating BRK. Typically, the receiver will begin its receive decoding, which will cause an error after 8 clocks (eg, FERIF_qclk) and a stop bit clock. Conventional receivers may be undetectable except for such errors. In contrast, expansion systems according to various embodiments can automatically detect such BRK. Due to the fact that the BRK is of a predetermined length (eg, 11 clocks), the BRK detector counter (described in more detail below with reference to FIG. 5) detects this BRK signal and individually Detection signals can be generated. The counter can start on the falling edge of the receive line and stop on the next rising edge. If the counter reaches a predetermined number of BRKs, BRK is detected.

  In some known systems, if a UART receives a BRK in the middle of a byte, the UART may not recognize the BRK. FIG. 2 illustrates a BRK 202 received by a UART in the middle of a byte 204, according to an embodiment of the present disclosure. This may not be an ideal operation for protocols such as Local Interconnect Network (LIN). According to various embodiments, a UART module may include a hardware counter in its receiver unit that signals a BRK whenever it occurs. According to various embodiments, a hardware counter is provided in the interface that counts low periods. Whenever the receive (“RX”) line goes low, the counter starts counting. Depending on the serial data transmitted, the BRK detector counter may be set and reset at various times until the BRK signal starts. A short stop caused by serial data will not trigger any detection. However, the BRK signal in the intermediate byte transmission can be easily detected by a counter and a separate detection signal can be generated.

  FIG. 3 illustrates an exemplary known transmitter module of a known universal asynchronous receiver transmitter as implemented in a known microcontroller. FIG. 4 illustrates an exemplary known receiver module of a known universal asynchronous receiver transmitter as implemented in a known microcontroller. The UART module is a serial I / O communication peripheral device. It contains all the clock generators, shift registers, and data buffers necessary to perform input or output serial data transfers independent of device program execution. UART, also known as Serial Communication Interface (SCI), can be configured as a full duplex asynchronous system. Full duplex mode is useful for communication with peripheral device systems such as CRT terminals and personal computers.

  In various embodiments, the UART module illustrated in FIGS. 3-4 may include, among other things, the following capabilities: full duplex asynchronous transmission and reception, 2 character input buffer, 1 character output buffer, programmable 8 bit or 9 bit It may include character length, address detection in 9-bit mode, input buffer overrun error detection, received character framing error detection, sleep operation, and the like.

  In various embodiments, the UART module implements the following additional features and is more suitable for use in a local interconnect network ("LIN") bus system: baud rate automatic detection and calibration, upon break reception Wake-up, 13-bit break character transmission. During sleep mode, all clocks for UART are suspended. For this reason, the baud rate generator is inactive and proper character reception cannot be performed. The automatic wakeup feature allows the controller to wake up due to the receive / data transmission ("RX / DT") line. In some embodiments, this feature may be available only in asynchronous mode. The auto wakeup feature may be enabled by configuring certain memory portions of the UART. For example, the auto wakeup feature may be enabled by setting the wakeup enable (“WUE”) bit in the BAUDCON register. Once set, the normal receive sequence on RX / DT may be disabled and the extended universal synchronous / asynchronous receiver / transmitter (“EUSART”) remains idle and independent of CPU mode. Thus, a wake-up event may be monitored. A wake-up event may consist, for example, of a high / low transition on the RX / DT line. (This coincides with the start of a synchronous break or wake-up signal character for the LIN protocol.) The EUSART module may generate a receive interrupt flag (eg, an RCIF interrupt) that matches the wake-up event. In normal CPU operation, the interrupt may be generated asynchronously in synchronism with the Q clock when the device is in the sleep mode. The interrupt condition may be cleared by reading another memory portion of the UART (eg, the RCREG register). The WUE bit may be automatically cleared by a low / high transition on the RX line at the end of the break. This signals to the user that the break event has ended. At this point, the EUSART module may be in an idle mode that waits to receive the next character.

  The UART may transmit and receive data using a standard non-zero return (NRZ) format. NRZ is accompanied by two levels: a high voltage output (“VOH”) mark state representing “1” data bits and a low voltage output (“VOL”) space state representing “0” data bits. Implemented. NRZ refers to the fact that continuously transmitted data bits of the same value remain at the output level of that bit without returning to the neutral level between each bit transmission. The NRZ transmission port is idle in the mark state. Each character transmission consists of one start bit followed by 8 or 9 data bits, and is always terminated by one or more stop bits. The start bit is always a space, and the stop bit is always a mark. The most common data form is 8 bits. Each transmitted bit lasts for a period of 1 / (baud rate). An on-chip dedicated 8-bit / 16-bit baud rate generator is used to derive the standard baud rate frequency from the system oscillator. The UART may transmit and receive the least significant bit first. The UART transmitter and receiver are functionally independent but may share the same data format and baud rate. Parity may not be supported according to some embodiments, but may be implemented in software and stored as the ninth data bit.

  Asynchronous mode is typically used in certain embodiments that implement the RS-232 standard. Referring again to FIG. 4, in some embodiments, data is received on the RX / DT 402 pin, which may drive the data recovery block 404. In some embodiments, the data recovery block 404 may be a high speed shifter that operates at a rate higher than the baud rate (eg, 16 times the baud rate). In some embodiments, the receiver 400 may also include a serial receive shift register (“RSR”) 406. The RSR 406 may be a shifter that operates at or about that bit rate. As all 8 or 9 bits of a character are shifted in, they are immediately transferred to a first-in first-out (“FIFO”) memory 408. In some embodiments, memory 408 may be a two character FIFO. In some embodiments, FIFO buffering allows reception of the start of two full characters and a third character before the software has to start UART receiver servicing. The FIFO and RSR registers are not directly accessible by software, according to some embodiments. Access to the received data may be provided via the memory portion of the UART (eg, the RCREG register).

  FIG. 5 illustrates a receiver unit 500 or any other similar serial interface unit for a UART operable to provide an automatic BRK detector according to an embodiment of the present disclosure. In some embodiments, the receiver unit 500 may be clocked by a programmable receiver clock 504. In some embodiments, programmable receiver clock 504 may be clocked by baud rate generator 506. Programmable receiver clock 504 may be operable to sample incoming data signals (eg, data arriving at receiver pin 508).

  In some embodiments, the receiver unit 500 may include a counter that is clocked by the programmable receiver clock 504. The counter may be reset to start counting with a portion of the data signal and trigger the BRK detection signal if the counter reaches a programmable threshold. For example, as described in more detail above with reference to FIGS. 1-4, the BRK may include 11 clock cycles. Therefore, when the counter reaches 11, the BRK detection signal may be triggered.

  In some embodiments, the counter may include a configurable state machine 502 coupled to the BRK detector 504. In some embodiments, the configuration of state machine 502 may be controlled by configuration register signals (eg, MODE [3: 0]). For example, as shown in FIG. 5, the configuration register signal (MODE [3: 0]) may have 4 bits and allow various settings. Other registers may be used. In some embodiments, state machine 502 may be coupled with BRK detector 504. In various embodiments, the BRK detector 504 may be a counter that starts and stops on the incoming falling and rising edges of the received signal, respectively.

  In some embodiments, the counter may be further coupled to a memory buffer 508. For example, the counter may be coupled to a first-in first-out memory buffer, such as the exemplary buffer illustrated in FIG.

  According to various embodiments, a UART is described that enables automatic detection of a BRK regardless of when the BRK is received.

Claims (20)

Universal asynchronous receiver / transmitter (UART) module,
A receiver unit comprising a counter clocked by a programmable receiver clock configured to sample an incoming data signal and clocked by the receiver clock, the counter being reset and rising of the data signal; A UART module that starts counting on every falling edge and triggers a BRK detection signal when the counter reaches a programmable threshold.   The UART according to claim 1, wherein the counter stops counting on a rising edge of the data signal.   The UART of claim 1 or 2, wherein the threshold value can be programmed to be 11.   The UART according to one of the preceding claims, wherein the receiver unit comprises a state machine for controlling the counter.   The UART of claim 4, wherein the state machine is programmable to operate in different modes of operation.   The UART according to claim 4 or 5, further comprising a first in first out buffer memory for receiving a plurality of sampled data.   The UART of claim 1, wherein the programmable receiver clock is coupled to a baud rate generator. A microprocessor,
A universal asynchronous receiver / transmitter (UART) module comprising a receiver unit, clocked by a programmable receiver clock configured to sample an incoming data signal and comprising a counter clocked by the receiver clock The microprocessor is reset, starts counting on each falling edge of the data signal, and triggers a BRK detection signal when the counter reaches a programmable threshold.   The microprocessor of claim 8, wherein the counter stops counting on a rising edge of the data signal.   10. Microprocessor according to claim 8 or 9, wherein the threshold value can be programmed to be 11.   11. A microprocessor according to claim 8, 9 or 10, wherein the receiver unit comprises a state machine for controlling the counter.   The microprocessor of claim 11, wherein the state machine is programmable to operate in different modes of operation.   The microprocessor according to claim 11 or 12, further comprising a first in first out buffer memory for receiving a plurality of sampled data.   The microprocessor of any one of claims 8-13, wherein the programmable receiver clock is coupled to a baud rate generator. A method for controlling a universal asynchronous receiver / transmitter (UART) module, the method comprising:
Clocking the receiver unit with a programmable receiver clock configured to sample the incoming data signal;
Resetting a counter clocked by the programmable receiver clock, wherein the counter is reset and starts counting on each falling edge of the data signal;
Triggering a BRK detection signal when the counter reaches a programmable threshold.   The method of claim 15, wherein the counter stops counting on a rising edge of the data signal.   17. A method according to claim 15 or 16, wherein the threshold can be programmed to be 11.   18. A method according to one of claims 15-17, wherein the receiver unit comprises a state machine for controlling the counter.   The method of claim 18, wherein the state machine is programmable to operate in different modes of operation.   20. A method according to claim 18 or 19, further comprising transmitting a plurality of sampled data to a first in first out buffer memory.