JP2018206336A - Semiconductor device and memory module - Google Patents

Abstract

To detect failures of a circuit for executing processing of a memory address in a memory module and of wiring for transmitting the memory address.SOLUTION: A selection decoder 303 controls the levels of a plurality of selecting signals cen1-cenn based on at least one or more address bits. Memory modules 30-i(i=1 to N) are selected when the corresponding selecting signal ceni is at an activation level, so that data read and write are allowed. A failure determination section 304 determines whether the selection decoder 303 is in a failed state based on the levels of the plurality of selecting signals cen1-cenn.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a semiconductor device and a memory module, and can be suitably used for, for example, a semiconductor device incorporating a memory.

  2. Description of the Related Art Conventionally, a memory module that can detect an error in data in a memory and correct it to correct data is known.

  For example, in Patent Document 1, an ECC (Error Correction Code) encoding unit generates encoded data by adding an error correction code to write data to a memory, and the first error detection unit reads from the memory. It describes that error detection and correction processing is performed on data.

JP, 2006-663337, A

  In the device described in Patent Document 1, it is possible to detect a failure in a circuit that performs processing on data in a memory module and a wiring that transfers data.

  However, the apparatus described in Patent Document 1 has a problem that it cannot detect a failure in a circuit that executes processing for a memory address in a memory module and a wiring that transmits the memory address.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In one embodiment, the selection decoder controls the levels of a plurality of selection signals corresponding to the plurality of memory modules based on at least one address bit. The failure determination unit determines whether the selection decoder is in a failure state based on the levels of the plurality of selection signals.

  According to the semiconductor device of one embodiment, it is possible to detect a failure of a circuit that executes processing for a memory address in a memory module and a wiring that transmits the memory address.

It is a figure showing the structure of the semiconductor device of 1st Embodiment. 6 is a diagram illustrating a configuration of a semiconductor device of Reference Example 1. FIG. 7 is a diagram illustrating a configuration of a first memory module of Reference Example 1. FIG. It is a figure showing the structure of the semiconductor device of 2nd Embodiment. It is a figure showing the relationship between an input and an output in case a selection decoder is normal. 4 is a flowchart showing a failure determination procedure of a selection decoder 62. It is a figure showing the structure of the semiconductor device of 3rd Embodiment. It is a figure showing the structure of the semiconductor device of 4th Embodiment. It is a figure showing the structure of the semiconductor device of 5th Embodiment. It is a figure showing the structure of the semiconductor device of 6th Embodiment. It is a figure showing the structure of the semiconductor device of 7th Embodiment. It is a figure showing the structure of the data memorize | stored in the memory array of 7th Embodiment. It is a figure showing the structure of the semiconductor device of 8th Embodiment. It is a figure showing the structure of the data memorize | stored in the memory array of 8th Embodiment. 7 is a diagram illustrating a configuration of a semiconductor device of Reference Example 2. FIG. It is a figure showing the structure of the 1st memory module with an address output function. It is a figure showing the structure of the semiconductor device of 9th Embodiment. It is a figure showing the structure of the semiconductor device of 10th Embodiment. It is a figure showing the structure of the semiconductor device of 11th Embodiment. It is a flowchart showing the process sequence of CPU when a failure is notified. It is a figure showing the structure of the semiconductor device 1600 of 12th Embodiment. It is a figure showing the structure of the 1st memory module 281 with an address output function. It is a figure showing the layout of the 1st memory module 281 with an address output function. It is a figure showing the structure of the semiconductor device 1700 of 13th Embodiment. It is a figure showing the structure of the 1st memory module 381 with an address output function. It is a figure showing the structure of the semiconductor device 1800 of 14th Embodiment. It is a figure showing the structure of the 1st memory module 481 with an address output function.

  Hereinafter, embodiments will be described with reference to the drawings. In the drawings, components having the same reference numerals are the same components.

[First Embodiment]
FIG. 1 is a diagram illustrating a configuration of a semiconductor device 300 according to the first embodiment.

  Referring to FIG. 1, the semiconductor device includes N memory modules 30-1 to 30-N, a selection decoder 303, and a failure determination unit 304. N is a natural number of 2 or more.

  The selection decoder 303 controls the levels of the plurality of selection signals cen1 to cenn based on at least one address bit.

  The memory module 30-i (i = 1 to n) is selected when the corresponding selection signal ceni is at the activation level, and data can be read and written.

  The failure determination unit 304 determines whether or not the selection decoder 303 is in a failure state based on the levels of the plurality of selection signals cen1 to cen.

  For future automatic driving, in-vehicle semiconductors are required to have a function for improving safety. For example, a design based on the ISO 26262 (functional safety) standard is required. According to this standard, when a failure occurs assuming a random failure such as aging of hardware, it is required to correct or detect the failure and perform risk avoidance processing. Moreover, in a highly reliable product, an ECC function is often mounted on a memory that is susceptible to malfunction due to radiation (α rays and neutrons). Thereby, it is possible to correct or detect not only the destruction of retained data with respect to radiation but also a random failure with respect to data. On the other hand, there is a problem that it is impossible to detect a failure of a circuit that processes an address because it is a non-data signal that cannot be corrected and detected by ECC. According to the present embodiment, it is possible to detect a failure of the selection decoder 303 that processes an address designating which of a plurality of memory modules is selected.

[Semiconductor Device of Reference Example 1]
FIG. 2 is a diagram illustrating a configuration of the semiconductor device 400 according to the first reference example.

  Referring to FIG. 2, the semiconductor device 400 includes a first memory module 41, a second memory module 42, a flash memory 350, an ECC encoder 21, and redundancy control circuits 31 to 34. The semiconductor device 400 further includes a selector 51, an ECC decoder 22, an address divider 61, a selection decoder 62, a redundant decoder 68, an interrupt control unit 201, a CPU 202, and flip-flops (FF) 71 and 72. Is provided.

  The first memory module 41 and the second memory module 42 are, for example, SRAM (Static Random Access Memory) macros provided as libraries in the design environment of the semiconductor device. The first memory module 41 and the second memory module 42 can also be represented by the words “memory unit”, “memory block”, and “memory macro”, respectively.

  The first memory module 41 includes a memory array 43 having a plurality of SRAM memory cells and an SRAM logic circuit.

  Memory array 43 includes a regular block 363 and a redundant block 364. The normal block 363 includes a plurality of normal memory cell columns. The plurality of regular memory cell columns serve as data write locations unless they are defective. The redundant block 364 includes one or more redundant memory cell columns. One or more redundant memory cell columns are provided to relieve a defective memory cell column having a defective memory cell among a plurality of normal memory cell columns included in the normal block 363. One or more redundant memory cell columns serve as data write locations instead of defective memory cell columns.

  The second memory module 42 includes a memory array 44 having a plurality of SRAM memory cells and an SRAM logic circuit. Memory array 44 includes a regular block 365 and a redundant block 366. The regular block 365 is composed of a plurality of regular memory cell columns. The redundant block 366 includes one or more redundant memory cell columns.

  FIG. 3 is a diagram illustrating the configuration of the first memory module 41 of the first reference example. The configuration of the second memory module 42 is the same as this.

  Referring to FIG. 3, the first memory module 41 includes an address input terminal ADA, a clock input terminal CK, a data input / output terminal DA, a memory array MARY, a word line driving circuit WD, and a data input / output unit. IO and the control part CTRL are provided.

  A second address bit Add [0: N−1] sent from the address divider 61 is input to the address input terminal ADA. The clock CLK is input to the clock input terminal CK. A data signal D1 [0: M] is input / output to / from the data input / output terminal DA.

  The memory array MARY has a plurality of memory cells selected by the word lines WL0 to WLi.

  The control unit CTRL includes a temporary storage circuit 650 including latch circuits 1_0 to 1_N−1 and an address decoder ADRCTL. The latch circuits 1_0 to 1_N-1 take in the address bits Add [0] to Add [N-1] in synchronization with the clock CLK and output them as internal address bits AQ1 [0] to AQ1 [N-1]. The latch circuits 1_0 to 1_N-1 continue to hold the fetched address bits Add [0] to Add [N-1] until the edge of the clock CLK is input. The address decoder ADRCTL outputs address decode signals (X0 to Xi and Y0 to Yj) based on the internal address bits AQ1 [0] to AQ1 [N-1].

  The word line driving circuit WD selects and drives the corresponding word line WL of the memory array MARY based on the row selection signals X0 to Xi among the address decode signals.

  The data input / output unit IO outputs the data of the memory cell selected by the word line WL in the memory array MARY as the data signal D1 [0: M] through the data input / output terminal DA.

  The data input / output unit IO writes the data signal D1 [0: M] selected by the word line WL in the memory array MARY and input to the memory cell through the data input / output terminal DA.

  Referring to FIG. 2 again, the address divider 61 uses the (N + 1) -bit address signal A [0: N] output from the CPU 202 as the first address bit Add [N] (high order bit). ) And N second address bits Add [0: N−1] (lower first number of bits). The N second address bits Add [0: N−1] are supplied to the first memory module 41 and the second memory module 42. The address divider 61 includes a latch circuit that latches the first address bit Add [N] and the second address bit Add [0: N−1] for timing control.

  The ECC encoder 21 performs error correction detection encoding on the data signal Data [0: M], which is write data, and outputs the error correction detection encoded data to the first memory module 41 and the second memory module 42. . Specifically, the ECC encoder 21 generates s-bit check bits for error correction detection of the (M + 1) -bit data signal Data [0: M], and the (M + s + 1) -bit bits to which the check bits are added. The data signal EData [0: M + s] is generated as error detection / correction encoded data.

  The check bit is a code that can be corrected to X bits or less and can detect an error of Y bits (Y> X) or less. For example, the check bits can be SEC-DED (Single Error-Correcting Double-Error-Detecting) Code, that is, an error correction code that can correct a 1-bit error and detect a 2-bit error.

  The selection decoder 62 controls the level of the first selection signal cen1 and the level of the second selection signal cen2 based on the selection permission signal CEN and the first address bit Add [N]. The selection decoder 62 sets the level of the first selection signal cen1 to the activation level when the selection permission signal CEN is “1” of the activation level and the first address bit Add [N] is “1”. In addition to being set to “1”, the level of the second selection signal cen2 is set to the deactivation level “0”. The selection decoder 62 sets the level of the first selection signal cen1 to the inactivation level when the selection permission signal CEN is “1” of the activation level and the first address bit Add [N] is “0”. And the level of the second selection signal cen2 is set to the activation level “1”. The selection decoder 62 sets the level of the first selection signal cen1 to the deactivation level “0” and the second selection signal cen2 when the selection permission signal CEN is the deactivation level “0”. Set the level to the deactivation level “0”.

  The flash memory 350 stores an address signal C_Add1 indicating a defective memory cell column existing in the normal block 363 and an address indicating a defective memory cell column C_Add2 existing in the normal block 365.

  The redundant decoder 68 decodes the address signal C_Add1 of the defective memory cell column in the plurality of normal memory columns in the normal block 363, and outputs an address decode signal R1. The redundant decoder 68 decodes the address signal C_Add2 of the defective memory cell column in the plurality of normal memory columns in the normal block 365, and outputs an address decode signal R2.

  The redundancy control circuit 31 writes the output of the ECC encoder 21 to the redundant memory cell column in the redundant block 364 instead of the defective memory cell column in the normal block 363 according to the address decode signal R1 when writing data. Control. For example, when the redundant block 364 is arranged on the right side in the memory array 43 and the plurality of data input / output lines are connected to the plurality of bit lines of the normal memory cell column, the redundancy control circuit 31 writes the data In some cases, control is performed so that the data input / output line connected to the bit line of the defective memory cell column and the data input / output line arranged on the right side thereof are connected to the right bit line.

  The redundancy control circuit 32 writes the output of the ECC encoder 21 to the redundant memory cell column in the redundant block 366 instead of the defective memory cell column in the normal block 365 according to the address decode signal R2 when writing data. Control.

  In the first memory module 41, when data is written, when the first selection signal cen1 is “1”, an error is detected and corrected at a location specified by the second address bits Add [0: N−1]. When the encoded data Edata [0: M + s] is written and the first selection signal cen1 is “0”, the error detection / correction encoded data Data [0: M + s] is not written. In the second memory module 42, when data is written, when the second selection signal cen2 is “1”, an error is detected and corrected at a location specified by the second address bits Add [0: N−1]. When the encoded data Edata [0: M + s] is written and the second selection signal cen2 is “0”, the error detection / correction encoded data Edata [0: M + s] is not written.

  In the first memory module 41, when the data is read, when the first selection signal cen1 is “1”, the data is stored from the location specified by the second address bits Add [0: N−1]. The data signal Q1 is output. In the first memory module 41, when the data is read, the stored data signal Q1 is not output when the first selection signal cen1 is “0”. In the second memory module 42, when the second selection signal cen2 is “1”, the data is read from the location specified by the second address bits Add [0: N−1] when reading data. The data signal Q2 is output. In the second memory module 42, when the data is read, the stored data signal Q2 is not output when the second selection signal cen2 is “0”.

  The redundancy control circuit 33 controls to read data from the redundant memory cell column in the redundant block 364 instead of the defective memory cell column in the normal block 363 according to the address decode signal R1 when reading data. For example, when the redundant block 364 is arranged on the right side in the memory array 43 and a plurality of data input / output lines are connected to a plurality of bit lines of the normal memory cell column, the redundancy control circuit 33 reads the data. In some cases, control is performed so that the data input / output line connected to the bit line of the defective memory cell column and the data input / output line arranged on the right side thereof are connected to the right bit line.

  The redundancy control circuit 34 controls to read data from the redundant memory cell column in the redundant block 366 instead of the defective memory cell column in the normal block 365 in accordance with the address decode signal R2 when reading data.

  The selector 51 receives the data signal Q1 output from the first memory module 41 and the data output from the second memory module 42 based on the level of the first selection signal cen1 and the level of the second selection signal cen2. One of the signals Q2 is selected and output to the ECC decoder 22.

  The selector 51 starts from the first memory module 41 when the level of the first selection signal cen1 is “1” of the activation level and the level of the second selection signal cen2 is “0” of the inactivation level. The data signal Q1 to be output is selected and output to the ECC decoder 22. The selector 51 starts from the second memory module 42 when the level of the first selection signal cen1 is “0”, which is the inactivation level, and the level of the second selection signal cen2 is “1”, which is the activation level. The output data signal Q 2 is selected and output to the ECC decoder 22. When the level of the first selection signal cen1 is “0”, which is the deactivation level, and the level of the second selection signal cen2 is “0”, which is the deactivation level, the selector 51 The data signal Q1 output from the first memory module 42 and the data signal Q2 output from the second memory module 42 are selected and output. The selector 51 outputs from the first memory module 41 when the level of the first selection signal cen1 is “1” of the activation level and the level of the second selection signal cen2 is “1” of the activation level. The data signal Q1 to be output and the data signal Q2 output from the second memory module 42 are selected and output. Which one to select when cen1 = "1" and cen2 = "1" and cen1 = "0" and cen2 = "0" is the one that has been previously selected. It is possible to select one of them, or to select the one determined by the logic gate mapped by the logic design.

  The ECC decoder 22 detects and corrects the output of the selector 51. When the ECC decoder 22 detects an error in the output of the selector 51, it outputs a failure notification signal ERROR. When receiving the failure notification signal ERROR, the interrupt control unit 201 notifies the CPU 202 that the failure has been detected.

  The CPU 202 controls the entire semiconductor device. When the CPU 202 receives a failure interrupt notification from the interrupt control unit 201, the CPU 202 performs necessary processing.

  The FF 71 is provided in the transmission path of the first selection signal cen1 from the selection decoder 62 to the selector 51. The FF 72 is provided in the transmission path of the second selection signal cen2 from the selection decoder 62 to the selector 51. The clocks supplied to the FF 71, FF 72, the first memory module 41, and the second memory module 42 are the same.

  The FF 71 is provided to synchronize the timing when the first selection signal cen1 is sent to the selector 51 and the timing when the output Q1 from the first memory module 41 is sent to the selector 51. The FF 72 is provided to synchronize the timing at which the second selection signal cen2 is sent to the selector 51 and the timing at which the output Q2 from the second memory module 42 is sent to the selector 51. Such synchronous control is necessary because the first memory module 41 and the second memory module 42 require time for one cycle of the clock CLK for data output.

  In the semiconductor device 400 of the first reference example, a failure of the selection decoder 62 that processes the address signal Add [0: N] and a wiring related thereto, and a failure of the redundant decoder 68 that processes the address signals C_Add1 and C_Add2 and a wiring related thereto. There is a problem that cannot be detected.

[Second Embodiment]
FIG. 4 is a diagram illustrating the configuration of the semiconductor device 500 according to the second embodiment.

  The semiconductor device 500 includes a first memory module 45, a second memory module 46, an ECC encoder 21, a selector 51, an ECC decoder 22, an address divider 61, a selection decoder 62, and a failure determination unit. 121, an interrupt control unit 201, a CPU 202, and FFs 71 and 72.

  The ECC encoder 21, the address divider 61, the selection decoder 62, the ECC decoder 22, the FFs 71 and 72, the selector 51, the interrupt control unit 201, and the CPU 202 according to the second embodiment are the same as those in the reference example 1, and thus description thereof will not be repeated. .

  Similar to the first memory module 41 of the first reference example, the first memory module 45 includes a memory array having a plurality of SRAM memory cells and an SRAM logic circuit. The first memory module 45 does not have a redundant column repair function.

  Similar to the second memory module 42 of Reference Example 2, the second memory module 46 includes a memory array having a plurality of SRAM memory cells and an SRAM logic circuit. It is assumed that the second memory module 46 does not have a redundant column repair function.

  The failure determination unit 121 determines whether or not the selection decoder 62 is in failure based on the level of the first selection signal cen1, the level of the second selection signal cen2, and the level of the selection permission signal CEN. The failure determination unit 121 outputs a failure notification signal ERROR to the interrupt control unit 201 when the selection decoder 62 determines that there is a failure.

  FIG. 5 shows inputs (selection permission signal CEN, most significant bit Add [N] of the address signal) and outputs (first selection signal cen1, second selection signal cen2) when the selection decoder 62 is normal. FIG.

  When the selection decoder 62 is normal, when the level of the selection permission signal CEN is “1” of the activation level and the most significant bit Add [N] of the address signal is “1”, the first selection The level of the signal cen1 is set to the activation level “1”, and the level of the second selection signal cen2 is set to the deactivation level “0”. When the selection decoder 62 is normal, when the level of the selection permission signal CEN is “1” of the activation level and the most significant bit Add [N] of the address signal is “0”, the first selection The level of the signal cen1 is set to the deactivation level “0”, and the level of the second selection signal cen2 is set to the activation level “1”. When the selection decoder 62 is normal and the level of the selection permission signal CEN is “0”, the first selection signal cen1 is independent of the level of the first selection signal cen1 and the level of the second selection signal cen2. The level of cen1 is set to the deactivation level “0”, and the level of the second selection signal cen2 is set to the deactivation level “0”.

FIG. 6 is a flowchart showing a failure determination procedure of selection decoder 62.
Referring to FIG. 6, when the level of selection permission signal CEN is “1” in step S301 (YES), the process proceeds to step S302, and when the level of selection permission signal CEN is “0” (NO), The process proceeds to step S303.

  In step S302, when both the level of the first selection signal cen1 and the level of the second selection signal cen2 are “1” or “0” (YES), the process proceeds to step S305, and the first selection signal cen1. When one of the level of the second selection signal and the level of the second selection signal cen2 is “1” and the other is “0” (NO), the process proceeds to step S304.

  In step S303, when both the level of the first selection signal cen1 and the level of the second selection signal cen2 are “0” (YES), the process proceeds to step S304, and the level of the first selection signal cen1. When at least one of the levels of the second selection signal cen2 is “1” (NO), the process proceeds to step S305.

  In step S304, the failure determination unit 121 determines that the selection decoder 62 is in a normal state.

  In step S305, the failure determination unit 121 determines that the selection decoder 62 is in a failure state. The failure determination unit 121 outputs a failure notification signal ERROR to the interrupt control unit 201. When receiving the failure notification signal ERROR, the interrupt control unit 201 notifies the CPU 202 of the failure.

  In the above description, when the level of the selection permission signal CEN is “1”, the failure state of the selection decoder 62 is obtained only when only one of the first selection signal cen1 and the second selection signal cen2 is inverted. The reason is determined to detect a single failure having a high occurrence frequency.

  As described above, in the present embodiment, it is determined whether or not the selection decoder 62 is in failure based on the level of the first selection signal cen1, the level of the second selection signal cen2, and the level of the selection permission signal CEN. can do.

[Third Embodiment]
FIG. 7 is a diagram illustrating a configuration of a semiconductor device 600 according to the third embodiment.

  The semiconductor device 600 includes a first memory module 45, a second memory module 46, an ECC encoder 21, a selector 149, an ECC decoder 22, an address divider 61, a selection decoder 62, and a failure determination unit. 131, an interrupt control unit 201, a CPU 202, and FFs 71 and 72.

  The first memory module 45, the second memory module 46, the ECC encoder 21, the ECC decoder 22, the address divider 61, the selection decoder 62, the interrupt control unit 201, the CPU 202, and the FFs 71 and 72 of the third embodiment are Since it is the same as that of 2nd Embodiment, description is not repeated.

  The failure determination unit 131 determines whether or not the selection decoder 62 has a failure in the same manner as the failure determination unit 121 of the second embodiment. The failure determination unit 131 outputs a failure detection signal ER to the selector 149 when the selection decoder 62 determines that there is a failure.

  Upon receiving the failure detection signal ER, the selector 149 inverts the X bit among the plurality of bits of data output from the selected one of the first memory module 45 and the second memory module 46. The X bits exceed the upper limit of the number of bits that can be corrected by the ECC decoder 22 and are equal to or less than the upper limit of the number of bits that can be detected. The inspection bit is X = 2 in the case of SEC-DED Code.

  According to the present embodiment, it is possible to detect a failure of the selection decoder 62 that processes the address signal Add [0: N] and a wiring related thereto without providing a new circuit.

[Fourth Embodiment]
FIG. 8 is a diagram illustrating a configuration of a semiconductor device 700 according to the fourth embodiment.

  The semiconductor device 700 includes a first memory module 45, a second memory module 46, an ECC encoder 21, a selector 141, a selector 142, an ECC decoder 122, an address divider 61, and a selection decoder 62. , An interrupt control unit 201, a CPU 202, and FFs 73, 74, 75, and 76.

  Since the first memory module 45, the second memory module 46, the ECC encoder 21, the address divider 61, the selection decoder 62, the interrupt control unit 201, and the CPU 202 of the fourth embodiment are the same as those of the second embodiment. , I will not repeat the explanation.

  At the time of data reading, the plurality of bits constituting the data output from the first memory module 45 are divided into a plurality of bits Qa of group A (first group) and a plurality of bits Qb of group B (second group). being classified. The first memory module 45 outputs the group A multiple bits Qa to the selector 141 and the group B multiple bits Qb to the selector 142.

  At the time of data reading, the plurality of bits constituting the data output from the second memory module 46 are divided into a plurality of bits Qc of group C (first group) and a plurality of bits Qd of group D (second group). being classified. The second memory module 46 outputs the group C multiple bits Qc to the selector 141, and outputs the group D multiple bits Qd to the selector 142.

  The positions of the plurality of bits Qa of the group A and the positions of the plurality of bits Qc of the group C are the same. The positions of the plurality of bits Qb in the group B and the positions of the plurality of bits Qd in the group D are the same.

  For example, the group A multiple bits Qa are odd bits in the plurality of bits output from the first memory module 46, and the group B multiple bits Qb are in the plurality of bits output from the first memory module 46. Even bits. The plurality of bits Qc of group C are odd bits in the plurality of bits output from the second memory module 46, and the plurality of bits Qd of group D are odd numbers in the plurality of bits output from the second memory module 46. Can be a bit.

  Alternatively, the multiple bits Qa of the group A are the upper half bits on the MSB (Most Significant Bit) side among the multiple bits output from the first memory module 46, and the multiple bits Qb of the group B are the first memory The lower half bits on the LSB (Least Significant Bit) side of the plurality of bits output from the module 46 can be used. The multiple bits Qc of group C are the upper half bits on the MSB side of the multiple bits output from the second memory module 46, and the multiple bits Qd of group D are the multiple bits output from the second memory module 46. The lower half of the bits on the LSB side can be used.

  The selector 141 outputs a plurality of bits of the group A output from the first memory module 45 when the level of the first selection signal cen1 is “1” and the level of the second selection signal cen2 is “0”. Qa and a plurality of bits Qa of group A out of a plurality of bits Qc of group C output from second memory module 46 are selected and output to ECC decoder 22.

  The selector 141 is configured to output a plurality of bits of the group A output from the first memory module 45 when the level of the first selection signal cen1 is “0” and the level of the second selection signal cen2 is “1”. Among Qa and a plurality of bits Qc of the group C output from the second memory module 46, the plurality of bits Qc of the group C are selected and output to the ECC decoder 22.

  The selector 141 is configured to output a plurality of bits of the group A output from the first memory module 45 when the level of the first selection signal cen1 is “0” and the level of the second selection signal cen2 is “0”. Qa and any one of the plurality of bits Qc of the group C output from the second memory module 46 are output.

  The selector 141 outputs a plurality of bits of the group A output from the first memory module 45 when the level of the first selection signal cen1 is “1” and the level of the second selection signal cen2 is “1”. Qa and any one of the plurality of bits Qc of the group C output from the second memory module 46 are output.

  The selector 142 is configured to output the plurality of bits of the group B output from the first memory module 45 when the level of the first selection signal cen1 is “1” and the level of the second selection signal cen2 is “0”. Among the plurality of bits Qd of group D output from Qb and the second memory module 46, the plurality of bits Qb of group B are selected and output to the ECC decoder 22.

  The selector 142 is configured to output a plurality of bits of the group B output from the first memory module 45 when the level of the first selection signal cen1 is “0” and the level of the second selection signal cen2 is “1”. Of the plurality of bits Qd of group D output from Qb and the second memory module 46, the plurality of bits Qd of group D are selected and output to the ECC decoder 22.

  The selector 142 is configured to output a plurality of bits of the group B output from the first memory module 45 when the level of the first selection signal cen1 is “0” and the level of the second selection signal cen2 is “0”. Qb and any one of the plurality of bits Qd of the group D output from the second memory module 46 are output.

  The selector 142 outputs a plurality of bits of the group B output from the first memory module 45 when the level of the first selection signal cen1 is “1” and the level of the second selection signal cen2 is “1”. Qb and any one of the plurality of bits Qd of the group D output from the second memory module 46 are output.

  The ECC decoder 122 detects and corrects a bit obtained by combining the output of the selector 141 and the output of the selector 142. When the ECC decoder 122 detects an error in the combined bits, it outputs a failure notification signal ERROR.

  The FF 73 is provided in the middle of the transmission path of the first selection signal cen1 from the selection decoder 62 to the selector 141. The FF 74 is provided in the middle of the transmission path of the second selection signal cen2 from the selection decoder 62 to the selector 141. The FF 75 is provided in the transmission path of the first selection signal cen1 from the selection decoder 62 to the selector 142. The FF 76 is provided in the transmission path of the second selection signal cen2 from the selection decoder 62 to the selector 142. The clocks supplied to the FF 73, FF 74, FF 75, FF 76, the first memory module 45, and the second memory module 46 are the same.

  With the above configuration, a failure of FF73, FF74, FF75, or FF76 can be detected.

  For example, when cen1 = 1 and cen2 = 0, when the FF 73 is normal, the selector 141 outputs a plurality of bits Qa of the group A. When the FF 73 is faulty, the selector 141 outputs a plurality of bits of the group A. It is uncertain whether to output bit Qa or a plurality of bits Qc of group C. When a plurality of group C bits Qc are output, the ECC decoder 122 detects an error by detecting and correcting a bit obtained by combining the plurality of group B bits Qb and the plurality of group C bits Qc. To do. As a result, it is possible to detect that any of the FF 73 to FF 76 has a failure.

[Fifth Embodiment]
FIG. 9 is a diagram illustrating a configuration of a semiconductor device 800 according to the fifth embodiment.

  Referring to FIG. 9, this semiconductor device 800 includes a memory module 47, an ECC encoder 21, redundant control circuits 35 and 36, an ECC decoder 22, a redundant decoder 168, an encoder 151, a comparator 152, An interrupt control unit 201 and a CPU 202 are provided.

  Since the ECC encoder 21, the ECC decoder 22, the interrupt control unit 201, and the CPU 202 are the same as those in the first reference example, description thereof will not be repeated.

  The memory module 47 includes a memory array 155 having a plurality of SRAM memory cells and an SRAM logic circuit.

  Memory array 155 includes a regular block 153 and a redundant block 154. The normal block 153 includes a plurality of normal memory cell columns. The plurality of regular memory cell columns serve as data write locations unless they are defective. The redundant block 154 includes one or more redundant memory cell columns. One or more redundant memory cell columns are provided to relieve a defective memory cell column having a defective memory cell among a plurality of normal memory cell columns included in the normal block 153. One or more redundant memory cell columns serve as data write locations instead of defective memory cell columns.

  The redundant decoder 168 decodes the address signal C_Add of the defective memory cell column in the plurality of normal memory columns in the normal block 153, and outputs an address decode signal R1.

  The redundancy control circuit 35 writes the output of the ECC encoder 21 to the redundant memory cell column in the redundant block 154 instead of the defective memory cell column in the normal block 153 according to the address decode signal R1 when writing data. Control.

  In the memory module 47, the error detection / correction encoded data Data [0: M + s] is written at a location specified by the address signal Add [0: N] at the time of data writing.

  In the memory module 47, the stored data signal Q1 is output from the location specified by the address signal Add [0: N] when reading data.

  The redundancy control circuit 36 controls the data to be read from the redundant memory cell column in the redundant block 154 instead of the defective memory cell column in the normal block 153 according to the address decode signal R1.

  The encoder 151 encodes the address decode signal R1 and outputs the address signal C_Add ′ of the defective memory cell column in the plurality of normal memory columns in the normal block 153. This encoding is an inverse conversion of the decoding (conversion) of the redundant decoder 168.

  The comparator 152 compares the address signal C_Add ′ output from the encoder 151 with the address signal C_Add input to the redundancy decoder 168, and outputs a failure notification signal ERROR if they do not match.

  With the above configuration, when the redundant decoder 168 is in a failure state, the address decode signal R1 generated from the address signal C_Add becomes an erroneous signal, and the address signal C_Add ′ obtained by encoding the address decode signal R1 becomes the address signal. Different from C_Add. By detecting this difference, a failure of the redundant decoder 168 can be determined.

[Sixth Embodiment]
FIG. 10 is a diagram illustrating a configuration of a semiconductor device 900 according to the sixth embodiment.

  Referring to FIG. 10, this semiconductor device 900 includes a memory module 47, an ECC encoder 21, redundancy control circuits 35 and 36, an ECC decoder 22, redundancy decoders 168 and 169, an interrupt control unit 201, and a CPU 202. With.

  Since the memory module 47, the ECC encoder 21, the interrupt control unit 201, and the CPU 202 are the same as those in the fifth embodiment, description thereof will not be repeated.

  The redundant decoder 168 decodes the address signal C_Add of the defective memory cell column in the plurality of normal memory columns in the normal block 153 at the time of data writing, and outputs an address decode signal R1.

  The redundancy control circuit 35 writes the output of the ECC encoder 21 to the redundant memory cell column in the redundant block 154 instead of the defective memory cell column in the normal block 153 according to the address decode signal R1 when writing data. Control.

  The redundant decoder 169 decodes the address signal C_Add of the defective memory cell column in the plurality of normal memory columns in the normal block 153 at the time of reading data, and outputs an address decode signal R2.

  The redundancy control circuit 36 controls the data to be read from the redundant memory cell column in the redundant block 154 instead of the defective memory cell column in the normal block 153 according to the address decode signal R2 when reading data.

  The ECC decoder 22 detects and corrects an output from the memory module 47 whose reading is controlled by the redundancy control circuit 36. When the ECC decoder 22 detects an error in the output of the memory module 47, the ECC decoder 22 outputs a failure notification signal ERROR. Since at least one of the redundant decoder 168 and the redundant decoder 169 is in a failure state, the ECC decoder 22 detects an error in the output of the memory module 47 when the address decode signal R1 and the address decode signal R2 are different. When receiving the failure notification signal ERROR, the interrupt control unit 201 notifies the CPU 202 that the failure has been detected.

[Seventh Embodiment]
FIG. 11 is a diagram illustrating a configuration of a semiconductor device 1000 according to the seventh embodiment.

  Referring to FIG. 11, the semiconductor device 1000 includes a memory module 161, an ECC encoder 221, an ECC decoder 222, a comparator 166, an interrupt control unit 201, and a CPU 202.

  Since the interrupt control unit 201 and the CPU 202 are the same as those in the first reference example, the description will not be repeated.

  The memory module 161 includes a memory array 162 including a plurality of SRAM cells and SRAM logic such as a control unit CTRL.

  The memory array 162 includes a data area 163 that stores a data signal Data [0: M], an address area 164 that stores an address signal Add [0: N], a data signal Data [0: M], and an address signal Add [ 0: N], and a check bit area 165 for storing check bits generated based on [0: N]. The data area 163 includes (M + 1) columns. The address area 164 includes (N + 1) columns. The inspection bit area 165 includes S columns.

  FIG. 12 is a diagram illustrating a configuration of data stored in the memory array 162 according to the seventh embodiment.

  One row of the memory array 162 stores a bit string including (M + 1) -bit data signal Data [0: M], (N + 1) -bit address signal Add [0: N], and S-bit check bits. Is done.

  The control unit CTRL including the temporary storage circuit 650 and the address decoder ADRCTL as shown in FIG. 3 decodes the write address Add [0: N] when writing data to the memory array 162 to generate the first address decode signal. WR is output.

  The ECC encoder 221 generates an S-bit check bit by performing error detection / correction coding on a bit string composed of the data signal Data [0: M] and the write address signal Add [0: N] when writing data. To do.

  At the position of the row designated by the first address decode signal WR in the memory array 162, the data Data [0: M] output from the ECC encoder 221 and the write address Add [0: M] A bit string consisting of bits is written.

  The control unit CTRL decodes the read address Add [0: N] when reading data from the memory array 162 and outputs a second address decode signal RR.

  When reading data, the memory array 162 includes data Data ′ [0: M], address Add ′ [0: N], and check bits from the row position specified by the second address decode signal RR. Outputs a bit string.

  The ECC decoder 222 performs error detection / correction decoding on the bit string output from the memory module 161 and outputs data Data ″ [0: M] and address Add ″ [0: N].

  The comparator 166 compares the address Add ″ [0: N] output from the ECC decoder 222 with the read address Add [0: N]. The comparator 166 outputs a failure notification signal when there is a mismatch. ERROR is output.

  When there is no failure in the control unit CTRL, the address Add ″ [0: N] output from the ECC decoder 222 matches the read address Add [0: N]. A failure has occurred in the control unit CTRL. As a result, the first address decode signal WR obtained by decoding the write address may be different from the second address decode signal RR obtained by decoding the same read address as the write address. In this case, the address Add ″ [0: N] output from the ECC decoder 222 does not match the read address Add [0: N]. By detecting this mismatch, a failure of the control unit CTRL can be detected.

[Eighth Embodiment]
FIG. 13 is a diagram illustrating a configuration of a semiconductor device 1100 according to the eighth embodiment.

  Referring to FIG. 13, the semiconductor device 1100 includes a memory module 171, an ECC encoder 321, an ECC decoder 322, an interrupt control unit 201, and a CPU 202.

  Since the interrupt control unit 201 and the CPU 202 are the same as those in the first reference example, the description will not be repeated.

  The memory module 171 includes a memory array 172 including a plurality of SRAM cells and SRAM logic such as a control unit CTRL.

  The memory array 172 stores a data area 173 for storing the data signal Data [0: M], and check bits generated based on the data signal Data [0: M] and the address signal Add [0: N]. And a check bit area 174. The data area 173 is composed of (M + 1) columns. The inspection bit area 174 is composed of S columns.

  FIG. 14 is a diagram illustrating a configuration of data stored in the memory array 172 according to the eighth embodiment.

  In one row of the memory array 172, a bit string including (M + 1) -bit data signal Data [0: M] and S-bit check bits is stored.

  The control unit CTRL including the temporary storage circuit 650 and the address decoder ADRCTL as shown in FIG. 3 decodes the write address Add [0: N] at the time of writing data to the memory array 172 to generate the first address decode signal. WR is output.

  When the data is written, the ECC encoder 321 performs error detection / correction coding on a bit string including the data signal Data [0: M] and the write address signal Add [0: N], and generates an S-bit check bit. To do.

  A bit string including data Data [0: M] output from the ECC encoder 321 and check bits is written at a row position designated by the first address decode signal WR in the memory array 172.

  The control unit CTRL decodes the read address Add [0: N] at the time of reading data from the memory array 172 and outputs a second address decode signal RR.

  The memory array 172 outputs a bit string including data Data ′ [0: M] and check bits from the row position specified by the second address decode signal RR when reading data.

  The ECC decoder 322 adds the address Add [0: N] for reading to the bit string output from the memory module 171 to check the data Data ′ [0: M] and the address Add [0: N]. A bit string consisting of bits is generated. The ECC decoder 322 performs error detection / correction decoding on the generated bit string and outputs data Data ″ [0: M] and address Add ″ [0: N]. The ECC decoder 322 outputs a failure notification signal ERROR to the interrupt control unit 201 when an error is detected.

The ECC decoder 322 does not detect an error when there is no failure in the control unit CTRL.
As a result of the failure in the control unit CTRL, the first address decode signal WR obtained by decoding the write address is different from the second address decode signal RR obtained by decoding the same read address as the write address. There is a case. In such a case, the check bit read from the memory module 171 input to the ECC decoder 322 is different from that generated from the read address Add [0: N] input to the ECC decoder 322. Therefore, the ECC decoder 322 can detect an error based on the check bit.

[Reference Example 2]
FIG. 15 is a diagram illustrating a configuration of a semiconductor device 1200 of Reference Example 2. In FIG. 15, circuits and wirings for processing the data signal Data [0: M] are omitted.

  Referring to FIG. 15, this semiconductor device 1200 includes a first memory module 181 with an address output function, a second memory module 182 with an address output function, an address divider 61, a selection decoder 62, an AFB ( Address FeedBack) selector 183, FFs 77, 78, and 79, a comparator 184, an interrupt control unit 201, and a CPU 202.

  Since address divider 61, selection decoder 62, interrupt control unit 201, and CPU 202 are the same as in Reference Example 1, description thereof will not be repeated.

  Similar to the first memory module 45 of the second embodiment, the first memory module 181 with an address output function includes a memory array having a plurality of SRAM memory cells and an SRAM logic circuit.

  In each of the first memory module 181 with an address output function and the second memory module 182 with an address output function, an N-bit second address bit Add [0: N−1] output from the address divider 61 is provided. Is entered.

  FIG. 16 is a diagram showing the configuration of the first memory module 181 with an address output function. The same applies to the second memory module 182 with the address output function.

  Referring to FIG. 16, the first memory module 181 with the address output function is different from the first memory module 41 of FIG. 3 in that the first memory module 181 with the address output function has the internal address bit AQ1. It further includes an internal address output terminal AQ for outputting [0] to AQ1 [N-1] (hereinafter also referred to as AQ1). The first memory module 181 with the address output function receives the internal address bits AQ1 [0] to AQ1 [N-1] generated from the input N second address bits Add [0: N-1]. Output from address output terminal AQ.

  The second memory module 182 with an address output function has internal address bits AQ2 [0] to AQ2 [N−1] (generated from the input N second address bits Add [0: N−1] ( (Hereinafter also referred to as AQ2) is output from the address output terminal AQ.

  In the first memory module 181 with the address output function, when the data is written, when the first selection signal cen1 is “1”, the first memory module 181 has a location specified by the second address bit Add [0: N−1]. When the data signal Data [0: M] is written and the first selection signal cen1 is “0”, the data signal Data [0: M] is not written. In the first memory module 181 with the address output function, when data is read, when the first selection signal cen1 is “1”, from the location specified by the second address bits Add [0: N−1]. The stored data signal Q1 is output. In the first memory module 181 with the address output function, the stored data signal Q1 is not output when the first selection signal cen1 is “0” when reading data. The first memory module 181 with the address output function outputs the internal address bits AQ1 [0] to AQ1 [N-1] regardless of the level of the first selection signal cen1.

  In the second memory module 182 with the address output function, at the time of data writing, when the second selection signal cen2 is “1”, the second memory module 182 has a location specified by the second address bit Add [0: N−1]. When the data signal Data [0: M] is written and the second selection signal cen2 is “0”, the data signal Data [0: M] is not written. In the second memory module 182 with the address output function, when data is read, when the second selection signal cen2 is “1”, from the location specified by the second address bits Add [0: N−1]. The stored data signal Q2 is output. In the second memory module 182 with the address output function, the stored data signal Q2 is not output when the second selection signal cen2 is “0” when reading data. The second memory module 182 with the address output function outputs the internal address bits AQ2 [0] to AQ2 [N-1] regardless of the level of the second selection signal cen2.

  Referring to FIG. 15 again, the ERROR selector 283 determines whether the internal address bit AQ1 output from the first memory module 181 is based on the level of the first selection signal cen1 and the level of the second selection signal cen2. One of the internal address bits AQ 2 output from the second memory module 182 is selected and output to the comparator 184.

  The ERROR selector 283 starts from the first memory module 181 when the level of the first selection signal cen1 is “1” of the activation level and the level of the second selection signal cen2 is “0” of the activation level. The output internal address bit AQ 1 is selected and output to the comparator 184. The ERROR selector 283 is configured to detect the second memory module 182 when the level of the first selection signal cen1 is “0” that is the inactivation level and the level of the second selection signal cen2 is “1” that is the activation level. Is selected and output to the comparator 184. The ERROR selector 283 includes the internal address bits AQ1 output from the first memory module 181 when the level of the first selection signal cen1 is “0” and the level of the second selection signal cen2 is “0”. One of the internal address bits AQ2 output from the second memory module 182 is output. The ERROR selector 283 includes an internal address bit AQ1 output from the first memory module 181 when the level of the first selection signal cen1 is “1” and the level of the second selection signal cen2 is “1”. One of the internal address bits AQ2 output from the second memory module 182 is output.

  The comparator 184 combines the internal address bit AQ1 or AQ2 output from the ERROR selector 283 and the first address bit Add [N] output from the address divider 61, and the address output from the CPU 202. The signal Add [0: N] is compared. The comparator 184 outputs a failure notification signal ERROR in the case of mismatch.

  The FF 77 is provided in the transmission path of the first selection signal cen1 from the selection decoder 62 to the ERROR selector 283. The FF 78 is provided in the transmission path of the second selection signal cen2 from the selection decoder 62 to the ERROR selector 283. The FF 79 is provided in the middle of the transmission path of the first address bit Add [N] from the address divider 61 to the input of the comparator 184.

  The clocks supplied to the FF77, FF78, FF79, the first memory module 181 with an address output function, and the second memory module 182 with an address output function are the same.

  In the semiconductor device 1200 of the reference example 2, there is a problem that a failure of the selection decoder 62 that processes the address signal Add [0: N] and a wiring related thereto cannot be detected.

  Even if at least one of the level of the first selection signal cen1 and the level of the second selection signal cen2 is incorrect, the output AQ1 of the first memory module 181 and the output AQ2 of the second memory module 182 This is because any of the above is input to the comparator 184 via the ERROR selector 283.

[Ninth Embodiment]
FIG. 17 is a diagram illustrating a configuration of a semiconductor device 1300 according to the ninth embodiment.

  Referring to FIG. 17, this semiconductor device 1300 includes a first memory module 181 with an address output function, a second memory module 182 with an address output function, an address divider 61, a selection decoder 62, and an ERROR selector. 283, FFs 77, 78, and 79, an encoder 191, a comparator 194, an interrupt control unit 201, and a CPU 202.

  The first memory module 181 with an address output function, the second memory module 182 with an address output function, an address divider 61, a selection decoder 62, an ERROR selector 283, FFs 77, 78, 79, an interrupt control unit 201, and a CPU 202 are Since it is the same as that of the reference example 2, description is not repeated.

  The encoder 191 encodes the first selection signal cen1 and the second selection signal cen2 output from the selection decoder 62, and outputs the first address bit Add ′ [N]. This encoding is an inverse conversion of the decoding (conversion) of the selection decoder 62 when the selection permission signal CEN = 1.

  The encoder 191 outputs the first address bit Add ′ [N] (= “1”) when the first selection signal cen1 is “1” and the second selection signal cen2 is “0”. The encoder 191 outputs the first address bit Add ′ [N] (= “0”) when the first selection signal cen1 is “0” and the second selection signal cen2 is “1”.

  The comparator 194 combines the internal address bit AQ 1 or AQ 2 output from the ERROR selector 283 and the first address bit Add ′ [N] output from the encoder 191 and the address signal output from the CPU 202. Compare with Add [0: N]. The comparator 194 outputs a failure notification signal ERROR in the case of mismatch.

  When both the level of the first selection signal cen1 output from the selection decoder 62 and the level of the second selection signal cen2 are inverted due to the failure of the selection decoder 62, the first address bit Add ′ [ N] is different from the address bit Add [N]. By detecting this difference, a failure of the selection decoder 62 can be determined.

[Tenth embodiment]
FIG. 18 is a diagram illustrating a configuration of a semiconductor device 1400 according to the tenth embodiment.

  Referring to FIG. 18, this semiconductor device 1400 includes a first memory module 181 with an address output function, a second memory module 182 with an address output function, an address divider 61, a selection decoder 62, and an ERROR selector. 283. The semiconductor device 1400 includes FFs 77, 78, 79, CGC (Clock Gating Circuit) 192, 193, a comparator 184, an interrupt control unit 201, and a CPU 202.

  First memory module 181 with address output function, second memory module 182 with address output function, address divider 61, selection decoder 62, ERROR selector 283, FF77, 78, 79, comparator 184, interrupt control unit 201, Since CPU 202 and CPU 202 are the same as in Reference Example 2, description thereof will not be repeated.

  The CGC 192 outputs the clock CLK to the first memory module 181 when the first selection signal cen1 is at the activation level “1”. The CGC 193 outputs the clock CLK to the second memory module 182 when the second selection signal cen2 is at the activation level “1”.

  The first memory module 181 receives the second address bits Add [0: N−1] and updates the input second address bits Add [0: N−1] at the timing of the edge of the clock CLK. Capture value. The first memory module 181 executes writing of data to the memory array MARY or reading of data from the memory array MARY based on the latest value of the second address bits Add [0: N−1]. The internal address bit AQ1 of the latest value of the second address bit Add [0: N−1] is output. Therefore, when the first selection signal cen1 is “1”, the first memory module 181 outputs the internal address bit of the latest value of the second address bits Add [0: N−1]. When the first selection signal cen1 is “0”, the internal address bits of the previous value of the second address bits Add [0: N−1] are output from the first memory module 181.

  The second memory module 182 receives the second address bit Add [0: N−1], and receives the second address bit Add [0: N−1] at the timing of the edge of the clock CLK. Capture the latest value. The second memory module 182 executes writing of data to the memory array MARY or reading of data from the memory array MARY based on the latest value of the second address bits Add [0: N−1]. The internal address bit AQ2 of the latest value of the second address bit Add [0: N-1] is output. Therefore, when the second selection signal cen2 is “1”, the second memory module 182 outputs the internal address bit of the latest value of the second address bits Add [0: N−1]. When the second selection signal cen2 is “0”, the internal address bits of the previous value of the second address bits Add [0: N−1] are output from the second memory module 182.

  The comparator 184 compares the bit obtained by combining the internal address bit AQ1 or AQ2 output from the ERROR selector 283 and the most significant bit Add [N] with the address signal Add [0: N] output from the CPU 202. To do. The comparator 184 outputs a failure notification signal ERROR in the case of mismatch.

  When the level of the selection permission signal CEN becomes “1”, the level of the first selection signal cen1 becomes “0”, and the level of the second selection signal cen2 becomes “0” due to the failure of the selection decoder 62, Operation like this is performed. The output AQ1 of the first memory module 181 is the internal address bit of the previous value of the second address bit (that is, the value of the previous cycle), and the output AQ2 of the second memory module 182 is also the second address. It becomes the internal address bit of the previous value of the bit. The ERROR selector 283 selects one of the output AQ1 of the first memory module 181 and the output AQ2 of the second memory module 182 and inputs the selected one to the comparator 184. Thus, since the internal address bits having the previous value of the second address bits Add [0: N−1] are input to the comparator 184, a failure can be detected.

[Eleventh embodiment]
FIG. 19 is a diagram illustrating a configuration of a semiconductor device 1500 according to the eleventh embodiment.

  The semiconductor device 1500 includes a first memory module 181 with an address output function, a second memory module 182 with an address output function, an address divider 61, a selection decoder 62, an ECC encoder 21, an ERROR selector 283, Is provided. The semiconductor device 1500 further includes a selector 141, a selector 142, an ECC decoder 122, a failure determination unit 121, a comparator 184, FFs 73, 74, 75, 76, 77, 78, an interrupt control unit 301, CPU302.

  The first memory module 181 with address output function, the second memory module 182 with address output function, the address divider 61, the selection decoder 62, the ECC encoder 21, and the ERROR selector 283 Since it is the same as that described in the embodiment, the description will not be repeated. In addition, the selector 141, the selector 142, the ECC decoder 122, the failure determination unit 121, the comparator 184, and the FFs 73, 74, 75, 76, 77, and 78 are those described in any of the above embodiments. The description is not repeated because it is the same.

  The failure determination unit 121 outputs a first failure notification signal ERROR1 to the interrupt control unit 301 when the selection decoder 62 determines that the failure state is the first failure state. The first failure state is that when the selection permission signal CEN is “1”, one of the first selection signal cen1 and the second selection signal cen2 is “1” and the other is “0”. In this case, the first selection signal cen1 and the second selection signal cen2 are both “0” or “1”. In addition, when the selection permission signal CEN is “1”, when it is correct that both the first selection signal cen1 and the second selection signal cen2 are “0”, at least one is set to “1”. It is a serious failure.

  The comparator 184 outputs the second failure notification signal ERROR2 when the two input addresses do not match because the selection decoder 62 is in the second failure state. The second failure state is a failure in which the level of the first selection signal cen1 is inverted and the level of the second selection signal cen2 is also inverted.

  The ECC decoder 122 outputs a third failure notification signal ERROR3 to the interrupt control unit 301 when any of the FFs 73, 74, 75, and 76 detects an error as a result of the failure state.

  The interrupt controller 301 transmits to the CPU 302 the first failure notification signal ERROR1, the second failure notification signal ERROR2, and the third failure notification signal ERROR3. It is assumed that the first failure notification signal ERROR1 has the highest priority, the second failure notification signal ERROR2 has the next highest priority, and the third failure notification signal ERROR3 has the lowest priority.

  FIG. 20 is a flowchart showing the processing procedure of CP 302 when a failure is notified.

  Referring to FIG. 20, in step S501, when CPU 302 receives first failure notification signal ERROR1, the process proceeds to step S510. When CPU 302 does not receive first failure notification signal ERROR1, the process proceeds to step S502. Proceed to

  In step S502, when the CPU 302 receives the second failure notification signal ERROR2, the process proceeds to step S507. When the CPU 302 does not receive the second failure notification signal ERROR2, the process proceeds to step S503.

  In step S503, when the CPU 302 receives the third failure notification signal ERROR3, the process proceeds to step S505, and when the CPU 302 does not receive the third failure notification signal ERROR3, the process proceeds to step S504.

  In step S505, when the CPU 302 receives the third failure notification signal ERROR3 for the second time, the process proceeds to step S509, and when the CPU 302 receives the third failure notification signal ERROR3 for the first time. The process proceeds to step S506.

In step S507, the CPU 302 executes a test.
In step S508, if the test result is good, the process proceeds to step S503. If the test result is bad, the process proceeds to step S509.

In step S504, the CPU 302 controls so that normal processing is executed.
In step S <b> 506, the CPU 302 performs control so that a repeated process that repeats the previous operation is executed.

In step S509, the CPU 302 controls the replacement process to be executed.
In step S510, the CPU 302 controls the danger avoidance process to be executed.

  As described above, in the present embodiment, when there is a possibility that a plurality of types of failures may occur, processing according to the priority of the types of failures that have occurred can be executed.

[Twelfth embodiment]
FIG. 21 is a diagram illustrating a configuration of a semiconductor device 1600 according to the twelfth embodiment.

  Referring to FIG. 21, a semiconductor device 1600 includes a first memory module 281 with an address output function, a second memory module 282 with an address output function, an address divider 61, a selection decoder 62, and an ERROR selector. 283, a comparator 284, FFs 77, 78, and 79, an interrupt control unit 401, and a CPU 202.

  Since address divider 61, selection decoder 62, FFs 77, 78, 79, and CPU 202 are the same as in Reference Example 2, their description will not be repeated.

  The first memory module 281 with an address output function and the second memory module 282 with an address output function are similar to the first memory module 45 of the second embodiment, a memory array having a plurality of SRAM memory cells, SRAM logic circuit.

  In each of the first memory module 281 with an address output function and the second memory module 282 with an address output function, the N second address bits Add [0: N−1] output from the address divider 61 are provided. (First address signal) and N address bits A [0: N−1] (second address signal) directly sent from the CPU 202 are input. The address bits A [0: N−1] function as an expected value signal for checking whether or not the internal address bits AQ1 [0: N−1] are normal.

  The first memory module 281 with an address output function receives the first selection signal cen1. The first memory module 281 with the address output function can read and write data when the level of the first selection signal cen1 is the activation level “1”. The first memory module 281 with the address output function cannot read or write data when the level of the first selection signal cen1 is “0”, which is an inactivation level.

  The second memory module 282 with an address output function receives the second selection signal cen2. The second memory module 282 with the address output function can read and write data when the level of the second selection signal cen2 is “1” of the activation level. The second memory module 282 with the address output function cannot read or write data when the level of the second selection signal cen2 is “0”, which is an inactivation level.

  FIG. 22 is a diagram showing the configuration of the first memory module 281 with an address output function. The same applies to the second memory module 282 with the address output function.

  Referring to FIG. 22, the first memory module 181 with the address output function is different from the first memory module 41 of FIG. 3 in that a comparator 285, a failure notification output terminal EA, and an address input terminal ADB. And a clock supply source 888 and a selection terminal CN.

  The address input terminal ADB directly receives the N-bit address bits A [0: N−1] (lower first number of bits) of the (N + 1) -bit address signal A [0: N] from the CPU 202. .

  The selection terminal CN receives the first selection signal cen1 and outputs it to the clock supply source 888. The clock supply source 888 supplies the clock CLK to the first memory module 381 with an address output function when the level of the first selection signal cen1 is “1” of the activation level. The clock supply source 888 does not supply the clock CLK to the first memory module 381 with an address output function when the level of the first selection signal cen1 is “0” which is an inactivation level.

  The comparator 285 includes N-bit address bits A [0: N−1] sent from the address input terminal ADB and N-bit internal address bits AQ1 [0: N−1] output from the temporary storage circuit 650. Compare The comparator 285 outputs a failure notification signal ERROR1 when the comparison results do not match.

The failure notification output terminal EA outputs a failure notification signal ERROR1.
Similarly, the second memory module 282 with an address output function outputs a failure notification signal ERROR2.

  Referring to FIG. 21 again, the ERROR selector 283 generates a failure notification signal ERROR1 output from the first memory module 281 based on the level of the first selection signal cen1 and the level of the second selection signal cen2. One of the failure notification signals ERROR2 output from the second memory module 282 is selected, and the selected failure notification signal is output to the interrupt control unit 401 as the failure notification signal ERROR3.

  The ERROR selector 283 is configured such that when the level of the first selection signal cen1 is “1” of the activation level and the level of the second selection signal cen2 is “0” of the inactivation level, the first memory module 281 is provided. The failure notification signal ERROR1 output from is selected. The ERROR selector 283 is configured to detect the second memory module 282 when the level of the first selection signal cen1 is “0” that is the inactivation level and the level of the second selection signal cen2 is “1” that is the activation level. The failure notification signal ERROR2 output from is selected. The ERROR selector 283 includes a failure notification signal ERROR1 output from the first memory module 281 when the level of the first selection signal cen1 is “0” and the level of the second selection signal cen2 is “0”. One of the failure notification signals ERROR2 output from the second memory module 282 is selected. The ERROR selector 283 includes a failure notification signal ERROR1 output from the first memory module 281 when the level of the first selection signal cen1 is “1” and the level of the second selection signal cen2 is “1”. One of the failure notification signals ERROR2 output from the second memory module 282 is selected.

  The comparator 284 compares the first address bit Add [N] output from the address divider 61 with the first address bit A [N] sent directly from the CPU 202. The comparator 284 outputs a failure notification signal ERROR4 to the interrupt control unit 401 when the comparison results do not match.

  When receiving the failure notification signal ERROR3 or the failure notification signal ERROR4, the interrupt control unit 401 notifies the CPU 202 that a failure has been detected.

  According to this embodiment, a comparator is provided in the memory module, and a failure is determined by comparing addresses in the memory module. As a result, conventionally, a signal corresponding to the number of bits of the address signal is output from the memory module, but in the present embodiment, only a 1-bit signal is output from the memory module.

  FIG. 23 is a diagram showing a layout of the first memory module 281 with an address output function. The same applies to the second memory module 282 with the address output function.

  Input / output terminals to the memory module 281 are concentrated in the vicinity of the control unit CTRL. When the number of signal lines connected to the input / output terminals is large, current concentration tends to occur in the vicinity of the control unit CTRL. In this embodiment, by reducing the number of bits of a signal to be output, it is possible to suppress a large amount of current from flowing in a specific location.

[Thirteenth embodiment]
FIG. 24 is a diagram illustrating a configuration of a semiconductor device 1700 according to the thirteenth embodiment.

  Referring to FIG. 24, this semiconductor device 1700 includes a first memory module 381 with an address output function, a second memory module 382 with an address output function, an address divider 61, a selection decoder 62, and an ERROR selector. 283, a comparator 284, FFs 77, 78, and 79, an interrupt control unit 401, and a CPU 202.

  Since address divider 61, selection decoder 62, FFs 77, 78, 79, and CPU 202 are the same as in Reference Example 2, their description will not be repeated. Since the ERROR selector 283, the comparator 284, and the interrupt control unit 401 are the same as those in the twelfth embodiment, description thereof will not be repeated.

  The first memory module 381 with an address output function and the second memory module 382 with an address output function, like the first memory module 45 of the second embodiment, a memory array having a plurality of SRAM memory cells, SRAM logic circuit.

  In each of the first memory module 381 with the address output function and the second memory module 382 with the address output function, the N second address bits Add [0: N−1] output from the address divider 61 are provided. And a test address is input.

  The first memory module 381 with an address output function receives the first selection signal cen1. The first memory module 381 with an address output function can read and write data when the level of the first selection signal cen1 is “1”, which is the activation level. The first memory module 381 with an address output function cannot read or write data when the level of the first selection signal cen1 is “0”, which is an inactivation level.

  The second memory module 382 with an address output function receives the second selection signal cen2. The second memory module 382 with the address output function can read and write data when the level of the second selection signal cen2 is the activation level “1”. The second memory module 382 with the address output function cannot read or write data when the level of the second selection signal cen2 is “0”, which is an inactivation level.

  FIG. 25 is a diagram showing the configuration of the first memory module 381 with an address output function. The same applies to the second memory module 382 with the address output function.

  25, the first memory module 381 with the address output function is different from the first memory module 41 of FIG. 3 in that a comparator 385, a failure notification output terminal EA, and a test address input terminal It is a point provided with TA, selector 386, clock supply source 888, and selection terminal CN.

  For example, an N-bit test address signal TAdd [0: N−1] directly sent from the CPU 202 is input to the test address input terminal TA. For example, the test address signal TAdd [0: N−1] can be a signal in which all bits are 0 or a signal in which all bits are 1.

  Note that the test address signal input to the test address input terminal TA is not limited to the N-bit test address signal TAdd [0: N−1]. For example, it may be a 1-bit test address signal. When the memory module 382 receives a 1-bit test address signal, the memory module 382 may generate an N-bit test address signal and supply it to the selector 386.

  The selection terminal CN receives the first selection signal cen1 and outputs it to the clock supply source 888. The clock supply source 888 supplies the clock CLK to the first memory module 381 with an address output function when the level of the first selection signal cen1 is “1” of the activation level. The clock supply source 888 does not supply the clock CLK to the first memory module 381 with an address output function when the level of the first selection signal cen1 is “0” which is an inactivation level.

  The selector 386, in accordance with a control signal (not shown), N-bit second address bits Add [0: N−1] sent from the address input terminal ADB and N-bit test address signal TAdd sent from the test address input terminal TA. Any one of [0: N-1] is selected, and the selected one is output to the comparator 385 as address bits B [0: N-1]. When the second address bit Add [0: N-1] is selected, the second address bit Add [0: N-1] indicates whether or not the internal address bit AQ1 [0: N-1] is normal. It functions as an expected value signal for checking. When the test address signal TAdd [0: N−1] is selected, the test address signal TAdd [0: N−1] functions as a signal for checking whether or not the comparator 385 is normal.

  The comparator 385 receives the N-bit address bits B [0: N−1] output from the selector 386 and the N-bit internal address bits AQ1 [0: N−1] output from the temporary storage circuit 650. Compare. The comparator 385 outputs a failure notification signal ERROR1 when the comparison results do not match.

The failure notification output terminal EA outputs a failure notification signal ERROR1.
Similarly, the second memory module 382 with an address output function outputs a failure notification signal ERROR2.

  In the present embodiment, by setting the test address to less than N bits, the number of input terminals of the memory module can be reduced as compared with the twelfth embodiment. As a result, the wiring area around the memory module can be reduced, and the vacant area can be opened as a power enhancement area. Therefore, current concentration can be further avoided. In the present embodiment, it is also possible to detect a failure of the comparator in the memory module.

  In the memory module of the twelfth embodiment, the test address input terminal TA for inputting the test address, the test address TA, and the address bits A [0: N−1] are selected and supplied to the comparator. It is good also as what provides the selector which performs.

[Fourteenth embodiment]
FIG. 26 is a diagram illustrating a configuration of a semiconductor device 1800 according to the fourteenth embodiment.

  Referring to FIG. 26, this semiconductor device 1800 includes a first memory module 481 with an address output function, a second memory module 482 with an address output function, an address divider 61, a selection decoder 62, an ERROR / An AQ selector 483, a comparator 284, FFs 77, 78, and 79, an interrupt control unit 401, an error address holding circuit 484, and a CPU 202 are provided.

  Since address divider 61, selection decoder 62, FFs 77, 78, 79, and CPU 202 are the same as in Reference Example 2, their description will not be repeated. Since the comparator 284 and the interrupt control unit 401 are the same as those in the twelfth embodiment, description thereof will not be repeated.

  The first memory module 481 with an address output function and the second memory module 482 with an address output function are similar to the first memory module 45 of the second embodiment, a memory array having a plurality of SRAM memory cells, SRAM logic circuit.

  In each of the first memory module 481 with an address output function and the second memory module 482 with an address output function, the N second address bits Add [0: N−1] output from the address divider 61 are provided. Then, N-bit address bits A [0: N−1] sent directly from the CPU 202 are input.

  The first memory module 481 with the address output function receives the first selection signal cen1. The first memory module 481 with the address output function can read and write data when the level of the first selection signal cen1 is “1” of the activation level. The first memory module 481 with the address output function cannot read or write data when the level of the first selection signal cen1 is “0”, which is an inactivation level.

  The second memory module 482 with the address output function receives the second selection signal cen2. The second memory module 482 with the address output function can read and write data when the level of the second selection signal cen2 is “1” of the activation level. The second memory module 482 with the address output function cannot read or write data when the level of the second selection signal cen2 is “0”, which is an inactivation level.

  FIG. 27 is a diagram showing the configuration of the first memory module 481 with an address output function. The same applies to the second memory module 482 with an address output function.

  Referring to FIG. 27, the first memory module 481 with an address output function is different from the first memory module 281 with an address output function in FIG. 22 in that a selector 584 is provided.

  Selector 584 selects one of N-bit internal address bits AQ1 [0: N−1] output from temporary storage circuit 650 and data signal D1 [0: M] output from data input / output unit IO. The selected signal is output to the data input / output terminal DA as memory module output data ADTA1. The selector 584 selects the data signal D1 [0: M] when it does not receive the failure notification signal ERROR1. When selector 584 receives failure notification signal ERROR1, it selects internal address bits AQ1 [0: N−1].

  The second memory module 482 with an address output function outputs a failure notification signal ERROR2 and memory module output data ADTA2.

  The ERROR / AQ selector 483 receives the failure notification signal ERROR1 output from the first memory module 481 and the second memory module 482 based on the level of the first selection signal cen1 and the level of the second selection signal cen2. One of the failure notification signals ERROR2 to be output is selected. The ERROR / AQ selector 483 outputs the selected failure notification signal as the failure notification signal ERROR3 to the interrupt control unit 401 and the error address holding circuit 484.

  The ERROR / AQ selector 483 includes the memory module output data ADTA1 output from the first memory module 481 and the second memory module 482 based on the level of the first selection signal cen1 and the level of the second selection signal cen2. Is selected from the memory module output data ADTA2 output from. The ERROR / AQ selector 483 outputs the selected one as memory module output data ADTA3 to the error address holding circuit 484.

  The ERROR / AQ selector 483 includes the first memory module when the level of the first selection signal cen1 is “1” that is the activation level and the level of the second selection signal cen2 is “0” that is the activation level. The failure notification signal ERROR1 and memory module output data ADTA1 output from 481 are selected.

  The ERROR / AQ selector 483 causes the second memory when the level of the first selection signal cen1 is “0” that is the inactivation level and the level of the second selection signal cen2 is “1” that is the activation level. The failure notification signal ERROR2 and the memory module output data ADTA2 output from the module 482 are selected.

  The ERROR / AQ selector 483 selects one of the failure notification signal ERROR1 and the failure notification signal ERROR2 when the level of the first selection signal cen1 is “0” and the level of the second selection signal cen2 is “0”. Is selected, and one of the memory module output data ADTA1 and the memory module output data ADTA2 is selected.

  The ERROR / AQ selector 483 selects one of the failure notification signal ERROR1 and the failure notification signal ERROR2 when the level of the first selection signal cen1 is “1” and the level of the second selection signal cen2 is “1”. Is selected, and one of the memory module output data ADTA1 and the memory module output data ADTA2 is selected.

  Error address holding circuit 484 receives memory module output data ADTA3. The error address holding circuit 484 holds the memory module output data ADTA3 when receiving the failure notification signal ERRO3. This is because when the failure notification signal ERRO3 is received, the memory module output data ADTA3 represents the internal address bits AQ1 [0: N-1] or AQ2 [0: N-1].

  Further, the error address holding circuit 484 receives the first address bit Add [N]. The error address holding circuit 484 holds the first address bit Add [N] when receiving the failure notification signal ERROR4.

  According to the present embodiment, when a failure notification signal is output, an address related to the failure is held in the error address holding circuit. Accordingly, when a failure is notified, a memory BIST (Built-In Self Test) is performed, and an operation for specifying an address related to the failure can be made unnecessary.

(Modification)
The present disclosure is not limited to the above-described embodiment, and includes, for example, the following modifications.

(1) Number of Memory Modules In the second to eleventh embodiments, the case where the semiconductor device includes one or two memory modules has been described. However, the present invention is not limited to this. For example, the semiconductor device may include 2 ^N memory modules.

When there are 2 ^N memory modules, the address divider 61 uses the upper N bits from the MSB side of the address signal as the first address bits for selecting the memory module, and the other as the second address bits. can do. The selection decoder generates selection signals cen1 to cen2 ^N to be supplied to 2 ^N memory modules. 4, the malfunction determining unit 121 and 131 of FIG. 7, on the basis of the selection enable signal CEN, and the selection signal Cen1～cen2 ^N, determines a failure of the select decoder 62. The selector 141 of FIG. 8 is based on the selection signal Cen1～cen2 ^N, select one of the plurality of bits of ^the 2 ^N of the first group output from ^the 2 ^N of the memory module. The selector 142 of FIG. 8 is based on the selection signal Cen1～cen2 ^N, select one of the plurality of bits of ^the 2 ^N of the second group output from ^the 2 ^N of the memory module. Figure 17, ERROR selector 283 in FIG. 18, based on the selection signal Cen1～cen2 ^N, selects and outputs one of ^the 2 ^N of the internal address bits output from ^the 2 ^N of the memory module.

(2) ECC of the seventh embodiment
The ECC encoder 221 and the ECC decoder 222 of the seventh embodiment may be omitted, and only the data and address may be stored in the memory array 162.

(3) Memory Module The memory module described in the ninth embodiment may operate when a selection signal is activated. For example, when the selection signal is inactivated, the clock source in the memory module may stop supplying the clock to each component in the memory module.

(Appendix)
In addition, based on said embodiment, this invention also includes the following inventions.

(Claim A)
A memory array having a plurality of normal memory cells and redundant memory cells;
A redundant decoder for decoding an address signal of a defective memory cell in the plurality of normal memories and outputting an address decode signal;
A first redundancy control circuit for controlling data to be written in the redundant memory cell instead of the defective memory cell in accordance with the address decode signal;
A second redundancy control circuit that controls to read data from the redundant memory cell instead of the defective memory cell in accordance with the address decode signal;
An encoder that encodes the address decode signal and outputs an address signal;
A semiconductor device comprising: a comparator that compares the address signal input to the redundancy decoder and the address signal output from the encoder.

(Claim B)
A memory array having a plurality of normal memory cells and redundant memory cells;
A first redundant decoder that decodes an address signal of a defective memory cell in the plurality of normal memories and outputs a first address decode signal when writing data;
A second redundant decoder that decodes an address signal of a defective memory cell in the plurality of normal memories and outputs a second address decode signal when reading data;
An ECC encoder for error detection and correction coding of data to the memory array;
A first redundancy control circuit for controlling the output of the ECC encoder to be written in the redundant memory cell instead of the defective memory cell in accordance with the first address decode signal when writing data;
A second redundancy control circuit that controls to read data from the redundant memory cell instead of the defective memory cell in accordance with the second address decode signal when reading data;
A semiconductor device comprising: an ECC decoder that detects and corrects data output from the memory array.

(Claim C)
A memory array for storing a bit string including data, an address, and a check bit;
When writing data to the memory array, the write address is decoded and a first decode signal is output, and when reading data from the memory array, the read address is decoded and a second decode signal is output. An address decoder to
An ECC encoder that generates a check bit by performing error detection and correction coding on a bit string including data and the address for writing when writing data;
A bit string composed of the data, the write address, and the check bit is written at a position specified by the first decode signal in the memory array,
When reading data, the memory array outputs data, a bit string composed of an address and a check bit from a position specified by the second decode signal,
An ECC decoder for detecting and correcting a bit string output from the memory array;
A semiconductor device comprising: a comparator that compares an address output from the ECC decoder and the read address.

(Claim D)
A memory array for storing a bit string composed of data and check bits;
When writing data to the memory array, the write address is decoded and a first decode signal is output, and when reading data from the memory array, the read address is decoded and a second decode signal is output. An address decoder to
An ECC encoder that generates a check bit by performing error detection and correction coding on a bit string including data and the address for writing when writing data;
A bit string composed of the data and the check bit is written at a position specified by the first decode signal in the memory array,
At the time of reading data, the memory array outputs data and a bit string composed of check bits from the position specified by the second decode signal,
A semiconductor device comprising: an ECC decoder that adds an address for reading to the bit string output from the memory array to detect and correct an error.

(Claim E)
A plurality of memory modules, wherein a plurality of bits representing an address signal indicating a storage position of data in the plurality of memory modules includes a first address bit and a second address bit; Each of which receives the second address bit and outputs an internal address bit generated from the second address bit;
A selection decoder that decodes the first address bits to control the levels of a plurality of selection signals;
A failure determination unit that determines whether or not the selection decoder is in a failure state based on the levels of the plurality of selection signals, and that outputs a first failure notification signal in a failure state;
An encoder that encodes the plurality of selection signals and outputs address bits;
A first selector that selects one of internal address bits output from the plurality of memory modules based on the levels of the plurality of selection signals;
The bit string obtained by combining the internal address bits output from the first selector and the address bits output from the encoder is compared with a plurality of bits representing the address signal. A comparator that outputs a notification signal;
An ECC encoder that performs error detection and correction coding on the write data;
Each of the plurality of memory modules is written with the error detection / correction encoded write data when the corresponding selection signal is at the activation level,
A plurality of bits of output data from each of the plurality of memory modules are classified into a plurality of bits in a first group and a plurality of bits in a second group,
A second selector for selecting and outputting one of a plurality of bits of a plurality of first groups output from the plurality of memory modules based on the levels of the plurality of selection signals;
A third selector that selects and outputs one of a plurality of bits of a plurality of second groups output from the plurality of memory modules based on the levels of the plurality of selection signals;
An ECC decoder that detects and corrects a bit string obtained by combining the output of the second selector and the output of the third selector, and outputs a third failure notification signal when an error is detected;
A semiconductor device comprising: a CPU that executes processing according to the type of the received failure notification signal.

(Claim F)
A plurality of memory modules, wherein a plurality of bits representing an address signal indicating a storage position of data in the plurality of memory modules includes a first address bit and a second address bit; Each of which receives the second address bit and outputs an internal address bit generated from the second address bit;
A selection decoder that decodes the first address bits to control the levels of a plurality of selection signals;
An encoder that encodes the plurality of selection signals and outputs address bits;
A selector that selects any of the internal address bits output from the plurality of memory modules based on the levels of the plurality of selection signals;
A semiconductor device comprising: a bit string obtained by combining the internal address bits output from the selector and the address bits output from the encoder; and a comparator that compares the plurality of bits representing the address signal.

(Claim G)
A plurality of memory modules, wherein a plurality of bits representing an address signal indicating a storage position of data in the plurality of memory modules includes a first address bit and a second address bit; Each of which receives the second address bit and outputs an internal address bit generated from the second address bit;
A selection decoder that decodes the first address bits to control the levels of a plurality of selection signals;
A plurality of clock gates each receiving a clock and outputting the clock to the corresponding memory module when the corresponding selection signal is at an activation level;
Each of the plurality of memory modules outputs the internal address bit generated from the latest value of the second address bit when receiving the clock output from the corresponding clock gate,
A selector that selects any of the internal address bits output from the plurality of memory modules based on the levels of the plurality of selection signals;
A comparator that compares the address signal with a bit obtained by combining the internal address bit output from the selector and the first address bit;
Each comprising a plurality of flip-flops provided in a path through which the corresponding selection signal is supplied to the selector;
The semiconductor device, wherein the same clock signal is input to the plurality of flip-flops and the plurality of memory modules.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  1_0 to 1_N-1 latch circuit, 21, 221, 321 ECC encoder, 22, 122, 222, 322 ECC decoder, 31, 32, 33, 34, 35, 36 redundancy control circuit, 41, 45 first memory module, 43, 44, 155, 162, 172, MARY memory array, 42, 46 second memory module, 47, 161, 171, 30-1 to 30-N memory module, 51, 141, 142, 149 selector, 61 address Divider, 62, 303 selection decoder, 71, 72, 73, 75, 76, 77, 78, 79 FF, 81, 68, 168, 169 Redundant decoder, 121, 131, 304 Failure determination unit, 151, 191 Encoder, 152,166,184,194,284,285,385 Comparator, 1 3,363,365 Regular block, 154,364,366 Redundant block, 163,173 Data area, 164 Address area, 165,174 Check bit area, 181,281,381,481 First memory module with address output function, 182, 282, 382, 482 Second memory module with address output function, 183 AFB selector, 192, 193 CGC, 201, 301, 401 Interrupt control unit, 202, 302 CPU, 283 ERROR selector, 483 ERROR / AQ selector, 484 error address holding circuit, 386, 584 selector, 300, 400, 500, 600, 700, 800, 900, 100, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 18 00 Semiconductor device, 350 flash memory, 650 temporary memory circuit, 888 clock supply source, ADA, ADB address input terminal, AQ internal address output terminal, CK clock input terminal, DA data input / output terminal, EA failure notification output terminal, WD word Line drive circuit, IO data input / output unit, ADRCTL address decoder, CTRL control unit, CN selection terminal.

Claims (20)

A selection decoder for controlling the levels of a plurality of selection signals based on at least one address bit;
A plurality of memory modules that are selected when the corresponding selection signal is at an activation level and are capable of reading and writing data;
A semiconductor device comprising: a failure determination unit that determines whether or not the selection decoder is in a failure state based on the levels of the plurality of selection signals. A CPU,
The semiconductor device according to claim 1, wherein the failure determination unit outputs a signal notifying the failure state to the CPU when the selection decoder determines that the failure state is present. An ECC encoder that performs error detection / correction encoding of write data is provided,
Each of the plurality of memory modules is written with the error detection / correction encoded write data when the corresponding selection signal is at an activation level,
A selector for selecting any of output data from the plurality of memory modules based on the levels of the plurality of selection signals;
An ECC decoder that detects and corrects the output of the selector;
When it is determined that the selected decoder is in the failure state, the selector inverts a first number of bits among the plurality of bits of the selected output data, and the first number of bits is determined in the ECC decoder. 2. The semiconductor device according to claim 1, wherein the number of bits exceeds the upper limit of the number of bits that can be corrected and is not more than the upper limit of the number of bits that can be detected. An ECC encoder that performs error detection / correction encoding of write data is provided,
At the time of data writing, each of the plurality of memory modules is written with the error detection / correction encoded write data when the corresponding selection signal is at the activation level,
When reading data, the plurality of bits constituting the output data of each of the plurality of memory modules are classified into a plurality of bits in a first group and a plurality of bits in a second group,
A first selector that selects and outputs one of a plurality of bits of a plurality of first groups output from the plurality of memory modules based on levels of the plurality of selection signals;
A second selector for selecting and outputting one of a plurality of bits of a plurality of second groups output from the plurality of memory modules based on the levels of the plurality of selection signals;
An ECC decoder that detects and corrects a bit string obtained by combining the output of the first selector and the output of the second selector;
Each comprising a plurality of flip-flops provided in a path through which the corresponding selection signal is supplied to the first selector or the second selector;
The semiconductor device according to claim 1, wherein the same clock signal is input to the plurality of flip-flops and the plurality of memory modules.   The plurality of bits of the first group are odd bits among the plurality of bits constituting the output data of each of the plurality of memory modules, and the plurality of bits of the second group are each of the plurality of memory modules. 5. The semiconductor device according to claim 4, wherein the number of bits is an even number of a plurality of bits constituting the output data.   The plurality of bits of the first group are upper half bits of the plurality of bits constituting the output data of each of the plurality of memory modules, and the plurality of bits of the second group are the plurality of memory modules. 5. The semiconductor device according to claim 4, wherein the bits are the lower half bits of a plurality of bits constituting each output data. The plurality of memory modules include a first memory module and a second memory module, and the plurality of selection signals include a first selection signal input to the first memory module, and the first memory module. And a second selection signal input to the memory module,
In a normal state, the selection decoder sets either the first selection signal or the second selection signal as an activation level when the selection permission signal is at an activation level, and the selection permission signal is When at the deactivation level, both the first selection signal and the second selection signal are set to the deactivation level,
The failure determination unit is configured such that when the selection permission signal is at an activation level, the selection decoder is operable when both the first selection signal and the second selection signal are at an activation level or an inactivation level. The semiconductor device according to claim 1, wherein the semiconductor device is determined to be in the failure state.   The failure determination unit is configured such that when the selection permission signal is at an inactivation level, and at least one of the first selection signal and the second selection signal is at an activation level, the selection decoder The semiconductor device according to claim 7, wherein the semiconductor device is determined to be in a failure state.   2. The semiconductor device according to claim 1, wherein data is written in each of the plurality of memory modules only when the corresponding selection signal is at an activation level.   2. The semiconductor device according to claim 1, wherein each of the plurality of memory modules reads data only when the corresponding selection signal is at an activation level. A plurality of memory modules, wherein a plurality of bits representing an address signal indicating a storage position of data in the plurality of memory modules includes a first address bit and a second address bit; Each of which receives the second address bit and outputs an internal address bit generated from the second address bit;
A selection decoder that decodes the first address bits to control the levels of a plurality of selection signals;
A plurality of clock gates each receiving a clock and outputting the clock to the corresponding memory module when the corresponding selection signal is at an activation level;
Each of the plurality of memory modules outputs the internal address bit generated from the latest value of the second address bit when receiving the clock output from the corresponding clock gate,
A selector that selects any of the internal address bits output from the plurality of memory modules based on the levels of the plurality of selection signals;
A semiconductor device comprising: a comparator that compares the address signal with a bit obtained by combining the internal address bit output from the selector and the first address bit.   The semiconductor device according to claim 11, wherein each of the plurality of memory modules continues to hold the value of the internal address bit until the clock from the corresponding clock gate is input. The plurality of memory modules includes two memory modules,
The semiconductor device according to claim 11, wherein the first address bit is a most significant bit of the address signal. A first address input terminal to which a first address signal is input;
A clock input terminal to which a clock signal is input;
A memory array having a plurality of memory cells selectable by a word line;
A data input / output terminal for outputting data from the memory cell and inputting data to the memory cell;
A failure notification output terminal from which a first failure notification signal is output;
A temporary storage circuit that captures the first address signal in synchronization with the clock signal and outputs the first address signal as an internal address bit;
An address decoder that outputs an address decode signal based on the internal address bits;
A word line driving circuit for selecting and driving a corresponding word line of the memory array based on the address decode signal;
A data input / output unit for outputting data of the memory cell selected by the word line to the data input / output terminal;
A memory module, comprising: a first comparator that generates a first failure notification signal by comparing a second address signal with the internal address bits and outputs the first failure notification signal to the failure notification output terminal. The first address signal is composed of a lower first number of bits of the address signal divided by an address divider that divides the address signal output from the CPU.
The memory module according to claim 14, further comprising: a second address input terminal that directly receives the first number of lower bits of the address signal from the CPU as the second address signal. A test address input terminal to which a test address signal is input;
A first selector that selects one of the test address signal and the first address signal and supplies the selected signal to the first comparator as the second address signal; The memory module according to claim 14. A second selector which receives the data of the memory cell supplied from the data input / output unit and the internal address bit, selects either one as memory module output data, and outputs the selected data to the data input / output terminal; With
The second selector selects the internal address bit when receiving the first failure notification signal from the first comparator, and receives the first failure notification signal from the first comparator. The memory module according to claim 15, wherein when there is no data, data of the memory cell is selected. A plurality of memory modules according to claim 15;
The CPU;
An interrupt control unit for notifying the CPU of an interrupt,
The address signal output from the CPU represents a data storage position in the plurality of memory modules,
The address divider for dividing the address signal into an upper second number of first address bits and a lower order first number of second address bits;
The first address input terminal of each of the plurality of memory modules receives the second address bit as the first address signal,
By comparing the first address bit output from the address divider and the second number of address bits higher than the address signal directly sent from the CPU, a second failure notification signal is obtained. A second comparator that generates and outputs to the interrupt controller;
A selection decoder that decodes the second number of address bits above the address signal to control the level of a plurality of selection signals;
Based on the level of the plurality of selection signals, one of the first failure notification signals output from the plurality of memory modules is selected, and the selected first failure notification signal is controlled by the interrupt control. And a third selector for outputting to the semiconductor device. A plurality of memory modules according to claim 17;
The CPU;
An interrupt control unit for notifying the CPU of an interrupt;
An error address holding circuit for holding an error address,
The address signal output from the CPU represents a data storage position in the plurality of memory modules,
The address divider for dividing the address signal into an upper second number of first address bits and a lower order first number of second address bits;
The first address input terminal of each of the plurality of memory modules receives the second address bit as the first address signal,
By comparing the first address bit output from the address divider and the second number of address bits higher than the address signal directly sent from the CPU, a second failure notification signal is obtained. A second comparator that generates and outputs to the interrupt controller;
A selection decoder that decodes the second number of address bits above the address signal to control the level of a plurality of selection signals;
Based on the level of the plurality of selection signals, one of the first failure notification signals output from the plurality of memory modules is selected, and the selected first failure notification signal is controlled by the interrupt control. And a fourth selector for outputting to the error address holding circuit,
The fourth selector selects any one of the memory module output data output from the plurality of memory modules based on the levels of the plurality of selection signals, and selects the selected memory module output data. Output to the error address holding circuit,
The error address holding circuit holds the memory module output data output from the fourth selector when receiving the first failure notification signal. The error address holding circuit receives the first address bit output from the address divider,
The second comparator outputs the second failure notification signal to the error address holding circuit;
20. The semiconductor device according to claim 19, wherein the error address holding circuit holds the first address bit when receiving the second failure notification signal.

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