JP2018205293A - Clocking device, electronic apparatus, and movable body - Google Patents

Abstract

To provide a clocking device capable of more easily performing clocking correction than the prior art.SOLUTION: A clocking device comprises: a first clocking circuit synchronizing with a clock signal and generating first clocking data; a second clocking circuit generating second clocking data updated in a longer cycle than a cycle when the first clocking data is updated; an interface circuit transmitting the first clocking data to an external device and receiving a first correction value from the external device; and a storage circuit storing the first correction value. The first clocking circuit corrects update timing of the second clocking data by setting the first correction value to the first clocking data.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a timing device, an electronic device, and a moving object.

  Patent Document 1 discloses a time synchronization apparatus that synchronizes the time of a slave with a master. Patent Document 2 discloses a system that corrects the slave clock time of a slave based on the master clock time of the master.

  Since both the device described in Patent Document 1 and the system described in Patent Document 2 synchronize slave time information with time information held by the master, the power supply to the master stops and the time information is If it disappears, there is a problem that the time information of the slave cannot be synchronized with the time information of the master until the master acquires the time information after resuming the power supply. In order to solve this problem, there is a case in which a clocking device (real-time clock device) that synchronizes with the time information of the master and can count with a backup power supply even when power supply to the master is stopped may be used. In a general system using such a timing device, the master sets the slave time in units of one second, and the reflection of the set time and the count start timing in the timing device are based on the transmission timing of the command from the master. There are many cases.

Japanese Patent Laying-Open No. 2015-203667 JP-A-4-96115

  By the way, in a system in which a minute error is a problem, there is a case where the master periodically repeats the time setting to the time measuring device in order to ensure the time measuring accuracy of the time measuring device. Thereby, the time of the time measuring device is periodically corrected. However, for example, in such a system, the count initial value of the frequency divider circuit of less than 1 Hz cannot be set as an absolute value, and therefore, a time setting deviation of 1 second at maximum occurs unless timing adjustment is performed by complicated communication control. there is a possibility. Furthermore, when reading the time from the timing device, there is a possibility that a time lag due to communication time or the like may occur. As a result of such time lag, there is a problem that it is difficult to accurately correct the time measured by the time measuring device.

  According to some aspects of the present invention, it is possible to provide a time measuring device capable of performing time correction more easily than in the past. In addition, according to some aspects of the present invention, it is possible to provide an electronic apparatus and a moving body using the time measuring device.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following aspects or application examples.

[Application Example 1]
The timing device according to this application example includes a first timing circuit that generates first timing data in synchronization with a clock signal, and a first timing circuit that is updated at a cycle longer than a cycle at which the first timing data is updated. A second timing circuit that generates two timing data, an interface circuit that transmits the first timing data to an external device and receives a first correction value from the external device, and the first correction value. And a storage circuit for storing, wherein the first timing circuit corrects the update timing of the second timing data by setting the first correction value to the first timing data.

  The timing device according to this application example may further include an oscillation circuit that outputs the clock signal. The second timing circuit may generate the second timing data that is updated at a longer period than the period at which the first timing data is updated based on the clock signal. Here, “based on the clock signal, the second timing data that is updated at a period longer than the period at which the first timing data is updated” is generated by the rising edge of each pulse of the clock signal. In addition to the case where the second timing data is updated at the falling timing, a signal generated at the rising or falling timing of at least some of the pulses of the clock signal (for example, from the first timing circuit) The case where the second time measurement data is updated by a carry signal) is also included.

  According to this application example, the external device recognizes a time shift based on the first time data transmitted from the time measuring device via the interface circuit, and transmits a first correction value for eliminating the time shift to the time measuring device. be able to. Then, the timing device receives the first correction value via the interface circuit, stores the first correction value in the storage circuit, and the first correction value stored in the storage circuit is set as the first timing data. The update timing of the second timing data is corrected. That is, according to the time measuring device according to this application example, the time lag including the communication delay is corrected by the first correction value, so that it is possible to perform time correction more easily than in the past.

[Application Example 2]
In the timing device according to the application example, the first timing circuit sets the first correction value to the first timing data when the first timing data is a predetermined value, so that the update is performed. The timing may be corrected.

  According to the timing device according to this application example, since the first correction value is set in the first timing data at a fixed timing, the external device can accurately correct the update timing of the second timing data. The first correction value to be often performed can be transmitted.

[Application Example 3]
In the timing device according to the application example, the first correction value may be a value generated by the external device based on the first timing data and the timing data included in the external device.

  According to this application example, the external device recognizes a time shift based on the first time measurement data transmitted from the time measuring device via the interface circuit and the reference time measurement data, and an accurate first for eliminating the time shift. The correction value can be transmitted to the timing device. Therefore, according to the timing device according to this application example, it is possible to accurately correct the time lag including the communication delay with the first correction value.

[Application Example 4]
In the timing device according to the application example, the first timing circuit updates the first timing data in units of 1/1000 second, and the second timing circuit updates the second timing in units of 1 second. Data may be updated.

  According to the timing device according to this application example, it is possible to accurately correct a time lag including a communication delay in units of 1/1000 seconds.

[Application Example 5]
In the timing device according to the application example described above, the frequency of the clock signal is 4096 Hz, and the first timing circuit selects 40 and 41 at a ratio of 4 to 96 and sets the number of pulses of the clock signal to 6 A counter that counts in bits may be included, and a count value of the upper 4 bits of the 6-bit count value output by the counter may be output as part of the first time measurement data.

  According to the timing device according to this application example, the low-order time measuring unit can easily calculate the high-order 4-bit count values “0000” to “1001” of the 6-bit count values “000000” to “100111” counted by the counter. With the circuit configuration, it is possible to output time measurement data representing decimal numbers “0” to “9” as 1/1000 second time without increasing current consumption.

[Application Example 6]
In the timing device according to the application example, the storage circuit further stores a second correction value and a correction cycle, and the first timing circuit adds the first timing data to the first timing data in the correction cycle. The update timing may be corrected by setting a second correction value.

  According to the timing device according to this application example, the second correction value stored in the storage circuit is set to the first timing data in the correction cycle stored in the storage circuit, so that the second The timing for updating the timing data is corrected. Therefore, according to the timing device according to this application example, for example, even when the correction of the update timing of the second timing data by the first correction value is not performed for a long time, it occurs due to secular change or the like. It is possible to correct the time difference.

[Application Example 7]
An electronic apparatus according to this application example includes any one of the above timing devices and a control device that transmits the first correction value to the timing device as the external device.

  According to the electronic apparatus according to this application example, since the time lag of the time measuring device including the communication delay is corrected by the first correction value transmitted by the control device, the time correction of the time measuring device is easier than before. Can be done. Therefore, for example, it is possible to realize a more reliable electronic device at a lower cost than in the past.

[Application Example 8]
The moving body according to this application example includes any one of the above timing devices.

  According to the moving body according to this application example, it is possible to perform time correction of the time measuring device more easily than in the past. Therefore, for example, it is possible to realize a moving body having higher reliability than the conventional one at a lower cost.

The figure which shows the functional block of the timing device of 1st Embodiment, and the structural example of a processing system. The figure which shows the structural example of an oscillation circuit. The circuit diagram which shows the structural example of a frequency divider. The figure which shows the structural example of a high-order time measuring part. The figure which shows the structural example of the low-order time measuring part in 1st Embodiment. The figure which shows an example of the timing chart before and behind a second update. The figure which shows another example of the timing chart before and behind the second update. The figure which shows another example of the timing chart before and behind the second update. The flowchart figure which shows an example of the procedure of the process for the time correction by a master control apparatus. The flowchart figure which shows an example of the procedure of the process for the time correction by the time measuring device of 1st Embodiment. The figure which shows the functional block of the timing device of 2nd Embodiment, and the structural example of a processing system. The figure which shows the structural example of the low-order time measuring part in 2nd Embodiment. The flowchart figure which shows an example of the procedure of the process for the time correction by the time measuring device of 2nd Embodiment. The figure which shows the structural example of the time measuring device of the modification 1. FIG. 3 is a functional block diagram illustrating an example of a configuration of an electronic apparatus according to the embodiment. 1 is a diagram illustrating an example of an appearance of an electronic apparatus according to an embodiment. The functional block diagram which shows an example of a structure of the mobile body of this embodiment. The figure which shows an example of the external appearance of the mobile body of this embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Timekeeping device (real-time clock device)
1-1. First Embodiment [Configuration and Operation of Timekeeping Device]
FIG. 1 is a diagram illustrating a configuration example of a functional block of a timing device (real-time clock device) 1 according to the first embodiment and a processing system using the timing device 1. As shown in FIG. 1, the processing system includes a timing device 1, a master control device 2, a plurality of slave devices 3, a main power supply 4, and a backup power supply 5.

The master control device 2 is extremely accurate time information, has master timing data 200 as a reference, and distributes it to each slave device 3 in response to a request from each slave device 3 or periodically. Each slave device 3 performs various processes according to its own internal time in accordance with the master timing data 200. The master timing data 200 is, for example, time information acquired from the GPS (Global Positioning System) or the network by the master control device 2, and the timing error is, for example, 10 ⁻⁶ seconds or less. The master timing data 200 is updated at a necessary timing or periodically.

  The master control device 2 and each slave device 3 operate with power supplied from the main power supply 4 and stop operating when power supply from the main power supply 4 is interrupted. On the other hand, the timing device 1 normally performs the timing operation by being supplied with power from the main power supply 4, but immediately after the power supply from the main power supply 4 is cut off, the power supplied from the backup power supply 5. Switches to the timing operation by. That is, the timing device 1 continues the timing operation while the power supply from the main power supply 4 is interrupted.

When the power supply from the main power supply 4 is resumed, the master control device 2 tries to update the master timing data 200, but the update may take a long time (for example, several minutes to several tens of minutes). Therefore, when the power supply from the main power supply 4 is resumed, the master control device 2 reads the timing data from the timing device 1 and substitutes it as the master timing data 200. In the present embodiment, the master control device 2 reads time data including year, month, day, hour, minute, second, and millisecond information from the time measuring device 1 until it can acquire accurate time data from the GPS or the network. The timing data read from the timing device 1 is set as master timing data 200. In this case, the timing data from the timing device 1 is required to be accurate to an extent that the error is within about 13 seconds per month (about ± 5 ppm when converted to a deviation from the reference frequency), for example.

  As shown in FIG. 1, the timing device 1 includes an oscillation circuit 10, a frequency dividing circuit 20, a frequency dividing circuit 30, an arbitration circuit 40, a lower timing unit 50, an arbitration circuit 60, an upper timing unit 70, an interface circuit 80, and a storage circuit. (Storage unit) 90 and a power supply switching circuit 100 are included. However, the timing device 1 may have a configuration in which some of these elements are omitted or changed, or other elements are added. The time measuring device 1 has a function of a real time clock (RTC) that generates time measuring data by performing a time measuring operation in synchronization with a clock signal.

The oscillation circuit 10 performs an oscillation operation to generate a clock signal CLK0 having a power of 2 frequency, for example, 32768 Hz (= 2 ¹⁵ Hz).

  FIG. 2 is a diagram illustrating a configuration example of the oscillation circuit 10. As shown in FIG. 2, the oscillation circuit 10 includes a vibrator 11, an inverter (logic inversion element) 12, a resistor 13, a capacitor 14, a capacitor group 15, a switch circuit 16, and a decode circuit 17.

  The inverter 12 has an input terminal connected to one end of the vibrator 11 and an output terminal connected to the other end of the vibrator 11. The resistor 13 has one end connected to the input terminal of the inverter 12 and the other end connected to the output terminal of the inverter 12. The capacitor 14 has one end connected to the other end of the resistor 13 and the other end grounded.

  The capacitor group 15 includes a plurality of capacitors, and each of the plurality of capacitors has one end connected to the input terminal of the inverter 12 and the other end grounded via the switch circuit 16 or open (high impedance). Become. The switch circuit 16 makes the other end of each capacitor included in the capacitor group 15 ground or open (high impedance) in accordance with a control signal output from the decode circuit 17. For example, the decode circuit 17 decodes data (capacity selection data) stored in the storage circuit 90 (see FIG. 1) and outputs a control signal for the switch circuit 16.

  In the oscillation circuit 10 configured as described above, the inverter 12 inverts and amplifies the output signal of the vibrator 11 and feeds back the inverted and amplified signal to the vibrator 11. As a result, the vibrator 11 oscillates at a natural resonance frequency or a frequency close thereto, and the output signal of the inverter 12 (a signal obtained by inverting and amplifying the output signal of the vibrator 11) is output from the oscillation circuit 10 as the clock signal CLK0. The Since it is possible to finely adjust the oscillation frequency of the oscillation circuit 10 by changing the combined capacitance value of the capacitor group 15, for example, in the inspection process of the time measuring device 1, the capacitance selection data for obtaining a desired oscillation frequency is determined. The data is written in a nonvolatile memory (not shown) included in the memory circuit 90.

  For example, the oscillation circuit 10 may be a crystal oscillation circuit using a tuning fork type crystal resonator, an AT cut crystal resonator, an SC cut crystal resonator, or the like as the resonator 11, or a SAW (Surface Acoustic) as the resonator 11. (Wave) An oscillation circuit using a piezoelectric vibrator other than a resonator or a crystal vibrator may be used. The oscillation circuit 10 may be an oscillation circuit using a MEMS (Micro Electro Mechanical Systems) vibrator made of a silicon semiconductor as the vibrator 11. The vibrator 11 may be excited by a piezoelectric effect or may be driven by a Coulomb force (electrostatic force).

Returning to FIG. 1, the clock signal CLK <b> 0 output from the oscillation circuit 10 is supplied to the frequency dividing circuit 20. However, the timing device 1 may omit the oscillation circuit 10 and supply the clock signal CLK0 to the frequency dividing circuit 20 from the outside. The frequency dividing circuit 20 generates a clock signal CL.
By dividing K0, a clock signal CLK1 having a frequency of 4096 Hz (= 2 ¹² Hz) is generated.

FIG. 3 is a circuit diagram illustrating a configuration example of the frequency dividing circuit 20. As shown in FIG. 3, the frequency dividing circuit 20 is configured by connecting, for example, T (toggle) type flip-flops 21 to 23 in series. Each of the T-type flip-flops 21 to 23 divides the signal input to the input terminal T by 2 by inverting the output signal every time the signal input to the input terminal T changes by one cycle. Accordingly, the frequency dividing circuit 20 divides the clock signal CLK0 having a frequency of 32768 Hz (= 2 ¹⁵ Hz), for example, by 8 (= 2 ³ ), and has a frequency of 4096 Hz (= 2 ¹² Hz). Generate CLK1. FIG. 3 shows a configuration example of the frequency dividing circuit 20 when the clock signal CLK0 is 32768 Hz (= 2 ¹⁵ Hz). The clock signal CLK0 is 2 ^N Hz (N is an integer of 13 or more). If so, a configuration in which N-12 T-type flip-flops are connected in series may be used.

  Returning to FIG. 1, the clock signal CLK <b> 1 is supplied to the frequency dividing circuit 30 and is also supplied to the lower timer unit 50 through the arbitration circuit 40. The frequency dividing circuit 30 divides the clock signal CLK1 to generate a clock signal CLK2 having an arbitrary frequency. Similarly to the frequency divider circuit 20 (FIG. 3), the frequency divider circuit 30 may be configured by a number of T-type flip-flops corresponding to the frequency division ratio. The clock signal CLK2 may be supplied to various circuits inside the timing device 1, or may be output to the outside of the timing device 1 and supplied to various devices.

  The lower timing unit 50 (an example of “first timing circuit”) generates timing data T1 and T0 (an example of “first timing data”) by performing a timing operation in synchronization with the clock signal CLK1. . The time data T1 is time data representing time in units of 1/100 seconds, and the time data T0 is time data representing time in units of 1/1000 seconds. That is, the lower timing unit 50 updates the timing data T1 and T0 in units of 1/1000 second. Further, the lower timing unit 50 generates a clock signal CLK3 having a frequency of 1 Hz based on the clock signal CLK1. The clock signal CLK3 is supplied to the upper timer unit 70 via the arbitration circuit 40. Further, the lower timing unit 50 generates a count disable signal CNTDIS that stops the timing operation of the upper timing unit 70.

  The upper timer unit 70 performs timing operation in synchronization with the clock signal CLK3 generated on the basis of the clock signal CLK1, thereby measuring time data updated in a longer cycle than the cycle in which the time data T1 and T0 are updated. For example, the time data T8 representing the time in seconds and the time data T8 representing the time in years are generated.

The interface circuit 80 is an interface circuit for communication between the timing device 1 and the master control device 2, receives various commands from the master control device 2, and writes various data to the storage circuit 90 in accordance with the received commands. And reading, generation of various control signals, reading of timing data from the lower timing unit 50 and the upper timing unit 70, and the like. The interface circuit 80 may be an interface circuit compatible with various serial buses such as SPI (Serial Peripheral Interface) and I ² C (Inter-Integrated Circuit), or may be an interface circuit compatible with a parallel bus. Good.

In the present embodiment, when the interface circuit 80 receives a timing data read command with an address specified, the interface circuit 80 activates one of the read enable signals E0 to E8 (for example, high level) according to the address specified in the received command. To. When the read enable signal E0 becomes active, the lower timing unit 50 outputs the timing data T0 to the interface circuit 80, and outputs the timing data T1 to the interface circuit 80 when the read enable signal E1 becomes active. Similarly, when the read enable signals E <b> 2 to E <b> 8 are activated, the upper timer unit 70 outputs time measurement data T <b> 2 to T <b> 8 to the interface circuit 80, respectively. Then, the interface circuit 80 transmits any of the timing data T0 to T8 output from the lower timing unit 50 or the upper timing unit 70 to the master control device 2 (an example of “external device”). Note that when receiving the time data read command, the interface circuit 80 may sequentially activate the read enable signals E0 to E8, sequentially acquire the time data T0 to T8, and continuously transmit them to the master controller 2.

  In the present embodiment, the interface circuit 80 receives an offset setting command in which offset data in units of 1/1000 second in a range of −999 milliseconds to +999 milliseconds used for time measurement by the lower time measuring unit 50 is specified. The offset data specified in the received command is written in the offset register 91 of the storage circuit 90, and the flag set signal FS is activated (for example, high level) and output to the lower time measuring unit 50. The offset data OFS held in the offset register 91 is supplied to the lower timer unit 50 and cleared to zero when the clear signal CLR1 output from the lower timer unit 50 becomes active.

The storage circuit 90 includes, for example, a register group including an offset register 91 and a nonvolatile memory that stores various control data such as capacity selection data. Each data stored in the nonvolatile memory is transferred from the nonvolatile memory to each register and held when the timing device 1 is started, and each part of the timing device 1 is controlled according to the data held in each register. . Non-volatile memory is, for example, EEPROM (Electrically
Various rewritable nonvolatile memories such as Erasable Programmable Read-Only Memory (Erasable Programmable Read-Only Memory) and flash memory, and various non-rewritable nonvolatile memories such as One Time Programmable Read Only Memory (PROM) It may be.

  The arbitration circuit 40 is included in the clock signal CLK1 during a period in which the timing data is read so that the timing data does not change while the timing data is being read from the lower timing unit 50 or the upper timing unit 70. Delay the pulse. In other periods, the arbitration circuit 40 outputs the clock signal CLK1 supplied from the frequency dividing circuit 20 as it is. Similarly, the arbitration circuit 60 uses a pulse included in the clock signal CLK3 during a period in which the time data is being read so that the time data does not change while the time data is being read from the higher-order time unit 70. Delay. In other periods, the arbitration circuit 60 outputs the clock signal CLK3 supplied from the lower timing unit 50 as it is. If the interface circuit 80 always transmits the timing data T0 to T8 continuously to the master control device 2, the arbitration circuit 40 delays the pulse included in the clock signal CLK1 during that period. The arbitration circuit 60 is not necessary.

  The power supply switching circuit 100 outputs the power supply voltage VA as the power supply voltage (operating voltage) of each part of the time measuring device 1 when the main power supply 4 is supplied with a power supply voltage VA equal to or higher than a predetermined voltage value. Is switched to output the power supply voltage VB output from the backup power supply 5. In other words, the timing device 1 can continue the timing operation by the power supply switching circuit 100 using the power supply voltage VB supplied from the backup power supply 5 even when the desired power supply voltage VA is not supplied from the main power supply 4.

[Configuration and operation of the upper timing unit]
FIG. 4 is a diagram illustrating a configuration example of the upper timer unit 70. As shown in FIG. 4, the upper timer unit 70 includes counters 71a to 74a, a shift register 75a, counters 76a and 77a, and output control circuits 71b to 77b. Each of the output control circuits 71b to 77b includes, for example, a plurality of transmission gates.

  The counter 71a (an example of a “second clock circuit”) generates a count value representing time in seconds by performing a count operation in synchronization with the clock signal CLK3. For example, the counter 71a is a 60-digit BCD (binary coded decimal) counter, and sequentially generates BCD count values representing decimal numbers “0” to “59” in synchronization with the pulse of the clock signal CLK3. When the count value becomes equal to the value representing the decimal number “59”, the counter 71a resets the count value to “0” and outputs the carry signal CA1 in synchronization with the next pulse of the clock signal CLK3. However, when the count disable signal CNTDIS is active, the counter 71a does not perform the counting operation even if the pulse of the clock signal CLK3 is supplied, and holds the BCD count value at that time.

  The count value generated by the counter 71a is used as time data T2 (an example of “second time data”) representing time in seconds. That is, the counter 71a updates the time measurement data T2 in units of 1 second. When the read enable signal E2 becomes active, the output control circuit 71b outputs the time measurement data T2 generated by the counter 71a to the interface circuit 80.

  The counter 72a generates a count value representing time in minutes by performing a count operation in synchronization with the carry signal CA1. For example, the counter 72a is a 60-digit BCD counter, and sequentially generates BCD count values representing decimal numbers “0” to “59” in synchronization with the pulse of the carry signal CA1. When the count value becomes equal to the value representing the decimal number “59”, the counter 72a resets the count value to “0” and outputs the carry signal CA2 in synchronization with the next pulse of the carry signal CA1.

  The count value generated by the counter 72a is used as time measurement data T3 representing the time in minutes. That is, the counter 72a updates the time measurement data T3 in units of minutes. When the read enable signal E3 becomes active, the output control circuit 72b outputs the timing data T3 generated by the counter 72a to the interface circuit 80.

  The counter 73a performs a count operation in synchronization with the carry signal CA2, thereby generating a count value representing time in hours. For example, the counter 73a is a 24 BCD counter and sequentially generates BCD count values representing decimal numbers “0” to “23” in synchronization with the pulse of the carry signal CA2. When the count value becomes equal to the value representing the decimal number “23”, the counter 73a resets the count value to “0” and outputs the carry signal CA3 in synchronization with the next pulse of the carry signal CA2.

  The count value generated by the counter 73a is used as time-measurement data T4 representing time in time units. That is, the counter 73a updates the time measurement data T4 on an hourly basis. When the read enable signal E4 becomes active, the output control circuit 73b outputs the timing data T4 generated by the counter 73a to the interface circuit 80.

  The counter 74a performs a count operation in synchronization with the carry signal CA3, thereby generating a count value that represents a time in days. For example, the counter 74a is a decimal BCD counter, and sequentially generates BCD count values representing decimal numbers “1” to “31” in synchronization with the pulse of the carry signal CA3.

However, depending on the month, the last day of the month needs to be “28” or “30”, and in the case of February in a leap year, the last day of the month needs to be “29”. Thus, the counter 74a compares the count value representing the time in the day with the count upper limit value set based on the count value representing the time in the month and the count value representing the time in the year. When the count value becomes equal to the count upper limit value, the counter 74a resets the count value to “1” and outputs the carry signal CA4 in synchronization with the next pulse of the carry signal CA3.

  The count value generated by the counter 74a is used as time measurement data T5 representing the time in days. That is, the counter 74a updates the time measurement data T5 on a daily basis. When the read enable signal E5 becomes active, the output control circuit 74b outputs the timing data T5 generated by the counter 74a to the interface circuit 80.

  The shift register 75a generates time measurement data T6 representing the day of the week in synchronization with the carry signal CA3. For example, the shift register 75a is a 7-bit shift register including seven D-type flip-flops connected in a ring shape. The seven flip-flops correspond to seven days of the week from Sunday to Saturday.

  When setting the initial state, the interface circuit 80 sets the data of one flip-flop to “1” and sets the data of the other flip-flop to “0” according to the 7-bit initial value data supplied from the master control device 2. To "". Thereafter, the shift register 75a shifts the day data in one direction in synchronization with the carry signal CA3. Therefore, the current day of the week is represented by the position of data “1” in the seven flip-flops of the shift register 75a.

  The day of the week data generated by the shift register 75a is used as time measurement data T6 representing the day of the week. That is, the shift register 75a updates the time measurement data T6 in units of days. When the read enable signal E6 becomes active, the output control circuit 75b outputs the timing data T6 generated by the shift register 75a to the interface circuit 80.

  The counter 76a performs a count operation in synchronization with the carry signal CA4, thereby generating a count value representing the time in units of months. For example, the counter 76a is composed of a decimal BCD counter, and sequentially generates BCD count values representing decimal numbers “1” to “12” in synchronization with the pulse of the carry signal CA4. When the count value becomes equal to the value representing the decimal number “12”, the counter 76a resets the count value to “1” and outputs the carry signal CA5 in synchronization with the next pulse of the carry signal CA4.

  The count value generated by the counter 76a is used as time measurement data T7 representing the time in units of months. That is, the counter 76a updates the time measurement data T7 on a monthly basis. When the read enable signal E7 becomes active, the output control circuit 76b outputs the timing data T7 generated by the counter 76a to the interface circuit 80.

  The counter 77a performs a count operation in synchronization with the carry signal CA5, thereby generating a count value representing time in units of years. For example, the counter 77a is composed of a decimal BCD counter, and in synchronization with the pulse of the carry signal CA5, the decimal number “2015”, “2016”, “2017”,. BCD count values representing two digits are sequentially generated.

  The count value generated by the counter 77a is used as time-measurement data T8 representing time in units of years. That is, the counter 77a updates the time measurement data T8 in units of years. When the read enable signal E8 becomes active, the output control circuit 77b outputs the timing data T8 generated by the counter 77a to the interface circuit 80.

[Configuration and operation of sub-timer]
FIG. 5 is a diagram illustrating a configuration example of the lower timing unit 50. As shown in FIG. 5, the lower timing unit 50 includes a count control circuit 51, a counter 52, an output control circuit 53, a control flag register 54, a counter 55, an output control circuit 56, a data conversion circuit 57, a status flag register 58, and a minute. The circuit includes peripheral circuits 59a and 59b.

  The counter 52 is composed of, for example, a 6-bit binary counter. The counter 52 performs a counting operation in synchronization with a pulse of the clock signal CLK1 having a frequency of 4096 Hz in order to perform a timekeeping operation in units of 1/100 second, and thereby, in each count cycle, a decimal number “0”. To “39” are generated as 6-bit C5 to C0 count values. Here, C5 is the most significant bit and C0 is the least significant bit.

  The output control circuit 53 is composed of, for example, a plurality of transmission gates. When the read enable signal E0 becomes active, the output control circuit 53 uses the upper 4 bits C5 to C2 of the count value generated by the counter 52 as 4-bit timing data T0 representing time in units of 1/1000 second. Output to 80.

  Since one cycle of the clock signal CLK1 is about 244 microseconds, the time data T0 representing the time in units of 1/1000 second is generated by selecting the upper 4 bits C5 to C2 of the count value of the counter 52. As described above, according to the present embodiment, the upper 4 bits “0000” to “1001” of the 6-bit count values “000000” to “100111” generated in order to perform the timing operation in units of 1/100 second are calculated. By selecting, it is possible to generate 4-bit timing data T0 representing decimal numbers “0” to “9” as a time in 1/1000 second without increasing current consumption by a simple circuit configuration. it can.

  However, the four periods of the clock signal CLK1 include an error of about −23.4 microseconds with respect to 1/1000 second. In order to eliminate this error, the counting operation performed by the counter 52 includes a 40-count cycle in which the count value sequentially changes from “0” to “39” and then returns to “0”, and the count value continues twice. 41 count cycles returning to “0” after becoming “39” are included. Therefore, the low-order time measuring unit 50 is provided with a control flag register 54 for storing a 1-bit count control flag FL1 representing information of the 40th count. The control flag register 54 is composed of, for example, a D-type flip-flop.

  When setting the initial state, the count control circuit 51 sets the count initial value supplied from the interface circuit 80 in the counter 52 and the counter 55, and sets the count control flag FL1 stored in the control flag register 54 to “0”. Reset. The count control circuit 51 is configured by a state machine including a sequential circuit, for example.

  The count values of 6 bits C5 to C0 generated by the counter 52 are also supplied to the count control circuit 51. When the count cycle is a predetermined number of times, the count control circuit 51 sets the count control flag FL1 to “1” when the count value generated by the counter 52 becomes equal to the value representing the decimal number “39”. . Thereby, the counter 52 maintains the count value even when the next pulse of the clock signal CLK1 arrives, and the first state in which the counter value is reset to “0” in synchronization with the further next pulse of the clock signal CLK1. A transition is set.

On the other hand, when the count cycle is not a predetermined number of times, the count control circuit 51 determines that the count value generated by the counter 52 is equal to the value representing the decimal number “39”.
The count control flag FL1 is maintained at “0”. Thereby, the second state transition is set in which the counter 52 resets the count value to “0” in synchronization with the next pulse of the clock signal CLK1.

  In the 41 count cycle, the period of one count cycle corresponds to 41 cycles of the clock signal CLK1 having a frequency of 4096 Hz, which is about 10.01 milliseconds. On the other hand, in the 40 count cycle, the period of one count cycle corresponds to 40 cycles of the clock signal CLK1, which is about 9.77 milliseconds. Therefore, the count control circuit 51 sets the 41-count cycle 96 times and the 40-count cycle 4 times among the 100 consecutive count cycles, thereby setting the 41-count cycle and the 40-count cycle. The error in the cycle can be relaxed, and the time error represented by the time measurement data can be reduced.

  For example, in the count control circuit 51, the count value generated by the counter 52 is sufficient in cycles other than the thirteenth, thirty-eighth, the thirty-sixth, and the eighty-eighth out of 100 consecutive cycles. When it becomes equal to the value representing the decimal number “39”, the first state transition is set by setting the count control flag FL1 to “1”. In the first state transition, the count control circuit 51 stops the count operation of the counter 52 and resets the count control flag FL1 to “0” in synchronization with the next pulse of the clock signal CLK1. In addition, the count control circuit 51 cancels the stop of the counting operation of the counter 52 and resets the count value to “0” in synchronization with the next pulse of the clock signal CLK1, and counts only during the one pulse. The enable signal CNTEN is activated (for example, high level). Thereby, a cycle of 41 counts is realized.

  In addition, the count control circuit 51 determines that the count value generated by the counter 52 is a decimal number in the thirteenth, thirty-eighth, the thirty-sixth, and the eighty-eighth cycles in 100 consecutive cycles. Is set equal to a value representing “39”, the second state transition is set by maintaining the count control flag FL1 at “0”. In the second state transition, the count control circuit 51 resets the count value of the counter 52 to “0” in synchronization with the next pulse of the clock signal CLK1, and also outputs the count enable signal CNTEN only during the one pulse. Activate. Thereby, a cycle of 40 counts is realized.

  In this way, the counter 52 selects 40 and 41 at a ratio of 4 to 96, and counts the number of pulses of the clock signal CLK1 having a frequency of 4096 Hz with 6 bits. , T0, the upper 4 bit count value of the 6 bit count value output by the counter 52 is output as the timing data T0. Therefore, the low-order time measuring unit 50 consumes almost no current with a simple circuit configuration by the high-order 4-bit count values “0000” to “1001” of the 6-bit count values “000000” to “100111” counted by the counter 52. Without increasing, it is possible to output time measurement data T0 representing decimal numbers “0” to “9” as a time in units of 1/1000 second.

  The count enable signal CNTEN output from the count control circuit 51 is supplied to the counter 55. The counter 55 performs a count operation in synchronization with the clock signal CLK1 when the count enable signal CNTEN is active, thereby generating a count value representing a time in units of 1/100 seconds.

  The counter 55 is composed of, for example, an 8-bit decimal BCD counter. The BCD count value generated by the counter 55 includes 4 bits B7 to B4 representing 1 / 10th of a decimal number and 4 bits B3 to B0 representing 1 / 100th of a decimal. .

  The counter 55 sequentially generates count values representing decimal numbers “0” to “99” in synchronization with the pulse of the clock signal CLK1 when the count enable signal CNTEN is active. When the count value becomes equal to the value representing the decimal number “99”, the counter 55 resets the count value to “0” in synchronization with the pulse of the clock signal CLK1 when the count enable signal CNTEN is active next. .

The period of 100 counts of the counter 55 is 4096 ⁻¹ × (41 × 96 + 40 × 4) = 1 second. In addition, although one count period of the counter 55 includes an error of about ± 117 microseconds at the maximum, it accurately corresponds to a 1/100 second period in the long term.

  The upper 4 bits B7 to B4 and the lower 4 bits B3 to B0 of the count value generated by the counter 55 are used as time measurement data T1 representing the time in units of 1/100 seconds. The output control circuit 56 is configured by, for example, a plurality of transmission gates and the like, and outputs the timing data T1 generated by the counter 55 to the interface circuit 80 when the read enable signal E1 becomes active.

  Further, the counter 55 sets four cycles in which only the first pulse of the supplied clock signal CLK1 is output as it is, out of 100 count cycles in which decimal numbers “0” to “99” are counted. At the same time, the clock signal CLK4 having a frequency of 4 Hz is output by setting a cycle in which no pulse of the clock signal CLK1 is output 96 times. For example, the counter 55 outputs the first pulse of the clock signal CLK1 only in four cycles in which the count values are decimal numbers “0”, “25”, “50”, and “75”. A clock signal CLK4 is generated based on the signal CLK1.

  The frequency dividing circuit 59a divides the clock signal CLK4 having a frequency of 4 Hz by 2 to generate a clock signal CLK5 having a frequency of 2 Hz. Further, the frequency dividing circuit 59b generates a clock signal CLK3 having a frequency of 1 Hz by dividing the clock signal CLK5 having a frequency of 2 Hz by two. The rising edge of the clock signal CLK3 coincides with the timing at which the count value of the counter 55 is updated from the decimal number “99” to “0”.

  The data conversion circuit 57 converts the offset data OFS in units of 1/1000 second in the range of −999 milliseconds to +999 milliseconds held in the offset register 91 into a signed 13-bit BCD offset value and outputs the result. . In this signed 13-bit BCD offset value, the 12th bit is the code value SIGN, the 11th to 4th bits are the offset value OFS1 set in the bits B7 to B0 of the counter 55, and the 3rd to 0th bits are This is the offset value OFS0 set in the bits C5 to C2 of the counter 52. In the range where the offset data OFS is 0 to +999 milliseconds, the sign value SIGN is “0”, and the offset value OFS1 and the offset value OFS0 are respectively the upper two digits of the decimal number corresponding to the offset data OFS and the lower order. Corresponds to a single digit value. For example, if the offset data OFS is +123 milliseconds, the 13-bit BCD offset value is “00001001000011” (corresponding to +123). On the other hand, when the offset data OFS is in the range of −999 milliseconds to −1 milliseconds, the code value SIGN is “1”, and the offset value OFS1 and the offset value OFS0 are respectively changed from the decimal number “1000” to the offset data OFS. It corresponds to the numerical value of the upper 2 digits and the numerical value of the lower 1 digit obtained by subtracting the decimal number corresponding to. For example, if the offset data OFS is +123 milliseconds, the 13-bit BCD offset value is “1100001110111” (corresponding to −877).

The status flag register 58 stores a status flag FL2. The status flag FL2 is set to “1” when the flag set signal FS changes from inactive to active. The status flag register 58 is composed of, for example, an SR (set / reset) type flip-flop.

  The count control circuit 51 synchronizes with the pulse of the clock signal CLK1 when the count enable signal CNTEN becomes active when the count value of the counter 55 is decimal "99" and the status flag FL2 is "1". Then, the bits B7 to B0 of the count value of the counter 55 are updated to the offset value OFS1, the bits C5 to C2 of the counter value of the counter 52 are updated to the offset value OFS0, and the bits C1 and C0 are updated to “00”. . At the same time, the count control circuit 51 outputs the clear signal CLR1 only for one pulse of the clock signal CLK1, and the offset data OFS is cleared to zero by the clear signal CLR1. If the code value SIGN is “1”, the count control circuit 51 activates the count disable signal CNTDIS only during the pulse of the clock signal CLK1, and outputs a pulse of the clock signal CLK4 having a frequency of 4 Hz. do not do. By updating the count values of the counter 55 and the counter 52 to the offset values OFS1 and OFS0 (offset setting process), the update timing of the timing data T2 (seconds) by the upper timing unit 70 is changed in units of 1/1000 second. be able to. The offset setting process is performed in preference to the counting operation of the counter 55 and the counter 52 (operation for advancing the count value by 1).

  FIG. 6 is a diagram illustrating an example of a timing chart before and after the second update when the offset setting process is not performed. 7 and 8 are diagrams illustrating examples of timing charts before and after the second update when the offset setting process is performed.

  In the example of FIG. 6, the timing data T1 (1/100 second) is updated from “99” to “0”, and the timing data T0 (1/1000 seconds) is updated from “9” to “0”. At the timing (second update timing), the time measurement data T2 (seconds) is updated from “59” to “0”.

  On the other hand, in the example of FIG. 7 and FIG. 8, the lower timing unit 50 has the timing data T1 (1/100 second) of “99” and the timing data T0 (1/1000 second) of “9”. ”(When the timing data T1 and T0 are a predetermined value“ 999 ”determined in advance), that is, at the timing when the timing data T2 (seconds) is scheduled to be updated (second update scheduled timing), the timing data T1 By setting the offset values OFS1, OFS0 in (1/100 seconds) and T0 (1/1000 seconds), the update timing of the timing data T2 (seconds) is corrected. Therefore, in the example of FIG. 7, the time measurement data T1 (1/100 second) is updated from “99” to “0” (offset value OFS1) in synchronization with the clock signal CLK1 (not shown), and the time measurement data is updated. T0 (1/1000 second) is updated from “9” to “3” (offset value OFS0). At the second update scheduled timing, the time measurement data T2 (seconds) is updated from “59” to “0”. That is, when the code value SIGN is “0” (the offset data OFS is zero or a positive value), the timing of the offset setting process (second update scheduled timing) coincides with the second update timing.

On the other hand, in the example of FIG. 8, the time measurement data T1 (1/100 second) maintains “99” (“99” (offset value OFS1) is set) and the clock signal CLK1 ( In synchronization with (not shown), the timing data T0 (1/1000 second) is updated from “9” to “7” (offset value OFS0). The time measurement data T2 (seconds) maintains “59” at the second update scheduled timing, and is updated from “59” to “0” after 3/1000 seconds. That is, when the code value SIGN is “1” (offset data OFS is a negative value), the second update timing is delayed from the offset setting processing timing (second update scheduled timing).

[Time correction]
The above-described offset setting process by the time measuring device 1 is used for time correction in units of 1/1000 second. FIG. 9 is a flowchart illustrating an example of a processing procedure for the time correction of the time measuring device 1 by the master control device 2. FIG. 10 is a flowchart illustrating an example of a processing procedure for timing correction by the timing device 1.

  As shown in FIG. 9, when the power supply from the main power supply 4 starts (Y in step S10), the master control device 2 first determines whether or not the timing data of the timing device 1 can be used ( S20). For example, the master control device 2 determines whether or not there is an abnormality in the timing operation during the backup operation by the timing device 1 (while the power from the main power supply is cut off). It is determined that the timing data of the device 1 can be used, and if there is an abnormality, it is determined that it cannot be used. For example, the timing device 1 includes a circuit for detecting an abnormality such as oscillation stop of the oscillation circuit 10 or a power supply voltage of the timing device 1 (an output voltage of the power supply switching circuit 100) being lower than a predetermined voltage value. Is stored in the memory circuit 90. Then, the master control device 2 may read flag information indicating a result of abnormality detection from the timing device 1 and determine whether or not the timing data of the timing device 1 can be used.

  When it is determined that the timing data of the timing device 1 can be used (Y in Step S20), the master control device 2 transmits a timing data read command to the timing device 1 (Step S30).

  Next, the master control device 2 waits until time data is received from the time measuring device 1 (N in step S40). When time data is received (Y in step S40), the master control device 2 is based on the received time data T0 to T8. The master timing data 200 is updated (step S50). In the procedure of FIG. 9, it is assumed that all the timing data T0 to T8 are received in steps S30 and S40, but only the necessary timing data including at least the timing data T0 and T1 is sequentially received. Good.

  On the other hand, when it is determined that the timing data of the timing device 1 cannot be used (N in Step S20), the master control device 2 separately performs an initial time adjustment process on the timing device 1 (Step S60).

  Next, the master control device 2 starts various processes (step S70). The master control device 2 performs, for example, processing for distributing the master timing data 200 to each slave device 3.

  Next, the master control device 2 waits until the time information is acquired from the GPS or the network (N in Step S80). When the time information is acquired (Y in Step S80), the master timekeeping is performed based on the acquired time information. Data 200 is updated (step S90).

  Next, the master control device 2 transmits a timing data read command to the timing device 1 (step S100).

Next, the master control device 2 waits until receiving time data from the time measuring device 1 (N in step S110). When time data is received (Y in step S110), the master time data 200 and the received time data T0 are received. The relative deviation from ~ T8 is calculated, and offset data corresponding to the deviation is generated (step S120). The master control device 2 generates positive offset data corresponding to the delay time when the timing data T0 to T8 is behind the master timing data 200, and the timing data T0 to T8 is greater than the master timing data 200. If it is advanced, negative offset data corresponding to the advance time is generated.

  Next, the master control device 2 transmits an offset setting command in which the generated offset data is designated to the timing device 1 (step S130). Thereby, in the time measuring apparatus 1, an offset setting process is performed and time correction is implement | achieved.

  Next, when a predetermined time has elapsed (N in Step S140), the master control device 2 performs the processes after Step S100 again. Here, the predetermined time corresponds to the timing correction period, and may be, for example, a time in which the relative deviation between the master timing data 200 and the timing data T0 to T8 does not become ± 1 second or more. In this way, it is not necessary to reset the time measurement data T2 to T8 for time correction, and the processing of the master control device 2 is simplified.

  On the other hand, when the power from the main power supply 4 is cut off before the predetermined time has elapsed (N in step S140 and Y in step S150), the master control device 2 resumes the power supply from the main power supply 4 (N in step S10). Then, when the power supply from the main power supply 4 is resumed (Y in step S10), the master control device 2 performs the processes after step S20 again. Note that the timing device 1 continues the timing operation with the power supplied from the backup power source 5 even while the power from the main power source 4 is cut off. Therefore, immediately after the power supply from the main power supply 4 is restarted, the master control device 2 uses the time data T0 to T8 with relatively high accuracy from the time measuring device 1 that has been time-corrected by the processing of the previous step S130. The timing data 200 can be updated. Thereafter, the master control device 2 can acquire time information from the GPS or the network, update the master timing data 200 to an accurate time, and can correct the timing of the timing device 1 based on the accurate master timing data 200. .

  On the other hand, as shown in FIG. 10, when the master control device 2 receives the time data read command transmitted in step S30 or step S100 in FIG. 9 (Y in step S210), the time measuring device 1 measures the time data T0. -T8 is transmitted to the master controller 2 (step S220).

  When the time measuring device 1 receives the offset setting command transmitted by the master control device 2 in step S130 of FIG. 9 (Y in step S230), first, the offset data specified by the received offset setting command is stored in the offset register 91. (Step S240).

  Next, the timing device 1 converts the offset data OFS held in the offset register 91 into a code value SIGN and offset values OFS1, OFS0 (step S250).

  Next, the timing device 1 stands by until the second update scheduled timing arrives (N in step S260). Then, when the second update scheduled timing arrives (Y in step S260), the timing device 1 updates the count values of the counters 55 and 52 of the lower timing unit 50 to the offset values OFS1 and OFS0 (step S270), and after step S210. Repeat the process.

As described above, the master control device 2 and the timing device 1 perform the processing shown in FIGS. 9 and 10, respectively, so that the master control device 2 periodically performs the processing based on the timing data T1 and T0 and the master timing data 200. The generated offset data OFS (an example of “first correction value”) is stored in the storage circuit 90 (offset register 91), and the offset data OFS (offset) is added to the timing data T1 and T0 at the scheduled update timing of the timing data T2. The value OFS1, OFS0) is set. As a result, the time correction in the 1/1000 second unit of the time measuring device 1 is periodically performed.

[Function and effect]
As described above, in the present embodiment, the master control device 2 calculates the relative deviation between the timing data T0 to T8 read from the timing device 1 and the accurate master timing data 200, and eliminates the deviation. The offset data OFS is transmitted to the timing device 1. Then, the timing device 1 receives the offset data OFS and stores it in the offset register 91. The lower timing unit 50 of the timing device 1 sets the offset data OFS (offset values OFS1, OFS0) stored in the offset register 91 to the timing data T1 (1/100 seconds) and T0 (1/1000 seconds). Thus, the update timing of the timing data T2 (seconds) is corrected. Specifically, the timing device 1 sets the offset data OFS in the range of −999 milliseconds to −1 milliseconds, thereby delaying the update timing of the timing data T2 (seconds) in units of 1/1000 seconds. By setting the offset data OFS in the range of +1 millisecond to +999 milliseconds, the update timing of the timing data T2 (second) is advanced in units of 1/1000 second. Here, since the communication delay required for reading the timing data T0 to T8 is the same every time in 1/1000 second units, if the master control device 2 reads the timing data T0 to T8 immediately after correction, Deviation is zero. In other words, the timing device 1 measures the time difference T0 to T8 read from the master timing data 200 by a delay time required for reading the timing data T0 to T8, so that the timing data T0 to T8 read by the master control device 2 becomes the master. The state coincides with the timing data 200 (the timing data T0 to T8 can be substituted as the master timing data 200). As described above, according to the time measuring device 1 of the first embodiment, the time lag including the communication delay with the master control device 2 is corrected by the offset data OFS. It can be carried out.

1-2. Second Embodiment FIG. 11 is a diagram illustrating a configuration example of a processing system using a functional block of a timing device (real-time clock device) 1 and a timing device 1 according to a second embodiment. In FIG. 11, the same components as those in FIG. Description is omitted.

  As shown in FIG. 11, the timing device 1 according to the second embodiment is similar to the timing device 1 according to the first embodiment. The oscillation circuit 10, the frequency dividing circuit 20, the frequency dividing circuit 30, the arbitration circuit 40, and the subordinate time measuring unit 50. , An arbitration circuit 60, a host timing unit 70, an interface circuit 80, a storage circuit 90, and a power supply switching circuit 100, and further includes a timing correction unit 110. In the time measuring device 1 of the second embodiment, the time correction data 92 is stored in the storage circuit 90.

  The time correction data 92 is data for correcting a time shift that occurs with the passage of time, and includes information on a correction value (an example of a “second correction value”) and information on a correction cycle. . For example, when it is known in advance that the timekeeping of the time measuring device 1 is delayed (or advanced) by about X seconds in one year based on information such as the accuracy of the vibrator 11 and the secular change of the vibrator 11, the correction cycle is set. Time correction data with a correction value of + X × Y / 12 seconds (or −X × Y / 12 seconds) may be set for Y months. For example, Y is selected such that (X × Y / 12 <1) so that the correction value is in the range of −999 milliseconds to +999 milliseconds. The time correction data 92 (correction value and correction cycle) may be written in advance in a non-volatile memory (not shown) of the storage circuit 90 in the inspection process or the like of the time measuring device 1, or the master control device 2 stores the storage circuit. 90 may be written. Further, the time correction data 92 (correction value and correction cycle) may be variable during the operation of the time measuring device 1.

  The time correction unit 110 corrects the time measurement data T1 (1/100 seconds) and T0 (1/1000 seconds) based on the time correction data 92 stored in the storage circuit 90. Specifically, the time correction unit 110 determines whether or not the correction period has elapsed based on the correction period included in the time correction data 92 and the time measurement data T2 to T8. The time correction unit 110 writes the correction value included in the time correction data 92 to the offset register 91 as the offset data OFS and activates the flag set signal FS2 (for example, high level) every time the correction period elapses. Is output to the lower timing unit 50. The offset data OFS held in the offset register 91 is supplied to the lower timer unit 50 and cleared to zero when the clear signal CLR1 output from the lower timer unit 50 becomes active.

  As described above, in the timing device 1 of the second embodiment, the offset register 91 is also used, and in the same way as the timing device 1 of the first embodiment, by receiving the offset setting command from the master control device 2, a unit of 1/1000 second is obtained. In addition, it is possible to perform the time correction in the period of 1/1000 second periodically in the correction cycle included in the time correction data 92.

  Note that a value of +1 second or more or −1 second or less may be allowed as a correction value included in the time correction data 92. In this case, the time correction unit 110 writes a value less than 1 second of the correction value to the offset register 91 to correct the time measurement data T1 (1/100 seconds) and T0 (1/1000 seconds) (offset correction). What is necessary is just to correct | amend at least one part of time-measurement data T2 (second)-T8 (year) based on the value of 1 second or more of a correction value.

  FIG. 12 is a diagram illustrating a configuration example of the lower timing unit 50 in the second embodiment. As shown in FIG. 12, the lower timing unit 50 in the second embodiment is configured to include an OR circuit 120 in addition to the same configuration as the lower timing unit 50 (FIG. 5) in the first embodiment. ing.

  The logical sum circuit 120 outputs a logical sum signal of the flag set signal FS and the flag set signal FS2. That is, the OR circuit 120 outputs a high level (active) signal when at least one of the flag set signal FS and the flag set signal FS2 is at a high level (active), and the flag set signal FS and the flag set signal FS2 are When both are low level (inactive), a low level (inactive) signal is output. The state flag FL2 stored in the state flag register 58 is set to “1” when the output signal of the OR circuit 120 changes from inactive to active. That is, the state flag FL2 is set to “1” when the flag set signal FS or the flag set signal FS2 changes from inactive to active.

  Other configurations and functions of the lower timing unit 50 according to the second embodiment are the same as those of the lower timing unit 50 (FIG. 5) according to the first embodiment, and thus description thereof is omitted.

  In addition, when one of the timing correction based on the reception of the offset setting command and the timing correction based on the timing correction data 92 can be performed while the other start timing may occur, the start timing has arrived first. An arbitration circuit may be provided so that the time correction is performed after the start timing comes after waiting for the time correction to end.

  FIG. 13 is a flowchart illustrating an example of a processing procedure for timing correction by the timing device 1 according to the second embodiment. In FIG. 13, steps that perform the same processing as in FIG. Note that the processing procedure for time correction by the master control device 2 is the same as that in the first embodiment (FIG. 9), and therefore illustration and description thereof are omitted.

As shown in FIG. 10, first, the timing device 1 reads time correction data from the storage circuit 90 and sets a correction cycle (step S200).

  Next, when the timing device 1 receives the timing data read command (Y in step S210), the timing device 1 transmits the timing data T0 to T8 to the master control device 2 (step S220).

  When the time measuring apparatus 1 receives the offset setting command (Y in step S230), it writes the offset data specified by the offset setting command to the offset register 91 (step S240), and the offset data held in the offset register 91 OFS is converted into a code value SIGN and offset values OFS1, OFS0 (step S250).

  Next, the timing device 1 waits until the second update scheduled timing arrives (N in Step S260), and when the second update scheduled timing comes (Y in Step S260), the counters 55 and 52 of the lower timing unit 50 count. The value is updated to the offset value OFS1, OFS0 (step S270), and the processing after step S210 is performed again.

  On the other hand, if the timing device 1 does not receive the timing data read command (N in Step S210), it determines whether or not the correction cycle set in Step S200 has elapsed based on the timing data T2 to T8 (Step S210). S232). And if the correction period has not passed (N of step S232), the time measuring apparatus 1 will perform the process after step S210 again.

  If the correction cycle has elapsed (Y in step S232), the time measuring device 1 reads the time correction data from the storage circuit 90, sets the correction value as offset data, and sets the correction cycle (step S234). .

  Next, the timing device 1 writes the offset data (correction value) in the offset register 91 (step S240), and converts the offset data OFS held in the offset register 91 into the code value SIGN and the offset values OFS1, OFS0 ( Step S250).

  Next, the timing device 1 waits until the second update scheduled timing arrives (N in Step S260), and when the second update scheduled timing comes (Y in Step S260), the counters 55 and 52 of the lower timing unit 50 count. The value is updated to the offset value OFS1, OFS0 (step S270), and the processing after step S210 is performed again.

  By such processing, the correction value specified by the time correction data 92 is set to the time measurement data T1 and T0 at the correction cycle specified by the time correction data 92, and the time correction is performed.

  In the timing device 1 according to the second embodiment described above, the lower timing unit 50 of the timing device 1 uses the offset data OFS (offset value) stored in the offset register 91 at the correction cycle specified by the time correction data 92. By setting OFS1, OFS0) (correction value specified by time correction data 92) to time data T1 (1/100 seconds) and T0 (1/1000 seconds), the update timing of time data T2 (seconds) is set. to correct. Therefore, for example, even when the time correction by receiving the offset setting command from the master control device 2 is not performed for a long period of time, the correction cycle included in the time correction data 92 is periodically 1/1000 second. By performing the time correction in units, it is possible to correct a time shift caused by a secular change or the like.

1-3. Modification [Modification 1]
In each of the above embodiments, the clock signal CLK3 having a frequency of 1 Hz is generated and output by the lower timer unit 50. However, the clock signal CLK1 having a frequency of 4096 may be generated by dividing the frequency of the clock signal CLK1 of 4096 Hz by a frequency dividing circuit. FIG. 14 is a diagram illustrating a configuration example of the timing device 1 according to the first modification. The example of FIG. 14 is a modification of the second embodiment (FIG. 11), but the first embodiment (FIG. 1) may be similarly modified. In FIG. 14, the same components as those in FIG. 11 are denoted by the same reference numerals, and the description will focus on the contents different from the first embodiment or the second embodiment, and overlap with the first embodiment or the second embodiment. Description to be omitted is omitted.

As shown in FIG. 14, the timing device 1 of the first modification is different from the timing device 1 (FIG. 11) of the second embodiment in that a frequency divider 130 and an arbitration circuit are used instead of the frequency divider 30 and the arbitration circuit 60. 140. The frequency dividing circuit 130 divides the clock signal CLK1 having a frequency of 4096 Hz (= 2 ¹² Hz) by 4096 to generate a clock signal CLK3 having a frequency of 1 Hz. Similarly to the frequency divider circuit 20 (FIG. 3), the frequency divider circuit 130 may be configured by 12 T-type flip-flops corresponding to the frequency division ratio. The clock signal CLK3 is supplied to the upper timer unit 70 via the arbitration circuit 140.

  The arbitration circuit 140 delays a pulse included in the clock signal CLK3 during a period in which the time measurement data is being read so that the time measurement data does not change while the time measurement data is being read from the upper time measurement unit 70. . In other periods, the arbitration circuit 140 outputs the clock signal CLK3 supplied from the frequency divider circuit 130 as it is. In addition, the arbitration circuit 140 includes the timing data T2 to T8 in units of seconds or more, the timing data T1 in units of 1/100 seconds, and the timing data T0 in units of 1/1000 seconds when the upper timing unit 70 updates the timing data. The counters 55 and 52 (see FIG. 5) of the lower timer unit 50 are forcibly reset in synchronization with the clock signal CLK3 so that no inconsistency occurs. The arbitration circuit 140 is configured by a logic circuit including a combinational circuit or a sequential circuit, for example.

  Since the low-order time measuring unit 50 does not need to output the clock signal CLK3, the frequency dividing circuits 59a and 59b are unnecessary in the configuration shown in FIG.

  According to the timing device 1 of the first modification, the same effect as that of each of the embodiments described above is obtained, and, for example, a circuit for generating a clock signal CLK3 and generating a plurality of count values representing times in seconds or more. Since the configuration can maintain a simple configuration similar to that of a conventional model that performs a timekeeping operation in units of seconds or more, compatibility with the conventional model in terms of circuit layout and the like can be improved.

[Modification 2]
In each of the embodiments described above, the oscillation circuit 10 outputs the clock signal CLK0 having a power of 2 (32768 Hz (= 2 ¹⁵ Hz)) in order to facilitate the generation of the clock signal CLK3 having a frequency of 1 Hz. I am doing so. That is, in each of the above-described embodiments, for example, the vibrator 11 having a resonance frequency near 32768 Hz is used. Therefore, the counter 52 selects 40 and 41 and the pulse of the clock signal CLK1 having a frequency of 4096 Hz. The count data T0 is created in a pseudo 1/1000 second unit. On the other hand, the time measuring device 1 of the modification 2 creates accurate time measuring data T0 in units of 1/1000 second by using the vibrator 11 having a resonance frequency that is a power of 2 × 1 kHz. For example, using the vibrator 11 whose resonance frequency is around 32000 Hz, the oscillation circuit 10 outputs a clock signal CLK0 of 32000 Hz, and the frequency divider circuit 20 divides the clock signal CLK0 by 32 to generate a clock signal CLK1 of 1 kHz. Then, it is supplied to the lower timing unit 50. Although not shown in the figure, in the lower timing unit 50, the counter 52 is replaced with a 4-bit decimal BCD counter in the configuration shown in FIG. 5, and the counter 52 counts the pulses of the clock signal CLK1 to measure the time data T0 ( 1/1000 second), and the count control circuit 51 activates the count enable signal CNTEN (for example, high level) when the counter 52 carries. Further, the counter 55, which is an 8-bit decimal BCD counter, performs the count operation in synchronization with the clock signal CLK1 when the count enable signal CNTEN is active, thereby generating the time measurement data T1 (1/100 second). Then, the upper timer unit 70 generates the time data T2 to T8 based on the clock signal CLK1, specifically, based on the carry signal (the signal having a period of 1 second) from the counter 55 of the lower timer unit 50. That's fine. Note that the control flag register 54 and the frequency dividing circuits 59a and 59b in the configuration of FIG. 5 are unnecessary.

  Similarly to each of the above-described embodiments, in the timing device 1 of the second modified example, the offset data OFS (offset values OFS1, OFS0) is stored in the timing data T1 (1/100 seconds) at the scheduled update timing of the timing data T2 (seconds). ), T0 (1/1000 seconds) and the update timing of the timing data T2 (seconds) is corrected, so that accurate timing correction can be performed more easily than in the past.

2. Electronic Device FIG. 15 is a functional block diagram showing an example of the configuration of the electronic device of the present embodiment. FIG. 16 is a diagram illustrating an example of the appearance of a smartphone that is an example of the electronic apparatus of the present embodiment.

  The electronic device 300 according to the present embodiment includes a timing device 310, a control unit 320, an operation unit 330, a storage unit 340, a communication unit 350, a display unit 360, and a sound output unit 370. Note that the electronic device 300 of the present embodiment may be configured such that some of the components (each unit) in FIG. 15 are omitted or changed, or other components are added.

  The timing device 310 performs a timing operation and outputs timing data in accordance with a command from the control unit 320.

  The control unit 320 performs various calculation processes and control processes in accordance with programs stored in the storage unit 340 and the like. Specifically, the control unit 320 performs various processes in accordance with operation signals from the operation unit 330, processes for controlling the communication unit 350 to perform data communication with other devices, and various types of information on the display unit 360. Processing for transmitting a display signal for display, processing for transmitting a sound signal for outputting various sounds from the sound output unit 370, and the like are performed. In addition, the control unit 320 reads (receives) the time data from the time measuring device 310 and performs various calculation processes and control processes, and also, for example, offset data in units of 1/1000 second as a correction value of the time data. Send. The control unit 320 is realized by, for example, an MCU (Micro Controller Unit) or an MPU (Micro Processor Unit).

  The operation unit 330 is an input device including operation keys, button switches, and the like, and outputs an operation signal corresponding to an operation by the user to the control unit 320. For example, the control unit 320 can set time information in the time measuring device 310 in accordance with a signal input from the operation unit 330.

  The storage unit 340 stores programs, data, and the like for the control unit 320 to perform various types of calculation processing and control processing. The storage unit 340 is used as a work area of the control unit 320, and programs and data read from the storage unit 340, data input from the operation unit 330, calculation results executed by the control unit 320 according to various programs, and the like. Is temporarily stored. The storage unit 340 includes a ROM (Read Only Memory) and a RAM (Random Access Memory), and includes, for example, a hard disk, a flexible disk, an MO, an MT, various memories, a CD-ROM, or a DVD-ROM. Realized.

  The communication unit 350 performs various controls for establishing data communication between the control unit 320 and an external device.

  The display unit 360 is a display device configured by an LCD (Liquid Crystal Display) or the like, and displays various types of information based on a display signal input from the control unit 320. The display unit 360 may be provided with a touch panel that functions as the operation unit 330.

  The sound output unit 370 is configured by a speaker or the like, and outputs various types of information as sound or sound based on the sound signal input from the control unit 320.

  By applying the timing device 1 of each embodiment described above as the timing device 310, for example, an electronic device that maintains high reliability over a long period of time can be realized. The control unit 320, or the control unit 320 and the storage unit 340 correspond to the master control device 2 of each embodiment described above, and the display unit 360, the sound output unit 370, or the control unit 320 is connected via the communication unit 350. The external device that performs communication corresponds to the slave device 3.

  Various electronic devices can be considered as such an electronic device 300, for example, movement of an electronic watch, a personal computer (for example, a mobile personal computer, a laptop personal computer, a tablet personal computer), a smartphone, a mobile phone, or the like. Terminals, digital cameras, inkjet discharge devices (for example, inkjet printers), storage area network devices such as servers (time servers), routers, switches, local area network devices, mobile terminal base station devices, televisions, video cameras , Video recorders, car navigation devices, real-time clock devices, pagers, electronic notebooks (including those with communication functions), electronic dictionaries, calculators, electronic game devices, game consoles Troller, word processor, workstation, video phone, security TV monitor, electronic binoculars, POS terminal, medical equipment (eg electronic thermometer, blood pressure monitor, blood glucose meter, electrocardiogram measuring device, ultrasonic diagnostic device, electronic endoscope), fish school Detectors, various measuring instruments such as gas meters, water meters, and watt hour meters (smart meters) that have a wired or wireless communication function and can transmit various types of data, meters (for example, vehicles, aircraft, and ship meters) ), Flight simulator, head mounted display, motion trace, motion tracking, motion controller, PDR (pedestrian position and orientation measurement), and the like.

3. Mobile Object FIG. 17 is a functional block diagram showing an example of the configuration of the mobile object of this embodiment. FIG. 18 is a diagram (top view) showing an example of the appearance of an automobile that is an example of the moving object of the present embodiment. The moving body 400 according to the present embodiment includes a time measuring device 410, an arithmetic processing device 420, and control devices 430, 440, and 450. Note that the mobile body of the present embodiment may have a configuration in which some of the components (each unit) in FIGS. 17 and 18 are omitted or other components are added.

  The timing device 410 performs a timing operation and outputs timing data in accordance with a command from the arithmetic processing device 420.

  The arithmetic processing unit 420 performs various calculation processes and control processes in accordance with programs stored in a built-in storage unit (not shown). Specifically, the arithmetic processing unit 420 performs processing for controlling the control devices 430, 440, and 450. The arithmetic processing unit 420 reads out (receives) the time-measurement data from the time-measurement device 410 and performs various calculation processes, and transmits offset data, for example, in units of 1/1000 second as a correction value of the time-measurement data. .

  The control devices 430, 440, and 450 perform various controls such as an engine system, a brake system, and a keyless entry system on the moving body 400, for example.

  By applying the timing device 1 of each embodiment described above as the timing device 410, for example, it is possible to realize a moving body that maintains high reliability over a long period of time. Note that the arithmetic processing device 420 corresponds to the master control device 2 of each embodiment described above, and the control devices 430, 440, and 450 correspond to the slave device 3.

  As such a moving body 400, various moving bodies can be considered, and examples thereof include automobiles (including electric automobiles), aircraft such as jets and helicopters, ships, rockets, and artificial satellites.

  The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the gist of the present invention.

  The above-described embodiments and modifications are merely examples, and the present invention is not limited to these. For example, it is possible to appropriately combine each embodiment and each modification.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 1 ... Time measuring device, 2 ... Master control device, 3 ... Slave device, 4 ... Main power supply, 5 ... Backup power supply, 10 ... Oscillation circuit, 11 ... Vibrator, 12 ... Inverter (logic inversion element), 13 ... Resistance, 14 ... Capacitor, 15 ... Capacitor group, 16 ... Switch circuit, 17 ... Decode circuit, 20 ... Division circuit, 21-23 ... T-type flip-flop, 30 ... Division circuit, 40 ... Arbitration circuit, 50 ... Lower timing unit, 51 ... Count control circuit 52 ... Counter 53 ... Output control circuit 54 ... Control flag register 55 ... Counter 56 ... Output control circuit 57 ... Data conversion circuit 58 ... Status flag register 59a, 59b ... Division Circuit, 60 ... Arbitration circuit, 70 ... Upper clock section, 71a to 74a ... Counter, 75a ... Shift register, 76a, 77a ... Count , 71b to 77b ... output control circuit, 80 ... interface circuit, 90 ... memory circuit, 91 ... offset register, 92 ... time correction data, 100 ... power supply switching circuit, 110 ... time correction unit, 120 ... OR circuit, 130 DESCRIPTION OF SYMBOLS ... Dividing circuit 140 ... Arbitration circuit 200 ... Master timing data 300 ... Electronic device 310 ... Timing device 320 ... Control unit 330 ... Operation unit 340 ... Storage unit 350 ... Communication unit 360 ... Display unit 370, sound output unit, 400, moving body, 410, timing device, 420, arithmetic processing device, 430, 440, 450, control device

Claims (8)

A first timing circuit that generates first timing data in synchronization with the clock signal;
A second timing circuit that generates second timing data that is updated at a cycle longer than the cycle at which the first timing data is updated;
An interface circuit for transmitting the first timing data to an external device and receiving a first correction value from the external device;
A storage circuit for storing the first correction value,
The first timing circuit includes:
A timing device that corrects the update timing of the second timing data by setting the first correction value in the first timing data. The first timing circuit includes:
The timing device according to claim 1, wherein the update timing is corrected by setting the first correction value in the first timing data when the first timing data is a predetermined value. The first correction value is
The timing device according to claim 1, wherein the timing device is a value generated by the external device based on the first timing data and the timing data of the external device. The first timing circuit includes:
Updating the first timekeeping data in units of 1/1000 second;
The second timing circuit includes:
The timing device according to any one of claims 1 to 3, wherein the second timing data is updated in units of one second. The frequency of the clock signal is 4096 Hz;
The first timing circuit includes:
6-bit output from the counter as part of the first time-measurement data, having a counter that selects 40 and 41 at a ratio of 4 to 96 and counts the number of pulses of the clock signal in 6 bits The time measuring device according to claim 4, wherein the count value of the upper 4 bits of the count value is output. The memory circuit is
Further storing the second correction value and the correction cycle,
The first timing circuit includes:
6. The timing device according to claim 1, wherein the update timing is corrected by setting the second correction value in the first timing data in the correction period. 7. A timing device according to any one of claims 1 to 6;
An electronic apparatus comprising: a control device that transmits the first correction value to the time measuring device as the external device.   A moving body comprising the timing device according to claim 1.

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