JP2018195774A - Electronic component - Google Patents

Abstract

To provide an electronic component in which mounting defects hardly occur.SOLUTION: A die is mounted on an upper surface of a substrate, and a capacitor is mounted on a lower surface of the substrate. Among lands on the upper surface of the substrate, a first upper-surface land and a second upper-surface land connected to two terminals of the die are respectively connected to a lower upper-surface land and a second lower-surface land connected to a pair of external electrodes of the capacitor among the lands on the lower surface of the substrate through a conductor layer and the via. A via positioned on a lowermost surface side among a plurality of vias connecting the first upper-surface land and the first lower-surface land has a field via structure and is disposed inside the first lower-surface land in a plan view. The same applies to a plurality of vias connecting the second upper-surface land and the second lower-surface land. A distance between centers of the first upper-surface land and the second upper-surface land is different from a distance between centers of the first lower-surface land and the second lower-surface land.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic component including a substrate and a die mounted on the substrate.

  A decoupling capacitor is connected to a power supply circuit that supplies power to the semiconductor integrated circuit element (die) in order to suppress fluctuations in power supply voltage and generation of noise. A capacitor mounting structure in which a decoupling capacitor is arranged between a package substrate (interposer) on which a die is mounted and a printed circuit board on which the package substrate is mounted is known (Patent Document 1).

  In the device disclosed in Patent Document 1, a die and a decoupling capacitor are connected via a through via penetrating a package substrate.

U.S. Patent No. 9263186

  The through via is generally composed of a conductor covering the side surface of the through hole, and a cavity is left inside the through hole. When a capacitor is arranged and mounted so that a terminal of the capacitor such as a decoupling capacitor and the through via overlap, the cavity in the through via is blocked by the capacitor terminal or solder. For this reason, mounting failure is likely to occur due to solder explosion, popcorn phenomenon, and the like due to thermal expansion during mounting.

  An object of the present invention is to provide an electronic component that is unlikely to cause mounting defects.

The electronic component according to the first aspect of the present invention is:
A plurality of lands are provided on the upper surface and the lower surface, a plurality of conductor layers and a plurality of vias are provided therein, and at least a part of the lands on the upper surface and at least a part of the lands on the lower surface are a plurality of the conductor layers. And a first substrate electrically connected through the plurality of vias;
A plurality of terminals, each of which is connected to the land on the upper surface of the first substrate and mounted on the first substrate;
A pair of external electrodes is provided, and the pair of external electrodes is connected to the lands on the lower surface of the first substrate and mounted on the first substrate;
Of the lands on the upper surface of the first substrate, the first upper surface land and the second upper surface land connected to the two terminals of the die are the lands on the lower surface of the first substrate. Connected to the first lower surface land and the second lower surface land connected to the pair of external electrodes of the first capacitor through the conductor layer and the via, respectively.
Of the plurality of vias that connect the first upper surface land and the first lower surface land, the via disposed at the lowermost surface has a filled via structure, and the first lower surface land has a filled via structure in plan view. The via disposed on the lowermost side among the plurality of vias that are disposed inside and connect the second upper surface land and the second lower surface land has a filled via structure, and in plan view Arranged inside the second lower surface land,
A center-to-center distance between the first top surface land and the second top surface land and a center-to-center distance between the first bottom surface land and the second bottom surface land are different.

  Since the lowermost via has a filled via structure, solder explosion, popcorn phenomenon and the like are unlikely to occur when the first capacitor is mounted. For this reason, it becomes difficult to generate mounting defects. The center-to-center distance between the first upper surface land and the second upper surface land is different from the center-to-center distance between the first lower surface land and the second lower surface land. For this reason, it becomes possible to mount the first capacitors of various sizes without being restricted by the distance between the terminals of the die.

In addition to the configuration of the electronic component according to the first aspect, the electronic component according to the second aspect of the present invention includes:
Of the plurality of vias connecting the first upper surface land and the first lower surface land, paying attention to the two vias arranged above and below one conductor layer, the lower via is the upper side The via is disposed at a position shifted in an in-plane direction toward the first lower surface land.

  The current path from the die to the first lower surface land can be shortened. When the first capacitor is a decoupling capacitor, the noise suppression effect can be enhanced.

In addition to the configuration of the electronic component according to the second aspect, the electronic component according to the third aspect of the present invention includes:
Of the plurality of vias connecting the first upper surface land and the first lower surface land, the two vias arranged above and below one conductor layer partially overlap in plan view. It has the characteristics.

  The current path from the die to the first lower surface land can be made shorter.

In addition to the configuration of the electronic component according to the first to third aspects, the electronic component according to the fourth aspect of the present invention includes:
And a solder ball placed on the plurality of lands other than the first lower surface land and the second lower surface land among the plurality of lands on the lower surface of the first substrate.

  The first substrate can be mounted on another substrate such as a mother board by the solder ball reflow process.

In addition to the configuration of the electronic component according to the fourth aspect, the electronic component according to the fifth aspect of the present invention includes:
And a second substrate on which the first substrate is mounted.
The first capacitor is electrically connected to the second substrate, and the land on which the solder ball is placed among the lands on the lower surface of the first substrate is connected to the first capacitor via the solder ball. 2 is electrically connected to the substrate.

  The first capacitor is electrically connected to both the first substrate and the second substrate. The first lower surface land and the second lower surface land of the first substrate are electrically connected to the second substrate via the first capacitor.

In addition to the configuration of the electronic component according to the fifth aspect, the electronic component according to the sixth aspect of the present invention includes:
And a second capacitor connected to the land on the lower surface of the first substrate,
The height of the second capacitor relative to the lower surface of the first substrate is lower than the height of the first capacitor;
Two compensation conductors having a height corresponding to the difference between the height of the first capacitor and the height of the second capacitor are formed on the second substrate. It is characterized in that it is electrically connected to the second substrate through the compensation conductor.

  Even when the heights of the two capacitors are different, the two capacitors can be connected to the second substrate.

  Since the lowermost via has a filled via structure, solder explosion, popcorn phenomenon and the like are unlikely to occur when the first capacitor is mounted. For this reason, it becomes difficult to generate mounting defects. The center-to-center distance between the first upper surface land and the second upper surface land is different from the center-to-center distance between the first lower surface land and the second lower surface land. For this reason, it becomes possible to mount the first capacitors of various sizes without being restricted by the distance between the terminals of the die.

FIG. 1 is a cross-sectional view of an electronic component according to the first embodiment. FIG. 2 is a cross-sectional view of the electronic component shown in FIG. 1 mounted on a motherboard. FIG. 3A is a partial cross-sectional view of an electronic component according to the second embodiment. FIG. 3B shows a hot upper surface land, a hot lower surface land, a ground upper surface land, a ground lower surface land, and a plurality of vias connecting these. It is a figure which shows the planar positional relationship of these. 4A is a cross-sectional view of an electronic component according to a comparative example, and FIG. 4B is an upper surface land for hot, a lower surface land for hot, an upper surface land for ground, and a lower surface land for ground, and these are connected. It is a figure which shows the planar positional relationship of a penetration via. FIG. 5 is a cross-sectional view of an electronic component according to the third embodiment.

[First embodiment]
With reference to FIG.1 and FIG.2, the electronic component by 1st Example is demonstrated.
FIG. 1 is a cross-sectional view of an electronic component 20 according to the first embodiment. The electronic component 20 according to the first embodiment includes a package substrate (first substrate) 10, a die (semiconductor chip) 30, and a capacitor 40. The package substrate 10 includes a plurality of lands 11 provided on the upper surface, a plurality of lands 12 provided on the lower surface, a plurality of conductor layers 13 and a plurality of vias 14 provided therein. The plurality of vias 14 connect the plurality of conductor layers 13 in the thickness direction.

  The plurality of lands 11 on the upper surface include a hot upper surface land 11H and a ground upper surface land 11G. The plurality of lands 12 on the lower surface also include a hot lower surface land 12H and a ground lower surface land 12G. The center-to-center distance between the hot lower surface land 12H and the ground lower surface land 12G is different from the center-to-center distance between the hot upper surface land 11H and the ground upper surface land 11G. The hot lower surface land 12 </ b> H is electrically connected to the hot upper surface land 11 </ b> H through the plurality of conductor layers 13 and the plurality of vias 14. Similarly, the ground lower surface land 12 </ b> G is electrically connected to the ground upper surface land 11 </ b> G via the plurality of conductor layers 13 and the plurality of vias 14.

  The die 30 is mounted on the upper surface of the package substrate 10. For example, the die 30 is flip-chip bonded to the package substrate 10. The hot terminal (power supply terminal) and the ground terminal of the package substrate 10 are electrically connected to the hot upper surface land 11H and the ground upper surface land 11G, respectively. The die 30 is molded with a mold resin 31.

  The capacitor 40 is mounted on the lower surface of the package substrate 10. A pair of external electrodes 41 of the capacitor 40 are electrically connected to the hot lower surface land 12H and the ground lower surface land 12G, respectively. For example, solder can be used to connect one external electrode 41 of the capacitor 40 to the hot lower surface land 12H and to connect the other external electrode 41 to the ground lower surface land 12G.

  Of the plurality of vias 14 connecting the hot lower surface land 12H and the hot upper surface land 11H, the lowermost via 14H has a filled via structure. Similarly, the lowermost via 14G among the plurality of vias 14 connecting the ground lower surface land 12G and the ground upper surface land 11G also has a filled via structure. That is, the via holes of the vias 14H and 14G are filled with the conductor, and no cavity is left. In plan view, the via 14H is disposed at a position overlapping the hot lower surface land 12H, and the via 14G is disposed at a position overlapping the ground lower surface land 12G. More specifically, in plan view, the via 14H is disposed inside the hot lower surface land 12H, and the via 14G is disposed inside the ground lower surface land 12G.

  Solder balls 17 are respectively placed on the plurality of lands 12 to which the capacitor 40 is not connected among the lands 12 on the lower surface. Further, solder balls 18 are placed on the surfaces of the capacitor 40 facing the lower side of the pair of external electrodes 41. The solder ball 18 is smaller than the solder ball 17 placed on the land 12.

  FIG. 2 is a cross-sectional view of the electronic component 20 shown in FIG. 1 mounted on a mother board (second substrate) 50. A plurality of lands 51 are provided on the upper surface of the mother board 50, and a plurality of conductor layers 52 and a plurality of vias 53 are provided therein.

  The electronic component 20 is mounted on the mother board 50 by positioning the lower surface of the package substrate 10 facing the mother board and performing a solder reflow process. Of the plurality of lands 12 on the lower surface of the package substrate 10, the lands 12 that are not connected to the capacitor 40 are electrically connected to the lands 51 of the mother board 50 through the solder balls 17. The capacitor 40 is electrically connected to the land 51 of the motherboard 50 via the solder ball 18 (FIG. 1) placed on the external electrode 41. The hot lower surface land 12 </ b> H and the ground lower surface land 12 </ b> G of the package substrate 10 are electrically connected to the land 51 of the motherboard 50 through the external electrode 41 of the capacitor 40.

Next, the excellent effect of the electronic component according to the first embodiment will be described.
In the first embodiment, the vias 14H and 14G (FIG. 1) on the lowermost side of the package substrate 10 have a filled via structure. For this reason, even if the hot lower surface land 12H and the ground lower surface land 12G are arranged so as to overlap the vias 14H and 14G, mounting defects due to solder explosion or the like during mounting of the capacitor are unlikely to occur.

  Furthermore, in the first embodiment, the center-to-center distance between the hot lower surface land 12H and the ground lower surface land 12G can be made different from the center-to-center distance between the hot upper surface land 11H and the ground upper surface land 11G. is there. This makes it possible to mount capacitors 40 of various sizes on the lower surface of the package substrate 10 without depending on the distance between the terminals of the die 30. Since the types of capacitors 40 that can be mounted are increased, the effect of increasing the degree of freedom in design can be obtained.

  The capacitor 40 functions as a decoupling capacitor. Since the decoupling capacitor is disposed directly under the die 30, a higher noise reduction effect can be obtained as compared with the configuration in which the decoupling capacitor is disposed at a position far from the die 30.

  1 and 2 show an example in which one capacitor 40 is mounted on the lower surface of the package substrate 10, but a plurality of capacitors may be mounted. The connection structure between each capacitor and the die 30 is the same as the connection structure between the capacitor 40 and the die 30.

[Second Embodiment]
Next, an electronic component according to a second embodiment will be described with reference to FIGS. 3A and 3B. Hereinafter, the description of the configuration common to the electronic component according to the first embodiment shown in FIGS. 1 and 2 is omitted. In the second embodiment, the position and size of the via 14 inside the package substrate 10 are optimized as compared with the first embodiment.

  FIG. 3A is a partial cross-sectional view of an electronic component according to a second embodiment. The hot upper surface land 11 </ b> H and the hot lower surface land 12 </ b> H of the package substrate 10 are electrically connected through a plurality of conductor layers 13 and a plurality of vias 14.

  FIG. 3B is a diagram showing a planar positional relationship between the hot upper surface land 11H, the hot lower surface land 12H, the ground upper surface land 11G, the ground lower surface land 12G, and the plurality of vias 14 connecting these.

  Of the plurality of vias 14 that connect the hot upper surface land 11H and the hot lower surface land 12H, attention is paid to two vias 14 arranged above and below one conductor layer 13. Of the two vias 14 of interest, the lower via 14 with respect to the upper via 14 is disposed at a position shifted in the in-plane direction toward the hot lower surface land 12H. The plurality of vias 14 connecting the ground upper surface land 11G and the ground lower surface land 12G have the same positional relationship.

  Two vias 14 adjacent to each other in the thickness direction partially overlap in a plan view as shown in FIG. 3B. The lowermost via 14H directly connected to the hot lower surface land 12H is disposed inside the hot lower surface land 12H. Similarly, the lowermost via 14G directly connected to the ground lower surface land 12G is disposed inside the ground lower surface land 12G.

  Next, the superior effect of the electronic component according to the second embodiment will be described as compared with the electronic component according to the comparative example shown in FIGS. 4A and 4B.

  FIG. 4A is a cross-sectional view of an electronic component according to a comparative example. FIG. 4B shows a planar positional relationship between the hot upper surface land 11H, the hot lower surface land 12H, the ground upper surface land 11G, the ground lower surface land 12G, and the through vias 15H and 15G that connect them. FIG.

  In the comparative example, the hot upper surface land 11H and the hot lower surface land 12H are connected by a through via 15H penetrating the package substrate 10 in the thickness direction. Similarly, the ground upper surface land 11G and the ground lower surface land 12G are connected by another through via 15G penetrating the package substrate 10 in the thickness direction.

  A wiring 16H connecting the lower end of the through via 15H and the hot lower surface land 12H is formed on the lower surface of the package substrate 10. Similarly, a wiring 16G that connects the lower end of the through via 15G and the ground lower surface land 12G is formed on the lower surface of the package substrate 10.

  In the comparative example shown in FIGS. 4A and 4B, the current path connecting the hot upper surface land 11H and the hot lower surface land 12H, and the current path connecting the ground upper surface land 11G and the ground lower surface land 12G are: It becomes L-shaped as shown in FIG. 4A. In contrast, in the second embodiment shown in FIGS. 3A and 3B, an oblique current path is formed in the package substrate 10. For this reason, in the second embodiment, the current path connecting the die 30 and the capacitor 40 is shorter than the current path of the comparative example. As a result, the noise reduction effect of the decoupling capacitor can be enhanced.

[Third embodiment]
Next, an electronic component according to a third embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the electronic component according to the first embodiment shown in FIGS. 1 and 2 is omitted.

  FIG. 5 is a cross-sectional view of an electronic component according to the third embodiment. In the third embodiment, a capacitor 45 is mounted on the lower surface of the package substrate 10 in addition to the capacitor 40. The height of the capacitor 45 is lower than the height of the capacitor 40 with reference to the lower surface of the package substrate 10.

  Compensation conductors 55 are disposed on the two lands 51 connected to the pair of external electrodes 46 of the capacitor 45 among the plurality of lands 51 of the motherboard 50. The height of the compensation conductor 55 corresponds to the difference between the height of the capacitor 40 and the height of the capacitor 45, and compensates for the shortage of the height of the capacitor 45. The pair of external electrodes 46 of the capacitor 45 are electrically connected to the land 51 via the compensation conductor 55.

  The compensation conductor 55 can be formed, for example, by forming the land 51 by plating and further plating only on the land 51 connected to the capacitor 45.

  In the third embodiment, since the difference in height between the capacitors 40 and 45 is compensated by the compensating conductor 55, it is possible to mount a plurality of capacitors having different heights on the lower surface of the package substrate 10. .

  Each embodiment is an exemplification, and needless to say, partial replacement or combination of the configurations shown in the different embodiments is possible. About the same effect by the same composition of a plurality of examples, it does not refer to every example one by one. Furthermore, the present invention is not limited to the embodiments described above. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

10 Package substrate (first substrate)
11 Upper surface land 11H Hot upper surface land (first upper surface land)
Top land for 11G ground (second top land)
12 Lower surface land 12H Hot lower surface land (first lower surface land)
12G Ground bottom land (second bottom land)
13 Conductor layer 14 Via 14H Via 14G directly connected to hot lower surface land Via 15H, 15G Through via 16H, 16G directly connected to ground lower surface land 17 and 18 Solder ball 20 Electronic component 30 Die 31 Mold resin 40 Capacitor (first capacitor)
41 External electrode 45 Capacitor (second capacitor)
46 External electrode 50 Mother board (second substrate)
51 Land 52 Conductor layer 53 Via 55 Compensation conductor

Claims (6)

A plurality of lands are provided on the upper surface and the lower surface, a plurality of conductor layers and a plurality of vias are provided therein, and at least a part of the lands on the upper surface and at least a part of the lands on the lower surface are a plurality of the conductor layers. And a first substrate electrically connected through the plurality of vias;
A plurality of terminals, each of which is connected to the land on the upper surface of the first substrate and mounted on the first substrate;
A pair of external electrodes is provided, and the pair of external electrodes is connected to the lands on the lower surface of the first substrate and mounted on the first substrate;
Of the lands on the upper surface of the first substrate, the first upper surface land and the second upper surface land connected to the two terminals of the die are the lands on the lower surface of the first substrate. Connected to the first lower surface land and the second lower surface land connected to the pair of external electrodes of the first capacitor through the conductor layer and the via, respectively.
Of the plurality of vias that connect the first upper surface land and the first lower surface land, the via disposed at the lowermost surface has a filled via structure, and the first lower surface land has a filled via structure in plan view. The via disposed on the lowermost side among the plurality of vias that are disposed inside and connect the second upper surface land and the second lower surface land has a filled via structure, and in plan view Arranged inside the second lower surface land,
An electronic component in which a center-to-center distance between the first top surface land and the second top surface land is different from a center-to-center distance between the first bottom surface land and the second bottom surface land.   Of the plurality of vias connecting the first upper surface land and the first lower surface land, paying attention to the two vias arranged above and below one conductor layer, the lower via is the upper side The electronic component according to claim 1, wherein the electronic component is disposed at a position shifted in an in-plane direction toward the first lower surface land with respect to the via.   Of the plurality of vias connecting the first upper surface land and the first lower surface land, the two vias arranged above and below one conductor layer partially overlap in plan view. The electronic component according to claim 2.   The solder ball mounted on the plurality of lands other than the first lower surface land and the second lower surface land among the plurality of lands on the lower surface of the first substrate. The electronic component according to claim 1. And a second substrate on which the first substrate is mounted.
The first capacitor is electrically connected to the second substrate, and the land on which the solder ball is placed among the lands on the lower surface of the first substrate is connected to the first capacitor via the solder ball. The electronic component according to claim 4, wherein the electronic component is electrically connected to the second substrate. And a second capacitor connected to the land on the lower surface of the first substrate,
The height of the second capacitor relative to the lower surface of the first substrate is lower than the height of the first capacitor;
Two compensation conductors having a height corresponding to the difference between the height of the first capacitor and the height of the second capacitor are formed on the second substrate. The electronic component according to claim 5, wherein the electronic component is electrically connected to the second substrate via the compensation conductor.

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