JP2018189993A - Driving device of display panel - Google Patents

Abstract

PURPOSE: To provide a driving device of a display panel capable of downsizing the device scale, and reducing the power consumption and heat quantity.CONSTITUTION: A driving device of a display panel of the present invention includes a gradation voltage interpolation circuit. In accordance with first analog data corresponding to a first pixel drive voltage to be applied to a first data line; second analog data corresponding to a second pixel drive voltage to be applied to a second data line; and digital data indicating a pixel drive voltage corresponding to a third data line disposed between the first data line and second data line, the gradation voltage interpolation circuit generates third analog data corresponding to the pixel drive voltage to be applied to the third data line.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a drive device for driving a display panel, and more particularly to a drive device for applying a gradation voltage to a data line of a display panel.

  For example, in a liquid crystal display panel as a flat display panel, a plurality of scanning lines extending in the horizontal direction of a two-dimensional screen and a plurality of data lines extending in the vertical direction of a two-dimensional screen are arranged so as to intersect each other. Yes. At the intersection of the data line and the scan line, an electrode that bears the display cell is formed.

  The liquid crystal display panel is equipped with a data driver for applying a voltage based on the input video signal to each of the data lines. At this time, such a data driver is provided with a decoder for each data line that converts display data corresponding to each pixel into a gradation voltage having a voltage value corresponding to a luminance level (see, for example, Patent Document 1). ).

  Therefore, when the number of data lines increases as the liquid crystal display panel becomes higher in definition, the number of decoders increases correspondingly, resulting in a problem that the chip size of the data driver increases.

  Therefore, a data driver has been proposed that can drive the data lines of the liquid crystal display panel by using a smaller number of decoders than the number of data lines by time-sharing three data lines with one decoder. (For example, refer to Patent Document 2).

JP 2006-292807 A Japanese Patent Laid-Open No. 11-259036

  According to the data driver disclosed in Patent Document 2, it is possible to reduce the chip size, but driving based on display data for one horizontal scan must be divided in time and executed. Therefore, it is necessary to increase the operating frequency by the number of divisions. Therefore, such a data driver has a problem that the power consumption and the heat generation amount are increased as the operating frequency is increased.

  An object of the present invention is to provide a display panel drive device capable of reducing the device scale, power consumption, and heat generation.

  A display panel driving apparatus according to the present invention is a driving apparatus for applying a pixel driving voltage to a display panel having a plurality of data lines, and corresponds to a first pixel driving voltage applied to a first data line. 1 analog data, 2nd analog data corresponding to the 2nd pixel drive voltage applied to the 2nd data line, and 3rd data arranged between the 1st data line and the 2nd data line A gradation voltage interpolation circuit is provided that generates third analog data corresponding to the pixel drive voltage applied to the third data line in accordance with digital data indicating the pixel drive voltage for the line.

  In the present invention, only a partial video data group of a plurality of video data pieces corresponding to one horizontal scanning line of the display panel is subjected to an analog voltage value by a D / A converter. The gradation voltage is converted into a gradation voltage, and the gradation voltage corresponding to each of the video data pieces belonging to the other video data group is obtained by the interpolation processing based on each gradation voltage.

  As a result, the circuit scale, power consumption, and heat generation can be reduced as compared with the case where the gradation voltage conversion processing by the D / A converter is performed on all the video data pieces for one horizontal scanning line. It becomes possible.

It is a figure which shows schematic structure of the display apparatus provided with the drive device of the display panel which concerns on this invention. 2 is a block diagram showing an internal configuration of a data driver 12. FIG. 6 is a diagram illustrating an example of the operation of the shift register 121. FIG. 3 is a block diagram illustrating an example of an internal configuration of a gradation voltage output unit 124. FIG. It is a block diagram which shows an example of an internal structure of each of the gradation voltage interpolation circuits KS1-KS6. 6 is a diagram illustrating another example of the operation of the shift register 121. FIG. It is a block diagram which shows another example of each internal structure of each gradation voltage interpolation circuit KS1-KS6. It is a block diagram which shows another example of the internal structure of the gradation voltage output part 124. FIG. It is a figure which shows another example of the format of the input video data VD, and the operation | movement of the shift register 121. FIG.

  FIG. 1 is a diagram showing a schematic configuration of a display device including a display panel driving device according to the present invention.

In FIG. 1, for example, a display panel 20 as a liquid crystal panel includes a liquid crystal layer (not shown) and n (n is an integer of 2 or more) horizontal scanning lines S ₁ to S that extend in the horizontal direction of a two-dimensional screen. _Sn and m (m is an integer of 3 or more) data lines D _{1 to} D _m extending in the vertical direction of the two-dimensional screen are provided. A red display cell P _R responsible for red display, a green display cell P _G responsible for green display, or a blue display cell P _B responsible for blue display is formed at the intersection of the horizontal scanning line and the data line.

The data line among the data lines _{D 1 ~D m (3 · t} -2) th (t is a natural number of 1 to 320), i.e. _{D 1, D 4, D 7} , ···, D m- the ₂ each is formed with a red display cell P _R. Further, (3 · t-1) th are arranged in the data line among the data lines D ₁ to D _m, that is _{D 2, D 5, D 8} , ···, each of D _m-1 is green display cell P _G is formed. Further, (3 · t) th are arranged in the data line among the data lines D ₁ to D _m, that is _{D 3, D 6, D 9} , ···, the D _m blue display cell P _B Is formed.

Here, as shown in FIG. 1, on each of the horizontal scan lines S ₁ to S _n, 3 one display cells adjacent to each other, i.e. red display cell P _R, the green display cell P _G, and blue display cell P _B One pixel PX (region surrounded by a broken line) is formed. Therefore, (m / 3) pixels PX are juxtaposed on one horizontal scanning line.

  The drive control unit 10 generates a scanning control signal synchronized with the input video data VD and supplies it to the scanning driver 11. Note that the input video data VD is composed of a series of video data pieces representing the luminance level corresponding to each pixel. At this time, in one pixel PX, a video data piece representing the luminance level of the red component in 8 bits, a video data piece representing the luminance level of the green component in 8 bits, and a luminance level of the blue component in 8 bits. Three video data pieces consisting of the video data pieces correspond to each other.

Based on the input video data VD, the drive control unit 10 is a video that represents the luminance level of each of the red display cell P _R , the green display cell P _G , and the blue display cell P _B corresponding to each pixel in, for example, 8 bits. Video data PD as a data piece is supplied to the data driver 12.

The scan driver 11 generates a scan pulse in response to the scan control signal supplied from the drive control unit 10 sequentially alternatively applies it to the horizontal scanning lines S ₁ to S _n of the display panel 20.

The data driver 12 takes in a series of video data PD supplied from the drive control unit 10. Here, every time one horizontal scanning line is captured, that is, m video data PD _{1 to} PD _m are captured, the data driver 12 performs gradation corresponding to the luminance level indicated by each video data PD. Pixel drive voltages G _{1 to} G _m having voltages are generated and applied to the corresponding data lines D _{1 to} D _m .

  FIG. 2 is a block diagram showing the internal configuration of the data driver 12.

The shift register 121 sequentially takes in the series of video data PD supplied from the drive control unit 10. As shown in FIG. 3, the shift register 121 supplies the following video data QD _{1 to} QD _m to the data latch unit 122 every time the capturing of the video data PD _{1 to} PD _m for one horizontal scanning line is completed. . The (3 · t−2) -th video data PD in the video data PD _{1 to} PD _m is data representing a red luminance component by, for example, 8 bits, and the (3 · t−1) -th video data PD. Is data representing the green luminance component in, for example, 8 bits, and the (3 · t) -th video data PD is data representing the blue luminance component in, for example, 8 bits.

Shift register 121 in the video data _{PD 1 ~PD m (6 · t} -5) th, (6 · t-4) th and (6 · t-3) -th image data PD (first video For the data group, as shown in FIG. 3, the 8-bit data represented by the video data PD is supplied as it is to the data latch unit 122 as video data QD. That is, the shift register 121 supplies the video data PD as it is to the data latch unit 122 as the video data QD for the video data PD corresponding to the odd-numbered pixels PX.

The shift register 121 also includes (6 · t−2) -th, (6 · t−1) -th and (6 · t) -th video data PD (second video) among the video data PD _{1 to} PD _m. For the data group), for example, lower 2 bits are extracted from the video data PD, and the video data QD consisting of 2 bits is supplied to the data latch unit 122. That is, the shift register 121 has each of the video data PD corresponding to the even-numbered pixels PX among the (m / 3) pixels PX juxtaposed on one horizontal scanning line of the display panel 20. The lower 2 bits are extracted from the image data, and each of the 2-bit video data QD is supplied to the data latch unit 122.

For example, the shift register 121 obtains the image data PD ₄ video data QD ₄ ~QD ₆ follows from -PD ₆ corresponding to the second-are arranged pixel PX on one horizontal scan line, these data Supply to the latch unit 122. That is, the shift register 121, video data QD ₄ consisting of low-order 2 bits of the video data PD _4, the video data QD ₅ consisting of the lower 2 bits of the video data PD _5, consisting of the lower 2 bits of the video data PD ₆ The video data QD ₆ is supplied to the data latch unit 122.

The data latch unit 122 takes in the video data QD _{1 to} QD _m for one horizontal scanning line supplied from the shift register 121 and holds them for one horizontal scanning period, respectively, while holding them for the video data LD _{1 to} LD. _m is supplied to the level shifter 123 as _m .

The level shift unit 123 supplies video data SD _{1 to} SD _m obtained by level shifting the values of the video data LD _{1 to} LD _m by a predetermined level to the gradation voltage output unit 124.

Gradation voltage output unit 124 converts the image data SD ₁ to SD _m to the gradation voltage G ₁ ~G _m corresponding to the luminance level represented by the individually the video data, the gradation level voltage G ₁ ~G applying a _m to the data lines D ₁ to D _m of the display panel 20.

  FIG. 4 is a block diagram showing an internal configuration of the gradation voltage output unit 124.

In FIG. 4, only the functional modules related to the video data SD _{1 to} SD ₁₂ are extracted from all the functional modules constituting the gradation voltage output unit 124.

In FIG. 4, D / A converters C1 converts the image data SD _1, the grayscale voltage corresponding to the luminance level represented by the 8-bit data, the amplifier A1 and the same as the gradation voltages V ₁ This is supplied to the input terminal VA of the gradation voltage interpolation circuit KS1.

D / A converter C2 converts the image data SD _2, the analog gradation voltage corresponding to the luminance level represented by the 8-bit data, amplifier A2 and tone it as gradation voltage V ₂ The voltage is supplied to the input terminal VA of the voltage interpolation circuit KS2.

D / A converter C3 converts the image data SD _3, the analog gradation voltage corresponding to the luminance level represented by the 8-bit data, amplifier A3 and tone it as gradation voltage V ₃ The voltage is supplied to the input terminal VA of the voltage interpolation circuit KS3.

D / A converter C4 is the picture data SD _7, into an analog gradation voltage corresponding to the luminance level represented by the 8-bit data, amplifier A7, tone it as gradation voltage V ₇ The voltage is supplied to the input terminal VB of the voltage interpolation circuit KS1 and the input terminal VA of the gradation voltage interpolation circuit KS4.

D / A converter C5 is video data SD _8, into an analog gradation voltage corresponding to the luminance level represented by the 8-bit data, amplifier A8, tone it as gradation voltage V ₈ The voltage is supplied to the input terminal VB of the voltage interpolation circuit KS2 and the input terminal VA of the gradation voltage interpolation circuit KS5.

D / A converter C6 converts the image data SD _9, the analog gradation voltage corresponding to the luminance level represented by the 8-bit data, the amplifier A9 it as gradation voltages V _9, gradation The voltage is supplied to the input terminal VB of the voltage interpolation circuit KS3 and the input terminal VA of the gradation voltage interpolation circuit KS6.

  The gradation voltage interpolation circuits KS1 to KS6 have the same internal configuration.

  FIG. 5 is a block diagram showing an internal configuration of each of the gradation voltage interpolation circuits KS1 to KS6.

  In FIG. 5, an average calculation unit 51 calculates an average value of the gradation voltage supplied to the input terminal VA and the gradation voltage supplied to the input terminal VB, and calculates an average gradation voltage VM indicating the average value. This is supplied to the selector 52. The weighted average calculation unit 53 calculates an average value by assigning different weights to the gradation voltage supplied to the input terminal VA and the gradation voltage supplied to the input terminal VB, and the weighted average indicating the average value The gradation voltage VW is supplied to the selector 52.

  The selector 52, based on the 2-bit video data supplied to the selection control terminal SS, the gradation voltage supplied to the input terminal VA, the gradation voltage supplied to the input terminal VB, the average gradation voltage VM, and the weight One of the average gradation voltages VW is selected, and the selected voltage is output via the output terminal Y.

  For example, when the 2-bit video data supplied to the selection control terminal SS indicates [00], the selector 52 selects the gradation voltage supplied to the input terminal VA, and this is output via the output terminal Y. Output. In addition, when the video data indicates [01], the selector 52 selects the average gradation voltage VM and outputs it through the output terminal Y. In addition, when the video data indicates [10], the selector 52 selects the gradation voltage supplied to the input terminal VB and outputs it via the output terminal Y. Further, when the video data indicates [11], the selector 52 selects the weighted average gradation voltage VW based on the gradation voltages supplied to the input terminals VA and VB, and uses this as the output terminal Y. Output via.

  Next, the operation of each of the gradation voltage interpolation circuits KS1 to KS6 having the internal configuration shown in FIG. 5 will be described.

The gradation voltage interpolation circuit KS1 is an average based on the gradation voltage V ₁ generated by the D / A converter C1, the gradation voltage V ₇ generated by the D / A converter C4, and V ₁ and V _7. One of the gradation voltage VM and the weighted average gradation voltage VW based on V ₁ and V ₇ is selected based on the video data SD ₄ supplied to the selection control terminal SS, and is selected as the gradation voltage V. ₄ is supplied to the amplifier A4.

The gradation voltage interpolation circuit KS2 is an average based on the gradation voltage V ₂ generated by the D / A converter C2, the gradation voltage V ₈ generated by the D / A converter C5, and V ₂ and V _8. One of the gradation voltage VM and the weighted average gradation voltage VW based on V ₂ and V ₈ is selected based on the video data SD ₅ supplied to the selection control terminal SS, and is selected as the gradation voltage V. ₅ is supplied to the amplifier A5.

Average gradation voltage interpolation circuit KS3 is, a gradation voltage V ₃ generated by the D / A converter C3, the gray scale voltage V ₉ generated by the D / A converter C6, based on V ₃ and V ₉ One of the gradation voltage VM and the weighted average gradation voltage VW based on V ₃ and V ₉ is selected based on the video data SD ₆ supplied to the selection control terminal SS, and is selected as the gradation voltage V. ₆ is supplied to the amplifier A6.

Gradation voltage interpolator KS4 includes a gray scale voltage V ₇ generated by the D / A converter C4, the gray scale voltage V _13, and the average gray level voltage VM based on V ₇ and V _13, V ₇ and V from among the weighted average gradation voltage VW based on ₁₃ to select one based on the video data SD ₁₀ supplied to the selection control terminal SS, and supplies to the amplifier A10 so as gradation voltage V _10. The gradation voltage V ₁₃ is generated by a D / A converter (not shown) that converts the video data SD ₁₃ into an analog gradation voltage.

Gradation voltage interpolator KS5 includes a gray scale voltage V ₈ generated by the D / A converter C5, the gray scale voltage V _14, and the average gray level voltage VM based on V ₈ and V _14, V ₈ and V _One of the weighted average gradation voltages VW based on ₁₄ is selected based on the video data SD ₁₁ supplied to the selection control terminal SS, and this is supplied to the amplifier A11 as the gradation voltage V ₁₁ . The gradation voltage V ₁₄ is generated by a D / A converter (not shown) that converts the video data SD ₁₄ into an analog gradation voltage.

The gradation voltage interpolation circuit KS6 includes the gradation voltage V ₉ generated by the D / A converter C6, the gradation voltage V ₁₅ , the average gradation voltage VM based on V ₉ and V ₁₅ , and V ₉ and V from among the weighted average gradation voltage VW based on ₁₅ to select one based on the video data SD ₁₂ supplied to the selection control terminal SS, and supplies to the amplifier A12 so as gray scale voltage V _12. The gradation voltage V ₁₅ is generated by a D / A converter (not shown) that converts the video data SD ₁₅ into an analog gradation voltage.

Amplifier A1~A12 is, D / A converters C1 -C6, gradation voltages supplied gradation voltages V ₁ ~V ₁₂ individually amplified gradation voltages G ₁ obtained ~ from the interpolation circuit KS1~KS6 G ₁₂ is applied to the data lines D _{1 to} D ₁₂ of the display panel 20. In addition, as each of amplifier A1-A12, you may employ | adopt the voltage follower circuit by an operational amplifier.

Here, as described above, the gradation voltage output portion 124, as a functional block for converting the video data SD ₁₃ to SD _m to the gradation voltage G ₁₃ ~G _m, and the D / A converter C1~C6 The same functional blocks as those of the gradation voltage interpolation circuits KS1 to KS6 and the amplifiers A1 to A12 are formed in the same form as in FIG. 4 (not shown).

As described above, the gradation voltage output unit 124 applies the odd numbered pixels PX among the (m / 3) pixels PX arranged in parallel along one horizontal scanning line of the display panel 20. Only the corresponding video data SD is subjected to gradation voltage conversion processing by the D / A converter. That is, a plurality of video data pieces corresponding to one horizontal scanning line of the display panel are different from the first video data group (for example, SD _{1 to} SD ₃ , SD _{7 to} SD ₉ ) and the first video data group. The second video data group (eg, SD _{4 to} SD ₆ , SD _{10 to} SD ₁₂ ) is divided. Then, D / A converter by (C1 -C6), gradation voltage having only the video data pieces belonging to the first image data group to the analog voltage value (e.g., _{V 1 ~V 3, V 7 ~V} 9) Is converted to.

Further, in the gradation voltage output unit 124, the gradation voltage interpolation circuit (for example, KS1 to KS6) performs the second video data group by the interpolation processing based on each of the gradation voltages generated by the D / A converter. The gradation voltages (V _{4 to} V ₆ , V _{10 to} V ₁₂ ) corresponding to each of the video data pieces belonging to are obtained.

Specifically, the average calculation unit (51) of the gradation voltage interpolation circuit performs D / D based on one video data piece (for example, SD ₁ ) out of each video data piece belonging to the first video data group. Generated by the D / A converter based on the first gradation voltage (for example, V ₁ ) generated by the A converter and another video data piece (for example, SD ₇ ) belonging to the first video data group An average value of the second gradation voltage (for example, V ₇ ) is obtained as an average gradation voltage (VM). The weighted average calculator (53) of the gradation voltage interpolation circuit obtains the weighted average of the first gradation voltage and the second gradation voltage as the weighted average gradation voltage (VW). Then, the selector (52) of the gradation voltage interpolating circuit, based on the video data piece (for example, SD ₄ ) belonging to the second video data group, the first gradation voltage, the second gradation voltage, One of the average gradation voltage and the weighted average gradation voltage is selected, and this is output as a gradation voltage (for example, V ₄ ) corresponding to the video data piece belonging to the second video data group.

  At this time, the circuit scale and power consumption of the gradation voltage interpolation circuits (KS1 to KS6) are smaller than the circuit scale and power consumption of the D / A converters (C1 to C6).

Therefore, according to the configuration shown in FIG. 4, compared to the case where the gradation voltage conversion processing by the D / A converter is performed on all the video data SD _{1 to} SD _m for one horizontal scanning line, the circuit scale, It is possible to reduce power consumption and heat generation.

In the above configuration, since the number of bits of the video data pieces (for example, SD _{4 to} SD ₆ , SD _{10 to} SD ₁₂ ) corresponding to the even-numbered pixels PX is 2 bits, the data latch unit 122. In addition, the circuit scale and power consumption of the level shift unit 123 are reduced.

Further, according to the configuration described above, the gradation voltages G _{1 to} G _m corresponding to the video data PD _{1 to} PD _m for one horizontal scanning line are applied to the data lines D _{1 to} D _m of the display panel 20 all at once. Therefore, the operating frequency can be lowered as compared with the case where the gray scale voltage is applied in a time division manner within one horizontal scanning period.

  Therefore, according to the data driver 12 of the present embodiment, it is possible to reduce the device scale, power consumption, and heat generation.

  In the above embodiment, the shift register 121 extracts the lower 2 bits from the video data PD corresponding to the even-numbered pixels PX as shown in FIG. Although QD is supplied to the data latch unit 122, the number of bits extracted from the video data PD is not limited to 2 bits. For example, as shown in FIG. 6, the shift register 121 extracts the lower 3 bits from the video data PD corresponding to the even-numbered pixels PX, and uses the 3-bit video data QD as a data latch unit. 122 may be supplied. At this time, for example, the configuration shown in FIG. 7 is adopted as each of the gradation voltage interpolation circuits KS1 to KS6 corresponding to the 3-bit video data QD.

  In FIG. 7, an average calculation unit 51 calculates an average value of the gradation voltage supplied to the input terminal VA and the gradation voltage supplied to the input terminal VB, and selects the average gradation voltage VM indicating the average value as a selector. 52a.

  The weighted average calculator 53a multiplies the gradation voltage supplied to the input terminal VA by a coefficient of 0.2, for example, and multiplies the gradation voltage supplied to the input terminal VB by a coefficient of 0.8, for example. An average value is calculated, and a weighted average gradation voltage VWa indicating the average value is supplied to the selector 52a.

  The weighted average calculation unit 53b multiplies the gradation voltage supplied to the input terminal VA by a coefficient of 0.3, for example, and multiplies the gradation voltage supplied to the input terminal VB by a coefficient of 0.7, for example. An average value is calculated, and a weighted average gradation voltage VWb indicating the average value is supplied to the selector 52a.

  The weighted average calculation unit 53c multiplies the grayscale voltage supplied to the input terminal VA by a coefficient of 0.4, for example, and multiplies the grayscale voltage supplied to the input terminal VB by a coefficient of 0.6, for example. An average value is calculated, and a weighted average gradation voltage VWc indicating the average value is supplied to the selector 52a.

  The weighted average calculation unit 53d multiplies the grayscale voltage supplied to the input terminal VA by a coefficient of 0.6, for example, and multiplies the grayscale voltage supplied to the input terminal VB by a coefficient of 0.4, for example. An average value is calculated, and a weighted average gradation voltage VWd indicating the average value is supplied to the selector 52a.

  The weighted average calculation unit 53e multiplies the gradation voltage supplied to the input terminal VA by a coefficient of 0.8, for example, and multiplies the gradation voltage supplied to the input terminal VB by a coefficient of 0.2, for example. An average value is calculated, and a weighted average gradation voltage VWe indicating the average value is supplied to the selector 52a.

  The selector 52a, based on the 3-bit video data supplied to the selection control terminal SS, the gradation voltage supplied to the input terminal VA, the gradation voltage supplied to the input terminal VB, and the average gradation voltage VM , One of the weighted average gradation voltages VWa to VWd is selected, and the selected voltage is output via the output terminal Y.

  For example, when the 3-bit video data supplied to the selection control terminal SS indicates [000], the selector 52a selects the gradation voltage supplied to the input terminal VA, and this is selected via the output terminal Y. Output. In addition, when the video data indicates [001], the selector 52a selects the average gradation voltage VM and outputs it via the output terminal Y. Further, when the video data indicates [010], the selector 52a selects the gradation voltage supplied to the input terminal VB and outputs it via the output terminal Y. In addition, when the video data indicates [011], the selector 52a selects the weighted average gradation voltage VWa and outputs it via the output terminal Y. In addition, when the video data indicates [100], the selector 52a selects the weighted average gradation voltage VWb and outputs it via the output terminal Y. In addition, when the video data indicates [101], the selector 52a selects the weighted average gradation voltage VWc and outputs it via the output terminal Y. In addition, when the video data indicates [110], the selector 52a selects the weighted average gradation voltage VWd and outputs it via the output terminal Y. In addition, when the video data indicates [111], the selector 52a selects the weighted average gradation voltage VWe and outputs it via the output terminal Y.

  Therefore, according to the configuration shown in FIG. 7, since the types of weighted average gradation voltages are five systems of weighted average gradation voltages VWa to VWe, only one system is used as the weighted average gradation voltage VW as shown in FIG. Compared to the case where the configuration is adopted, a highly accurate gradation voltage can be obtained.

  In the above embodiment, only the video data SD corresponding to the odd-numbered pixels PX is subjected to the gradation voltage conversion processing using the D / A converter to generate the gradation voltage, and based on this gradation voltage. The gradation voltage corresponding to the even-numbered pixels PX is obtained. However, only the video data SD corresponding to the even-numbered pixels PX is subjected to the gradation voltage conversion process using the D / A converter to generate the gradation voltage, and the odd-numbered pixels are arranged based on the gradation voltage. A gradation voltage corresponding to the pixel PX may be obtained.

  Further, in the above embodiment, only the video data SD corresponding to the pixels PX arranged evenly or oddly on one horizontal scanning line, that is, every other pixel PX arranged on one horizontal scanning line. Are subjected to gradation voltage conversion processing using a D / A converter.

  However, the gradation voltage conversion processing by the D / A converter is performed only on the video data SD (first video data group) corresponding to the pixels PX arranged every k (k is a natural number) on one horizontal scanning line. You may make it give. At this time, the gradation voltage corresponding to the other video data SD (second video data group) is obtained by interpolation processing based on each of the gradation voltages generated by the D / A converter.

  FIG. 8 is a block diagram showing another configuration of the gradation voltage output unit 124 made in view of the above points.

In FIG. 8, D / A converter C1a is video data SD _1, to convert the grayscale voltage corresponding to the luminance level represented by the 8-bit data, the gradation voltage as the gradation voltages V ₁ The signals are supplied to the input terminals VA of the interpolation circuits KS1a and KS4a and the amplifier A1.

D / A converter C2a is the video data SD _2, into an analog gradation voltage corresponding to the luminance level represented by the 8-bit data, the gradation voltage interpolating circuit as a gray-scale voltage V ₂ KS2a and KS5a are supplied to the input terminal VA and the amplifier A2.

D / A converter C3a converts the image data SD _3, the analog gradation voltage corresponding to the luminance level represented by the 8-bit data, the gradation voltage interpolating circuit as a gradation voltage V ₃ The signal is supplied to the input terminal VA of each of KS3a and KS6a and the amplifier A3.

D / A converter C4a converts the image data SD _10, into an analog gradation voltage corresponding to the luminance level represented by the 8-bit data, the gradation voltage interpolating circuit as a gray scale voltage V ₁₀ KS1a and KS4a are supplied to the input terminal VB and the amplifier A10.

D / A converter C5a converts the image data SD _11, into an analog gradation voltage corresponding to the luminance level represented by the 8-bit data, the gradation voltage interpolating circuit as a gray scale voltage V ₁₁ KS2a and KS5a are supplied to the input terminal VB and the amplifier A11.

D / A converter C6a converts the image data SD _12, into an analog gradation voltage corresponding to the luminance level represented by the 8-bit data, the gradation voltage interpolating circuit as a gray scale voltage V ₁₂ The signals are supplied to the input terminals VB of the KS3a and KS6a and the amplifier A12.

  Each of the gradation voltage interpolation circuits KS1a to KS6a has a configuration shown in FIG. 5 or FIG.

Average gradation voltage interpolator KS1a includes a gradation voltages V ₁ generated by the D / A converter C1a, a gray scale voltage V ₁₀ generated by the D / A converter C4a, based on the V ₁ and V ₁₀ One of the gradation voltage VM and the weighted average gradation voltage VW based on V ₁ and V ₁₀ is selected based on the video data SD ₄ supplied to the selection control terminal SS, and this is selected as the gradation voltage V. ₄ is supplied to the amplifier A4.

Average gradation voltage interpolator KS2a includes a gray scale voltage V ₂ generated by the D / A converter C2a, the gray scale voltage V ₁₁ generated by the D / A converter C5a, based on V ₂ and V ₁₁ One of the gradation voltage VM and the weighted average gradation voltage VW based on V ₂ and V ₁₁ is selected based on the video data SD ₅ supplied to the selection control terminal SS, and is selected as the gradation voltage V. ₅ is supplied to the amplifier A5.

Average gradation voltage interpolator KS3a includes a gray scale voltage V ₃ generated by the D / A converter C3a, the gray scale voltage V ₁₂ generated by the D / A converter C6a, based on V ₃ and V ₁₂ One of the gradation voltage VM and the weighted average gradation voltage VW based on V ₃ and V ₁₂ is selected based on the video data SD ₆ supplied to the selection control terminal SS, and is selected as the gradation voltage V. ₆ is supplied to the amplifier A6.

Average gradation voltage interpolator KS4a includes a gradation voltages V ₁ generated by the D / A converter C1a, a gray scale voltage V ₁₀ generated by the D / A converter C4a, based on the V ₁ and V ₁₀ One of the gradation voltage VM and the weighted average gradation voltage VW based on V ₁ and V ₁₀ is selected based on the video data SD ₇ supplied to the selection control terminal SS, and is selected as the gradation voltage V. ₇ is supplied to the amplifier A7.

Average gradation voltage interpolator KS5a includes a gray scale voltage V ₂ generated by the D / A converter C2a, the gray scale voltage V ₁₁ generated by the D / A converter C5a, based on V ₂ and V ₁₁ One of the gradation voltage VM and the weighted average gradation voltage VW based on V ₂ and V ₁₁ is selected based on the video data SD ₈ supplied to the selection control terminal SS, and is selected as the gradation voltage V. ₈ is supplied to the amplifier A8 as.

Average gradation voltage interpolator KS6a includes a gray scale voltage V ₃ generated by the D / A converter C3a, the gray scale voltage V ₁₂ generated by the D / A converter C6a, based on V ₃ and V ₁₂ One of the gradation voltage VM and the weighted average gradation voltage VW based on V ₃ and V ₁₂ is selected based on the video data SD ₉ supplied to the selection control terminal SS, and is selected as the gradation voltage V. ₉ is supplied to the amplifier A9.

The amplifiers A1 to A12 have gradation voltages G ₁ to G obtained by individually amplifying the gradation voltages V _{1 to} V ₁₂ supplied from the D / A converters C1a to C6a and the gradation voltage interpolation circuits KS1a to KS6a. G ₁₂ is applied to the data lines D _{1 to} D ₁₂ of the display panel 20.

As described above, in the configuration shown in FIG. 8, only the video data pieces (for example, SD _{1 to} SD ₃ , SD _{10 to} SD ₁₂ ) corresponding to every second pixel PX arranged on one horizontal scanning line. applying a gradation voltage conversion processing by the D / a converter (C1a～C6a) by, generating a grayscale voltage corresponding to the video data pieces (e.g. _{V 1 ~V 3, V 10 ~V} 12) on. Then, by interpolation processing based on each of the gradation voltage D / A converter is generated, other video data pieces (e.g., SD ₄ to SD ₉₎ grayscale voltage corresponding to (e.g., V ₄ ~V ₉₎ To get.

Therefore, if the configuration shown in FIG. 8 is adopted as the gradation voltage output unit 124, (m / 3) D / A converters for _m pixel data SD _{1 to} SD _m for one horizontal scanning line. Should be provided. Therefore, as compared with the case where the configuration shown in FIG. 4 is adopted in which (m / 2) D / A converters are required for _m pixel data SD _{1 to} SD _m for one horizontal scanning line. The circuit scale of the D / A converter provided in the data driver 12 can be reduced. As a result, the chip size of the data driver 12 can be further reduced, and power consumption and heat generation can be reduced.

  In the above embodiment, the number of bits of the video data piece (PD, QD, LD, SD) is 8 bits, but the number of bits of the video data piece is not limited to 8 bits.

  Further, in the display device shown in FIG. 1, the input video data VD consisting of a series of video data pieces representing the luminance level corresponding to each pixel is an input target. However, the following input video data VD is also an input target. good.

  That is, in the sequence of video data pieces in the input video data VD, the video data piece corresponding to the pixel PX that is not the target of gradation voltage conversion by the D / A converter is changed to a gradation voltage designation data piece. This is the input target. The gradation voltage designation data piece is data that designates the gradation voltage selected by the selector 52 or 52a described above.

  For example, when the configuration shown in FIG. 4 is adopted as the gradation voltage output unit 124, the input video data VD having the format shown in FIG. 9 becomes an input target of the display device shown in FIG.

The input video data VD shown in FIG. 9 corresponds to the odd-numbered pixels PX (first pixel group) on the horizontal scanning line of the display panel 20, for example, video data PD ₁ to 8 bits each consisting of 8 bits. _{PD 3, PD 7 ~PD 9,} PD 13 ~PD 15, ···, series of PD _m-2 ~PD _m are arranged. Further, the input video data VD is associated with each even-numbered pixel PX (second pixel group) on the horizontal scanning line, for example, gradation voltage designation data SQ _{4 to} SQ ₆ each consisting of 2 bits, A sequence of SQ _{10 to} SQ ₁₂ ,..., SQ _{m-5 to} PD _m-3 is arranged.

When the input video data VD shown in FIG. 9 is input, the shift register 121 of the data driver 12 receives a video data piece (by the input video data VD) every time the input video data VD for one horizontal scanning line is captured. PD) and a series of gradation voltage designation data pieces (SQ) are supplied to the data latch 122 as video data QD _{1 to} QD _m .

As a result, the D / A converters (for example, C1 to C6) of the gradation voltage output unit 124 have video data pieces (for example, SD _{1 to} SD ₃ , corresponding to each of the pixels PX belonging to the first pixel group described above). SD ₇ ~SD ₉₎ respectively obtained was converted into a voltage value of the analog gradation voltage having the voltage value (e.g., _{V 1 ~V 3, V 7 ~V} 9) of the.

Here, the grayscale voltage interpolation circuit (for example, KS1 to KS6) of the grayscale voltage output unit 124 performs the interpolation process based on each of the grayscale voltages generated by the D / A converter, thereby performing the second video data group. The gradation voltages (V _{4 to} V ₆ , V _{10 to} V ₁₂ ) corresponding to each of the video data pieces belonging to are obtained. In other words, the average calculator (51) of the gradation voltage interpolation circuit generates the first floor generated by the D / A converter based on one video data piece of each of the video data pieces belonging to the first pixel group. The average value of the gradation voltage and the second gradation voltage generated by the D / A converter based on the other image data pieces of each of the image data pieces belonging to the first pixel group is the average gradation voltage. Asking. The weighted average calculator (53) of the gradation voltage interpolation circuit obtains the weighted average of the first gradation voltage and the second gradation voltage as the weighted average gradation voltage. Then, the selector (52) of the gradation voltage interpolation circuit selects the first gradation voltage, the second gradation voltage, the average scale based on the gradation voltage selection data piece corresponding to the pixels belonging to the second pixel group. One of the regulated voltage and the weighted average gradation voltage is selected, and this is output as the gradation voltage corresponding to the pixels belonging to the second pixel group.

12 Data Driver 20 Display Panel 51 Average Calculation Unit 52 Selector 53 Weighted Average Calculation Unit 121 Shift Register 124 Grayscale Voltage Output Units C1 to C6 D / A Converters KS1 to KS6 Grayscale Voltage Interpolation Circuit

Claims (4)

A driving device for applying a pixel driving voltage to a display panel having a plurality of data lines,
First analog data corresponding to a first pixel driving voltage applied to a first data line, second analog data corresponding to a second pixel driving voltage applied to a second data line, and the first data line And a third analog corresponding to the pixel drive voltage applied to the third data line according to the digital data indicating the pixel drive voltage for the third data line disposed between the second data line and the third data line A display panel driving device comprising a gradation voltage interpolation circuit for generating data. The digital data consists of a plurality of bits,
2. The display panel drive according to claim 1, wherein the gradation voltage interpolation circuit generates the third analog data according to a value of a part of the plurality of bits of the digital data. apparatus. A first D / A converter that outputs the first analog data based on digital data indicating the first pixel driving voltage;
A second D / A converter that outputs the second analog data based on the digital data indicating the second pixel driving voltage;
The display panel driving apparatus according to claim 1, further comprising:   The grayscale voltage interpolation circuit corresponds to the digital data indicating the pixel driving voltage for the third data line among a plurality of voltages generated according to the first analog data and the second analog data. 4. The display panel driving apparatus according to claim 1, wherein a voltage to be generated is generated. 5.