JP2018170065A - Nonvolatile memory device and inspection method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile memory device and an inspection method thereof for making it possible to suppress variations in retention time of a resistance change element without increasing a cell size.SOLUTION: An inspection method of a nonvolatile memory device includes: determining whether or not a current flowing through a resistance change element is higher than a current flowing through a reference resistance element, when a first read voltage lower than a write voltage is applied to the resistance change element and the reference resistance element after applying the write voltage to the resistance change element; determining whether or not the current flowing through the resistance change element is higher than the current flowing through the reference resistance element, when a second read voltage which is lower than the write voltage and different from the first read voltage is applied to the resistance change element and the reference resistance element; and determining whether or not writing has normally been performed by the resistance change element on the basis of the two determination results.SELECTED DRAWING: Figure 11

Description

  The present invention relates to a nonvolatile memory device using a resistance change element and an inspection method thereof.

  The resistance change element includes a resistance change layer sandwiched between two metal electrodes (first electrode and second electrode). The resistance of the resistance change layer is reversibly changed by applying a voltage between both electrodes. In a low resistance state (ON state), metal bridges or oxygen vacancies are formed in the resistance change layer by applying a voltage. On the other hand, when transitioning to a high resistance state (OFF state), by applying a voltage opposite to the voltage transitioning to the ON state, the above-described metal bridges or oxygen vacancies formed in the resistance change layer are applied. Part or all is removed. When no voltage is applied, each state is maintained and the resistance value is maintained in a nonvolatile manner.

  Such nonvolatile resistance change is used for nonvolatile memories, nonvolatile switches in nonvolatile programmable logic, and the like. Non-volatile memories and non-volatile switches are required to retain resistance values for more than 10 years. In order to read the difference between the ON state and the OFF state, it is desirable that the difference between the ON / OFF resistance values is large. A non-volatile memory requires a resistance ratio of one digit, and a non-volatile switch requires a resistance ratio of four digits or more. As a device using a resistance change element as a nonvolatile memory, for example, there is a nonvolatile memory device having a cross-point type memory cell array configured using the resistance change element (see Patent Document 1).

The resistance in the ON state (ON resistance) can be controlled by the current that flows when transitioning from the OFF state to the ON state. Here, as shown in Equation (1) of Non-Patent Document 1, there is a proportional relationship between the ON resistance (R) and the inverse of the control current (I _C ). In order to reduce the ON resistance, the control current at the time of writing may be increased. Typically, in order to obtain an ON resistance of 1 kΩ, a current of about 0.5 mA is required. On the other hand, when the transition is made to the OFF state, a current comparable to the current that flows when transitioning to the ON state is required.

Republished Patent No. 2013/145733

D. Ielmini et al., "Universal Reset Characteristics of Unipolar and Bipolar Metal-Oxide RRAM", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 10, OCTOBER 2011

  The following analysis is given by the inventor.

  The inventors have found that the ON resistance has a correlation with the holding time. The lower the ON resistance, the longer the holding time. On the other hand, in order to reduce the ON resistance, a large write current, that is, a large transistor is required as described above, and the size of each memory or switch (cell size) increases.

  On the other hand, the inventors have also found that there is variation in holding characteristics even with resistance change elements having the same ON resistance. In order to guarantee an operation time of 10 years of a memory device including a large number of resistance change elements, the retention time needs to exceed the shortest 10 years. If the variation in the retention time is large, a lower ON resistance is required. That is, a higher write current is required. As a result, the cell size becomes large.

  By the way, a large number (for example, 1 mega or more) of resistance change elements are mounted on the nonvolatile memory and the nonvolatile programmable logic. It is desirable that the characteristics of all the mounted variable resistance elements are uniform, and in particular, the retention characteristics are related to reliability and are important. However, when the ON state and the OFF state are compared, the holding time in the ON state is shorter, the OFF state is more stable, and variation in the holding state in the ON state becomes a problem. As described above, the holding time in the ON state has a correlation with the ON resistance of the variable resistance element, and the holding time tends to be longer when the ON resistance is low. On the other hand, even if the ON resistance is equivalent, there is a problem that the holding time of a small number of resistance change elements becomes shorter than expected. In addition, this defect is difficult to predict in advance.

  The main subject of this invention is providing the non-volatile memory device which can suppress the dispersion | variation in the retention time of a resistance change element, and its test | inspection method, without enlarging a cell size.

  In the nonvolatile memory device according to the first aspect, a resistance change layer is disposed between the first electrode and the second electrode, and a write voltage is applied between the first electrode and the second electrode, A resistance change element in which a resistance between the first electrode and the second electrode reversibly changes, a reference resistance element set to a predetermined resistance value for reference, the resistance change element, and the reference resistance element And a control unit capable of comparing a current flowing through the resistance change element and a current flowing through the reference resistance element, and the control unit includes the resistance change After a write voltage is applied to the element, when a first read voltage lower than the write voltage is applied to the resistance change element and the reference resistance element, a current flowing through the resistance change element flows through the reference resistance element. Current And a second read voltage that is lower than the write voltage and different from the first read voltage is applied to the variable resistance element and the reference resistive element. The second determination process for determining whether or not the current flowing through the resistance change element is higher than the current flowing through the reference resistance element, and based on the results of the first determination process and the second determination process And a third determination process for determining whether or not writing is normally performed by the variable resistance element.

  In the nonvolatile memory device inspection method according to the second aspect, a resistance change layer is disposed between the first electrode and the second electrode, and a write voltage is applied between the first electrode and the second electrode. Accordingly, there is provided a method for inspecting a nonvolatile memory device including a resistance change element in which a resistance between the first electrode and the second electrode reversibly changes, and the nonvolatile memory device is predetermined for reference. When a first read voltage lower than the write voltage is applied to the resistance change element and the reference resistance element after applying a write voltage to the resistance change element. In addition, a first determination step for determining whether or not a current flowing through the resistance change element is higher than a current flowing through the reference resistance element, and the resistance change element and the reference resistance element are lower than the write voltage, A second determination step of determining whether a current flowing through the resistance change element is higher than a current flowing through the reference resistance element when a second read voltage different from the first read voltage is applied; And a third determination step of determining whether or not writing has been normally performed by the variable resistance element based on the results of the first determination step and the second determination step.

  According to the first and second viewpoints, variations in the holding time of the resistance change element can be suppressed without increasing the cell size, and the reliability is improved.

3 is a schematic diagram showing a configuration of a resistance change memory cell used in the nonvolatile memory device according to Embodiment 1. FIG. 3 is a schematic diagram illustrating a configuration of a reference resistance cell used in the nonvolatile memory device according to Embodiment 1. FIG. 3A is a configuration diagram and FIG. 5B is a graph showing current-voltage characteristics when a high-density bridge is formed in a variable resistance element used in the nonvolatile memory device according to Embodiment 1. FIG. 3A is a configuration diagram when a low density bridge portion is formed in a variable resistance element used in the nonvolatile memory device according to Embodiment 1, and FIG. 4B is a graph showing current-voltage characteristics. 1 is a circuit diagram illustrating a configuration of a part of a nonvolatile memory device according to Embodiment 1. FIG. 3 is a circuit diagram showing a detailed configuration of a read circuit in the nonvolatile memory device according to Embodiment 1. FIG. 3 is a timing chart schematically showing the operation of each signal of the read circuit in the nonvolatile memory device according to Embodiment 1. FIG. 6 is a graph showing variations in current-voltage characteristics when the resistance change element in the nonvolatile memory device according to Embodiment 1 is in an ON state. 3 is a flowchart schematically showing the operation of the nonvolatile memory device according to Embodiment 1. FIG. 4 is a circuit diagram illustrating a configuration of a part of a nonvolatile memory device according to a second embodiment. 5 is a flowchart schematically showing the operation of the nonvolatile memory device according to Embodiment 2.

  Hereinafter, embodiments will be described with reference to the drawings. Note that, in the present application, where reference numerals are attached to the drawings, these are only for the purpose of helping understanding, and are not intended to be limited to the illustrated embodiments. In addition, the following embodiment is an illustration to the last and does not limit this invention. In addition, connection lines between blocks such as drawings referred to in the following description include both bidirectional and unidirectional directions. The unidirectional arrow schematically shows the main signal (data) flow and does not exclude bidirectionality.

[Embodiment 1]
The nonvolatile memory device according to Embodiment 1 will be described.

  First, a resistance change memory cell and a reference resistance cell used in the nonvolatile memory device according to Embodiment 1 will be described with reference to the drawings. FIG. 1 is a schematic diagram illustrating a configuration of a resistance change memory cell used in the nonvolatile memory device according to the first embodiment. FIG. 2 is a schematic diagram illustrating a configuration of a reference resistance cell used in the nonvolatile memory device according to the first embodiment. FIG. 3 is a graph showing (A) a configuration diagram and (B) current-voltage characteristics when a high-density bridge is formed in the variable resistance element used in the nonvolatile memory device according to the first embodiment. FIG. 4A is a configuration diagram and FIG. 4B is a graph showing current-voltage characteristics when a low-density bridge is formed in the variable resistance element used in the nonvolatile memory device according to the first embodiment.

  Referring to FIG. 1, the resistance change memory cell 1 has a configuration in which a resistance change element 10 and an access transistor 20 are connected in series.

  The resistance change element 10 is an element of a laminated structure in which the resistance change layer 12 is disposed between the first electrode 11 and the second electrode 13 (see FIG. 1). The resistance change element 10 reversibly changes the resistance between the first electrode 11 and the second electrode 13 by applying a write voltage between the first electrode 11 and the second electrode 13. The first electrode 11 is electrically connected to a corresponding bit line (for example, any one of BL1 to BLm in FIG. 5). Second electrode 13 is electrically connected to the drain electrode of access transistor 20.

  The resistance change element 10 includes a metal bridge type in which a metal bridge portion (14 in FIG. 3A, 15 in FIG. 4A) is formed in the resistance change layer 12 by application of a voltage, and an oxygen deficient portion ( There is an oxygen deficient type in which (not shown) is formed. For the first electrode 11, a metal material can be used, and for example, copper, nickel, cobalt, iron, titanium, vanadium, chromium, zirconium, niobium, hafnium, tantalum, tungsten, or the like can be used. Similarly, the second electrode 13 can be made of a metal material having a lower ionization tendency than the metal material used for the first electrode 11, and the same metal material as that used for the first electrode 11. For example, ruthenium, Platinum, rhodium, palladium, silver, osnium, iridium, gold, or the like can be used. Similarly, a metal oxide can be used for the resistance change layer 12, and for example, tantalum oxide, titanium oxide, hafnium oxide, nickel oxide, or the like can be used. In the following description, the first electrode 11 is copper, the second electrode 13 is ruthenium, and the resistance change layer 12 is tantalum oxide.

  The access transistor 20 is a transistor (switch) for accessing the resistance change element 10 of the resistance change memory cell 1 (see FIG. 1). The access transistor 20 is used to control a current when writing to the resistance change element 10 and to select only one resistance change memory cell 1 in the two-dimensional array. As the access transistor 20, for example, an n-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) can be used. The gate electrode of access transistor 20 is electrically connected to a corresponding word line (for example, one of WL1 to WLn in FIG. 5). The drain electrode of access transistor 20 is electrically connected to second electrode 13 of resistance change element 10. The source electrode of access transistor 20 is electrically connected to ground.

  In the resistance change element 10 as described above, when a positive voltage is applied to the first electrode 11, the metal (for example, copper) in the first electrode 11 becomes a metal ion (for example, copper ion) by an electrochemical reaction, and resistance Implanted into the change layer 12 (eg, tantalum oxide). Thereafter, the metal ions implanted into the resistance change layer 12 move in the resistance change layer 12 by an electric field, and combine with electrons injected from the second electrode 13 (for example, ruthenium) side to become a metal. Precipitates in the resistance change layer 12. The resistance of the resistance change layer 12 changes from a high resistance (OFF resistance) to a low resistance (ON resistance) due to metal deposition. When the resistance of the resistance change layer 12 changes to a low resistance, the voltage applied to the resistance change element 10 decreases, and most of the voltage input from the access transistor 20 connected in series to the resistance change element 10 is a resistance. It will be applied to the change element 10. Since the voltage necessary for ionizing or precipitating the metal of the first electrode 11 is reduced, the metal deposition of the first electrode 11 stops and the resistance value is fixed. Since the current that flows when the metal deposition of the first electrode 11 stops is equal to the saturation current of the access transistor 20, the resistance of the resistance change element 10 is defined.

  The point where the metal of the first electrode 11 precipitates in the resistance change layer 12 is considered to be where the electric field is strongest, but there are structural variations such as local thickness of the resistance change layer 12 and unevenness of the electrode surface. For this reason, the resistance change element 10 is not constant. If the electric field is non-uniform, the interval between the deposited metal atoms is not constant and varies. The inventors have found that the temperature dependence of the ON resistance is different even when the ON resistances of the different variable resistance elements 10 are equal. It is also known that the linearity is different in the current / voltage characteristics of the variable resistance element 10. When the ON resistance increases as the temperature increases, it can be said that the scattering factor that causes the resistance is phonon scattering, and the metal bridge exhibits metallic conduction characteristics. The current / voltage characteristics at this time are linear, and the current is proportional to the voltage (see FIG. 3B).

  On the other hand, when the ON resistance decreases as the temperature increases, the electron concentration increases at a high temperature, indicating semiconductor-like conduction characteristics. The current / voltage characteristics at this time are non-linear, and the current is not proportional to the voltage, and a current different from the current value expected in the proportional relationship flows as the voltage is increased (see FIG. 4B). ).

  When showing metallic conduction, it is considered that the distance between metal atoms in the resistance change layer 10 is short, and the density of the metal is high. That is, the metal bridge has a small diameter and a high metal density (see the high-density metal bridge portion 14 in FIG. 3A). On the other hand, when semiconductor temperature dependence is exhibited, it is considered that the distance between metal atoms is large and the density of metal atoms is relatively small. That is, it can be said that the metal bridge has a large diameter and a low metal density (see the low-density metal bridge portion 15 in FIG. 4A).

  When the film thickness of the resistance change layer 12 is constant, the ON resistance of the metal bridge portion is determined by the thickness of the metal atom and its density. In addition, the retention property in the ON state is excellent when the density of metal atoms is high, and the retention property is poor when the density of metal atoms is low. The difference in the density of these metal atoms causes variations in retention characteristics. That is, it can be said that the variation in the ON resistance holding time of the variable resistance element 10 is related to the stability of the metal bridge portion in the variable resistance layer 12. The same can be said for the oxygen deficient resistance change element.

  By the way, in the normal reading of the ON / OFF state of the variable resistance element, it is possible to read by applying a constant voltage and the magnitude of the current. However, such a readout method cannot read out even the difference in density of metal atoms. Reading the difference in density is possible by measuring the current at two different voltages.

  Referring to FIG. 2, the reference resistance cell 2 has a configuration in which a reference resistance element 30 and an access transistor 40 are connected in series.

  The reference resistance element 30 is an element set to a predetermined resistance value for reference (see FIG. 2). For the reference resistance element 30, a resistance material capable of keeping the resistance value constant can be used. For example, polysilicon or the like can be used. The resistance value of the reference resistance element 30 can be set to about 1 kΩ, for example. One end of the reference resistance element 30 is electrically connected to a bit line (for example, BLref in FIG. 5). The other end of reference resistance element 30 is electrically connected to the drain electrode of access transistor 40.

  The access transistor 40 is a transistor (switch) for accessing the reference resistance element 30 of the reference resistance cell 2 (see FIG. 2). For the access transistor 40, for example, an n-type MOSFET can be used. The gate electrode of access transistor 40 is electrically connected to a word line (for example, WL1 to WLn in FIG. 5). The drain electrode of the access transistor 40 is electrically connected to the other end of the reference resistance element 30. The source electrode of access transistor 40 is electrically connected to ground.

  Referring to FIG. 3, the configuration and current-voltage characteristics of the variable resistance element 10 having a linear current-voltage characteristic are shown. The resistance of the resistance change element 10 is turned on and off by comparing the current flowing when a certain voltage is applied with the current flowing through the reference resistance element (30 in FIG. 2) to which the same voltage is applied. Can be distinguished. If the current-voltage characteristic of the resistance change element 10 is a linear type, the current flowing through the resistance change element 10 is larger than the current flowing through the reference resistance element 30 at any applied voltage (FIG. 3B). 8) (see FIG. 8A), the same, or small (see FIG. 8B). Therefore, in the resistance change element 10 having a linear current-voltage characteristic, the distinction between ON and OFF does not change depending on the applied voltage. That is, when the applied voltage V1 is applied to the reference resistance element 30, the current I1 flows, and when the voltage V2 is applied, the current I2 flows. However, when the current-voltage characteristic is the linear resistance change element 10, The current flowing through the resistance change element 10 is either larger than I1 and I2 (see FIG. 8A), the same, or smaller (see FIG. 8B).

  Referring to FIG. 4, a configuration and a current-voltage side property of the variable resistance element 10 having a nonlinear current-voltage characteristic are shown. When the current-voltage characteristic is a non-linear type, the magnitude relationship between the current flowing through the resistance change element 10 and the current flowing through the reference resistance element (30 in FIG. 2) varies depending on the applied voltage. In the reference resistance element 30, when the applied voltage V1 is applied, the current I1 flows, and when the voltage V2 is applied, the current I2 flows. However, in the case of the resistance change element 10 having a nonlinear current-voltage characteristic, the resistance I The current flowing through the change element 10 has a different magnitude relationship with I1 and I2. However, it is necessary to select V1 and V2 appropriately. When V1 and V2 are close to each other or when both are sufficiently large, the magnitude relationship between I1 and I2 may be the same.

  Next, the configuration of the nonvolatile memory device according to Embodiment 1 will be described with reference to the drawings. FIG. 5 is a circuit diagram illustrating a partial configuration of the nonvolatile memory device according to the first embodiment.

  The nonvolatile memory device 100 is a memory device having the variable resistance element 10 shown in FIG. 1 as a nonvolatile memory (see FIG. 5). The nonvolatile memory device 100 includes a resistance change memory cell array 3, a reference resistance cell array 4, a row decoder 51, a column decoder 52, a read circuit 60, a write circuit 70, and a control circuit 80.

  The resistance change memory cell array 3 is a portion in which a plurality of resistance change memory cells 1 are two-dimensionally arranged (see FIG. 5). In FIG. 5, in the resistance change memory cell array 3, resistance change memory cells 1 are arranged in N rows and M columns. The configuration of the resistance change memory cell 1 (the resistance change element 10 and the access transistor 20) is as described above (see FIG. 1). In the resistance change memory cell array 3, one end of the resistance change element 10 of each resistance change memory cell 1 in the same column is connected to a column decoder 52 via a corresponding bit line (any one of BL1 to BLm in FIG. 5). Electrically connected. Further, in the resistance change memory cell array 3, the gate electrode of the access transistor 20 of each resistance change memory cell 1 in the same row is a row decoder via a corresponding word line (any one of WL1 to WLn in FIG. 5). 51 is electrically connected. The source electrode of the access transistor 20 of each resistance change memory cell 1 in the resistance change memory cell array 3 is electrically connected to the ground.

  The reference resistance cell array 4 is a portion in which the plurality of reference resistance cells 2 shown in FIG. 2 are arranged one-dimensionally (see FIG. 5). In FIG. 5, the reference resistance cell array 4 includes reference resistance cells 2 arranged in N rows and 1 column. The configuration of the reference resistance cell 2 (reference resistance element 30 and access transistor 40) is as described above (see FIG. 2). In the reference resistance cell array 4, one end of the reference resistance element 30 of each reference resistance cell 2 is electrically connected to the column decoder 52 via the bit line BLref. In the reference resistor cell array 4, the gate electrode of the access transistor 40 of the reference resistor cell 2 is electrically connected to the row decoder 51 via a corresponding word line (any one of WL1 to WLn in FIG. 5). ing. The source electrode of the access transistor 40 of each reference resistance cell 2 in the reference resistance cell array 4 is electrically connected to the ground.

  The row decoder 51 is a decoder that can select one word line from a plurality of word lines WL1 to WLn arranged in n rows. The row decoder 51 functions as a cell selection circuit that selects one resistance change element 10 and one reference resistance element 30 from the resistance change memory cell array 3 and the reference resistance cell array 4 in cooperation with the column decoder 52. The row decoder 51 selects one word line from the word lines WL1 to WLn according to the ADD signal from the control circuit 80, and is electrically connected to the selected word line via the selected word line. A voltage is applied to the access transistors 20 and 40. Accordingly, the decoder 51 includes the resistance change memory cell 1 (resistance change element 10 and the access transistor 20) and the reference resistance cell 2 (reference resistance element 30) in one row from the resistance change memory cell array 3 and the reference resistance cell array 4. , The access transistor 40) can be selected. The column decoder 51 selects the word line WL1 in FIG.

  The column decoder 52 is a decoder capable of selecting one bit line from a plurality of bit lines BL1 to BLm arranged in m columns. The column decoder 52 can also select the bit line BLref. The column decoder 52 functions as a cell selection circuit that selects one resistance change element 10 from each of the resistance change memory cell array 3 and the reference resistance cell array 4 in cooperation with the row decoder 51. The column decoder 52 includes a column transistor 52a and a column transistor 52b arranged in m columns. The column decoder 52 selects one bit line from the bit lines BL1 to BLm by applying a voltage to any one of the gate electrodes of the column transistor 52a in accordance with the ADD signal from the control circuit 80. The resistance change element 10 electrically connected to the selected bit line is electrically connected to the read circuit 60 and the write circuit 70 via the bit line. Further, the column decoder 52 selects the bit line BLref by applying a voltage to the gate electrode of the column transistor 52b under the control of the control circuit 80, and the selected bit line BLref is selected via the selected bit line BLref. The reference resistance element 30 and the readout circuit 60 electrically connected to each other are electrically connected. In FIG. 6, the column decoder 52 selects the bit line BL2 and the bit line BLref.

  The read circuit 60 is a circuit that can read the resistance values of the resistance change element 10 and the reference resistance element 30 (see FIG. 5). The read circuit 60 can apply a read voltage to the selected resistance change element 10 and reference resistance element 30. Further, the readout circuit 60 can compare the current flowing through the selected resistance change element 10 with the current flowing through the reference resistance element 30. The readout circuit 60 controls the readout of the selected variable resistance element 10 and reference resistance element 30 under the control of the control circuit 80.

  The read circuit 60 performs the following processing after applying a write voltage to the variable resistance element 10. Whether the current flowing through the resistance change element 10 is higher than the current flowing through the reference resistance element 30 when the read circuit 60 applies a first read voltage lower than the write voltage to the resistance change element 10 and the reference resistance element 30. A first determination process is performed to determine whether or not. Further, the read circuit 60 has a current flowing through the resistance change element 10 when a second read voltage lower than the write voltage and different from the first read voltage is applied to the resistance change element 10 and the reference resistance element 30. A second determination process is performed to determine whether or not the current flowing through the reference resistance element 30 is higher. Further, the read circuit 60 performs a third determination process for determining whether or not writing has been normally performed in the resistance change element 10 based on the results of the first determination process and the second determination process. Note that the second read voltage can be lower than the first read voltage. In the third determination process, when it is determined in each of the first determination process and the second determination process that the current flowing through the resistance change element 10 is higher than the current flowing through the reference resistance element 30, the resistance change element 10 normally It is determined that writing has been performed. Further, in the third determination process, when it is determined in one or both of the first determination process and the second determination process that the current flowing through the resistance change element 10 is not higher than the current flowing through the reference resistance element 30, the resistance change It is determined that writing has not been normally performed in the element 10. The detailed configuration of the read circuit 60 will be described later.

  The write circuit 70 is a circuit that can apply a write voltage to the selected variable resistance element 10. The write circuit 70 controls writing to the selected variable resistance element 10 under the control of the control circuit 80.

  The control circuit 80 is a circuit that controls the row decoder 51, the column decoder 52, the read circuit 60, and the write circuit 70. The control circuit 80 selects the resistance change element 10 and the reference resistance element 30 via the row decoder 51, the column decoder 52, and the access transistors 20 and 40. The control circuit 80 applies a read voltage to the selected resistance change element 10 and the reference resistance element 30 via the read circuit 60. The control circuit 80 applies the write voltage to the corresponding resistance change element 10 again when it is determined in the third determination process in the read circuit 60 that writing has not been normally performed by the resistance change element 10. I do. The control circuit 80 applies a write voltage to the selected variable resistance element 10 via the write circuit 70.

  Next, a detailed configuration of the read circuit in the nonvolatile memory device according to Embodiment 1 will be described with reference to the drawings. FIG. 6 is a circuit diagram illustrating a detailed configuration of the read circuit in the nonvolatile memory device according to the first embodiment.

  The read circuit 60 includes a clamp switch 61, a sense amplifier 65, a register 66, and a logic circuit 67 (see FIG. 6).

  The clamp switch 61 is a switch for switching electrical connection between the column decoder 52 and the sense amplifier 65 (see FIG. 6). The clamp switch 61 includes a clamp transistor 61a and a clamp transistor 61b.

  The clamp transistor 61a is a transistor that can electrically connect the column transistor 52a of the column decoder 52 and the INA terminal of the sense amplifier 65 (see FIG. 6). The drain electrode of the clamp transistor 61a is electrically connected to the INA terminal of the sense amplifier 65. The source electrode of the clamp transistor 61 a is electrically connected to the drain electrode of each column transistor 52 a of the column decoder 52. The gate electrode of the clamp transistor 61a is connected to the control circuit (80 in FIG. 5), and the voltage VBIAS is applied from the control circuit 80 to electrically connect the column transistor 52a of the column decoder 52 and the INA terminal of the sense amplifier 65. Connect to.

  The clamp transistor 61b is a transistor that can electrically connect the column transistor 52b of the column decoder 52 and the INB terminal of the sense amplifier 65 (see FIG. 6). The drain electrode of the clamp transistor 61b is electrically connected to the INB terminal of the sense amplifier 65. The source electrode of the clamp transistor 61 b is electrically connected to the drain electrode of the column transistor 52 b of the column decoder 52. The gate electrode of the clamp transistor 61b is connected to the control circuit (80 in FIG. 5). When the voltage VBIAS is applied from the control circuit 80, the column transistor 52b of the column decoder 52 and the INB terminal of the sense amplifier 65 are electrically connected. Connect to.

  The sense amplifier 65 is a circuit that amplifies the current flowing through the selected resistance change element 10 and the current flowing through the reference resistance element 30 (see FIG. 6). The INA terminal of the sense amplifier 65 can be electrically connected to the selected resistance change element 10 via the clamp transistor 61a and the column transistor 52a. The INB terminal of the sense amplifier 65 can be electrically connected to the selected reference resistance element 30 via the clamp transistor 61b and the column transistor 52b. The SOUT terminal of the sense amplifier 65 is electrically connected to one of the input terminals of the logic circuit 67 and each of the input terminals of the register 66. The RD terminal of the sense amplifier 65 is electrically connected to the control circuit (80 in FIG. 5).

  When the RD signal is input from the control circuit 80, the sense amplifier 65 applies a read voltage corresponding to the voltage VRD of the RD signal to the selected resistance change element 10 and the reference resistance element 30, and the selected resistance change. The current applied to the element 10 and the reference resistance element 30 is compared with the current flowing through the selected resistance change element 10 and the current flowing through the reference resistance element 30. The sense amplifier 65 has “High” (“High”) depending on the magnitude of two currents (icell and iref) of one of the bit lines BL1 to BLm (BL2 in FIG. 6) and the INA terminal and INB terminal connected to the bit line BLref. A SOUT signal having a logic level of “power supply voltage level” or “Low” (ground level) is output from the SOUT terminal. When icell> iref, “High” is output from the SOUT terminal, and when icell <iref, “Low” is output from the SOUT terminal. Here, icell is a current flowing through the resistance change element 10. Further, iref is a current flowing through the reference resistance element 30. icell and iref are proportional to the applied voltage VRD, respectively. Thereby, the sense amplifier 65 can perform the first determination process and the second determination process.

  The register 66 is a circuit that temporarily holds the comparison result of the sense amplifier 65 (see FIG. 6). The input terminal of the register 66 is electrically connected to the SOUT terminal of the sense amplifier 65. The SE terminal of the register 66 is electrically connected to the control circuit (80 in FIG. 5). The DOUT terminal of the register 66 is electrically connected to the other input terminal of the logic circuit 67. For example, a D-type flip-flop can be used for the register 66. The register 66 controls the timing of holding the SOUT signal (the result of the first determination process) output from the sense amplifier 65 in accordance with the SE signal from the control circuit 80. The register 66 latches the SOUT signal (High or Low) output from the sense amplifier 65 in synchronization with the rising edge of the SE signal input from the control circuit 80 to the SE terminal, and is directed from the DOUT terminal to the logic circuit 67. To output “High” or “Low”. Thereby, the register 66 can temporarily hold the result of the first determination process in the sense amplifier 65.

  The logic circuit 67 is a circuit that outputs a logic result based on the DOUT signal output from the register 66 and the SOUT signal output from the sense amplifier 65 (see FIG. 6). One input terminal of the logic circuit 67 is electrically connected to the SOUT terminal of the sense amplifier 65. The other input terminal of the logic circuit 67 is electrically connected to the DOUT terminal of the register 66. The ROUT terminal of the logic circuit 67 is electrically connected to the control circuit (80 in FIG. 5). As the logic circuit 67, for example, an AND circuit can be used. The logic circuit 67 outputs the result of the third determination process based on the result of the first determination process held in the register 66 and the result of the second determination process in the sense amplifier 65.

  Next, the operation of the read circuit in the nonvolatile memory device according to Embodiment 1 will be described with reference to the drawings. FIG. 7 is a timing chart schematically showing the operation of each signal of the read circuit in the nonvolatile memory device according to the first embodiment. Refer to FIGS. 5 and 6 for the constituent parts of the nonvolatile memory device 100.

  FIG. 7 shows a timing chart of signals in the readout circuit 60 of FIG. The ADD signal is an address signal input to the row decoder 51 and the column decoder 52, the RD signal is a signal for determining a voltage applied to the bit line BL2 and the bit line BLref from the sense amplifier 65, and the SOUT signal is output from the sense amplifier 65. The signal and the SE signal are signals input to the register 66, the DOUT signal is a signal output from the register 66, and the ROUT signal is a signal output from the logic circuit 67. Here, it is assumed that the voltage VBIAS is applied to the clamp switch 61.

  First, at time T <b> 0, an ADD signal is input to the row decoder 51 and the column decoder 52, and one set of the resistance change element 10 and the reference resistance element 30 is selected by the row decoder 51 and the column decoder 52. As a result, the resistance change element 10 and the reference resistance element 30 are electrically connected to the sense amplifier 65. Here, the case where the selected variable resistance element 10 has a non-linear current-voltage characteristic in FIG. 4 will be described.

  Next, when a voltage with an amplitude VR1 is input as the RD signal to the sense amplifier 65 at time T1, the first read voltage V1 is applied to the selected resistance change element 10 and the reference resistance element 30. At this time, due to the voltage drop in the wiring resistance and the access transistors 20 and 40, the column transistors 52a and 52b, and the clamp transistors 61a and 61b, a voltage about 0.4V smaller than the voltage applied to the sense amplifier 65 is referred to. It is applied to the resistance element 30. Further, the electrical characteristics of the path from the sense amplifier 65 to the resistance change element 10 are made equal to the electrical characteristics of the path from the sense amplifier 65 to the reference resistance element 30. Here, the first read voltage V1 is set to a voltage lower than the write voltage. For example, the write voltage is about 3V, and the first read voltage V1 is about 1V. By applying the first read voltage V <b> 1, currents icell and iref flow through the sense amplifier 65 in the resistance change element 10 and the reference resistance element 30 according to the respective resistances. The sense amplifier 65 compares both currents. As shown in FIG. 4, since icell> iref at the first read voltage V1, the SOUT signal becomes “High”.

  Next, at time T2, the register 66 latches the SOUT signal by the rising edge of the SE signal, and the DOUT signal corresponding to the latched SOUT signal is output. At this time, since the latched SOUT signal is “High”, the DOUT signal is “High”.

  Next, when a voltage with an amplitude VR2 is input as the RD signal to the sense amplifier 65 at time T3, the second read voltage V2 is applied to the selected resistance change element 10 and the reference resistance element 30. Here, the second read voltage V2 lower than the amplitude VR2 is applied to the resistance change element 10 and the reference resistance element 30 due to the voltage drop, as in the case where the voltage of the amplitude VR1 is input. Here, the second read voltage V2 is set lower than the write voltage, and the first read voltage is set lower than V1. For example, the write voltage is about 3V, the read voltage V1 is about 1V, and the second read voltage V2 is about 0.5V. By applying the second read voltage V <b> 2, currents icell and iref flow through the sense amplifier 65 in accordance with the respective resistances in the resistance change element 10 and the reference resistance element 30. The sense amplifier 65 compares both currents. As shown in FIG. 4, since icell <iref at the second read voltage V2, the SOUT signal becomes “Low”. At this time, the DOUT signal remains “High”.

  Finally, when the DOUT signal (“High”) and the SOUT signal (“Low”) are input to the logic circuit 67, the ROUT signal becomes “Low” by AND logic.

  When the ROUT signal is “Low”, as shown in FIG. 8, the current-voltage characteristics of the resistance change element 10 are nonlinear (see FIGS. 8C and 8D), or the resistance change element 10 This is a case where the current-voltage characteristics are linear, and the resistance of the variable resistance element 10 is larger than the resistance of the reference resistance element 30 (see FIG. 8B). In these cases of FIGS. 8B, 8C, and 8D, since the retention time is short, writing is performed again until the current-voltage characteristics become as shown in FIG. In the case of FIG. 8A, as indicated by the broken lines in the waveforms of the SOUT signal and the ROUT signal in FIG. 7, when the DOUT signal is “High” and a voltage of amplitude VR2 is applied, icell> iref. The SOUT signal becomes “High”, and as a result of the AND logic, the ROUT signal becomes “High”.

  Next, the operation of the nonvolatile memory device according to Embodiment 1 will be described with reference to the drawings. FIG. 8 is a graph showing variations in current-voltage characteristics when the variable resistance element in the nonvolatile memory device according to Embodiment 1 is in the ON state. FIG. 9 is a flowchart schematically showing the operation of the nonvolatile memory device according to the first embodiment. Refer to FIGS. 5 and 6 for the constituent parts of the nonvolatile memory device 100.

  First, after a write voltage is applied to the selected resistance change element 10, the control circuit 80 is connected to the resistance change element 10 to which the write voltage is applied via the row decoder 51, the column decoder 52, and the access transistors 20 and 40. The same resistance change element 10 and the reference resistance element 30 in the same row as the resistance change element 10 are selected, and the selected resistance change element 10 and the reference resistance element 30 are connected to the selected resistance change element 10 and the reference resistance element 30 via the sense amplifier 65 of the readout circuit 60. A first read voltage V1 lower than the write voltage is applied (step A1).

  Next, the sense amplifier 65 of the read circuit 60 determines whether or not the current icell flowing through the resistance change element 10 is higher than the current iref flowing through the reference resistance element 30 when the first read voltage V1 is applied (first (Step A2).

  Next, the control circuit 80 holds the result of the first determination in the register 66 of the reading circuit 60 (step A3).

  Next, the control circuit 80 supplies the selected resistance change element 10 and the reference resistance element 30 to the selected resistance change element 10 and the reference resistance element 30 via the sense amplifier 65 of the read circuit 60 and is different from the first read voltage V1. 2 Read voltage V2 is applied (step A4).

  Next, the sense amplifier 65 of the read circuit 60 determines whether or not the current icell flowing through the resistance change element 10 is higher than the current iref flowing through the reference resistance element 30 when the second read voltage V2 is applied (second read). (Step A5).

  Next, the logic circuit 67 of the read circuit 60 determines whether or not the results of the first determination and the second determination are icell> iref (whether or not writing is normally performed by the resistance change element 10) ( (Third determination) (step A6).

  When it is determined in the third determination that icell> iref is satisfied (YES in step A6), the logic circuit 67 of the read circuit 60 determines that the writing is normally performed in the resistance change element 10 (step A7). The ROUT signal of “High” is output to the logic circuit 80, and then the process ends.

  When it is determined that icell> iref is not satisfied in the third determination (NO in Step A6), the logic circuit 67 of the read circuit 60 determines that the writing is not normally performed in the resistance change element 10 (Step A8). The ROUT signal of “Low” is output to the control circuit 80.

  Next, when the control circuit 80 receives the “Low” ROUT signal, the resistance change determined to have not been normally written in the third determination via the row decoder 51, the column decoder 52, and the access transistor 20. The same variable resistance element 10 as the element 10 is selected, a write voltage is applied to the selected variable resistance element 10 via the sense amplifier 65 of the read circuit 60 (step A9), and then the process returns to step A1.

  According to the first embodiment, by applying two read voltages V1 and V2 lower than the write voltage to the variable resistance element 10, it is determined whether or not the variable resistance element 10 has normally written, and the normal write is performed. If not performed, a normal writing state can be achieved. This eliminates the need for a large write current to flow through the resistance change element 10, and can suppress variations in the holding time of the resistance change element 10 without increasing the size of the device (particularly, the resistance change that shortens the holding time). The element can be eliminated) and the reliability is improved.

[Embodiment 2]
A non-volatile memory device according to Embodiment 2 will be described with reference to the drawings. FIG. 10 is a circuit diagram illustrating a partial configuration of the nonvolatile memory device according to the second embodiment.

  The non-volatile memory device 100 is a memory device having the variable resistance element 10 as a non-volatile memory. The nonvolatile memory device 100 includes a resistance change element 10, a reference resistance element 30, and a control unit 90.

  In the resistance change element 10, the resistance change layer 12 is disposed between the first electrode 11 and the second electrode 13, and a write voltage is applied between the first electrode 11 and the second electrode 13, whereby the first electrode 11 and an element in which the resistance between the second electrode 13 reversibly changes.

  The reference resistance element 30 is an element set to a predetermined resistance value for reference.

  The control unit 90 can apply a voltage to the resistance change element 10 and the reference resistance element 30 and can compare the current flowing through the resistance change element 10 with the current flowing through the reference resistance element 30. Part. The control unit 90 performs the following process after applying the write voltage to the variable resistance element 10.

  Whether the current flowing through the resistance change element 10 is higher than the current flowing through the reference resistance element 30 when the controller 90 applies a first read voltage lower than the write voltage to the resistance change element 10 and the reference resistance element 30. A first determination process is performed to determine whether or not. Further, the control unit 90 applies a current that flows through the resistance change element 10 when a second read voltage lower than the write voltage and different from the first read voltage is applied to the resistance change element 10 and the reference resistance element 30. A second determination process is performed to determine whether or not the current flowing through the reference resistance element 30 is higher. Furthermore, the control unit 90 performs a third determination process for determining whether or not writing is normally performed in the resistance change element 10 based on the results of the first determination process and the second determination process.

  Next, the operation of the nonvolatile memory device according to Embodiment 2 will be described with reference to the drawings. FIG. 11 is a flowchart schematically showing the operation of the nonvolatile memory device according to the second embodiment. Refer to FIG. 10 for components in the nonvolatile memory device 100.

  First, the control unit 90 applies the write voltage to the resistance change element 10, and then applies the first read voltage lower than the write voltage to the resistance change element 10 and the reference resistance element 30. It is determined (first determination) whether or not the flowing current is higher than the current flowing through the reference resistance element 30 (step B1).

  Next, the control unit 90 flows through the resistance change element 10 when a second read voltage lower than the write voltage and different from the first read voltage is applied to the resistance change element 10 and the reference resistance element 30. It is determined (second determination) whether or not the current is higher than the current flowing through the reference resistance element 30 (step B2).

  Finally, the control unit 90 determines (third determination) whether or not writing is normally performed in the anti-change element 10 based on the results of the first determination and the second determination (step B3). In the third determination, when it is determined that the current flowing through the resistance change element 10 is higher than the current flowing through the reference resistance element 30 in each of the first determination and the second determination, the resistance change element 10 writes normally. Judge that it was broken. Further, in the third determination, when it is determined in one or both of the first determination and the second determination that the current flowing through the resistance change element 10 is not higher than the current flowing through the reference resistance element 30, the resistance change element 10 It is determined that writing has not been performed normally.

  According to the second embodiment, after writing into the resistance change element 10, each current flowing through the resistance change element 10 and the reference resistance element 30 is compared to determine whether or not writing has been performed normally by the resistance change element 10. Therefore, it is not necessary to flow a large write current through the resistance change element 10, and variations in the holding time of the resistance change element can be suppressed without increasing the cell size.

(Appendix)
In the present invention, the nonvolatile memory device according to the first aspect is possible.

  In the nonvolatile memory device according to the first aspect, the second read voltage is lower than the first read voltage.

  In the nonvolatile memory device according to the first aspect, in the third determination process, the current flowing through the resistance change element in each of the first determination process and the second determination process is greater than the current flowing through the reference resistance element. Is determined to be high, it is determined that writing has been normally performed by the variable resistance element.

  In the nonvolatile memory device according to the first aspect, in the third determination process, a current flowing through the resistance change element flows through the reference resistance element in one or both of the first determination process and the second determination process. When it is determined that the current is not higher than the current, it is determined that the variable resistance element has not been normally written.

  In the nonvolatile memory device according to the first aspect, when the control unit determines in the third determination process that writing has not been normally performed by the resistance change element, the control unit applies the resistance change element to the corresponding resistance change element. The process of applying the write voltage is performed again.

  In the nonvolatile memory device according to the first aspect, a resistance change memory cell array in which memory cells in which the resistance change element and a first access transistor are connected in series are two-dimensionally arranged, and the reference resistance element; A reference resistance cell array in which reference resistance cells connected in series with a second access transistor are arranged in a one-dimensional manner, and the resistance change memory cell array by controlling the first access transistor and the second access transistor, A cell selection circuit that selects one resistance change element and one reference resistance element from the reference resistance cell array, and the control unit includes the cell selection circuit, the first access transistor, and the second access transistor. And selecting the resistance change element and the reference resistance element to which a voltage is applied. .

  In the nonvolatile memory device according to the first aspect, a plurality of word lines electrically connected to each of the gate electrodes of the first access transistor and the second access transistor in the same row, and the column in the same column A plurality of first bit lines electrically connected to the variable resistance element; and a second bit line electrically connected to each reference resistance element, wherein the cell selection circuit includes a plurality of word lines. A row decoder capable of selecting one word line from the column, and a column capable of selecting one bit line from the plurality of first bit lines and selecting the second bit line A decoder, and the control unit applies a voltage via the row decoder, the column decoder, the first access transistor, and the second access transistor. Selecting anti-change element and said reference resistance element.

  In the nonvolatile memory device according to the first aspect, the control unit is capable of applying a voltage to the selected resistance change element and the reference resistance element, and a current flowing through the resistance change element. A readout circuit capable of comparing a current flowing through the reference resistance element; and a control circuit for controlling the readout circuit and the cell selection circuit, wherein the control circuit includes the cell selection circuit, the first selection circuit, and the first selection circuit. The resistance change element and the reference resistance element to which a voltage is applied are selected via the access transistor and the second access transistor, and the selected resistance change element and the reference are selected via the read circuit. A voltage is applied to the resistance element, and the readout circuit is configured to perform a previous operation based on a current flowing through the resistance change element and a current flowing through the reference resistance element. First determination process, the second determination process, and performs the third determination process.

  In the nonvolatile memory device according to the first aspect, the read circuit is capable of applying a voltage to the selected resistance change element and the reference resistance element, and a current flowing through the resistance change element. A sense amplifier capable of performing the first determination process and the second determination process based on the current flowing through the reference resistance element, and temporarily holding a result of the first determination process in the sense amplifier And a logic circuit that outputs the result of the third determination process based on the result of the first determination process held in the register and the result of the second determination process in the sense amplifier And the control circuit applies a voltage to the selected resistance change element and the reference resistance element via the sense amplifier, and the register uses the first resistor. Controlling a timing for holding the result of the determination process.

  In the nonvolatile memory device according to the first aspect, the register is a D-type flip-flop.

  In the nonvolatile memory device according to the first aspect, the logic circuit is an AND circuit.

  In the nonvolatile memory device according to the first aspect, the read circuit further includes a clamp transistor in each wiring between the column decoder and the sense amplifier, and the control circuit controls the clamp transistor.

  In the nonvolatile memory device according to the first aspect, the control unit further includes a write circuit capable of applying the write voltage to the selected resistance change element, and the control circuit includes the write circuit. Then, the write voltage is applied to the selected variable resistance element.

  In the present invention, the nonvolatile memory device inspection method according to the second aspect is possible.

  It should be noted that the disclosures of the above-mentioned patent documents and non-patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims and drawings) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) within the framework of the entire disclosure of the present invention (necessary) Can be selected). That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea. Further, regarding numerical values and numerical ranges described in the present application, it is considered that any intermediate value, lower numerical value, and small range are described even if not specified.

DESCRIPTION OF SYMBOLS 1 Resistance change memory cell 2 Reference resistance cell 3 Resistance change memory cell array 4 Reference resistance cell array 10 Resistance change element 11 1st electrode 12 Resistance change layer 13 2nd electrode 14 High density metal bridge | crosslinking part 15 Low density metal bridge | crosslinking part 20 Access transistor ( First access transistor)
30 Reference resistance element 40 Access transistor (second access transistor)
51 Row Decoder 52 Column Decoder 52a, 52b Column Transistor 60 Read Circuit 61 Clamp Switch 61a, 61b Clamp Transistor 65 Sense Amplifier 66 Register 67 Logic Circuit 70 Write Circuit 80 Control Circuit 90 Control Unit 100 Nonvolatile Memory Device

Claims (10)

A resistance change layer is disposed between the first electrode and the second electrode, and a write voltage is applied between the first electrode and the second electrode, thereby providing a gap between the first electrode and the second electrode. A variable resistance element that reversibly changes its resistance;
A reference resistance element set to a predetermined resistance value for reference; and
A control unit capable of applying a voltage to the resistance change element and the reference resistance element, and capable of comparing a current flowing through the resistance change element and a current flowing through the reference resistance element;
With
The controller is
After applying a write voltage to the variable resistance element,
It is determined whether a current flowing through the resistance change element is higher than a current flowing through the reference resistance element when a first read voltage lower than the write voltage is applied to the resistance change element and the reference resistance element A first determination process to
When a second read voltage lower than the write voltage and different from the first read voltage is applied to the variable resistance element and the reference resistance element, a current flowing through the variable resistance element causes the reference resistance element to A second determination process for determining whether the current is higher than the flowing current;
A third determination process for determining whether or not writing is normally performed in the variable resistance element based on the results of the first determination process and the second determination process;
I do,
Non-volatile storage device. In the third determination process, when it is determined in each of the first determination process and the second determination process that the current flowing through the resistance change element is higher than the current flowing through the reference resistance element, the resistance change element It is determined that the writing was performed normally with
The nonvolatile memory device according to claim 1. In the third determination process, when it is determined in one or both of the first determination process and the second determination process that the current flowing through the resistance change element is not higher than the current flowing through the reference resistance element, It is determined that writing has not been performed normally with the resistance change element.
The nonvolatile memory device according to claim 1. A resistance change memory cell array in which memory cells in which the resistance change element and the first access transistor are connected in series are two-dimensionally arranged;
A reference resistor cell array in which reference resistor cells in which the reference resistor element and the second access transistor are connected in series are arranged one-dimensionally;
A cell selection circuit for selecting one resistance change element and one reference resistance element from each of the resistance change memory cell array and the reference resistance cell array by controlling the first access transistor and the second access transistor;
With
The control unit selects the variable resistance element and the reference resistance element to which a voltage is applied via the cell selection circuit, the first access transistor, and the second access transistor.
The non-volatile storage device according to claim 1. A plurality of word lines electrically connected to each of the gate electrodes of the first access transistor and the second access transistor in the same row;
A plurality of first bit lines electrically connected to the variable resistance elements in the same column;
A second bit line electrically connected to each reference resistance element;
With
The cell selection circuit includes:
A row decoder capable of selecting one word line from the plurality of word lines;
A column decoder capable of selecting one bit line from the plurality of first bit lines and selecting the second bit line;
With
The control unit selects the variable resistance element and the reference resistance element to which a voltage is applied via the row decoder, the column decoder, the first access transistor, and the second access transistor.
The nonvolatile memory device according to claim 4. The controller is
A read circuit capable of applying a voltage to the selected resistance change element and the reference resistance element, and comparing a current flowing through the resistance change element with a current flowing through the reference resistance element; ,
A control circuit for controlling the readout circuit and the cell selection circuit;
With
The control circuit includes:
Selecting the resistance change element and the reference resistance element to which a voltage is applied via the cell selection circuit, the first access transistor, and the second access transistor; and
A voltage is applied to the selected resistance change element and the reference resistance element through the readout circuit,
The readout circuit performs the first determination process, the second determination process, and the third determination process based on a current flowing through the resistance change element and a current flowing through the reference resistance element.
The non-volatile memory device according to claim 4 or 5. The readout circuit is
It is possible to apply a voltage to the selected resistance change element and the reference resistance element, and based on the current flowing through the resistance change element and the current flowing through the reference resistance element, the first determination process and the A sense amplifier capable of performing the second determination process;
A register capable of temporarily holding a result of the first determination process in the sense amplifier;
A logic circuit that outputs a result of the third determination process based on a result of the first determination process held in the register and a result of the second determination process in the sense amplifier;
With
The control circuit includes:
A voltage is applied to the selected resistance change element and the reference resistance element via the sense amplifier; and
Controlling the timing of holding the result of the first determination process in the register;
The nonvolatile memory device according to claim 6. The register is a D-type flip-flop.
The nonvolatile memory device according to claim 7. The logic circuit is an AND circuit.
The nonvolatile memory device according to claim 7 or 8. A resistance change layer is disposed between the first electrode and the second electrode, and a write voltage is applied between the first electrode and the second electrode, thereby providing a gap between the first electrode and the second electrode. A method for inspecting a nonvolatile memory device including a resistance change element whose resistance changes reversibly,
The nonvolatile memory device includes a reference resistance element set to a predetermined resistance value for reference,
After applying a write voltage to the variable resistance element,
It is determined whether a current flowing through the resistance change element is higher than a current flowing through the reference resistance element when a first read voltage lower than the write voltage is applied to the resistance change element and the reference resistance element A first determination step,
When a second read voltage lower than the write voltage and different from the first read voltage is applied to the resistance change element and the reference resistance element, a current flowing through the resistance change element is the reference resistance element. A second determination step for determining whether the current is higher than the current flowing through
A third determination step for determining whether or not writing is normally performed in the variable resistance element based on the results of the first determination step and the second determination step;
Nonvolatile memory device inspection method including:

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