JP2018164113A - Capacitor using middle of line (mol) conductive layers - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in which, at 20 nm process technology and beyond, it will no longer be feasible to use Fmom capacitors to provide small value capacitance for IC devices.SOLUTION: A method for fabricating a metal-insulator-metal (MIM) capacitor includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor, and a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL conductive layer on the insulator layer as a second plate of the MIM capacitor.SELECTED DRAWING: Figure 3

Description

  The present disclosure relates generally to capacitors. More particularly, the present disclosure relates to metal-insulator-metal (MIM) capacitors and methods of manufacturing MIM capacitors using middle-of-line (MOL) conductive layers.

  Capacitors are widely used in integrated circuits. Finger metal oxide metal (Fmom) capacitors are used in current process technology (eg, 28 nanometers (nm)). However, as the technology scales down to 20 nm and beyond, the changes in the thinner and slimmer metal wires used to implement Fmom capacitors become increasingly severe and the changes in Fmom capacitance become severe.

  In current integrated circuit (IC) devices, a significant amount of small value (eg, 20-30 fF) capacitors are specified. This was not an issue with previous process technologies (because of smaller changes in metal wire width / thickness (ie smaller capacitance changes)) starting at 45 nm and 28 nm, while meeting the design corner It becomes quite difficult to produce a small value of capacitance. Thus, it is no longer possible to use Fmom capacitors to provide low value capacitance for IC devices with process technology of 20 nm and beyond.

  Metal insulator metal (MIM) capacitors in the back end of line (BEOL) layer have been proposed. However, this solution requires three additional masks as well as a high-K (HiK) oxide deposition process to achieve high capacitor density.

  According to one aspect of the present disclosure, a method for making a capacitor is described. The method includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first set of local interconnects to the first plate of the capacitor and the source and drain regions of the semiconductor device. The method also includes depositing an insulator layer as a capacitor dielectric layer on the first MOL conductive layer. The method further includes depositing a second MOL conductive layer on the insulator layer as a second plate of the capacitor.

  According to another aspect of the present disclosure, a metal insulator metal (MIM) capacitor device is described. The MIM capacitor device includes a semiconductor substrate. The MIM capacitor device may also include a first middle of line (MOL) conductive layer on the semiconductor substrate. The first MOL conductive layer provides a first set of local interconnects to the first plate of the MIM capacitor and the source and drain regions of the semiconductor device. The MIM capacitor device may also include an insulator layer on the first capacitor plate to provide a dielectric layer for the MIM capacitor. The MIM capacitor device may further include a second MOL conductive layer on the insulator layer. The second MOL conductive layer provides a second plate of the MIM capacitor. The MIM capacitor device may also include a first interconnect coupled to the first capacitor plate and a second interconnect coupled to the second capacitor plate.

  According to a further aspect of the present disclosure, a metal insulator metal (MIM) capacitor device is described. The MIM capacitor device includes a semiconductor substrate. The MIM capacitor device also includes a first middle of line (MOL) conductive layer having means for storing a first charge on the semiconductor substrate. The MIM capacitor device may also include an insulator layer on the first capacitor plate to provide a dielectric layer for the MIM capacitor. The device MIM capacitor may also include a second MOL conductive layer having means for storing a second charge of an insulator layer deposited on the first charge storage means.

  According to another aspect of the present disclosure, a method for making a capacitor is described. The method includes depositing a first middle-of-line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first set of local interconnects to the first plate of the capacitor and the source and drain regions of the semiconductor device. The method also includes depositing an insulator layer as a capacitor dielectric layer on the first MOL conductive layer. The method further includes depositing a second MOL conductive layer on the insulator layer as a second plate of the capacitor.

  The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the present disclosure are described below. Those skilled in the art should appreciate that the present disclosure can be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes as the present disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features believed to characterize the present disclosure will be better understood when considering the subsequent description in conjunction with the accompanying figures, as well as further objects and advantages, both for its composition and method of operation. Let's go. However, it should be expressly understood that each of the figures is provided for purposes of illustration and description only and is not intended to define limitations of the present disclosure.

  The features, nature, and advantages of the present disclosure will become more apparent when the detailed description set forth below is read in conjunction with the drawings.

1 is a cross-sectional view illustrating an integrated circuit (IC) device that includes a first capacitor plate in a middle-of-line interconnect layer according to one aspect of the present disclosure. FIG. 2 is a cross-sectional view of the IC device of FIG. 1 including a second capacitor plate over a middle-of-line interconnect layer in accordance with an aspect of the present disclosure. FIG. FIG. 2 is a cross-section illustrating the IC device of FIG. 2 including a middle-of-line interconnect layer and a second capacitor plate over the second dielectric layer deposited over the first dielectric layer, according to one aspect of the present disclosure. FIG. 4 is a cross-sectional view of the IC device of FIG. 3 including interconnections to first and second capacitor plates according to one aspect of the present disclosure. FIG. 5 illustrates a method for making a metal insulator metal (MIM) capacitor using a middle-of-line (MOL) interconnect layer according to one aspect of the present disclosure. 1 is a cross-sectional view illustrating an integrated circuit (IC) device that includes a first capacitor plate in a middle-of-line interconnect layer according to one aspect of the present disclosure. FIG. 7 is a cross-sectional view of the IC device of FIG. 6 including a high-K dielectric layer deposited on a first capacitor plate in a middle-of-line interconnect layer according to one aspect of the present disclosure. FIG. FIG. 8 is a cross-sectional view of the IC device of FIG. 7 including a second capacitor plate deposited on a high-K dielectric layer over the first capacitor plate according to one aspect of the present disclosure. FIG. 9 is a cross-sectional view of the IC device of FIG. 8 including a second dielectric layer deposited on the first dielectric layer according to one aspect of the present disclosure. FIG. 10 is a cross-sectional view of the IC device of FIG. 9 including interconnection of high density capacitors to first and second capacitor plates according to one aspect of the present disclosure. FIG. 6 illustrates a method for making a high density metal insulator metal (MIM) capacitor using a middle-of-line (MOL) interconnect layer according to one aspect of the present disclosure. FIG. 1 illustrates an example wireless communication system in which an aspect of the present disclosure can be advantageously utilized. FIG. 13 is a block diagram illustrating a design workstation used for circuit design, layout design, and logic design of semiconductor components according to one aspect of the present disclosure.

  The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is intended to represent the only configurations in which the concepts described herein can be practiced. Absent. The detailed description includes specific details for providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. In the description herein, the use of the term “and / or” is intended to mean “inclusive OR”, and the use of the term “or” means “exclusive OR”. Intended.

  One aspect of the present disclosure is formed using an existing middle-of-line interconnect layer as one electrode and a conductive resistive layer as another electrode to make a MIM (metal insulator metal) capacitor. An MIM capacitor is described. In one configuration, the first plate of the MIM capacitor is provided by a first middle-of-line (MOL) interconnect layer deposited over a shallow trench isolation (STI) region of the semiconductor substrate. In this configuration, the first MOL conductive layer is an active contact (eg, MD1) that provides a first set of local interconnects to the source and drain regions of the semiconductor device. The second plate of the capacitor is provided by a second MOL interconnect layer deposited on the insulator. An insulator is deposited on the first MOL interconnect layer.

  In one configuration, the second MOL interconnect layer is provided by deposition and patterning of a conductive layer to form a second plate of the capacitor. In this configuration, the second set of local interconnects (eg, stacked contacts (MD2)) are connected to the first and second capacitor plates and the first set of local interconnects (eg, active contacts MD1). Combined. Accordingly, one aspect of the present disclosure has been introduced in current process technology as an MOL interconnect layer (MD1) and an MOL conductive resistive layer (one as an electrode) to make a MIM capacitor without additional masks or layers. Use). In another aspect of the present disclosure, a high density MIM capacitor is provided by using an additional high-K deposition that includes one lithography (one mask) step and one additional etching step.

  FIG. 1 illustrates a cross-sectional view of an integrated circuit (IC) device 100 that includes a first capacitor plate within a middle-of-line (MOL) interconnect layer 110 according to one aspect of the present disclosure. The IC device 100 typically includes a semiconductor substrate (eg, a silicon wafer) 102 having a shallow trench isolation (STI) region 103. Above the STI region 103 and the semiconductor substrate 102 is an active region in which an active device having a source region 104, a drain region 106, and a gate region 108 is formed. In order to protect the active device, a silicon nitride layer 112 having a thickness of about 30 nm is deposited on the active region. A middle-of-line (MOL) interconnect layer 110 is also provided.

  In FIG. 1, the first MOL interconnect layer 110 is a set of active (oxidized diffusion (OD)) contacts (MD1) 120 (120-1) fabricated on a semiconductor substrate 102 using existing process technology. ~ 120-4). Active contact 120 is coupled to the drain and source regions 104 of the active device. In this aspect of the present disclosure, a first capacitor plate (electrode) 130 is defined in the MOL interconnect layer 110 on the STI region 103 of the semiconductor substrate 102. Once defined, a first MOL conductive layer is deposited to form the first capacitor electrode plate 130. The first MOL conductive layer also provides a first set of local interconnects (active contacts 120) to the source region 104 and drain region 106 of the active device. In this configuration, the first MOL conductive layer used to form the active contact 120 is also used to form the capacitor electrode as the first capacitor electrode plate 130. The first MOL conductive layer may be composed of tungsten or other similar conductive material.

  FIG. 2 illustrates a cross-sectional view of an integrated circuit (IC) device 200 that includes a second capacitor electrode plate 250 over the MOL interconnect layer 110 in accordance with an aspect of the present disclosure. Typically, a first dielectric layer (eg, oxide layer) 240 is deposited over the active contact 120 and the first capacitor electrode plate 230. The first dielectric layer 240 can have a thickness in the range of 10 to 15 nanometers.

  In this configuration, the second MOL conductive layer is deposited on the surface of the first dielectric layer 240. In order to form the second capacitor electrode plate 250 on the first capacitor electrode plate 230, the second MOL conductive layer is patterned and etched. In this configuration, the capacitance value of the capacitor formed from the first capacitor electrode plate 230 and the second capacitor electrode plate 250 is determined by the thickness of the first dielectric layer 240. A conductive resistor 242 is also formed on the first dielectric layer 240. In this aspect of the present disclosure, deposition and patterning of the MOL conductive resistive layer is also used to provide the second conductive electrode as the second capacitor electrode plate 250.

  FIG. 3 illustrates an IC including a second capacitor electrode plate 350 on top of a MOL interconnect layer 110 and a second dielectric layer 370 deposited on the first dielectric layer 340, according to one aspect of the present disclosure. A cross-sectional view showing the device 300 is shown. In this configuration, a second dielectric layer 370 having a thickness in the range of 35 nanometers is a first dielectric layer 340 on the first capacitor electrode plate 330, a resistor 342, and a second capacitor electrode plate. 350 is deposited.

  FIG. 4 illustrates a cross-sectional view of an IC device 400 that includes interconnects 490-1 and 490-2 to a first capacitor electrode plate 430 and a second capacitor electrode plate 450, according to one aspect of the present disclosure. In this configuration, the second dielectric layer 470 is patterned and etched to expose the first capacitor electrode plate 430 and the second capacitor electrode plate 450. This patterning and etching is performed to expose resistor 442 and active contact 120 as part of current process technology. Once exposed, a third MOL conductive layer is formed to form interconnects 490 (490-1 and 490-2) to first capacitor electrode plate 430 and second capacitor electrode plate 450, respectively. A second dielectric layer 470 is deposited.

  In this configuration, the third MOL conductive layer is connected to a second set of local interconnects (stacked contacts (MD2) 480 (480-1 to 480-480) to the active contacts 120 using existing process technology. 4)) is also provided. In this configuration, the third MOL conductive layer used to form the stacked contacts 480 and the interconnects 482 and 484 to the resistors is interconnected 490-1 to the first capacitor electrode plate 430. , And also to form an interconnect 490-2 to the second capacitor electrode plate 450.

  FIG. 5 illustrates a method 500 for making a metal insulator metal (MIM) capacitor using a middle-of-line (MOL) conductive layer according to one aspect of the present disclosure. At block 502, a first plate of a capacitor is defined in a middle of line (MOL) interconnect layer over a shallow trench isolation (STI) region of a semiconductor substrate. At block 504, a first MOL conductive layer is deposited to form a first plate of capacitors. For example, as shown in FIG. 1, a first capacitor plate (electrode) 130 is defined in the MOL interconnect layer 110 on the STI region 103 of the semiconductor substrate 102. Once defined, a first MOL conductive layer is deposited to form the first capacitor electrode plate 130.

  Referring again to FIG. 5, at block 506, a dielectric layer is deposited on the first MOL conductive layer. For example, as shown in FIG. 2, a first dielectric layer (eg, oxide layer) 240 is deposited over the active contacts 120 and the first capacitor electrode plate 230. At block 508, a second MOL conductive layer is deposited on the first dielectric layer. At block 510, the second MOL conductivity is patterned and etched to form a second plate of the capacitor. For example, as shown in FIG. 2, a second MOL conductive layer is deposited on the surface of the first dielectric layer 240. In order to form the second capacitor electrode plate 250 on the first capacitor electrode plate 230, the second MOL conductive layer is patterned and etched.

  At block 512, a second dielectric layer is deposited on the second MOL conductive layer. At block 514, the second dielectric layer is patterned and etched to expose the first and second capacitor plates. At block 516, a third MOL conductive layer is deposited on the second dielectric layer to form an interconnect to the first and second capacitor plates. A third MOL conductive layer is patterned to form interconnections to the first and second capacitor electrode plates. For example, as shown in FIG. 4, the second dielectric layer 470 is patterned and etched to expose the first capacitor electrode plate 430 and the second capacitor electrode plate 450. This patterning and etching is performed to expose resistor 442 and active contact 120 as part of current process technology. Once exposed, a third MOL conductive layer is formed to form interconnects 490 (490-1 and 490-2) to first capacitor electrode plate 430 and second capacitor electrode plate 450, respectively. A second dielectric layer 470 is deposited.

  As described in FIGS. 1-5, a metal-insulator metal (MIM) capacitor provides a mask and process currently used to create MOL layers that are available in current process technology at no additional cost. Can be implemented using. The capacitance value of the MIM capacitor is determined by the thickness of the first dielectric layer. The thickness of the first dielectric layer can be determined by the foundry. In another aspect of the present disclosure, a high-density MIM capacitor can be implemented using existing process technology and one extra mask to provide a high-K dielectric layer, for example, as described in FIGS. Formed using.

  FIG. 6 illustrates a cross-sectional view of an integrated circuit (IC) device 600 that includes a first capacitor electrode plate 630 in the MOL interconnect layer 110 in accordance with an aspect of the present disclosure. This configuration of the IC device may be similar to the configuration of the IC device 100 shown in FIG. However, in this configuration, the first capacitor electrode plate 630 provides the first electrode of the high density capacitor.

  FIG. 7 illustrates a cross-sectional view of the IC device 700 of FIG. 6 including a high-K dielectric layer 760 deposited on the first capacitor electrode plate 730 in the MOL interconnect layer 110 according to one aspect of the present disclosure. Show. In this configuration, a first dielectric layer (eg, oxide layer) 740 is deposited over the active contact 120 and the first capacitor electrode plate 730. The first dielectric layer 740 can have a thickness in the range of 10 to 15 nanometers. The deposition of the first dielectric layer 740 may be similar to the first dielectric layer deposition shown in FIG. However, in this configuration, the first dielectric layer 740 is masked and etched to expose the first capacitor electrode plate 730. In this aspect of the present disclosure, when the first capacitor electrode plate 730 is exposed, a high-K dielectric layer 760 is deposited on the exposed surfaces of the first dielectric layer 740 and the first capacitor electrode plate 730. Is done. The thickness of the high-K dielectric layer 760 is in the range of 2 to 5 nanometers.

  FIG. 8 illustrates a second capacitor electrode plate 850 and a conductive resistor deposited on a high-K dielectric layer 860 (860-1, 860-2) on the MOL interconnect layer 110, according to one aspect of the present disclosure. FIG. 8 shows a cross-sectional view of the IC device 800 of FIG. In this configuration, the second MOL conductive layer is deposited on the surface of the high-K dielectric layer 860. A second MOL conductive layer is patterned and etched to form a second capacitor electrode plate 850 over the first capacitor electrode plate 830 and expose the first dielectric layer 840. In this configuration, a high-K dielectric layer 860-2 thickness between the first capacitor electrode plate 830 and the second capacitor electrode plate 850 is reduced (eg, 2 to 5 nanometers) due to the high The density capacitor is formed of a first capacitor electrode plate 830 and a second capacitor electrode plate 850. A conductive resistor 842 is also formed on the high-K dielectric layer 860-1 over the first dielectric layer 840. In this aspect of the present disclosure, the deposition and patterning of the MOL conductive resistive layer provides the second conductive electrode as the second capacitor electrode plate 850.

  FIG. 9 illustrates the IC device of FIG. 8 including a first dielectric layer 940, a resistor 942, and a second dielectric layer 970 deposited on the second capacitor electrode plate 950, in accordance with an aspect of the present disclosure. FIG. In this configuration, a second dielectric layer 970 having a thickness in the range of 35 nanometers comprises a first dielectric layer 940, a resistor 942, a second capacitor electrode plate 950, and a high-K dielectric layer. Deposited on the sidewalls of 960-1 and 960-2.

  FIG. 10 illustrates a cross-sectional view of an IC device 1000 that includes interconnects 1090-1 and 1090-2 to a first capacitor electrode plate 1030 and a second capacitor electrode plate 1050, according to one aspect of the present disclosure. In this configuration, the second dielectric layer 1070 is patterned and etched to expose the first capacitor electrode plate 1030 and the second capacitor electrode plate 1050. This patterning and etching is also performed to expose the resistor 1042 and the active contact 120 under the first dielectric layer 1040 as part of current process technology. Once exposed, the third MOL conductive layer is second to form an interconnect 1090-1 to the first capacitor electrode plate 1030 and an interconnect 1090-2 to the second capacitor electrode plate 1050. A dielectric layer 1070 is deposited.

  In this configuration, the third MOL conductive layer is connected to a second set of local interconnects (stacked contacts (MD2) 1080 (1080-1 to 1080-) to the active contacts 120 using existing process technology. 4)) is also provided. In this configuration, the third MOL conductive layer used to form the stacked contacts 1080 and the interconnects 1082 and 1084 to the resistor 1042 are interconnected to the first capacitor electrode plate 1030- Also used to form an interconnect 1090-2 to the first and second capacitor electrode plates 1050. Resistor 1042 is deposited on high-K dielectric layer 1060-1, and second capacitor electrode plate 1050 is deposited on high-K dielectric layer 1060-2.

  FIG. 11 illustrates a method 1100 for making a metal insulator metal (MIM) high density capacitor using a middle-of-line (MOL) interconnect layer according to one aspect of the present disclosure. At block 1102, a first plate of capacitors is defined in a middle-of-line (MOL) interconnect layer over a shallow trench isolation (STI) region of a semiconductor substrate. At block 1104, a first MOL conductive layer is deposited to form a first plate of capacitors. For example, as shown in FIG. 6, a first capacitor plate (electrode) 630 is defined in the MOL interconnect layer 110 on the STI region 103 of the semiconductor substrate 102. Once defined, a first MOL conductive layer is deposited to form a first capacitor electrode plate 630.

  Referring again to FIG. 11, at block 1106, a first dielectric layer is deposited on the first MOL conductive layer. For example, as shown in FIG. 7, a first dielectric layer (eg, oxide layer) 740 is deposited over active contact 120 and first capacitor electrode plate 730. At block 1108, the dielectric layer is masked and etched to expose the first capacitor plate. When the first capacitor plate is exposed, a high-K dielectric layer is deposited on the exposed surfaces of the first dielectric layer 740 and the first capacitor electrode plate 730, as shown in block 1110 and FIG. The

  At block 1112, a second MOL conductive layer is deposited on the high-K dielectric layer. At block 1114, the second MOL conductive layer is patterned and etched to form a second plate of the capacitor. For example, as shown in FIG. 8, a second MOL conductive layer is deposited on the surface of the high-K dielectric layer 860. A second MOL conductive layer is patterned and etched to form a second capacitor electrode plate 850 over the first capacitor electrode plate 830 and expose the first dielectric layer 840.

  At block 1116, a second dielectric layer is deposited on the second MOL conductive layer. At block 1118, the second dielectric layer is patterned and etched to expose the first and second capacitor plates. At block 1120, a third MOL conductive layer is deposited on the second dielectric layer to form an interconnect to the first and second capacitor plates. For example, as shown in FIG. 10, the second dielectric layer 1070 is patterned and etched to expose the first capacitor electrode plate 1030 and the second capacitor electrode plate 1050. This patterning and etching is performed to expose resistor 1042 and active contact 120 as part of current process technology. Once exposed, a third MOL conductive layer is formed on the second dielectric layer 1070 to form an interconnect 1090-1 to the first capacitor electrode plate 1030 and a second capacitor electrode plate 1050. Is deposited.

  In one configuration, a metal insulator metal (MIM) capacitor device includes a first middle-of-line (MOL) conductive layer having means for storing a first charge on a semiconductor substrate. In one aspect of the present disclosure, the first charge storage means may be a first capacitor plate 430/1030 configured to perform the function provided by the first charge storage means. The device may also include a second MOL conductive layer having means for storing a second charge on an insulator layer deposited on the first charge storage means. In one aspect of the present disclosure, the second charge storage means may be a second capacitor plate 450/1050 configured to perform the function provided by the second charge storage means. In another aspect, the means described above may be any device configured to perform the function provided by the means described above.

  FIG. 12 illustrates an example wireless communication system 1200 in which an aspect of the present disclosure can be advantageously utilized. For illustration purposes, FIG. 12 shows three remote units 1220, 1230, 1250 and two base stations 1240. It will be appreciated that a wireless communication system may have more remote units and base stations. Remote units 1220, 1230, and 1250 include MIM capacitors 1225A, 1225B, 1225C. FIG. 12 shows forward link signal 1280 from base station 1240 to remote units 1220, 1230, and 1250, and reverse link signal 1290 from remote units 1220, 1230, and 1250 to base station 1240.

  In FIG. 12, remote unit 1220 is shown as a mobile phone, remote unit 1230 is shown as a portable computer, and remote unit 1250 is shown as a fixed location remote unit in a wireless local loop system. For example, the remote unit can be a fixed location such as a cell phone, handheld personal communication system (PCS) unit, set top box, music player, video player, entertainment unit, portable data unit such as a navigation device, personal digital assistant, or meter reader It can be a data unit. Although FIG. 12 illustrates remote units that may utilize MIM capacitors 1225A, 1225B, 1225C in accordance with the teachings of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. For example, an MIM capacitor according to aspects of the present disclosure can be optimally used in any device.

  FIG. 13 is a block diagram illustrating a design workstation used for circuit design, layout design, and logic design of semiconductor components, such as the MIM capacitor device disclosed above. The design workstation 1300 includes a hard disk 1301 that includes operating system software, support files, and design software such as Cadence or OrCAD. The design workstation 1300 also includes a display 1302 to facilitate the design of the circuit 1310 or the semiconductor component 1312 such as MRAM. Storage medium 1304 is provided for tangibly storing circuit design 1310 or semiconductor component 1312. The circuit design 1310 or the semiconductor component 1312 may be stored in the storage medium 1304 in a file format such as GDSII or GERBER. Storage medium 1304 may be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. In addition, the design workstation 1300 includes a drive 1303 for accepting input from the storage medium 1304 or writing output to the storage medium 1304.

  Data recorded on storage medium 1304 may specify logic circuitry, pattern data for photolithography masks, or mask pattern data for continuous writing tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with the logic simulation. Providing data on storage medium 1304 facilitates the design of circuit design 1310 or semiconductor component 1312 by reducing the number of processes for designing a semiconductor wafer.

  Although specific circuits have been described, those skilled in the art will appreciate that not all of the disclosed circuits are required to practice the disclosed embodiments. In addition, in order to maintain attention to the present disclosure, some well-known circuits have not been described.

  The methodology described herein may be implemented by various means depending on the application. For example, these methodologies may be implemented in hardware, firmware, software, or any combination thereof. For a hardware implementation, each processing unit is one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), designed to perform the functions described herein, Implemented in a digital signal processing device (DSPD), programmable logic device (PLD), field programmable gate array (FPGA), processor, controller, microcontroller, microprocessor, electronic device, other electronic unit, or combinations thereof Also good.

  For firmware and / or software implementations, these methodologies may be implemented in modules (eg, procedures, functions, etc.) that perform the functions described herein. Any machine-readable or computer-readable medium that tangibly embodies the instructions may be used in implementing the methods described herein. For example, software code may be stored in memory and executed by a processor. The executing software code, when executed by a processor, provides an operating environment that implements various methods and functions in the teachings of the different aspects presented herein. The memory may be implemented within the processor or external to the processor. As used herein, the term “memory” refers to any type of long-term memory, short-term memory, volatile memory, non-volatile memory, or other memory, and any particular type or memory of memory Or the type of medium on which the memory is stored.

  Machine-readable or computer-readable media that store software code defining methods and functions described herein include physical computer storage media. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer readable media may be RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage device or other magnetic storage device, or any desired form in the form of instructions or data structures. Any other medium that can be used to store program code and accessed by a computer can be included. As used herein, a disc and / or disc is a compact disc (CD), a laser disc (registered trademark), an optical disc, a digital versatile disc (DVD), a floppy disc (registered trademark). , And Blu-ray discs, of which discs typically reproduce data magnetically, while discs optically reproduce data using a laser. Combinations of the above should also be included within the scope of computer-readable media.

  In addition to storage on computer-readable media, instructions and / or data may be provided as signals on transmission media included in the communication devices. For example, the communication device can include a transceiver having signals indicative of instructions and data. These instructions and data are configured to cause one or more processors to perform the functions outlined in the claims.

  Although the present teachings and their advantages have been described in detail, various modifications, substitutions, and alterations can be made herein without departing from the techniques of the present teachings as defined by the appended claims. I want you to understand. Furthermore, the scope of the present application is not intended to be limited to the specific aspects of the processes, machines, manufacture, material compositions, means, methods, and steps described herein. As those of ordinary skill in the art will readily appreciate from this disclosure, present or later developed that perform substantially the same function or achieve substantially the same results as the corresponding aspects described herein. Any process, machine, article of manufacture, composition, means, method, or step that may be utilized may be utilized in accordance with the present teachings. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

DESCRIPTION OF SYMBOLS 100 Integrated circuit (IC) device 102 Semiconductor substrate 103 Shallow trench isolation (STI) region 104 Source region 106 Drain region 108 Gate region 110 Middle of line (MOL) interconnection layer 112 Silicon nitride layer 120 Active contact 130 1st contact Capacitor electrode plate 200 integrated circuit (IC) device 230 first capacitor electrode plate 240 first dielectric layer 242 conductive resistor 250 second capacitor electrode plate 300 IC device 330 first capacitor electrode plate 340 first Dielectric layer 342 Resistor 350 Second capacitor electrode plate 370 Second dielectric layer 400 IC device 430 First capacitor electrode plate 442 Resistor 450 Second capacitor electrode Pole plate 470 Second dielectric layer 480 Stacked contacts 482 Interconnect 484 Interconnect 490-1 Interconnect 490-2 Interconnect 600 Integrated circuit (IC) device 630 First capacitor electrode plate 700 IC device 730 First Capacitor electrode plate 740 first dielectric layer 760 high-K dielectric layer 800 IC device 830 first capacitor electrode plate 840 first dielectric layer 842 conductive resistor 850 second capacitor electrode plate 860 high- K dielectric layer 900 IC device 940 First dielectric layer 942 Resistor 950 Second capacitor electrode plate 960-1 high-K dielectric layer 960-2 high-K dielectric layer 970 Second dielectric layer 1000 IC device 103 First capacitor electrode plate 1040 First dielectric layer 1042 Resistor 1050 Second capacitor electrode plate 1060-1 high-K dielectric layer 1060-2 high-K dielectric layer 1070 Second dielectric layer 1080 Stacked Contacts 1082 Interconnect 1084 Interconnect 1090-1 Interconnect 1090-2 Interconnect 1200 Wireless communication system 1220 Remote unit 1225A MIM capacitor 1225B MIM capacitor 1225C MIM capacitor 1230 Remote unit 1240 Base station 1250 Remote unit 1280 Forward link signal 1290 Reverse direction Link signal 1300 Design workstation 1302 Display 1303 Drive unit 1304 Storage medium 1310 Circuit 1312 Semiconductor Component

Claims (20)

A method for producing a capacitor, comprising:
As a first plate of the capacitor and as a first set of local interconnections to the source and drain regions of the semiconductor device, a first middle of line (STI) region above the shallow trench isolation (STI) region of the semiconductor substrate. MOL) depositing a conductive layer;
Depositing an insulator layer on the first MOL conductive layer;
Depositing a second MOL conductive layer on the insulator layer as a second plate of the capacitor. Masking the first plate before depositing the insulator layer;
Depositing and patterning a high-K insulator layer on the first plate instead of the insulator layer, wherein the second MOL conductive layer is replaced with the high- The method of claim 1, further comprising depositing on the K insulator layer.   The method of claim 1, further comprising patterning the second MOL conductive layer as a resistor.   The method of claim 1, further comprising patterning a second set of local interconnects that couple to the first plate, the second plate, and the first set of local interconnects.   The method of claim 4, wherein the first set of local interconnects comprises active contacts and the second set of local interconnects comprises stacked contacts.   Further comprising incorporating the capacitor in a cell phone, handheld personal communication system (PCS) unit, set top box, music player, video player, entertainment unit, navigation device, portable data unit, and / or fixed position data unit. The method according to 1. A semiconductor substrate;
A first middle-of-line (MOL) conductive layer comprising a first capacitor plate on the semiconductor substrate;
An insulator layer on the first capacitor plate;
A second MOL conductive layer comprising a second capacitor plate on the insulator layer;
A first interconnect coupled to the first capacitor plate;
And a second interconnect coupled to the second capacitor plate.   The device of claim 7, wherein the first conductive MOL layer comprises an active contact layer on the semiconductor substrate.   The device of claim 7, wherein the second conductive MOL layer comprises a stacked contact layer on the semiconductor substrate.   8. The device of claim 7, incorporated into a cell phone, handheld personal communication system (PCS) unit, set top box, music player, video player, entertainment unit, navigation device, portable data unit, and / or fixed position data unit. A semiconductor substrate;
A first middle-of-line (MOL) conductive layer comprising means for storing a first charge on the semiconductor substrate;
An insulator layer on the first charge storage means;
A second MOL conductive layer comprising means for storing a second charge on the insulator layer;
A first interconnect coupled to the first charge storage means;
And a second interconnect coupled to the second charge storage means.   The device of claim 11, wherein the first MOL conductive layer comprises an active contact layer on the semiconductor substrate.   The device of claim 11, wherein the second MOL conductive layer comprises a stacked contact layer on the semiconductor substrate.   12. A device according to claim 11, incorporated in a cell phone, handheld personal communication system (PCS) unit, set top box, music player, video player, entertainment unit, navigation device, portable data unit, and / or fixed position data unit. A method for producing a capacitor, comprising:
As a first plate of the capacitor and as a first set of local interconnections to the source and drain regions of the semiconductor device, a first middle of line (STI) region above the shallow trench isolation (STI) region of the semiconductor substrate. MOL) depositing a conductive layer;
Depositing an insulator layer on the first MOL conductive layer;
Depositing a second MOL conductive layer on the insulator layer as a second plate of the capacitor. Masking the first plate before depositing the insulator layer;
Depositing and patterning a high-K insulator layer on the first plate instead of the insulator layer, wherein the second MOL conductive layer is replaced with the high- The method of claim 15, further comprising: depositing on the K insulator layer.   The method of claim 15, further comprising patterning the second MOL conductive layer as a resistor.   16. The method of claim 15, further comprising patterning a second set of local interconnects that couple to the first plate, the second plate, and the first set of local interconnects.   The method of claim 18, wherein the first set of local interconnects comprises active contacts and the second set of local interconnects comprises stacked contacts.   Further comprising incorporating the capacitor in a cell phone, handheld personal communication system (PCS) unit, set top box, music player, video player, entertainment unit, navigation device, portable data unit, and / or fixed position data unit. 15. The method according to 15.