JP2018161751A - Liquid discharge device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a driving signal generation circuit for generating a driving signal to drive a head unit from having a high temperature.SOLUTION: A liquid discharge device includes: a head unit which is driven by a driving signal and is capable of discharging liquid; a circuit board 200; and a driving signal generation circuit which is provided on the circuit board and generates the driving signal. The driving signal generation circuit has a modulation section which performs pulse modulation of a waveform specifying signal for specifying a waveform of the driving signal and generates a modulation signal, an amplification section which is provided with a first transistor Tr[1] and a second transistor Tr[2], amplifies the modulation signal by the first transistor and the second transistor, and generates an amplification signal, and a smoothing section which smooths the amplification signal and generates the driving signal. The circuit board is provided with a screw hole HL between the first transistor and the second transistor, thereby suppressing the driving signal generation circuit from having a high temperature.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a liquid ejection apparatus.

A liquid discharge apparatus such as an ink jet printer forms an image on a recording medium by driving a head unit and discharging a liquid such as ink filled in a cavity of the head unit from a nozzle provided in the head unit. . Such a liquid ejection apparatus is provided with a drive signal generation circuit that generates a drive signal for driving the head unit (for example,
Patent Document 1).

JP 2010-221500 A

Incidentally, the drive signal for driving the head unit is a signal having a large amplitude, and the drive signal generation circuit generates heat when generating the drive signal. For this reason, when the drive signal generation circuit generates a drive signal, the temperature of the drive signal generation circuit increases. Then, the temperature of the drive signal generation circuit rises and the drive signal generation circuit becomes high temperature (for example, a temperature higher than the endurance temperature of the drive signal generation circuit), so that the operation of the drive signal generation circuit becomes inaccurate. In some cases, the image quality of the image formed by the liquid ejecting apparatus deteriorates.

The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a technique for reducing the possibility that the drive signal generation circuit becomes high temperature.

In order to solve the above-described problems, a liquid ejection device according to a preferred aspect of the present invention is provided on a head board, a circuit board, and a circuit board that are driven by a drive signal and can eject liquid. A drive signal generation circuit for generating a drive signal, the drive signal generation circuit,
A modulation unit that generates a modulation signal by pulse-modulating a waveform defining signal that defines the waveform of the drive signal;
An amplifying unit having a first transistor and a second transistor, amplifying the modulation signal by the first transistor and the second transistor to generate an amplified signal, and smoothing the amplified signal to generate the drive signal And a smoothing portion, wherein the circuit board is provided with a screw hole between the first transistor and the second transistor.

In general, in a drive signal generation circuit that generates a drive signal, a transistor pair (first transistor and second transistor) that plays a role of amplifying a signal has a higher temperature than other elements of the drive signal generation circuit. Is likely to be. On the other hand, according to the above-described aspect,
Since the screw hole is provided between the transistor pair, heat generated from the transistor pair can be radiated from the screw hole. For this reason, according to the aspect mentioned above, compared with the case where a screw hole is not provided between transistor pairs, it becomes possible to suppress possibility that a drive signal generation circuit will become high temperature low.

In the liquid ejecting apparatus described above, the first transistor and the second transistor may be field effect transistors.

According to this aspect, since the field effect transistor is employed as the first transistor and the second transistor, for example, the power consumption in the drive signal generation circuit is reduced compared with the case where a bipolar transistor is employed, and the drive signal generation is performed. It is possible to suppress the possibility that the circuit will be hot.

In the liquid ejecting apparatus described above, the first pad electrically connected to the source electrode of the first transistor and the second electrode electrically connected to the gate electrode of the first transistor are disposed on the circuit board. And a third pad electrically connected to the drain electrode of the first transistor, and the distance between the screw hole and the first pad is:
The distance between the screw hole and the third pad is longer than the distance between the screw hole and the second pad, and the distance between the screw hole and the third pad is longer than the distance between the screw hole and the third pad. It may be characterized by being long.

In general, in a transistor, the amount of heat generated at the drain electrode is larger than the amount of heat generated at the source electrode and the gate electrode. On the other hand, according to the above-described aspect, since the screw hole is provided in the vicinity of the third pad electrically connected to the drain electrode of the first transistor, the heat generated from the first transistor is efficiently radiated. It becomes possible to do.

In the liquid ejection device described above, a diameter of the screw hole may be larger than a distance between the screw hole and the third pad.

According to this aspect, since the diameter of the screw hole is larger than the distance between the screw hole and the third pad, the diameter of the screw hole is smaller than the distance between the screw hole and the third pad. Compared to the case, it is possible to efficiently dissipate the heat generated from the first transistor.

In the liquid ejecting apparatus described above, a fifth pad electrically connected to the gate electrode of the second transistor and a fourth pad electrically connected to the source electrode of the second transistor are provided on the circuit board. And a sixth pad electrically connected to the drain electrode of the second transistor, and the distance between the screw hole and the fourth pad is
The distance between the screw hole and the sixth pad is longer than the distance between the screw hole and the fifth pad. The distance between the screw hole and the sixth pad is longer than the distance between the screw hole and the sixth pad. It may be characterized by being long.

According to this aspect, since the screw hole is provided in the vicinity of the sixth pad electrically connected to the drain electrode of the second transistor, it is possible to efficiently dissipate the heat generated from the second transistor. .

In the liquid ejecting apparatus described above, a diameter of the screw hole may be larger than a distance between the screw hole and the sixth pad.

According to this aspect, since the diameter of the screw hole is larger than the distance between the screw hole and the sixth pad, the diameter of the screw hole is smaller than the distance between the screw hole and the sixth pad. Compared to the case, it is possible to efficiently dissipate the heat generated from the second transistor.

In the liquid ejecting apparatus described above, the circuit board may be fixed to a frame of the liquid ejecting apparatus with screws inserted into the screw holes.

According to this aspect, since the heat generated from the transistor pair is radiated to the frame via the screw inserted in the screw hole, the heat generated from the transistor pair can be efficiently radiated.

In the liquid ejection apparatus described above, the first transistor includes a first package provided on the circuit board, and a first semiconductor chip provided between the first package and the circuit board, The second transistor includes a second package provided on the circuit board, a second semiconductor chip provided between the second package and the circuit board,
It may be characterized by comprising.

According to this aspect, the first semiconductor chip can be protected by the first package, and the second semiconductor chip can be protected by the second package. According to this aspect, the first
Heat generated from various electrodes such as the drain electrode provided on the semiconductor chip is radiated to the circuit board via the first package, and heat generated from various electrodes such as the drain electrode provided on the second semiconductor chip. The heat can be radiated to the circuit board through the second package.

1 is a block diagram illustrating an example of a configuration of an inkjet printer 1 according to the present invention. 1 is a perspective view illustrating an example of a schematic internal structure of an inkjet printer 1. FIG. 4 is an explanatory diagram for explaining an example of a structure of a discharge unit D. FIG. 3 is a plan view illustrating an example of an arrangement of nozzles N in the recording head HD. FIG. 3 is a block diagram illustrating an example of a configuration of a drive signal generation circuit 8. FIG. 4 is a timing chart showing an example of the operation of the drive signal generation circuit 8; 5 is an explanatory diagram illustrating an example of a circuit arrangement on a substrate 200. FIG. It is explanatory drawing which shows an example of the wiring pattern on the board | substrate 200. FIG. It is a figure which shows an example of the external appearance of transistor Tr [q]. It is sectional drawing which shows an example of the structure of transistor Tr [q]. It is a block diagram showing an example of composition of head unit HU. 4 is a timing chart for explaining an example of an operation of the inkjet printer 1 in a printing process. It is explanatory drawing for demonstrating an example of the connection state designation | designated signal SL [m]. 3 is a block diagram illustrating an example of a configuration of a connection state designation circuit 11. FIG. 10 is an explanatory diagram illustrating an example of a wiring pattern on a substrate 200 in Modification 1. FIG.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. However, in each figure, the size and scale of each part are appropriately changed from the actual ones. Further, since the embodiments described below are preferable specific examples of the present invention, various technically preferable limitations are attached thereto. However, the scope of the present invention is particularly limited in the following description. Unless otherwise stated, the present invention is not limited to these forms.

<< A. Embodiment >>
In the present embodiment, ink (an example of “liquid”) is ejected to record paper P (an example of “medium”).
The liquid ejecting apparatus will be described by exemplifying an ink jet printer that forms an image.

<< 1. Overview of inkjet printers >>
Hereinafter, an example of the configuration of the inkjet printer 1 according to the present embodiment will be described with reference to FIGS. 1 and 2.

FIG. 1 is a functional block diagram illustrating an example of the configuration of the inkjet printer 1. Print data Img indicating an image to be formed by the inkjet printer 1 is supplied to the inkjet printer 1 from a host computer (not shown) such as a personal computer or a digital camera. The ink jet printer 1 executes a printing process for forming an image indicated by the print data Img supplied from the host computer on the recording paper P.

As illustrated in FIG. 1, the inkjet printer 1 includes a control module 2, a head unit HU provided with a discharge unit D that discharges ink, and conveyance for changing the relative position of the recording paper P with respect to the head unit HU. And a mechanism 7. Among these, the control module 2 includes a control unit 6 that controls the operation of each unit of the inkjet printer 1, a drive signal generation circuit 8 that generates a drive signal Com for driving the ejection unit D, and a memory that stores various types of information. Part 9. In the present embodiment, as an example, each component of the control module 2 (
It is assumed that the control unit 6, the drive signal generation circuit 8, and the storage unit 9) are formed on the substrate 200 (see FIG. 6).

The head unit HU includes a recording head HD having M ejection units D and a supply circuit 10 for switching whether or not to supply the drive signal Com output from the drive signal generation circuit 8 to the print head HD.
(In this embodiment, M is a natural number satisfying 1 ≦ M).
Hereinafter, in order to distinguish each of the M ejection portions D provided in the recording head HD, they may be referred to as “first stage, second stage,..., M stage” in order. Further, the m-stage discharge part D is connected to the discharge part D [m].
(The variable m is a natural number satisfying 1 ≦ m ≦ M). In addition, when the components, signals, etc. of the ink jet printer 1 correspond to the number of stages m of the discharge section D [m], the codes for representing the components, signals, etc. correspond to the number of stages m. May be expressed with a subscript [m].
Hereinafter, among the drive signals Com, the drive signal Com supplied to the ejection unit D may be referred to as a supply drive signal Vin. Further, the supply drive signal Vin supplied to the discharge unit D [m] is
It may be referred to as a supply drive signal Vin [m].

The storage unit 9 includes, for example, a volatile memory such as a RAM (Random Access Memory), an RO,
M (Read Only Memory), EEPROM (Electrically Erasable Programmable Read-On
ly Memory) or non-volatile memory such as PROM (Programmable ROM) and various information such as print data Img supplied from the host computer and control program for the inkjet printer 1 Remember.

The control unit 6 includes a CPU (Central Processing Unit). However, the control unit 6 does not use the CPU, or in addition to the CPU, the FPGA (field-programmable gat
e array) or the like.
The control unit 6 is configured such that a CPU provided in the control unit 6 executes a control program stored in the storage unit 9 and operates according to the control program.
Control the operation of each part. Specifically, the control unit 6 includes a print signal SI for controlling the supply circuit 10 provided in the head unit HU, a waveform defining signal dCom for controlling the drive signal generation circuit 8, and the transport mechanism 7. A signal for controlling the operation of each part of the ink jet printer 1, such as a signal for controlling, is generated.

Here, the waveform defining signal dCom is a digital signal that defines the waveform of the drive signal Com.
The drive signal Com is an analog signal for driving the ejection unit D. The drive signal generation circuit 8 has a drive signal Co having a waveform defined by the digital waveform defining signal dCom.
Generate m.
The print signal SI is a digital signal for designating the type of operation of the ejection unit D. Specifically, the print signal SI specifies the type of operation of the ejection unit D by designating whether or not to supply the drive signal Com to the ejection unit D. Here, the designation of the type of operation of the ejection part D is, for example, whether or not the ejection part D is to be driven or whether ink is ejected from the ejection part D when the ejection part D is driven. Or specifying the amount of ink ejected from the ejection unit D when the ejection unit D is driven.

When the printing process is executed, the control unit 6 first stores the print data Img supplied from the host computer in the storage unit 9. Next, based on various data such as print data Img stored in the storage unit 9, the control unit 6 performs various types such as a print signal SI, a waveform defining signal dCom, and a signal for controlling the transport mechanism 7. Generate a control signal. And the control part 6 is
Based on various control signals such as the print signal SI and various data stored in the storage unit 9, the ejection unit D controls the transport mechanism 7 so as to change the relative position of the recording paper P with respect to the head unit HU. The supply circuit 10 is controlled so as to be driven. Thereby, the control unit 6
Adjusting the presence / absence of ink ejection from the ejection part D, the ink ejection amount, the ink ejection timing, etc., so that a printing process for forming an image corresponding to the print data Img on the recording paper P is executed. Each part of the ink jet printer 1 is controlled.

FIG. 2 is a perspective view illustrating an example of a schematic internal structure of the inkjet printer 1.
As shown in FIG. 2, in the present embodiment, it is assumed that the ink jet printer 1 is a serial printer. Specifically, when performing the printing process, the inkjet printer 1 is configured to discharge the recording unit P while reciprocating the head unit HU in the main scanning direction intersecting the sub scanning direction while conveying the recording paper P in the sub scanning direction. By ejecting ink from D, dots corresponding to the print data Img are formed on the recording paper P.
In the following, the + X direction and the −X direction that is the opposite direction are collectively referred to as the “X axis direction”, the + Y direction and the −Y direction that is the opposite direction are collectively referred to as the “Y axis direction”, and the + Z direction The opposite direction-
The Z direction is collectively referred to as “Z-axis direction”. In the present embodiment, as shown in FIG. 2, the direction from the −X side (upstream side) to the + X side (downstream side) is the sub-scanning direction, and the Y-axis direction is the main scanning direction. In this embodiment, as an example, it is assumed that the X-axis direction, the Y-axis direction, and the Z-axis direction are directions orthogonal to each other. However, the X-axis direction, the Y-axis direction, and the Z-axis direction are assumed. May be in any direction that intersects each other.

As illustrated in FIG. 2, the inkjet printer 1 according to this embodiment includes a housing 100.
And a carriage 110 capable of reciprocating in the Y-axis direction inside the housing 100 and mounting the head unit HU. Note that the housing 100 and a metal member provided inside the housing 100 and fixed to the housing 100 may be referred to as a “frame”.

Further, as described above, the ink jet printer 1 according to the present embodiment includes the transport mechanism 7.
The transport mechanism 7 moves the carriage 110 back and forth in the Y-axis direction and transports the recording paper P in the + X direction when the printing process is executed, so that the head unit H of the recording paper P is obtained.
The relative position with respect to U is changed, and ink can land on the entire recording paper P.
As shown in FIG. 1, the transport mechanism 7 includes a transport motor 71 serving as a drive source for reciprocating the carriage 110, a motor driver 72 for driving the transport motor 71,
A paper feed motor 73 serving as a drive source for transporting the recording paper P and a motor driver 74 for driving the paper feed motor 73 are provided. Further, as shown in FIG. 2, the transport mechanism 7 is stretched between a carriage guide shaft 76 extending in the Y-axis direction, a pulley 711 that is rotationally driven by the transport motor 71, and a rotatable pulley 712. And a timing belt 710 extending in the Y-axis direction. The carriage 110 has a carriage guide shaft 7
6 and reciprocally supported in the Y-axis direction, and fixed to a predetermined portion of the timing belt 710 via a fixing tool 120. Therefore, the transport mechanism 7 can reciprocate the carriage 110 together with the head unit HU in the Y-axis direction along the carriage guide shaft 76 by driving the pulley 711 by the transport motor 71.

As shown in FIG. 2, the transport mechanism 7 rotates in accordance with the drive of the platen 75 provided on the lower side (−Z side) of the carriage 110 and the paper feed motor 73, and prints the recording paper P one by one. A paper feed roller (not shown) for feeding onto the platen 75, and a paper discharge roller 730 that rotates according to the drive of the paper feed motor 73 and conveys the recording paper P on the platen 75 to the paper discharge port. Prepare. Therefore, the transport mechanism 7 can transport the recording paper P on the platen 75 from the −X side (upstream side) to the + X side (downstream side) as shown in FIG.

In the present embodiment, as illustrated in FIG. 2, the carriage 1 of the inkjet printer 1.
In FIG. 10, four ink cartridges 31 are listed. More specifically, in this embodiment, as an example, four colors (CMYK) of cyan, magenta, yellow, and black are used.
Assume that four ink cartridges 31 corresponding one-to-one with these inks are mounted on the carriage 110.
In the present embodiment, as an example, the M ejection units D include four ink cartridges 3.
A case is assumed in which there are four groups corresponding to 1 and 1: 1. Each ejection unit D is supplied with ink from the ink cartridge 31 corresponding to the group to which the ejection unit D belongs. Thereby, each discharge part D can fill the supplied ink inside, and can discharge the filled ink from the nozzle N (refer FIG. 3). That is, head unit HU
The total of M ejection units D included in the can eject inks of four colors CMYK as a whole. Note that FIG. 2 is merely an example, and the ink cartridge 31 may be provided outside the carriage 110.

<< 2. Overview of recording head and discharge section >>
With reference to FIGS. 3 and 4, the recording head HD and the discharge section D provided in the recording head HD will be described.

FIG. 3 is a schematic partial cross-sectional view of the recording head HD in which the recording head HD is cut so as to include the ejection portion D.
As shown in FIG. 3, the ejection part D includes a piezoelectric element PZ, a cavity 320 filled with ink, a nozzle N communicating with the cavity 320, and a vibration plate 310. In the ejection part D, the supply drive signal Vin is supplied to the piezoelectric element PZ, and the piezoelectric element PZ supplies the supply drive signal V.
By being driven by in, the ink in the cavity 320 is ejected from the nozzle N. The cavity 320 is a space defined by the cavity plate 340, the nozzle plate 330 in which the nozzles N are formed, and the vibration plate 310. The cavity 320 communicates with the reservoir 350 via the ink supply port 360. The reservoir 350 communicates with the ink cartridge 31 corresponding to the ejection unit D via the ink intake port 370.

In the present embodiment, a unimorph (monomorph) type as shown in FIG. 3 is adopted as the piezoelectric element PZ. The piezoelectric element PZ is not limited to a unimorph type, but may be a bimorph type or a laminated type.
The piezoelectric element PZ includes an upper electrode Zu, a lower electrode Zd, and a piezoelectric body Zm provided between the upper electrode Zu and the lower electrode Zd. The lower electrode Zd is electrically connected to a power supply line LHd (see FIG. 8) set to the power supply potential VBS on the low potential side. The drive signal Com is applied to the upper electrode Zu.
When (supply drive signal Vin) is supplied and a voltage is applied between the upper electrode Zu and the lower electrode Zd, the piezoelectric element PZ is displaced in the + Z direction or the −Z direction according to the applied voltage, As a result, the piezoelectric element PZ vibrates.

A diaphragm 310 is installed in the upper surface opening of the cavity plate 340. Diaphragm 31
0 is joined to the lower electrode Zd. For this reason, when the piezoelectric element PZ is driven and displaced by the supply drive signal Vin, the diaphragm 310 is also displaced. Then, the volume of the cavity 320 changes due to the displacement of the vibration plate 310, and the ink filled in the cavity 320 is ejected from the nozzle N. Ink is supplied from the reservoir 350 when the ink in the cavity 320 decreases due to ink ejection.

FIG. 4 is an explanatory diagram for explaining an example of the arrangement of the M nozzles N provided in the recording head HD when the inkjet printer 1 is viewed in plan from the + Z direction or the −Z direction.

As shown in FIG. 4, the print head HD is provided with four nozzle rows Ln. Here, the nozzle row Ln is a plurality of nozzles N provided so as to extend in a row in a predetermined direction. In the present embodiment, it is assumed that each nozzle row Ln is configured by arranging a plurality of nozzles N so as to extend in a row in the X-axis direction.
In the following, four nozzle rows Ln provided in the recording head HD are respectively represented by nozzle rows Ln−.
They are referred to as BK, Ln-CY, Ln-MG, and Ln-YL. Here, the nozzle row Ln-BK is a nozzle row Ln in which the nozzles N of the discharge portion D that discharges black ink are arranged, and the nozzle row Ln-CY is the nozzle N of the discharge portion D that discharges cyan ink. Nozzle array Ln, and nozzle array Ln-MG
Is a nozzle row Ln in which the nozzles N of the discharge unit D that discharges magenta ink are arranged, and the nozzle row Ln-YL is a nozzle row L in which the nozzles N of the discharge unit D that discharges yellow ink are arranged.
n.

However, the nozzle row Ln shown in FIG. 4 is an example, and the plurality of nozzles N belonging to each nozzle row Ln are arranged with a predetermined width in a direction intersecting with the extending direction of the nozzle row Ln. Also good. In other words, in each nozzle row Ln, a plurality of nozzles N belonging to each nozzle row Ln are arranged in a staggered manner so that the even-numbered nozzles N and odd-numbered nozzles N have different positions in the Y-axis direction from the + X side. May be. Each nozzle row Ln may extend in a direction different from the X-axis direction. Further, in the present embodiment, the case where the number of nozzle rows Ln provided in the recording head HD is “4” is illustrated, but the recording head HD is provided with one or more nozzle rows Ln. Just do it.

<< 3. Overview of drive signal generation circuit >>
Next, the drive signal generation circuit 8 will be described with reference to FIGS.

FIG. 5 is a diagram illustrating an example of a circuit configuration of the drive signal generation circuit 8. As shown in this figure,
The drive signal generation circuit 8 generates a drive signal Com based on the waveform defining signal dCom.
As shown in FIG. 5, the drive signal generation circuit 8 includes an LSI (Large Scale Integration) 80.
, Transistor Tr [1] (an example of “first transistor”) and transistor Tr [2] (
An example of “second transistor”) and various elements such as a resistor and a capacitor. In the following, the transistors Tr [1] and Tr [2] are referred to as the transistor Tr [q].
(Q is 1 or 2).

The waveform defining signal dCom is input from the control unit 6 to the LSI 80 via the input terminal Tn-in. The LSI 80 inputs a gate signal to the gates of the transistors Tr [1] and Tr [2], for example, based on the waveform defining signal dCom. In this embodiment, as an example,
Transistors Tr [1] and Tr [2] are N-channel field effect transistors (FETs).
: Field Effect Transistor).

As shown in FIG. 5, the LSI 80 includes a DAC (Digital to Analog Converter) 802,
Subtractor 804, adder 806, attenuator 808, integral attenuator 812, comparator 820
, And a gate driver 830.
The DAC 802 converts the waveform defining signal dCom that defines the waveform of the drive signal Com into an analog signal Aa, and supplies the signal Aa to the input terminal (−) of the subtractor 804. The signal Aa
The voltage amplitude of is, for example, about 0 to 2 volts, and this voltage is amplified about 20 times.
It becomes the drive signal Com. That is, the signal Aa is a signal before the drive signal Com is amplified.

The integral attenuator 812 attenuates the drive signal Com fed back via the terminal Tn1 and supplies the integrated signal Ax to the input terminal (+) of the subtractor 804.
The subtractor 804 supplies a signal Ab indicating a voltage obtained by subtracting the voltage at the input terminal (−) from the voltage at the input terminal (+) to the adder 806.
Note that the power supply voltage of the circuit from the DAC 802 to the comparator 820 is a low voltage (for example, 3.3 volts). That is, the voltage of the signal Aa is about 2 volts at the maximum. On the other hand, the drive signal Com has a large amplitude and may exceed 40 volts, for example. Therefore, in the integral attenuator 812, the voltage of the drive signal Com is attenuated so that the amplitude range of the signal Ax is matched with the amplitude range of the signal in the circuit from the DAC 802 to the DAC 802.
The attenuator 808 supplies the adder 806 with the signal Ay obtained by attenuating the high frequency component of the drive signal Com fed back through the terminal Tn2. The attenuation in the attenuator 808 is the integral attenuator 8.
This is because the amplitude range of the signal Ay is matched with the amplitude range of the signal in the circuit from the DAC 802 to the comparator 820, as in the case of FIG.
The adder 806 supplies a signal As indicating a voltage obtained by adding the voltage indicated by the signal Ab and the voltage indicated by the signal Ay to the comparator 820. The voltage of the signal As is obtained by subtracting the voltage of the signal Aa from the voltage of the signal Ax obtained by attenuating the signal supplied to the terminal Tn1, and adding the voltage of the signal Ay obtained by attenuating the signal supplied to the terminal Tn2. It is. For this reason, the voltage of the signal As is obtained by correcting a deviation obtained by subtracting the target voltage Aa from the attenuation voltage of the drive signal Com output from the output terminal Tn-out with the high frequency component of the drive signal Com. It can be called a signal.
The comparator 820 outputs a modulation signal Ms obtained by pulse-modulating the signal As. Specifically, the comparator 820 is at the H level when the signal As is higher than the threshold voltage Vth1 when the voltage As is increased, and when the signal As is lower than the threshold voltage Vth2 when the signal As is decreased. The modulation signal Ms which becomes L level is output. The threshold voltage is set to have a relationship of “Vth1> Vth2”.

The gate driver 830 is supplied with a modulation signal Ms. The gate driver 830 supplies a gate signal obtained by converting the modulation signal Ms to a high logic amplitude to the gate electrode of the transistor Tr [1] via the terminal TnH and the resistor RH. The gate driver 830 supplies a gate signal obtained by converting a signal obtained by inverting the logic level of the modulation signal Ms to a high logic amplitude to the gate electrode of the transistor Tr [2] via the terminal TnL and the resistor RL. For this reason, the logic levels of the gate signals supplied to the gate electrodes of the transistors Tr [1] and Tr [2] are mutually exclusive. Note that timing control may be performed so that the logic levels of the two gate signals output from the gate driver 830 do not simultaneously become the H level. In other words, exclusive here means that the logic levels of the gate signals supplied to the gate electrodes of the transistors Tr [1] and Tr [2] do not simultaneously become H level (in other words, the transistor Tr [ 1] and Tr [2] do not turn on at the same time.

The modulation signal Ms in this embodiment is an example, and the modulation signal is a waveform defining signal dCom.
Accordingly, the signal may be any signal that drives the transistors Tr [1] and Tr [2]. That is, the modulation signal is not limited to the modulation signal Ms which is a narrowly defined modulation signal, and a signal obtained by inverting the logic level of the modulation signal Ms and the transistors Tr [1] and Tr [2] are simultaneously turned on. Including signals that are time-controlled so that

Hereinafter, a circuit for generating a modulation signal based on a defining signal that defines the waveform of the drive signal Com may be referred to as a “modulation unit”. That is, the modulation unit in the present embodiment is a circuit that generates the modulation signal Ms based on the waveform defining signal dCom, specifically, the DAC 802,
This circuit includes a subtracter 804, an adder 806, and a comparator 820.
In the present embodiment, the digital waveform defining signal dCom is described as an example of the waveform defining signal. However, the waveform defining signal is a signal that defines a target value for generating the drive signal Com. For example, the analog signal Aa may be a waveform defining signal. When the signal Aa is a waveform defining signal, the modulation unit may be configured without including the DAC 802.
When the modulation signal is widely recognized, that is, when the modulation signal includes not only the modulation signal Ms in a narrow sense but also a signal obtained by inverting the logic level of the modulation signal Ms, the modulation unit causes the gate driver 830 to operate. What is necessary is just to comprise.

As shown in FIG. 5, a voltage Vh (for example, 42 volts) is applied to the drain electrode of the high-order transistor Tr [1] (high-side transistor) among the transistors Tr [1] and Tr [2]. . Further, the source electrode of the low-order transistor Tr [2] (low-side transistor) is grounded (or electrically connected to the power supply line LHd set to the low-potential-side power supply potential VBS).
Each of the transistors Tr [1] and Tr [2] is turned on when the gate signal is at the H level. Therefore, an amplified signal Az obtained by amplifying the modulation signal Ms appears at the node Nd connecting the source electrode of the transistor Tr [1] and the drain electrode of the transistor Tr [2]. In other words, the transistors Tr [1] and Tr [2] generate an amplified signal obtained by amplifying the modulation signal Ms.
Hereinafter, a circuit that generates an amplified signal Az obtained by amplifying the modulation signal Ms is referred to as an amplifier circuit 81.
(An example of “amplifying unit”). In the present embodiment, the amplifier circuit 81 includes transistors Tr [1] and Tr [2].

As illustrated in FIG. 5, the drive signal generation circuit 8 includes an LPF (Low Pass Filter) 82 (an example of a “smoothing unit”) that generates the drive signal Com by smoothing the amplified signal Az. The LPF 82 includes an inductor L0 and a capacitor C0. The inductor L0 has one end electrically connected to the node Nd and the other end electrically connected to the output terminal Tn-out. One end of the capacitor C0 is electrically connected to the output terminal Tn-out, and the other end is grounded.

As shown in FIG. 5, the drive signal generation circuit 8 has a drive signal Co output to the output terminal Tn-out.
A pull-up circuit 83 that pulls up m and feeds back to the terminal Tn1 is provided. Pull-up circuit 8
3, a resistor R1 having one end electrically connected to the output terminal Tn-out and the other end electrically connected to the terminal Tn1, and one end electrically connected to the terminal Tn1 and the other end receiving the voltage Vh. Applied resistance R2
And including.
The drive signal generation circuit 8 includes a BPF (Band Pass Filter) 84 that cuts a DC component from a frequency component in a predetermined band of the drive signal Com and feeds it back to the terminal Tn2. The BPF 84 has a resistor R3, one end electrically connected to the output terminal Tn-out, the other end electrically connected to one end of the resistor R3, and one end electrically connected to one end of the resistor R3. A resistor R4 having the other end grounded to the ground, a capacitor C2 having one end electrically connected to the other end of the resistor R3, and the other end grounded to the ground, and one end electrically connected to the other end of the resistor R3. And a capacitor C3, the other end of which is electrically connected to the terminal Tn2. Among these, the capacitor C1 and the resistor R4 function as an HPF (High Pass Filter) that passes a high frequency component equal to or higher than the cutoff frequency in the drive signal Com. Note that the cutoff frequency of the HPF is set to about 9 MHz, for example. The resistor R3 and the capacitor C2 are connected to the drive signal C.
LPF (Low Pass Filter) that allows low frequency components below the cut-off frequency to pass.
Function as. Note that the cutoff frequency of the LPF is set to about 160 MHz, for example. In the present embodiment, in the BPF 84, the cutoff frequency of the HPF is set lower than the cutoff frequency of the LPF. For this reason, the BPF 84 includes the drive signal Com.
A frequency component in a predetermined band that is equal to or higher than the cutoff frequency of the HPF and lower than or equal to the cutoff frequency of the LPF is passed. Further, since the BPF 84 includes the capacitor C3, a signal obtained by cutting the DC component of the drive signal Com in a predetermined band that has passed through the HPF and the LPF is fed back to the terminal Tn2.

As shown in FIG. 5, the drive signal generation circuit 8 converts the amplified signal Az at the node Nd into the LPF.
The drive signal Com is generated by the smoothing by 82. The drive signal Com is integrated / subtracted by the integral attenuator 812 and then fed back to the subtractor 804. Therefore, self-oscillation occurs at a frequency determined by the feedback delay (the sum of the delay in the LPF 82 and the delay in the integral attenuator 812) and the transfer function of the feedback. However, since the delay amount of the feedback path via the terminal Tn1 is large, the self-excited oscillation frequency should be increased to a level that can sufficiently ensure the accuracy of the waveform of the drive signal Com only by the feedback via the terminal Tn1. I can't. On the other hand, in the present embodiment, a path for returning the high frequency component of the drive signal Com is provided via the terminal Tn2 in addition to the path via the terminal Tn1, so that the drive signal generation circuit 8 is viewed as a whole. The delay can be reduced. That is, in this embodiment, the frequency of the signal As obtained by adding the signal Ay, which is the high-frequency component of the drive signal Com, to the signal Ab can be increased as compared with the case where there is no path via the terminal Tn2. Thus, it is possible to sufficiently ensure the accuracy of the drive signal Com.

In the present embodiment, the frequency of self-excited oscillation (the frequency of the modulation signal Ms) is 1 MHz or more and 8 MHz or less. By setting the modulation signal Ms to such a frequency, the drive signal Com
It is possible to achieve both of sufficiently ensuring the accuracy of the waveform and suppressing the switching loss in the transistors Tr [1] and Tr [2].

FIG. 6 is a diagram illustrating a relationship among the signal Aa, the signal As, and the modulation signal Ms. Hereinafter, the generation of the modulation signal Ms in the comparator 820 will be described with reference to FIG.

As shown in FIG. 6, the signal As is a triangular wave, and its oscillation frequency varies according to the voltage (input voltage) of the signal Aa. Specifically, the oscillation frequency of the signal As is highest when the input voltage is an intermediate value, and decreases as the input voltage increases from the intermediate value, and decreases as the input voltage decreases from the intermediate value. . In addition, the slope of the triangular wave indicated by the signal As is substantially the same for ascending (rising voltage) and descending (decreasing voltage) when the input voltage is near the intermediate value. Therefore, the duty ratio of the modulation signal Ms, which is the result of comparing the signal As with the threshold voltages Vth1 and Vth2 by the comparator 820, is approximately 50%. When the input voltage increases from the intermediate value, the downward slope of the signal As becomes gentle. For this reason, the period during which the modulation signal Ms is at the H level is relatively long, and the duty ratio is increased. On the other hand, as the input voltage decreases from the intermediate value, the upward slope of the signal As becomes gentle. For this reason, the period during which the modulation signal Ms is at the H level becomes relatively short, and the duty ratio becomes small. For this reason, the modulation signal Ms
Is a pulse in which the duty ratio of the modulation signal Ms is approximately 50% at an intermediate value of the input voltage, increases as the input voltage becomes higher than the intermediate value, and decreases as the input voltage becomes lower than the intermediate value. It becomes a density modulation signal.

The gate driver 830 turns on the transistor Tr [1] when the modulation signal Ms is at the H level, and turns off the transistor Tr [1] when the modulation signal Ms is at the L level. Gate driver 83
0 turns off the transistor Tr [2] if the modulation signal Ms is at the H level.
If it is L level, it is turned on. Therefore, the voltage of the drive signal Com obtained by smoothing the amplified signal Az at the node Nd electrically connecting the transistors Tr [1] and Tr [2] with the LPF 82 increases as the duty ratio of the modulation signal Ms increases. As the duty ratio becomes smaller, it becomes lower. For this reason, the drive signal Com has a waveform obtained by enlarging the waveform of the analog signal Aa.

As described above, since the drive signal generation circuit 8 uses pulse density modulation, there is an advantage that a change width of the duty ratio can be increased as compared with pulse width modulation in which the modulation frequency is fixed.
Further, the drive signal generation circuit 8 is self-excited oscillation and does not require a circuit for generating a high frequency carrier wave such as separately excited oscillation. For this reason, other than circuits that handle high voltages, that is, LSI 80
Has the advantage of easy integration of the functions of
Further, in the drive signal generation circuit 8, there are not only a path via the terminal Tn1 but also a path for feeding back a high frequency component via the terminal Tn2 as a feedback path of the drive signal Com. Get smaller. For this reason, in the drive signal generation circuit 8, the frequency of the self-excited oscillation is increased, and the drive signal Com can be generated with high accuracy.

<< 4. Circuit layout on board >>
Hereinafter, the circuit arrangement and the like on the substrate 200 (an example of “circuit substrate”) will be described with reference to FIGS. 7 to 10. FIG. 7 shows the control unit 6 and the transistor Tr [1] on the substrate 200.
And FIG. 6 is an explanatory diagram for explaining an example of the arrangement with Tr [2]. FIG. 8 is a diagram illustrating an example of a schematic wiring pattern on the substrate 200.

As shown in FIG. 7, transistors Tr [1] and Tr [2] included in the drive signal generation circuit 8 and the control unit 6 are arranged on the substrate 200. The substrate 200 has a screw hole HL through which a screw for fixing the substrate 200 to the frame of the inkjet printer 1 is inserted.
It is formed between the transistors Tr [1] and Tr [2].
Hereinafter, the diameter of the screw hole HL is referred to as “Wr”, the distance between the screw hole HL and the transistor Tr [1] is referred to as “Wt1”, and the distance between the screw hole HL and the transistor Tr [2]. "Wt2"
The distance between the screw hole HL and the control unit 6 is referred to as “W0”. In this case, the diameter Wr, the distance Wt1, the distance Wt2, and the distance W0 satisfy the following expressions (1) to (5).
Wt1 <W0 Formula (1)
Wt2 <W0 Formula (2)
Wt1 <Wr Formula (3)
Wt2 <Wr Formula (4)
| Wt1−Wt2 | ≦ δ (5)

Here, the distance δ appearing in the equation (5) is a predetermined distance, for example, 1 mm. In the present embodiment, the constituent elements on the substrate 200 are arranged so as to satisfy the expressions (1) to (5), but the present invention is not limited to such an aspect. The above components may be arranged so as to satisfy at least the formula (1) and the formula (2), and more preferably the formula (
What is necessary is just to arrange | position so that 1)-Formula (4) may be satisfy | filled.

As shown in FIG. 8, on a substrate 200, a conductive pad Pd1 (an example of a “first pad”) electrically connected to a source electrode of the transistor Tr [1], and a transistor Tr [1] The conductive pad Pd2 (an example of “second pad”) electrically connected to the gate electrode of the transistor and the conductive pad Pd3 (“second pad” electrically connected to the drain electrode of the transistor Tr [1]) 3 ”), a conductive pad Pd4 electrically connected to the source electrode of the transistor Tr [2] (an example of“ fourth pad ”), and a gate electrode of the transistor Tr [2] An electrically connected conductive pad Pd5 (an example of a “fifth pad”) and a transistor Tr [2]
And a conductive pad Pd6 (an example of a “sixth pad”) electrically connected to the drain electrode. The screw hole HL is disposed between the pad Pd3 and the pad Pd6.
Hereinafter, the distance between the pad Pd1 and the screw hole HL will be referred to as “W1”, and the pad Pd2 and the screw hole HL will be referred to as “W1”.
The distance between the pad Pd3 and the screw hole HL is referred to as "W3".
The distance between 4 and the screw hole HL is referred to as “W4”, the distance between the pad Pd5 and the screw hole HL is referred to as “W5”, and the distance between the pad Pd6 and the screw hole HL is referred to as “W6”. In this case, the distances W1 to W6 satisfy the following expressions (6) to (15).
W3 <W1 Formula (6)
W3 <W2 ... Formula (7)
W6 <W4 Formula (8)
W6 <W5 ... Formula (9)
W3 <W0 ... Formula (10)
W6 <W0 Formula (11)
W3 <Wr Formula (12)
W6 <Wr Formula (13)
W2 <W1 Formula (14)
W4 <W5 ... Formula (15)

In the present embodiment, the constituent elements on the substrate 200 are arranged so as to satisfy the expressions (6) to (15). However, the present invention is not limited to such an aspect. The upper components may be arranged so as to satisfy at least the expressions (6) to (11), and more preferably, the elements may be arranged so as to satisfy the expressions (6) to (13).

Next, the structure of the transistor Tr [q] (Tr [1] and Tr [2]) will be described with reference to FIGS. Here, FIG. 9 is a perspective view showing an example of the appearance of the transistor Tr [q]. FIG. 10 is a cross-sectional view illustrating an example of the structure of the transistor Tr [q]. Note that FIG. 10 illustrates the case where the transistor Tr [q] illustrated in FIG. 7 is cut along an EE line.

As shown in FIGS. 9 and 10, the transistor Tr [q] is provided on the surface F1 on the substrate 200 side of the surfaces of the semiconductor chip CP [q] and the semiconductor chip CP [q]. Of the surfaces of the source electrode EnS [q] and the gate electrode EnG [q] and the semiconductor chip CP [q], the drain electrode EnD [q] provided on the surface F2 opposite to the surface F1, and the conductivity And package PK [q] connected to the drain electrode EnD [q].
As understood from FIG. 10, the semiconductor chip CP [q], the source electrode EnS [q], the gate electrode EnG [q], and the drain electrode EnD [q] are provided between the substrate 200 and the package PK [q]. It will be accommodated in the space. The source electrode EnS [q] is electrically connected to the source pad PdS [q], the gate electrode EnG [q] is electrically connected to the gate pad PdG [q], and the drain electrode EnD [q]. Are electrically connected to the drain pad PdD [q]. Here, the source pad PdS [1] corresponds to the pad Pd1, the gate pad PdG [1] corresponds to the pad Pd2, the drain pad PdD [1] corresponds to the pad Pd3, and the source pad PdS [2 ] Corresponds to the pad Pd4, the gate pad PdG [2] corresponds to the pad Pd5, and the drain pad PdD [2] corresponds to the pad Pd6.
It corresponds to.
That is, for the transistor Tr [1], the source electrode EnS [1] provided on the semiconductor chip CP [1] (an example of “first semiconductor chip”) is electrically connected to the pad Pd1, and the gate electrode EnG [1 ] Is electrically connected to the pad Pd2, and the drain electrode EnD [1] is connected to the package PK [1] (
An example of “first package” is electrically connected to the pad Pd3. Regarding the transistor Tr [2], the source electrode EnS [2] provided on the semiconductor chip CP [2] (an example of the “second semiconductor chip”) is electrically connected to the pad Pd4 and the gate electrode EnG [2 ] Is electrically connected to the pad Pd5, and the drain electrode EnD [2] is electrically connected to the pad Pd6 via the package PK [2] (an example of “second package”).

<< 5. Head unit overview >>
Hereinafter, an example of the configuration and operation of the head unit HU will be described with reference to FIGS. 11 to 14.

FIG. 11 is a block diagram showing an example of the configuration of the head unit HU. As mentioned above,
The head unit HU includes a recording head HD, a supply circuit 10, a wiring LHa to which a drive signal Com is supplied from the drive signal generation circuit 8, and a power supply line LHd.
The supply circuit 10 includes M switches SW (SW [1] to SW [M]) and a connection state designation circuit 11 that designates the connection state of each switch SW. For example, a transmission gate can be adopted as each switch SW. FIG. 11 shows a case where M = 3 for simplicity.
The connection state designation circuit 11 includes a clock signal CLK, a print signal SI,
Based on at least a part of the latch signal LAT and the change signal CNG, connection state designation signals SL [1] to SL [M] for designating on / off of the switches SW [1] to SW [M] are generated. .
The switch SW [m] is electrically connected to the wiring LHa and the upper electrode Zu [m] of the piezoelectric element PZ [m] provided in the discharge portion D [m] in response to the connection state designation signal SL [m]. And switching non-conduction. In the present embodiment, it is assumed that the switch SW [m] is turned on when the connection state designation signal SL [m] is at a high level and turned off when the connection state designation signal SL [m] is at a low level. As described above, of the drive signal Com, the signal that is actually supplied to the piezoelectric element PZ [m] of the discharge section D [m] via the switch SW [m] is the supply drive signal Vin [m].

  Next, the operation of the head unit HU will be described with reference to FIGS.

In the present embodiment, the operation period of the inkjet printer 1 includes one or a plurality of unit periods Tu. The ink jet printer 1 can drive each ejection unit D for printing processing in each unit period Tu. The ink jet printer 1 performs printing processing in a plurality of unit periods Tu provided continuously or intermittently, thereby ejecting ink from each ejection unit D one or more times, for example, and print data Img. Is formed.

FIG. 12 is a timing chart showing an example of the operation of the inkjet printer 1 in the unit period Tu.
As shown in FIG. 12, the control unit 6 outputs a latch signal LAT having a pulse PlsL.
Thereby, the control unit 6 defines the unit period Tu as a period from the rising of the pulse PlsL to the rising of the next pulse PlsL. Further, the control unit 6 outputs a change signal CNG having a pulse PlsC. Thereby, the control unit 6 changes the unit period Tu to the pulse PlsL.
The control period Tu1 from the rise of the pulse PlsC to the rise of the pulse PlsC and the control period Tu2 from the rise of the pulse PlsC to the rise of the pulse PlsL.
In addition, the print signal SI includes individual designation signals Sd [1] to Sd [M] that designate the type of operation of the ejection units D [1] to D [M] in each unit period Tu. When the printing process is executed in the unit period Tu, the control unit 6 prior to the unit period Tu, the individual designation signals Sd [1] to Sd [M].
Is supplied to the connection state designating circuit 11 in synchronization with the clock signal CLK. In this case, the connection state designating circuit 11 receives the individual designating signal Sd [m] during the unit period Tu.
Based on the above, a connection state designation signal SL [m] is generated.

As shown in FIG. 12, the drive signal Com has a waveform PX provided in the control period Tu1 and a waveform PY provided in the control period Tu2. In the present embodiment, the waveform PX and the waveform PY are determined so that the potential difference between the highest potential VHX and the lowest potential VLX of the waveform PX is larger than the potential difference between the highest potential VHY and the lowest potential VLY of the waveform PY. Specifically, the drive signal Co having the waveform PX
When the ejection portion D [m] is driven by m, the waveform PX is determined such that an amount of ink corresponding to a medium dot (medium amount) is ejected from the ejection portion D [m]. Further, when the ejection unit D [m] is driven by the drive signal Com having the waveform PY, the waveform is such that an amount of ink corresponding to a small dot (a small amount) is ejected from the ejection unit D [m]. Determine the PY waveform. In the waveforms PX and PY, the potential at the start and end is set to the reference potential V0.

FIG. 13 is an explanatory diagram for explaining the relationship between the individual designation signal Sd [m] and the connection state designation signal SL [m].
As shown in FIG. 13, in this embodiment, it is assumed that the individual designation signal Sd [m] is a 2-bit digital signal. Specifically, the individual designation signal Sd [m] discharges an amount of ink corresponding to a large dot (a large amount) (“large dot”) to the discharge unit D [m] in each unit period Tu. A value (1, 1) designating a medium amount of ink (which may be referred to as “medium dot formation”) (1, 0) A value (0, 1) that designates ejection of a small amount of ink (sometimes referred to as “small dot formation”) and a value (0, 0) that designates non-ejection of ink. One of the values is set.
When the individual designation signal Sd [m] is set to a value (1, 1) designating the formation of a large dot, the connection state designation circuit 11 sends the connection state designation signal SL [m] to the control period Tu1 and Set to high level at Tu2. In this case, the ejection unit D [m] is driven by the drive signal Com having the waveform PX in the control period Tu1 to eject a medium amount of ink, and is driven by the drive signal Com having the waveform PY in the control period Tu2. Eject a small amount of ink. Accordingly, the ejection unit D [m] ejects a large amount of ink in total in the unit period Tu, and a large dot is formed on the recording paper P.
When the individual designation signal Sd [m] is set to a value (1,0) designating the formation of medium dots, the connection state designation circuit 11 sends the connection state designation signal SL [m] in the control period Tu1. The high level is set to the low level in the control period Tu2. In this case, the discharge part D [m]
In the unit period Tu, a medium amount of ink is ejected, and medium dots are formed on the recording paper P.
When the individual designation signal Sd [m] is set to a value (0, 1) designating the formation of small dots, the connection state designation circuit 11 sends the connection state designation signal SL [m] in the control period Tu1. The low level is set to the high level in the control period Tu2. In this case, the discharge part D [m]
In the unit period Tu, a small amount of ink is ejected, and small dots are formed on the recording paper P.
When the individual designation signal Sd [m] is set to a value (0, 0) that designates non-ejection of ink, the connection state designation circuit 11 sends the connection state designation signal SL [m] to the control periods Tu1 and Tu2. Set to low level at. In this case, the ejection unit D [m] does not eject ink and does not form dots on the recording paper P in the unit period Tu.

FIG. 14 is a diagram illustrating an example of the configuration of the connection state designating circuit 11 according to the present embodiment. As shown in FIG. 14, the connection state designation circuit 11 generates connection state designation signals SL [1] to SL [M].
Specifically, the connection state designating circuit 11 includes transfer circuits SR [1] to SR [M] and a latch circuit LT [M] so as to correspond one-to-one with the discharge units D [1] to D [M]. 1] to LT [M] and decoders DC [1] to DC [M]
And having. Among these, the individual designation signal Sd [m] is supplied to the transfer circuit SR [m]. In this figure, the individual designation signals Sd [1] to Sd [M] are supplied serially. For example, the individual designation signal Sd [m] corresponding to m stages is transferred from the transfer circuit SR [1] to the transfer circuit SR. To [m], the clock signal CLK
The case where it transfers in order synchronously is illustrated. The latch circuit LT [m] latches the individual designation signal Sd [m] supplied to the transfer circuit SR [m] at the timing when the pulse PlsL of the latch signal LAT rises to a high level. Further, the decoder DC [m] generates a connection state designation signal SL [m] according to FIG. 13 based on the individual designation signal Sd [m], the latch signal LAT, and the change signal CNG.

<< 6. Conclusion of embodiment >>
In general, the drive signal Com for driving the ejection unit D is a signal having a large amplitude, and the drive signal generation circuit 8 generates heat when generating the drive signal Com. In particular, in the drive signal generation circuit 8,
The amount of heat generated from the transistors Tr [1] and Tr [2], which play a role of amplifying the signal, increases. That is, in the drive signal generation circuit 8, the transistors Tr [1] and Tr [2] are formed on the substrate 200.
There is a high possibility of high temperatures compared to other components formed on top.
In contrast, in the present embodiment, the substrate 200 is interposed between the transistors Tr [1] and Tr [2].
A screw hole HL for inserting a screw for fixing the frame to the frame is provided. Therefore, in the present embodiment, heat generated from the transistors Tr [1] and Tr [2] can be radiated to the frame via the screw holes HL and the screws inserted into the screw holes HL. Thereby, in this embodiment, compared with the case where the screw hole HL is not provided between the transistors Tr [1] and Tr [2],
The temperature of the drive signal generation circuit 8 can be kept low, and the possibility of occurrence of problems due to the drive signal generation circuit 8 becoming high temperature can be kept low.

In general, in a transistor, the amount of heat generated at the drain is larger than the amount of heat generated at the source and gate.
In contrast, in this embodiment, the pad Pd3 electrically connected to the drain electrode EnD [1] of the transistor Tr [1] and the drain electrode EnD [2] of the transistor Tr [2] are electrically connected. A screw hole HL is provided at a position between the pad Pd6 and the expression (6) to (9). Therefore, in the present embodiment, heat generated from the transistors Tr [1] and Tr [2] can be efficiently radiated to the frame through the screw holes HL and the screws inserted into the screw holes HL.

Further, in the present embodiment, as is clear from the formula (1), the formula (2), the formula (10), the formula (11), and the like, the screw hole HL is arranged more than the transistor Tr [1] and the control section 6. Provided at a position close to Tr [2]. For this reason, in this embodiment, compared with the case where the screw hole HL is provided at a position closer to the control unit 6 than the transistors Tr [1] and Tr [2], the transistors Tr [1] and Tr [2] The generated heat can be efficiently radiated, and the heat generated from the transistors Tr [1] and Tr [2] can be prevented from propagating to the control unit 6.

Further, in this embodiment, as is clear from the equations (3), (4), (12), (13), etc., the diameter Wr of the screw hole HL is set to the screw hole HL and the pads Pd3, Pd6. Is larger than the distances W3 and W6. For this reason, compared with the case where the diameter Wr of the screw hole HL is smaller than the distances W3 and W6, heat generated from the transistors Tr [1] and Tr [2] can be efficiently radiated.

<< B. Modification >>
Each of the above forms can be variously modified. Specific modifications are exemplified below. Two or more aspects arbitrarily selected from the following examples can be appropriately combined within a range that does not contradict each other. In addition, about the element which an effect | action and a function are equivalent to embodiment in the modification illustrated below, the code | symbol referred by the above description is diverted and each detailed description is abbreviate | omitted suitably.

<< Modification 1 >>
In the embodiment described above, one screw hole HL is provided between the transistors Tr [1] and Tr [2]. However, the present invention is not limited to such a mode, and the transistor Tr [ A plurality of screw holes HL may be provided between 1] and Tr [2].
FIG. 15 is a diagram illustrating an example of a wiring pattern on the substrate 200 provided in the inkjet printer 1 according to the present modification. As shown in FIG. 15, in this modification, the substrate 200 is
Two screw holes HL1 and HL2 are provided between the transistors Tr [1] and Tr [2]. Each of the screw holes HL1 and HL2 includes at least the expressions (1) to (2) and the expression (6) described above.
To the expression (11), preferably, the above-described expressions (1) to (4),
It is provided so that Formula (6)-Formula (13) may be satisfy | filled, More preferably, Formula (1)-mentioned above is carried out.
It is provided so as to satisfy all of Expression (15).
According to this modification, since the plurality of screw holes HL are provided between the transistors Tr [1] and Tr [2], heat generated from the transistors Tr [1] and Tr [2] is efficiently radiated. be able to.

<< Modification 2 >>
In the embodiment and the modification described above, the inkjet printer 1 includes one drive signal generation circuit 8 and one head unit HU. However, the present invention is not limited to such an aspect, and the inkjet printer 1 The printer 1 may include a plurality of drive signal generation circuits 8 or a plurality of head units HU.
For example, the inkjet printer 1 may drive the discharge unit D by selectively supplying a plurality of drive signals Com having different waveforms to the discharge units D included in the head unit HU. In this case, the substrate 200 may be provided with a plurality of drive signal generation circuits 8 so as to correspond to the plurality of drive signals Com on a one-to-one basis.
For example, the inkjet printer 1 may include a plurality of head units HU. In this case, the substrate 200 may be provided with a plurality of drive signal generation circuits 8 so as to correspond one-to-one with the plurality of head units HU, for example.
In the present modification, when a plurality of drive signal generation circuits 8 are provided on the substrate 200, one or more of the transistors Tr [1] and Tr [2] included in each drive signal generation circuit 8 are provided. A screw hole HL is preferably provided.

<< Modification 3 >>
In the embodiment and the modification described above, the control unit 6 and the drive signal generation circuit 8 are provided on the same substrate 200. However, the present invention is not limited to such a mode, and the drive signal generation circuit 8 is provided. May be provided on a board (another example of “circuit board”) different from the board on which the control unit 6 is provided.

<< Modification 4 >>
In the embodiment and the modification described above, it is assumed that the ink jet printer 1 is a serial printer. However, the present invention is not limited to such a mode, and the ink jet printer 1 includes a plurality of recording heads HD. A so-called line printer may be used in which the nozzles N are provided so as to extend wider than the width of the recording paper P.

DESCRIPTION OF SYMBOLS 1 ... Inkjet printer, 2 ... Control module, 6 ... Control part, 7 ... Conveyance mechanism, 8
... Drive signal generation circuit, 9 ... Storage section, 10 ... Supply circuit, 80 ... LSI, 81 ... Amplifier circuit, 8
2 ... LPF, 200 ... substrate, D ... discharge portion, HD ... recording head, HU ... head unit, HL
... Screw holes, Pd1 ... Pad, Pd2 ... Pad, Pd3 ... Pad, Pd4 ... Pad, Pd5 ... Pad,
Pd6 ... pad, Tr [1] ... transistor, Tr [2] ... transistor.

Claims (8)

A head unit driven by a drive signal and capable of discharging liquid;
A circuit board;
A drive signal generation circuit provided on the circuit board for generating the drive signal;
With
The drive signal generation circuit includes:
A modulation unit that generates a modulation signal by pulse-modulating a waveform defining signal that defines the waveform of the drive signal;
An amplifying unit comprising a first transistor and a second transistor, and amplifying the modulated signal by the first transistor and the second transistor to generate an amplified signal;
A smoothing unit that smoothes the amplified signal to generate the drive signal;
With
In the circuit board,
A screw hole is provided between the first transistor and the second transistor;
A liquid discharge apparatus characterized by that. The first transistor and the second transistor are field effect transistors,
The liquid ejecting apparatus according to claim 1, wherein the liquid ejecting apparatus is a liquid ejecting apparatus. On the circuit board,
A first pad electrically connected to a source electrode of the first transistor;
A second pad electrically connected to the gate electrode of the first transistor;
A third pad electrically connected to the drain electrode of the first transistor;
Is provided,
The distance between the screw hole and the first pad is:
Longer than the distance between the screw hole and the third pad,
The distance between the screw hole and the second pad is
Longer than the distance between the screw hole and the third pad,
The liquid ejecting apparatus according to claim 1, wherein the liquid ejecting apparatus is a liquid ejecting apparatus. The diameter of the screw hole is
Greater than the distance between the screw hole and the third pad;
The liquid ejecting apparatus according to claim 3, wherein the liquid ejecting apparatus is a liquid ejecting apparatus. On the circuit board,
A fourth pad electrically connected to the source electrode of the second transistor;
A fifth pad electrically connected to the gate electrode of the second transistor;
A sixth pad electrically connected to the drain electrode of the second transistor;
Is provided,
The distance between the screw hole and the fourth pad is:
Longer than the distance between the screw hole and the sixth pad,
The distance between the screw hole and the fifth pad is
Longer than the distance between the screw hole and the sixth pad,
The liquid ejection apparatus according to claim 1, wherein the liquid ejection apparatus is a liquid ejection apparatus according to claim 1. The diameter of the screw hole is
Greater than the distance between the screw hole and the sixth pad;
The liquid ejecting apparatus according to claim 5, wherein the liquid ejecting apparatus is a liquid ejecting apparatus. The circuit board is
It is fixed to the frame of the liquid ejection device by screws inserted into the screw holes.
The liquid ejection apparatus according to claim 1, wherein the liquid ejection apparatus is a liquid ejection apparatus according to claim 1. The first transistor is:
A first package provided on the circuit board;
A first semiconductor chip provided between the first package and the circuit board;
With
The second transistor is
A second package provided on the circuit board;
A second semiconductor chip provided between the second package and the circuit board;
Comprising
The liquid ejection apparatus according to claim 1, wherein the liquid ejection apparatus is a liquid ejection apparatus according to claim 1.

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