JP2018152444A - Semiconductor device and manufacturing method for the same - Google Patents

Semiconductor device and manufacturing method for the same Download PDF

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JP2018152444A
JP2018152444A JP2017046965A JP2017046965A JP2018152444A JP 2018152444 A JP2018152444 A JP 2018152444A JP 2017046965 A JP2017046965 A JP 2017046965A JP 2017046965 A JP2017046965 A JP 2017046965A JP 2018152444 A JP2018152444 A JP 2018152444A
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substrate
layer
alloy layer
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山崎　一寿
Kazuhisa Yamazaki
一寿 山崎
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To alloy an electrode and a solder layer appropriately.SOLUTION: A semiconductor device comprises: a first substrate 10a and a second substrate 10b; and connection terminals 14 for connecting the first substrate and the second substrate, which includes electrodes 12a, 12b which are provided at least on one surfaces of the first substrate and the second substrate, respectively, and consist chiefly of Cu, first alloy layers 22a, 22b which are provided on the electrodes, respectively, and consist chiefly of Cu and Ni, second alloy layers 24a, 24b which are provided on the first alloy layers, respectively, and consist chiefly of Ni and Sn, and third alloy layers 26a, 26b which are provided on the second alloy layers, respectively, and consist chiefly of Cu and Sn.SELECTED DRAWING: Figure 10

Description

本発明は、半導体装置およびその製造方法に関し、電極と半田とが接合する半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and relates to a semiconductor device in which an electrode and solder are joined and a manufacturing method thereof.

銅電極と半田層とを接合させることで、基板同士を接合する方法が用いられている。Ｃｕ（銅）電極とＳｎ(錫)含有半田との間にＮｉ（ニッケル）層またはＰ（リン）またはＢ（ホウ素）を含むＮｉＣｕ層を設け、リフローすることでＣｕ電極とＳｎ含有半田とを接合させることが知られている（例えば特許文献１）。   A method of bonding substrates together by bonding a copper electrode and a solder layer is used. A Ni (nickel) layer or a NiCu layer containing P (phosphorus) or B (boron) is provided between the Cu (copper) electrode and the Sn (tin) -containing solder, and the Cu electrode and the Sn-containing solder are reflowed. It is known to join (for example, Patent Document 1).

特開２００７−５９９３７号公報JP 2007-59937 A

Ｃｕ電極とＳｎ含有半田層とは、間に合金層が形成されることにより電流密度耐性が向上する。しかし、電極の酸化防止のため電極と半田層との間にＮｉ層を設けると、Ｎｉの半田への拡散速度が遅く、合金層が形成され難い。また、電極と半田層との間にＰまたはＢを含むＮｉＣｕ層を設けると、接合部にＰまたはＢが残存し、合金層が形成され難い。合金層が形成され難いと接合部の電流密度耐性が低くなる。   The current density resistance is improved by forming an alloy layer between the Cu electrode and the Sn-containing solder layer. However, if an Ni layer is provided between the electrode and the solder layer to prevent oxidation of the electrode, the diffusion rate of Ni into the solder is slow and it is difficult to form an alloy layer. In addition, when a NiCu layer containing P or B is provided between the electrode and the solder layer, P or B remains at the joint and it is difficult to form an alloy layer. If the alloy layer is difficult to be formed, the current density resistance of the joint is reduced.

本発明は、電極と半田層とを適切に合金化することを目的とする。   An object of the present invention is to appropriately alloy an electrode and a solder layer.

１つの態様では、半導体装置は、第１基板および第２基板と、前記第１基板および前記第２基板の少なくとも一方の表面上に設けられたＣｕを主成分とする電極と、前記電極上に設けられ、ＣｕとＮｉとを主成分とする第１合金層と、前記第１合金層上に設けられ、ＮｉとＳｎとを主成分とする第２合金層と、前記第２合金層上に設けられＣｕとＳｎとを主成分とする第３合金層と、を備え、前記第１基板と前記第２基板とを接続する接続端子と、を具備する。   In one aspect, a semiconductor device includes: a first substrate; a second substrate; an electrode having Cu as a main component provided on at least one surface of the first substrate and the second substrate; and A first alloy layer comprising Cu and Ni as main components; a second alloy layer comprising Ni and Sn as main components provided on the first alloy layer; and the second alloy layer. And a third alloy layer mainly composed of Cu and Sn, and a connection terminal for connecting the first substrate and the second substrate.

また、１つの態様では、半導体装置は、基板と、前記基板の表面上に設けられたＣｕを主成分とする電極と、前記電極上に設けられ、ＣｕとＮｉとを主成分とする合金層と、前記合金層上に設けられＳｎ合金を主成分とする半田層と、を具備する。   In one aspect, a semiconductor device includes a substrate, an electrode mainly composed of Cu provided on a surface of the substrate, and an alloy layer mainly formed of Cu and Ni provided on the electrode. And a solder layer provided on the alloy layer and containing a Sn alloy as a main component.

また、１つの態様では、半導体装置の製造方法は、半田層が第１基板と第２基板との間に設けられ、前記第１基板および前記第２基板の少なくとも一方の表面上に設けられたＣｕを主成分とする電極と前記半田層との間にＣｕとＮｉとを主成分とする第１合金層が設けられるように、前記第１基板上に前記第２基板を配置し、前記第１基板および前記第２基板を熱処理することで、前記第１基板と前記第２基板とを接合する。   In one embodiment, a method for manufacturing a semiconductor device includes a solder layer provided between a first substrate and a second substrate, and provided on at least one surface of the first substrate and the second substrate. The second substrate is disposed on the first substrate such that a first alloy layer mainly composed of Cu and Ni is provided between the electrode mainly composed of Cu and the solder layer. One substrate and the second substrate are heat-treated to join the first substrate and the second substrate.

１つの側面として、電極と半田層とを適切に合金化することができる。   As one aspect, the electrode and the solder layer can be appropriately alloyed.

図１（ａ）および図１（ｂ）は、比較例１に係る半導体装置の製造方法を示す断面図である。1A and 1B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 1. FIG. 図２（ａ）および図２（ｂ）は、比較例１におけるリフロー前後の半田層および電極付近の断面図である。2A and 2B are cross-sectional views of the vicinity of the solder layer and the electrode before and after reflow in Comparative Example 1. FIG. 図３（ａ）および図３（ｂ）は、比較例１における接合部断面の反射電子像を示す画像およびその模式図である。FIG. 3A and FIG. 3B are an image and a schematic diagram showing a backscattered electron image of a junction section in Comparative Example 1. FIG. 図４（ａ）および図４（ｂ）は、比較例２におけるリフロー前後の半田層および電極付近の断面図である。4A and 4B are cross-sectional views of the vicinity of the solder layer and the electrodes before and after reflow in Comparative Example 2. FIG. 図５（ａ）および図５（ｂ）は、比較例１における接合部断面の反射電子像を示す画像およびその模式図である。FIG. 5A and FIG. 5B are an image and a schematic diagram showing a backscattered electron image of a junction section in Comparative Example 1. FIG. 図６（ａ）は、実施例１におけるリフロー前の半田層および電極付近の断面図、図６（ｂ）および図６（ｃ）は、リフロー後の半田層および電極付近の断面図である。6A is a cross-sectional view of the vicinity of the solder layer and the electrode before reflowing in Example 1, and FIGS. 6B and 6C are cross-sectional views of the solder layer and the vicinity of the electrode after reflowing. 図７（ａ）および図７（ｂ）は、実施例１における接合部断面の反射電子像を示す画像およびその模式図である。FIG. 7A and FIG. 7B are an image and a schematic diagram showing a backscattered electron image of a junction cross section in the first embodiment. 図８（ａ）および図８（ｂ）は、実施例１に係る半導体装置の製造方法を示す断面図（その１）である。8A and 8B are cross-sectional views (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図９（ａ）から図９（ｃ）は、実施例１に係る半導体装置の製造方法を示す断面図（その２）である。FIG. 9A to FIG. 9C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図１０（ａ）および図１０（ｂ）は、実施例１に係る半導体装置の製造方法を示す断面図（その３）である。FIG. 10A and FIG. 10B are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図１１は、実施例２に係る半導体装置の断面図である。FIG. 11 is a cross-sectional view of the semiconductor device according to the second embodiment.

［比較例１］
図１（ａ）および図１（ｂ）は、比較例１に係る半導体装置の製造方法を示す断面図である。図１（ａ）に示すように、基板１０ａの上面に電極１２ａが設けられている。基板１０ｂの下面に電極１２ｂが設けられている。基板１０ａおよび１０ｂは、絶縁基板である。電極１２ａおよび１２ｂは、Ｃｕ電極であり、Ｃｕを主成分とする電極である。電極１２ｂの先端に半田層２０が設けられている。半田層２０はＳｎ合金を主成分とする。なお、ある元素（例えばＣｕ）を主成分とするとは、本願の作用効果が得られる程度にある元素を含むことであり、例えばある元素以外の元素はある元素の原子％以上含まないことである。以下の比較例および実施例についても同様である。 [Comparative Example 1]
1A and 1B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 1. FIG. As shown in FIG. 1A, an electrode 12a is provided on the upper surface of the substrate 10a. An electrode 12b is provided on the lower surface of the substrate 10b. The substrates 10a and 10b are insulating substrates. The electrodes 12a and 12b are Cu electrodes, and are electrodes mainly composed of Cu. A solder layer 20 is provided at the tip of the electrode 12b. The solder layer 20 is mainly composed of Sn alloy. It should be noted that a certain element (for example, Cu) as a main component means that an element is present to such an extent that the effect of the present application can be obtained. For example, an element other than a certain element does not include more than atomic% of the certain element. . The same applies to the following comparative examples and examples.

図１（ｂ）に示すように、半田層２０を電極１２ａの上面に接触させる。その後リフローする。これにより、半田層２０と電極１２ａおよび１２ｂとの間に合金層が形成される。合金層の形成により半田層２０と電極１２ａおよび１２ｂとが接合する。これにより、電極１２ａと１２ｂとが接合した接続端子１４が形成される。   As shown in FIG. 1B, the solder layer 20 is brought into contact with the upper surface of the electrode 12a. Then reflow. Thereby, an alloy layer is formed between the solder layer 20 and the electrodes 12a and 12b. The solder layer 20 and the electrodes 12a and 12b are joined by the formation of the alloy layer. Thereby, the connection terminal 14 in which the electrodes 12a and 12b are joined is formed.

電極１２ｂのようなＣｕピラーの先端に少量の半田層２０を設け、電極１２ａと接合することで、接続端子１４の微細化が可能となる。接続端子１４が微細化すると、接続端子１４を流れる電流密度が増加する。Ｓｎを含有する半田層２０に大きな電流密度の電流を長時間通電すると、接続端子１４が破損することがある。そこで、半田層２０と電極１２ａおよび１２ｂとの合金を形成する。半田層２０の多くが合金層となると、電流密度に対する耐性が向上する。   By providing a small amount of solder layer 20 at the tip of a Cu pillar such as the electrode 12b and joining the electrode 12a, the connection terminal 14 can be miniaturized. When the connection terminal 14 is miniaturized, the current density flowing through the connection terminal 14 increases. If a current having a large current density is passed through the solder layer 20 containing Sn for a long time, the connection terminal 14 may be damaged. Therefore, an alloy of the solder layer 20 and the electrodes 12a and 12b is formed. When many of the solder layers 20 are alloy layers, resistance to current density is improved.

図２（ａ）および図２（ｂ）は、比較例１におけるリフロー前後の半田層および電極付近の断面図である。電極１２ａと半田層２０との間または電極１２ｂと半田層２０との間を示している。以下の図も同様である。図２（ａ）に示すように、電極１２上に半田層２０が設けられている。図２（ｂ）に示すように、リフローすると、電極１２と半田層２０との間にＣｕとＳｎとの合金層３０が形成される。   2A and 2B are cross-sectional views of the vicinity of the solder layer and the electrode before and after reflow in Comparative Example 1. FIG. It shows between the electrode 12 a and the solder layer 20 or between the electrode 12 b and the solder layer 20. The same applies to the following figures. As shown in FIG. 2A, a solder layer 20 is provided on the electrode 12. As shown in FIG. 2B, when reflowing, an alloy layer 30 of Cu and Sn is formed between the electrode 12 and the solder layer 20.

図３（ａ）および図３（ｂ）は、比較例１における接合部断面の反射電子像を示す画像およびその模式図である。図３（ａ）中のバーの長さが５μｍに相当する。半田層２０はＡｇが２重量％のＳｎＡｇである。リフロー条件は以下である。まず、仮止めのためのリフローを、余熱を１４０℃から１６０℃で１２０秒行い、その後２４０℃から２５０℃がピークとなるように１０秒行った。次に本接合のためのリフローを、余熱を１４０℃から１６０℃で１２０秒行い、その後２６０℃から２８０℃がピークとなるように６０秒行った。反射電子像は平均原子量が大きいと明るく、平均原子量が小さいと暗くなる。図３（ａ）および図３（ｂ）に示すように、電極１２は、主にＣｕを含むため平均原子量が小さく暗い。半田層２０は、主にＳｎを含むため平均原子量が大きく明るい。電極１２と半田層２０との間に形成された合金層３０は、ＣｕとＳｎを含むため、電極１２と半田層２０の間の明るさである。ＥＰＭＡ（Electron Probe Micro Analysis）法を用いて分析した。合金層３０内の半田層２０側ではＣｕ６Ｓｎ５合金が多く、合金層３０内の電極１２側ではＣｕ３Ｓｎ合金が多い。 FIG. 3A and FIG. 3B are an image and a schematic diagram showing a backscattered electron image of a junction section in Comparative Example 1. FIG. The length of the bar in FIG. 3A corresponds to 5 μm. The solder layer 20 is SnAg with 2 wt% Ag. The reflow conditions are as follows. First, reflow for temporary fixing was performed at 140 to 160 ° C. for 120 seconds, followed by 10 seconds so that 240 to 250 ° C. peaked. Next, reflow for the main joining was performed at 140 to 160 ° C. for 120 seconds, followed by 60 seconds so that 260 to 280 ° C. peaked. The reflected electron image is bright when the average atomic weight is large, and dark when the average atomic weight is small. As shown in FIG. 3A and FIG. 3B, the electrode 12 mainly contains Cu, so that the average atomic weight is small and dark. Since the solder layer 20 mainly contains Sn, the average atomic weight is large and bright. Since the alloy layer 30 formed between the electrode 12 and the solder layer 20 contains Cu and Sn, the brightness is between the electrode 12 and the solder layer 20. Analysis was performed using an EPMA (Electron Probe Micro Analysis) method. There are many Cu 6 Sn 5 alloys on the solder layer 20 side in the alloy layer 30, and many Cu 3 Sn alloys on the electrode 12 side in the alloy layer 30.

ＣｕはＳｎとの間の拡散速度が速い。このため、リフローによりＣｕが半田層２０に内に拡散し厚い合金層３０が形成される。合金層３０としては抵抗の低いＣｕ３Ｓｎ合金が形成されることが好ましい。 Cu has a high diffusion rate with Sn. Therefore, Cu is diffused into the solder layer 20 by reflow to form a thick alloy layer 30. As the alloy layer 30, a Cu 3 Sn alloy having low resistance is preferably formed.

比較例１では、半田層２０にＣｕが拡散し合金層３０を形成する。これにより、電流密度の大きな電流を長時間通電しても接続端子１４が破壊することを抑制できる。しかしながら、Ｃｕは酸化し易い。例えば電極１２の形成工程および／または半田層２０の形成工程において、電極１２の表面が酸化される。酸化したＣｕは半田濡れ性が悪い。このため、電極１２と半田層２０との間に合金層３０が形成され難くなり、接合不良となってしまう。   In Comparative Example 1, Cu diffuses into the solder layer 20 to form the alloy layer 30. Thereby, it is possible to suppress the connection terminal 14 from being broken even when a current having a large current density is applied for a long time. However, Cu is easily oxidized. For example, in the step of forming the electrode 12 and / or the step of forming the solder layer 20, the surface of the electrode 12 is oxidized. Oxidized Cu has poor solder wettability. For this reason, it becomes difficult to form the alloy layer 30 between the electrode 12 and the solder layer 20, resulting in poor bonding.

［比較例２］
そこで、電極１２の表面に酸化し難く半田の濡れ性がよいＮｉ層を設ける。図４（ａ）および図４（ｂ）は、比較例２におけるリフロー前後の半田層および電極付近の断面図である。図４（ａ）に示すように、電極１２と半田層２０との間にＮｉ層３２を設ける。図４（ｂ）に示すように、リフローすると、Ｎｉ層３２と半田層２０との間にＮｉとＳｎとの合金層３４が形成される。 [Comparative Example 2]
Therefore, a Ni layer that hardly oxidizes and has good solder wettability is provided on the surface of the electrode 12. 4A and 4B are cross-sectional views of the vicinity of the solder layer and the electrodes before and after reflow in Comparative Example 2. FIG. As shown in FIG. 4A, a Ni layer 32 is provided between the electrode 12 and the solder layer 20. As shown in FIG. 4B, when reflowing, an alloy layer 34 of Ni and Sn is formed between the Ni layer 32 and the solder layer 20.

図５（ａ）および図５（ｂ）は、比較例１における接合部断面の反射電子像を示す画像およびその模式図である。半田層２０はＡｇが２重量％のＳｎＡｇであり、リフロー条件は比較例１と同じである。図５（ａ）および図５（ｂ）に示すように、Ｎｉ層３２と半田層２０との間にＮｉとＳｎを含む合金層３４が形成されている。合金層３４は図３の合金層３０に比べ薄い。   FIG. 5A and FIG. 5B are an image and a schematic diagram showing a backscattered electron image of a junction section in Comparative Example 1. FIG. The solder layer 20 is SnAg with 2 wt% Ag, and the reflow conditions are the same as in Comparative Example 1. As shown in FIGS. 5A and 5B, an alloy layer 34 containing Ni and Sn is formed between the Ni layer 32 and the solder layer 20. The alloy layer 34 is thinner than the alloy layer 30 of FIG.

比較例２では、電極１２の表面にＮｉ層３２を設けることで、電極１２の酸化を抑制することができる。しかしながら、ＮｉはＳｎ内への拡散速度が遅い。このため、合金層３４が形成され難く、合金層３４は薄い。よって、通電に対する耐性が低くなってしまう。   In Comparative Example 2, oxidation of the electrode 12 can be suppressed by providing the Ni layer 32 on the surface of the electrode 12. However, Ni has a slow diffusion rate into Sn. For this reason, the alloy layer 34 is difficult to be formed, and the alloy layer 34 is thin. Therefore, the resistance to energization is lowered.

また、比較例２のＮｉ層３２の代わりにＰまたはＢを含有するＮｉＣｕ層を用いると、ＰまたはＢがＣｕの半田層２０内への拡散を抑制する。よって、合金層が形成され難くなる。例えば、Ｎｉ層またはＮｉＣｕ層を無電解メッキ法を用い形成すると、ＮＩ層またはＮｉＣｕ層内にＰが含有してしまう。   When a NiCu layer containing P or B is used instead of the Ni layer 32 of Comparative Example 2, P or B suppresses diffusion of Cu into the solder layer 20. Therefore, it becomes difficult to form an alloy layer. For example, when a Ni layer or a NiCu layer is formed using an electroless plating method, P is contained in the NI layer or the NiCu layer.

実施例１では、電極１２の表面に酸化し難く半田の濡れ性がよいＮｉＣｕ合金層を設ける。図６（ａ）は、実施例１におけるリフロー前の半田層および電極付近の断面図、図６（ｂ）および図６（ｃ）は、リフロー後の半田層および電極付近の断面図である。図６（ａ）に示すように、電極１２と半田層２０との間にＮｉＣｕ合金層２２を設ける。ＮｉＣｕ合金層２２はＮｉおよびＣｕを主成分とする合金層であり、ＰおよびＢは意図的には添加していない。ＮｉＣｕ合金層２２は電解メッキ法を用い形成する。   In Example 1, a NiCu alloy layer that hardly oxidizes and has good solder wettability is provided on the surface of the electrode 12. 6A is a cross-sectional view of the vicinity of the solder layer and the electrode before reflowing in Example 1, and FIGS. 6B and 6C are cross-sectional views of the solder layer and the vicinity of the electrode after reflowing. As shown in FIG. 6A, a NiCu alloy layer 22 is provided between the electrode 12 and the solder layer 20. The NiCu alloy layer 22 is an alloy layer mainly composed of Ni and Cu, and P and B are not intentionally added. The NiCu alloy layer 22 is formed using an electrolytic plating method.

図６（ｂ）に示すように、リフローすると、ＮｉＣｕ合金層２２と半田層２０との間にＮｉとＳｎとを主成分とするＮｉＳｎ合金層２４が形成される。ＮｉＳｎ合金層２４と半田層２０との間にＣｕＳｎ合金層２６が形成される。ＣｕＳｎ合金層２６はＮｉＳｎ合金層２４より厚い。図６（ｃ）のように、半田層２０が全て合金化することもある。   As shown in FIG. 6B, when the reflow is performed, a NiSn alloy layer 24 mainly composed of Ni and Sn is formed between the NiCu alloy layer 22 and the solder layer 20. A CuSn alloy layer 26 is formed between the NiSn alloy layer 24 and the solder layer 20. The CuSn alloy layer 26 is thicker than the NiSn alloy layer 24. As shown in FIG. 6C, the solder layer 20 may be entirely alloyed.

図７（ａ）および図７（ｂ）は、実施例１における接合部断面の反射電子像を示す画像およびその模式図である。半田層２０はＡｇが２重量％のＳｎＡｇであり、ＮｉＣｕ合金層２２はＮｉおよびＣｕが各々５０原子％のＮｉＣｕである。リフロー条件は比較例１と同じである。図７（ａ）および図７（ｂ）に示すように、ＮｉＣｕ合金層２２と半田層２０との間にＮｉＳｎ合金層２４およびＣｕＳｎ合金層２６が形成されている。ＣｕＳｎ合金層２６はＮｉＳｎ合金層２４より厚い。ＮｉＳｎ合金層２４およびＣｕＳｎ合金層２６をＥＰＭＡ法を用いて分析した。ＮｉＳｎ合金層２４は、ＮｉおよびＳｎを主成分とし、Ｃｕを微量に含む合金層である。ＮｉＳｎ合金層２４は例えば（Ｎｉ１−ｘＣｕｘ）３Ｓｎ４（ｘは０．０１から０．２）のような比率の合金と考えられる。ＣｕＳｎ合金層２６は例えば（Ｃｕ１−ｘＮｉｘ）６Ｓｎ５（ｘは０．０１から０．２）のような比率の合金と考えられる。ＣｕはＮｉに比べＳｎ内への拡散速度が速いためＮｉＣｕ合金層２２内のＣｕは半田層２０内に拡散しＣｕＳｎ合金層２６を形成する。ＮｉＣｕ合金層２２内のＮｉはＣｕより遅く拡散しＣｕＳｎ合金層２６とＮｉＣｕ合金層２２との間にＮｉＳｎ合金層２４を形成すると考えられる。 FIG. 7A and FIG. 7B are an image and a schematic diagram showing a backscattered electron image of a junction cross section in the first embodiment. The solder layer 20 is SnAg with 2 wt% Ag, and the NiCu alloy layer 22 is NiCu with 50 atomic% Ni and Cu respectively. The reflow conditions are the same as in Comparative Example 1. As shown in FIGS. 7A and 7B, a NiSn alloy layer 24 and a CuSn alloy layer 26 are formed between the NiCu alloy layer 22 and the solder layer 20. The CuSn alloy layer 26 is thicker than the NiSn alloy layer 24. The NiSn alloy layer 24 and the CuSn alloy layer 26 were analyzed using the EPMA method. The NiSn alloy layer 24 is an alloy layer containing Ni and Sn as main components and containing a small amount of Cu. The NiSn alloy layer 24 is considered to be an alloy having a ratio such as (Ni 1-x Cu x ) 3 Sn 4 (x is 0.01 to 0.2). The CuSn alloy layer 26 is considered to be an alloy having a ratio such as (Cu 1-x Ni x ) 6 Sn 5 (x is 0.01 to 0.2). Since Cu has a faster diffusion rate into Sn than Ni, Cu in the NiCu alloy layer 22 diffuses into the solder layer 20 to form a CuSn alloy layer 26. It is considered that Ni in the NiCu alloy layer 22 diffuses slower than Cu and forms a NiSn alloy layer 24 between the CuSn alloy layer 26 and the NiCu alloy layer 22.

実施例１では、電極１２の表面にＮｉＣｕ合金層２２を設けることで、電極１２の酸化を抑制することができる。ＮｉＣｕ合金層２２内のＣｕが半田層２０に拡散し厚いＣｕＳｎ合金層２６を形成するため、通電に対する耐性を向上できる。   In Example 1, the oxidation of the electrode 12 can be suppressed by providing the NiCu alloy layer 22 on the surface of the electrode 12. Since Cu in the NiCu alloy layer 22 diffuses into the solder layer 20 to form a thick CuSn alloy layer 26, resistance to energization can be improved.

図８（ａ）から図１０（ｂ）は、実施例１に係る半導体装置の製造方法を示す断面図である。図８（ａ）に示すように、基板１０ａ上に電極１２ａを形成する。図８（ｂ）に示すように、電極１２ａ上にＮｉＣｕ合金層２２ａを形成する。ＮｉＣｕ合金層２２ａは、例えば電解めっき法を用い形成する。図９（ａ）に示すように、基板１０ｂ上に電極１２ｂを形成する。図９（ｂ）に示すように、電極１２ｂ上にＮｉＣｕ合金層２２ｂを形成する。ＮｉＣｕ合金層２２ｂは、例えば電解めっき法を用い形成する。図９（ｃ）に示すように、ＮｉＣｕ合金層２２ｂ上に半田層２０を形成する。半田層２０は、例えば電解めっき法を用い形成する。   8A to 10B are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. As shown in FIG. 8A, the electrode 12a is formed on the substrate 10a. As shown in FIG. 8B, a NiCu alloy layer 22a is formed on the electrode 12a. The NiCu alloy layer 22a is formed using, for example, an electrolytic plating method. As shown in FIG. 9A, the electrode 12b is formed on the substrate 10b. As shown in FIG. 9B, a NiCu alloy layer 22b is formed on the electrode 12b. The NiCu alloy layer 22b is formed using, for example, an electrolytic plating method. As shown in FIG. 9C, the solder layer 20 is formed on the NiCu alloy layer 22b. The solder layer 20 is formed using, for example, an electrolytic plating method.

基板１０ａおよび１０ｂは例えば半導体素子を有するシリコン基板等の半導体基板、または樹脂基板もしくはセラミックス基板等の絶縁基板である。基板１０ａおよび１０ｂの少なくとも一方は半導体基板である。電極１２ａおよび１２ｂはＣｕを主成分とする銅電極である。電極１２ａおよび１２ｂの少なくとも一方はＣｕピラーでもよい。ＮｉＣｕ合金層２２ａおよび２２ｂはＮｉとＣｕを主成分とし、ＰまたはＢは意図的に添加されていない。ＮｉＣｕ合金層２２ａは例えば電解メッキ法を用い形成する。半田層２０はＳｎ合金を主成分とする。半田層２０は例えば電解メッキ法を用い形成する。Ｓｎ合金は、例えばＳｎＡｇ半田またはＳｎＡｇＣｕ半田である。ＳｎＡｇ半田には、Ａｇは例えば１重量％から３重量％含まれている。ＳｎＡｇＣｕ半田には、Ａｇは例えば１重量％から３重量％、Ｃｕは例えば０．５重量％含まれている。   The substrates 10a and 10b are, for example, a semiconductor substrate such as a silicon substrate having semiconductor elements, or an insulating substrate such as a resin substrate or a ceramic substrate. At least one of the substrates 10a and 10b is a semiconductor substrate. The electrodes 12a and 12b are copper electrodes mainly composed of Cu. At least one of the electrodes 12a and 12b may be a Cu pillar. The NiCu alloy layers 22a and 22b are mainly composed of Ni and Cu, and P or B is not intentionally added. The NiCu alloy layer 22a is formed using, for example, an electrolytic plating method. The solder layer 20 is mainly composed of Sn alloy. The solder layer 20 is formed using, for example, an electrolytic plating method. The Sn alloy is, for example, SnAg solder or SnAgCu solder. The SnAg solder contains, for example, 1 wt% to 3 wt% of Ag. The SnAgCu solder contains, for example, 1% to 3% by weight of Ag and 0.5% by weight of Cu, for example.

図１０（ａ）に示すように、ＮｉＣｕ合金層２２ａ上に半田層２０を接触させる。図１０（ｂ）に示すように、半田リフローを行う。これにより、電極１２ａおよび１２ｂと半田層２０との間に各々接合層２５ａおよび２５ｂが形成される。接合層２５ａ（または２５ｂ）は、ＮｉＣｕ合金層２２ａ（または２２ｂ）、ＮｉＳｎ合金層２４ａ（または２４ｂ）およびＣｕＳｎ合金層２６ａ（または２６ｂ）を含む。電極１２ａ、１２ｂ、接合層２５ａ、２５ｂおよび半田層２０により接続端子１４が形成される。   As shown in FIG. 10A, the solder layer 20 is brought into contact with the NiCu alloy layer 22a. As shown in FIG. 10B, solder reflow is performed. Thereby, bonding layers 25a and 25b are formed between the electrodes 12a and 12b and the solder layer 20, respectively. The bonding layer 25a (or 25b) includes a NiCu alloy layer 22a (or 22b), a NiSn alloy layer 24a (or 24b), and a CuSn alloy layer 26a (or 26b). The connection terminals 14 are formed by the electrodes 12a and 12b, the bonding layers 25a and 25b, and the solder layer 20.

半田リフローの熱処理温度は、例えば２６０℃から３００℃である。熱処理時間は例えば１０秒から５分である。図６（ｃ）のように、半田層２０は全て合金化されていてもよい。   The heat treatment temperature for solder reflow is, for example, 260 ° C. to 300 ° C. The heat treatment time is, for example, 10 seconds to 5 minutes. As shown in FIG. 6C, the solder layer 20 may be entirely alloyed.

実施例１によれば、図１０（ａ）のように、基板１０ａ（第１基板）上に基板１０ｂ（第２基板）を配置する。このとき、半田層２０が基板１０ａと基板１０ｂとの間に設けられ、電極１２ａおよび１２ｂと半田層２０との間にＮｉＣｕ合金層２２ａおよび２２ｂが設けられるようにする。その後、図１０（ｂ）のように、基板１０ａおよび１０ｂを熱処理することで、基板１０ａと１０ｂとを接合する。   According to the first embodiment, as shown in FIG. 10A, the substrate 10b (second substrate) is arranged on the substrate 10a (first substrate). At this time, the solder layer 20 is provided between the substrate 10a and the substrate 10b, and the NiCu alloy layers 22a and 22b are provided between the electrodes 12a and 12b and the solder layer 20. Thereafter, as shown in FIG. 10B, the substrates 10a and 10b are bonded together by heat-treating the substrates 10a and 10b.

これにより、電極１２ａおよび１２ｂ、ＮｉＣｕ合金層２２ａおよび２２ｂ（第１合金層）、ＮｉＳｎ合金層２４ａおよび２４ｂ（第２合金層）、並びにＣｕＳｎ合金層２６ａおよび２６ｂ（第３合金層）を備える接続端子１４が形成される。   Thereby, the connection comprising the electrodes 12a and 12b, the NiCu alloy layers 22a and 22b (first alloy layer), the NiSn alloy layers 24a and 24b (second alloy layer), and the CuSn alloy layers 26a and 26b (third alloy layer). Terminal 14 is formed.

ＮｉＣｕ合金層２２ａおよび２２ｂにより、電極１２ａおよび１２ｂの酸化が抑制される。よって、比較例１のような半田層２０と電極１２ａおよび１２ｂとの接合不良を抑制できる。ＮｉＣｕ合金層２２ａおよび２２ｂ内のＣｕが半田層２０に拡散し厚いＣｕＳｎ合金層２６を形成する。比較例２に比べ厚い合金層を形成できるため、電流密度が大きな電流の通電に対する耐性を向上できる。このように、電極１２ａおよび１２ｂと半田層２０とを適切に合金化することができる。   The NiCu alloy layers 22a and 22b suppress the oxidation of the electrodes 12a and 12b. Therefore, it is possible to suppress the bonding failure between the solder layer 20 and the electrodes 12a and 12b as in the first comparative example. Cu in the NiCu alloy layers 22a and 22b diffuses into the solder layer 20 to form a thick CuSn alloy layer 26. Since a thick alloy layer can be formed as compared with Comparative Example 2, it is possible to improve resistance to current application with a large current density. Thus, the electrodes 12a and 12b and the solder layer 20 can be appropriately alloyed.

ＮｉＣｕ合金層２２ａおよび２２ｂは、ＮｉＣｕ合金であり、例えばＣｕとＮｉ以外に意図的に添加された元素を含まない。ＮｉＣｕ合金層２２ａおよび２２ｂがＣｕおよびＮｉ以外元素を含むと、電極１２ａおよび１２ｂのＣｕが半田層２０に拡散することを抑制するためである。   The NiCu alloy layers 22a and 22b are NiCu alloys and do not contain, for example, elements intentionally added other than Cu and Ni. This is because when the NiCu alloy layers 22 a and 22 b contain elements other than Cu and Ni, Cu of the electrodes 12 a and 12 b is prevented from diffusing into the solder layer 20.

ＮｉＳｎ合金層２４ａおよび２４ｂは、Ｃｕを含み、Ｎｉの原子濃度はＣｕの原子濃度より大きくなる。また、ＣｕＳｎ合金層２６ａおよび２６ｂは、Ｎｉを含み、Ｃｕの原子濃度はＮｉの原子濃度より大きくなる。   The NiSn alloy layers 24a and 24b contain Cu, and the atomic concentration of Ni is larger than the atomic concentration of Cu. The CuSn alloy layers 26a and 26b contain Ni, and the atomic concentration of Cu is higher than the atomic concentration of Ni.

ＣｕＳｎ合金層２６ａと２６ｂとの間には半田層２０が残存してもよいし、半田層２０は全て合金化されていてもよい。   The solder layer 20 may remain between the CuSn alloy layers 26a and 26b, or the solder layer 20 may be entirely alloyed.

電極１２ａおよび１２ｂの両方をＣｕを主成分とする電極として説明したが、電極１２ａおよび１２ｂの少なくとも一方がＣｕを主成分とする電極であればよい。   Although both the electrodes 12a and 12b have been described as electrodes having Cu as a main component, at least one of the electrodes 12a and 12b may be an electrode having Cu as a main component.

ＮｉＣｕ合金層２２ａおよび２２ｂの酸化を抑制するため、ＮｉとＣｕに対するＣｕの原子組成比は、８０原子％以下が好ましく、６０原子％以下がより好ましい。ＣｕＳｎ合金層２６ａおよび２６ｂを形成するため、ＮｉとＣｕに対するＣｕの原子組成比は、３０原子％以上が好ましく、４０原子％以上がより好ましい。電極１２ａおよび１２ｂの酸化を抑制するため、ＮｉＣｕ合金層２２ａおよび２２ｂの膜厚は、０．１μｍ以上が好ましく、０．５μｍ以上がより好ましい。ＣｕＳｎ合金層２６ａおよび２６ｂの形成を促進するため、ＮｉＣｕ合金層２２ａおよび２２ｂの膜厚は、５μｍ以下が好ましく、３μｍ以下がより好ましい。   In order to suppress the oxidation of the NiCu alloy layers 22a and 22b, the atomic composition ratio of Cu to Ni and Cu is preferably 80 atomic% or less, and more preferably 60 atomic% or less. In order to form the CuSn alloy layers 26a and 26b, the atomic composition ratio of Cu to Ni and Cu is preferably 30 atomic% or more, and more preferably 40 atomic% or more. In order to suppress oxidation of the electrodes 12a and 12b, the thickness of the NiCu alloy layers 22a and 22b is preferably 0.1 μm or more, and more preferably 0.5 μm or more. In order to promote the formation of the CuSn alloy layers 26a and 26b, the thickness of the NiCu alloy layers 22a and 22b is preferably 5 μm or less, and more preferably 3 μm or less.

図１１は、実施例２に係る半導体装置の断面図である。図１１に示すように、回路基板１１ａ上に半田ボール２１を介し半導体チップ１１ｂがフリップチップ実装されている。回路基板１１ａの上面および半導体チップ１１ｂの下面には電極１２が設けられている。電極１２はＣｕ電極である。電極１２と半田ボール２１との間には接合層２５が形成されている。接合層２５は実施例１のＮｉＣｕ合金層２２、ＮｉＳｎ合金層２４およびＣｕＳｎ合金層２６を含む。   FIG. 11 is a cross-sectional view of the semiconductor device according to the second embodiment. As shown in FIG. 11, a semiconductor chip 11b is flip-chip mounted on a circuit board 11a via solder balls 21. Electrodes 12 are provided on the upper surface of the circuit board 11a and the lower surface of the semiconductor chip 11b. The electrode 12 is a Cu electrode. A bonding layer 25 is formed between the electrode 12 and the solder ball 21. The bonding layer 25 includes the NiCu alloy layer 22, the NiSn alloy layer 24, and the CuSn alloy layer 26 of Example 1.

半導体チップ１１ｂ上に半導体チップ１１ｃが接続端子１４を介し搭載されている。半導体チップ１１ｂを貫通し電極１２と電気的に接続する貫通電極１６が設けられている。半導体チップ１１ｃの下面に電極パッド１８が形成されている。貫通電極１６上および電極パッド１８下に電極１２が設けられている。電極１２間に半田層２０が設けられ、半田層２０と電極１２との間に接合層２５が設けられている。接合層２５は実施例１のＮｉＣｕ合金層２２、ＮｉＳｎ合金層２４およびＣｕＳｎ合金層２６を含む。電極１２、接合層２５および半田層２０は接続端子１４を形成する。   A semiconductor chip 11c is mounted on the semiconductor chip 11b via a connection terminal 14. A through electrode 16 that penetrates the semiconductor chip 11 b and is electrically connected to the electrode 12 is provided. Electrode pads 18 are formed on the lower surface of the semiconductor chip 11c. The electrode 12 is provided on the through electrode 16 and the electrode pad 18. A solder layer 20 is provided between the electrodes 12, and a bonding layer 25 is provided between the solder layer 20 and the electrodes 12. The bonding layer 25 includes the NiCu alloy layer 22, the NiSn alloy layer 24, and the CuSn alloy layer 26 of Example 1. The electrode 12, the bonding layer 25, and the solder layer 20 form the connection terminal 14.

実施例２のように、第１基板および第２基板はそれぞれ回路基板および半導体基板でもよい。第１基板および第２基板はともに半導体基板でもよい。   As in the second embodiment, the first substrate and the second substrate may be a circuit substrate and a semiconductor substrate, respectively. Both the first substrate and the second substrate may be semiconductor substrates.

以上、本発明の実施例について詳述したが、本発明は係る特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

なお、以上の説明に関して更に以下の付記を開示する。
（付記１）第１基板および第２基板と、前記第１基板および前記第２基板の少なくとも一方の表面上に設けられたＣｕを主成分とする電極と、前記電極上に設けられ、ＣｕとＮｉとを主成分とする第１合金層と、前記第１合金層上に設けられ、ＮｉとＳｎとを主成分とする第２合金層と、前記第２合金層上に設けられＣｕとＳｎとを主成分とする第３合金層と、を備え、前記第１基板と前記第２基板とを接続する接続端子と、を具備する半導体装置。
（付記２）前記第２合金層は、Ｃｕを含み、Ｎｉの原子濃度はＣｕの原子濃度より大きく、前記第３合金層は、Ｎｉを含み、Ｃｕの原子濃度はＮｉの原子濃度より大きい付記１記載の半導体装置。
（付記３）前記接続端子は、前記第３合金層上に設けられ、Ｓｎ合金を主成分とする半田層を備える付記１または２記載の半導体装置。
（付記４）前記半田層は、ＳｎＡｇ半田またはＳｎＡｇＣｕ半田である付記３記載の半導体装置。
（付記５）前記第１合金層は、ＣｕＮｉ合金である付記１から４のいずれか一項記載の半導体装置。
（付記６）基板と、前記基板の表面上に設けられたＣｕを主成分とする電極と、前記電極上に設けられ、ＣｕとＮｉとを主成分とする合金層と、前記合金層上に設けられＳｎ合金を主成分とする半田層と、を具備する半導体装置。
（付記７）前記合金層は、ＣｕＮｉ合金である付記６記載の半導体装置。
（付記８）前記半田層は、ＳｎＡｇ半田またはＳｎＡｇＣｕ半田である付記６または７記載の半導体装置。
（付記９）半田層が第１基板と第２基板との間に設けられ、前記第１基板および前記第２基板の少なくとも一方の表面上に設けられたＣｕを主成分とする電極と前記半田層との間にＣｕとＮｉとを主成分とする第１合金層が設けられるように、前記第１基板上に前記第２基板を配置する工程と、前記第１基板および前記第２基板を熱処理することで、前記第１基板と前記第２基板とを接合する工程と、を含む半導体装置の製造方法。
（付記１０）前記第１基板と前記第２基板とを接合する工程において、前記第１合金層上に、ＮｉとＳｎとを主成分とする第２合金層が形成され、前記第２合金層上にＣｕとＳｎとを主成分とする第３合金層が形成される付記９記載の半導体装置の製造方法。 In addition, the following additional notes are disclosed regarding the above description.
(Additional remark 1) The 1st board | substrate and 2nd board | substrate, the electrode which has Cu as a main component provided on the surface of at least one of the said 1st board | substrate and the said 2nd board | substrate, provided on the said electrode, Cu, A first alloy layer mainly composed of Ni, a second alloy layer mainly composed of Ni and Sn, and Cu and Sn disposed on the second alloy layer. And a third alloy layer containing as a main component, and a connection terminal for connecting the first substrate and the second substrate.
(Supplementary note 2) The second alloy layer contains Cu, the atomic concentration of Ni is larger than the atomic concentration of Cu, the third alloy layer contains Ni, and the atomic concentration of Cu is larger than the atomic concentration of Ni. 1. The semiconductor device according to 1.
(Additional remark 3) The said connection terminal is a semiconductor device of Additional remark 1 or 2 provided with the solder layer which is provided on the said 3rd alloy layer and has Sn alloy as a main component.
(Supplementary note 4) The semiconductor device according to supplementary note 3, wherein the solder layer is SnAg solder or SnAgCu solder.
(Supplementary note 5) The semiconductor device according to any one of supplementary notes 1 to 4, wherein the first alloy layer is a CuNi alloy.
(Appendix 6) A substrate, an electrode having Cu as a main component provided on the surface of the substrate, an alloy layer having Cu and Ni as main components provided on the electrode, and on the alloy layer And a solder layer comprising a Sn alloy as a main component.
(Supplementary note 7) The semiconductor device according to supplementary note 6, wherein the alloy layer is a CuNi alloy.
(Supplementary note 8) The semiconductor device according to supplementary note 6 or 7, wherein the solder layer is SnAg solder or SnAgCu solder.
(Supplementary note 9) A solder layer is provided between the first substrate and the second substrate, and the electrode mainly composed of Cu provided on at least one surface of the first substrate and the second substrate and the solder Disposing the second substrate on the first substrate such that a first alloy layer mainly composed of Cu and Ni is provided between the layers, and the first substrate and the second substrate. A method of manufacturing a semiconductor device, comprising: joining the first substrate and the second substrate by heat treatment.
(Supplementary Note 10) In the step of bonding the first substrate and the second substrate, a second alloy layer mainly composed of Ni and Sn is formed on the first alloy layer, and the second alloy layer The manufacturing method of a semiconductor device according to appendix 9, wherein a third alloy layer mainly composed of Cu and Sn is formed thereon.

１０ａ、１０ｂ 基板
１２、１２ａ、１２ｂ 電極
１４ 接続端子
２０ 半田層
２２、２２ａ、２２ｂ ＮｉＣｕ合金層
２４、２４ａ，２４ｂ ＮｉＳｎ合金層
２６、２６ａ、２６ｂ ＣｕＳｎ合金層
10a, 10b Substrate 12, 12a, 12b Electrode 14 Connection terminal 20 Solder layer 22, 22a, 22b NiCu alloy layer 24, 24a, 24b NiSn alloy layer 26, 26a, 26b CuSn alloy layer

Claims (6)

第１基板および第２基板と、
前記第１基板および前記第２基板の少なくとも一方の表面上に設けられたＣｕを主成分とする電極と、前記電極上に設けられ、ＣｕとＮｉとを主成分とする第１合金層と、前記第１合金層上に設けられ、ＮｉとＳｎとを主成分とする第２合金層と、前記第２合金層上に設けられＣｕとＳｎとを主成分とする第３合金層と、を備え、前記第１基板と前記第２基板とを接続する接続端子と、
を具備する半導体装置。 A first substrate and a second substrate;
An electrode mainly composed of Cu provided on at least one surface of the first substrate and the second substrate; a first alloy layer mainly composed of Cu and Ni provided on the electrode; A second alloy layer mainly formed of Ni and Sn provided on the first alloy layer, and a third alloy layer mainly formed of Cu and Sn provided on the second alloy layer; A connection terminal for connecting the first substrate and the second substrate;
A semiconductor device comprising: 前記第２合金層は、Ｃｕを含み、Ｎｉの原子濃度はＣｕの原子濃度より大きく、
前記第３合金層は、Ｎｉを含み、Ｃｕの原子濃度はＮｉの原子濃度より大きい請求項１記載の半導体装置。 The second alloy layer includes Cu, the atomic concentration of Ni is greater than the atomic concentration of Cu,
The semiconductor device according to claim 1, wherein the third alloy layer contains Ni, and an atomic concentration of Cu is higher than an atomic concentration of Ni. 前記接続端子は、前記第３合金層上に設けられ、Ｓｎ合金を主成分とする半田層を備える請求項１または２記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the connection terminal includes a solder layer that is provided on the third alloy layer and includes a Sn alloy as a main component. 基板と、
前記基板の表面上に設けられたＣｕを主成分とする電極と、前記電極上に設けられ、ＣｕとＮｉとを主成分とする合金層と、前記合金層上に設けられＳｎ合金を主成分とする半田層と、を具備する半導体装置。 A substrate,
An electrode having Cu as a main component provided on the surface of the substrate, an alloy layer having Cu and Ni as main components provided on the electrode, and an Sn alloy provided as a main component on the alloy layer And a solder layer. 前記合金層は、ＣｕＮｉ合金である請求項４記載の半導体装置。   The semiconductor device according to claim 4, wherein the alloy layer is a CuNi alloy. 半田層が第１基板と第２基板との間に設けられ、前記第１基板および前記第２基板の少なくとも一方の表面上に設けられたＣｕを主成分とする電極と前記半田層との間にＣｕとＮｉとを主成分とする第１合金層が設けられるように、前記第１基板上に前記第２基板を配置する工程と、
前記第１基板および前記第２基板を熱処理することで、前記第１基板と前記第２基板とを接合する工程と、
を含む半導体装置の製造方法。
A solder layer is provided between the first substrate and the second substrate, and between the solder layer and the electrode mainly composed of Cu provided on at least one surface of the first substrate and the second substrate. Disposing the second substrate on the first substrate such that a first alloy layer mainly composed of Cu and Ni is provided on the first substrate;
Bonding the first substrate and the second substrate by heat-treating the first substrate and the second substrate;
A method of manufacturing a semiconductor device including:
JP2017046965A 2017-03-13 2017-03-13 Semiconductor device and manufacturing method for the same Pending JP2018152444A (en)

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