JP2018148214A - Normally-off operating diamond power element and inverter using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a diamond power element operating in a normally-off mode.SOLUTION: A normally-off operating diamond power element includes a diamond field effect transistor 10 and an enhancement-type p channel field effect transistor 20 coupled to the diamond field effect transistor 10 in series, and the diamond field effect transistor 10 includes a drain electrode provided on a diamond substrate, a source electrode provided on the diamond substrate at a distance from the drain electrode, a hydrogenated layer provided on the surface of the diamond substrate between the drain electrode and the source electrode and having a carbon hydrogen bond, a gate insulating film covering the hydrogenated layer, and a gate electrode provided on the gate insulating film.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a normally-off operation diamond power element and an inverter using the same.

  Diamond is expected as a semiconductor material suitable for power devices that are required to operate under conditions of high voltage and large current. Various field effect transistors (FETs) using a diamond substrate have been proposed. In Patent Document 1, a surface of a diamond substrate is hydrogenated to generate a two-dimensional hole gas (2DHG: two-dimensional hole gas) layer directly under the hydrogenated layer, which is used as a channel layer of a field effect transistor. A diamond FET to be used has been proposed.

JP 2014-60377 A

By the way, since the 2DHG layer generated by hydrogenating the surface of the diamond substrate exists even when no gate voltage is applied, the diamond FET proposed in Patent Document 1 operates in a normally-on mode. From the viewpoint of reducing power consumption, safety, and applicability to existing circuits, the power element preferably operates in a normally-off mode, and a diamond power element that operates in a normally-off mode is desired.
This invention is made | formed in view of the said situation, and provides the diamond power element which operate | moves in normally-off mode, and an inverter using the same.

  A first aspect of the present invention includes a diamond field effect transistor and an enhancement type p-channel field effect transistor connected in series to the diamond field effect transistor. The diamond field effect transistor includes a drain electrode provided on a diamond substrate, and a drain electrode. A source electrode provided on the diamond substrate spaced apart from the source electrode, a hydrogenated layer having a carbon-hydrogen bond provided on the surface of the diamond substrate between the drain electrode and the source electrode, a gate insulating film covering the hydrogenated layer, and a gate A diamond power device including a gate electrode provided on an insulating film is provided.

  A second aspect of the present invention provides an inverter comprising the diamond power element of the first aspect and an n-channel field effect transistor connected in series to the diamond power element.

  According to the present invention, a diamond power element operating in a normally-off mode and an inverter using the same are provided.

1 is a circuit diagram of a diamond power element according to a first embodiment of the present invention. It is sectional drawing which shows typically the diamond field effect transistor of the diamond power element of this embodiment. It is an equivalent circuit diagram of a diamond field effect transistor when a gate voltage is applied. It is an equivalent circuit diagram of a diamond field effect transistor when no gate voltage is applied. It is a graph which shows the current-voltage characteristic of the diamond power element of this embodiment. It is a graph which shows the other current-voltage characteristic of the diamond power element of this embodiment. For comparison, it is a graph showing current-voltage characteristics of a diamond field effect transistor in the diamond power element of the present embodiment. It is a graph which shows the withstand voltage characteristic of the diamond power element of this embodiment. It is a circuit diagram which shows the inverter by the 2nd Embodiment of this invention. It is a graph which shows the operating characteristic of the inverter of this embodiment. 1 is a circuit diagram of a complementary inverter of the present invention according to Example 1. FIG. FIG. 6 is a circuit diagram of a complementary inverter according to the present invention relating to Example 2. (A) is a figure which shows the input voltage waveform input into the 2nd stage circuit of the complementary inverter of this invention, (b) is input into the 1st stage circuit of the complementary inverter of this invention. FIG. 6 is a diagram illustrating an input voltage waveform and an output voltage waveform output from a second-stage circuit.

  Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In all the accompanying drawings, the same or corresponding members or parts are denoted by the same or corresponding reference numerals, and redundant description is omitted.

(First embodiment)
Hereinafter, a diamond power device according to a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a circuit diagram of a diamond power element 1 according to the present embodiment. As shown in the figure, the diamond power element 1 includes a diamond field effect transistor (hereinafter referred to as diamond FET (Field Effect Transistor)) 10 and a p-channel field effect transistor (hereinafter referred to as p-FET) 20. The diamond FET 10 and the p-FET 20 are connected in series with each other. That is, the source 10 s of the diamond FET 10 is connected to the drain 20 d of the p-FET 20. The gate 10g of the diamond FET 10 is connected to the source 20s of the p-FET 20. That is, the diamond power element 1 of this embodiment includes a drain terminal D (corresponding to the drain terminal of the diamond FET 10), a source terminal S (corresponding to the source terminal of the p-FET 20), and a gate terminal G (gate terminal of the p-FET 20). 3 terminal element-like configuration.

  Next, the diamond FET 10 will be described. Referring to FIG. 2, the diamond FET 10 includes a drain electrode 12 provided on the substrate 11, a source electrode 13 provided on the substrate 11 apart from the drain electrode 12, and the substrate 11 between the drain electrode 12 and the source electrode 13. A hydrogenated layer 15 provided on the surface and having a carbon-hydrogen (C—H) bond, a gate insulating film 16 covering the hydrogenated layer 15, and a gate electrode 14 provided on the gate insulating film 16 are included. The gate insulating film 16 has a contact hole 17 above the drain electrode 12 and the source electrode 13, and the drain electrode 12 and the source electrode 13 are exposed upward through the contact hole 17. The gate electrode 14 is provided on the gate insulating film 16 between the drain electrode 12 and the source electrode 13.

  The substrate 11 is made of diamond. In the present embodiment, the substrate 11 includes a single crystal (Ib (001)) diamond substrate 11a and an undoped diamond layer 11b epitaxially grown on the surface thereof. The diamond layer 11b can be grown by, for example, microwave chemical vapor deposition (CVD). The thickness of the diamond layer 11b may be about 100 nm, for example.

  The drain electrode 12 has a titanium carbide (TiC) layer 12a, a titanium (Ti) layer 12b, and a gold (Au) layer 12c. The Ti layer 12b and the Au layer 12c can be formed by sequentially using, for example, a photolithography technique, a vapor deposition method, and a lift-off method. The TiC layer 12a can be formed, for example, by heating the substrate 11 after the formation of the Ti layer 12b and the Au layer 12c, and diffusing Ti constituting the Ti layer 12b into the diamond layer 11b immediately below the Ti layer 12b. The drain electrode 12 is ohmically connected to the diamond layer 11b by the TiC layer 12a.

  The source electrode 13 includes a TiC layer 13a, a Ti layer 13b, and an Au layer 13c. Since the layers 13 a to 13 c of the source electrode 13 are the same as the layers 12 a to 12 c of the drain electrode 12, detailed description thereof is omitted.

  The thicknesses of the Ti layers 12b and 13b and the Au layers 12c and 13c may be determined as appropriate. For example, the thickness of the Ti layers 12b and 13b may be in the range from 3 nm to 50 nm, and the thickness of the Au layers 12c and 13c may be in the range from 50 nm to 1 μm. Specifically, it is preferable that the Ti layers 12b and 13b have a thickness of about 30 nm, and the Au layers 12c and 13c have a thickness of about 100 nm.

  The hydrogenation layer 15 is formed on the surface of the diamond layer 11 b between the drain electrode 12 and the source electrode 13. In the hydrogenated layer 15, dangling bonds of carbon (C) atoms forming the diamond layer 11b are terminated by hydrogen (H) atoms (that is, C—H bonds are formed). The hydrogenation layer 15 induces a two-dimensional hole gas (2DHG: two-dimensional hole gas) layer (not shown) in the diamond layer 11b immediately below it. The 2DHG layer functions as a p-type channel layer of the diamond FET 10. Since the 2DHG layer exists even when no gate voltage is applied to the diamond FET 10, the diamond FET 10 functions as a depletion type element.

  The hydrogenation layer 15 can be formed as follows, for example. First, the surface of the diamond layer 11b is exposed to hydrogen plasma while the substrate 11 on which the drain electrode 12 and the source electrode 13 are formed is heated to, for example, 600 ° C. As a result, the entire surface of the diamond layer 11b is hydrogen-terminated except for the portion covered with the drain electrode 12 and the source electrode 13. Next, after covering a predetermined range including a region between the drain electrode 12 and the source electrode 13 with a photoresist mask, the diamond layer 11b is exposed to oxygen plasma. The surface of the region exposed to the oxygen plasma is oxidized and the C—H bond disappears, and the hydrogenated layer 15 is removed from this region. On the other hand, C—H bonds remain in the region covered with the photoresist mask, and when this photoresist mask is removed, a hydrogenated layer 15 having a predetermined size is obtained.

The gate insulating film 16 is made of alumina (Al ₂ O ₃ ). The gate insulating film 16 electrically insulates the gate electrode 14 from the hydrogenated layer 15 and also functions as a protective film for protecting the hydrogenated layer 15. Although the thickness of the gate insulating film 16 can be determined as appropriate, from the viewpoint of improving the breakdown voltage of the diamond FET 10, it is set to 50 nm or more, preferably 100 nm or more, and more preferably 400 nm or more.

Note that the gate insulating film 16 can be formed by an atomic layer deposition (ALD) method using trimethylaluminum (TMA) and vapor phase water (H ₂ O) as raw materials.

The gate electrode 14 is disposed on the gate insulating film 16 with a predetermined distance from each of the drain electrode 12 and the source electrode 13. The gate - drain spacing _{L GD,} the gate - source distance _{L GS,} the gate length _{L G,} which may be appropriately determined, the gate - drain distance _{L GD} is 1 to 30 [mu] m, the gate - source distance _{L GS} is 1 to 10 [mu] m, the gate the length _{L G} is preferably set to within the range of 1 to 20 [mu] m. The gate electrode 14 is made of, for example, aluminum (Al). The gate electrode 14 can be formed by sequentially using, for example, a photolithography technique, a vapor deposition method, and a lift-off method. The thickness of the gate electrode 14 may be about 0.5 μm, for example.

  The contact hole 17 is formed, for example, by forming a photoresist mask having openings above the drain electrode 12 and the source electrode 13 and removing the gate insulating film 16 exposed to the openings with tetramethylammonium hydroxide (TMAH). Is done. As a result, the drain electrode 12 and the source electrode 13 are exposed through the contact hole 17. The contact hole 17 is preferably formed before the gate electrode 14 is formed. According to this, when forming the gate electrode 14, Al is also deposited on the drain electrode 12 and the source electrode 13 exposed through the contact hole 17, and the deposited Al layer is used as a contact layer (not shown). can do.

The p-FET 20 (FIG. 1) is an enhancement type (normally off type) p-channel FET made of silicon (Si) in this embodiment. For example, the gate threshold voltage (Vth) is in a range from −0.8 V to −4 V, and the drain-source breakdown voltage (V _{(BR) DSS} ) is not limited to these. FETs in the range of −100V to −200V can be used. Specifically, commercially available FETs such as 2SJ410 manufactured by Renesas Technology and 2SJ380 manufactured by Toshiba may be used.

Next, the operation of the diamond power element 1 will be described with reference to FIGS. FIG. 3 shows an equivalent circuit of the diamond power element 1 when the gate voltage V _GS is applied. When the gate voltage V _GS (the gate terminal G is negative with respect to the source terminal S) is applied, the p-FET 20 (enhancement type) of the diamond power element 1 is turned on. 0V. The voltage Vab corresponds to the voltage between the gate and the source of the diamond FET 10 and becomes 0 V, so that the depletion type diamond FET 10 remains conductive. That is, when the gate voltage V _GS is applied, both the diamond FET 10 and the p-FET 20 are turned on, and the diamond power element 1 is turned on.

FIG. 4 shows an equivalent circuit of the diamond power element 1 when the gate voltage V _GS is not applied. In this case, the p-FET 20 is off and is equivalent to the capacitor 20c generated between the drain and the source. At this time, the drain voltage _{V DS} instantaneous current flows from the depletion type diamond FET10 to p-FET 20, capacitor 20c is charged. As a result, the voltage Vab becomes a positive voltage (based on b), and the gate-source voltage of the diamond FET 10 becomes -Vab. When this voltage exceeds the threshold voltage of diamond FET 10, diamond FET 10 is turned off. Therefore, when the gate voltage V _GS is not applied, the diamond power element 1 is turned off. That is, the diamond power element 1 operates in the normally-off mode.

  From the viewpoint of power consumption reduction, safety, and applicability to existing circuits, it is generally preferable that the power element operates in a normally-off mode. However, the diamond FET 10 is a depletion type as described above, and the diamond FET 10 alone is normally on. Operate in mode. On the other hand, according to the diamond power element 1 according to the present embodiment, a power element that operates in the normally-off mode while using the diamond FET 10 is provided.

Next, the measurement results of the electrical characteristics of the diamond power element 1 according to the present embodiment will be described. FIG. 5 is a graph showing an example of current-voltage characteristics (gate voltage-drain current characteristics) of the diamond power element 1. The main specifications of the diamond FET 10 in the diamond power element 1 used for the measurement are as follows.
Diamond substrate 11a thickness: 500 μm
Diamond layer 11b thickness: 500 nm
Ti layer 12b, 13b thickness: 30 nm
Au layers 12c and 13c thickness: 100 nm
Gate electrode 14 thickness: 100 nm
Gate insulating film 16 thickness: 200 nm
Gate width (width of hydrogenation layer 15): 25 μm
Gate-drain spacing L _GD : 5 μm
Gate length L _G : 4 μm
Gate-source distance L _GS : 2 μm

  Further, as the p-FET 20, the above-mentioned FET (2SJ380) manufactured by Toshiba Corporation was used, and this FET was connected to the diamond FET 10 as shown in FIG. The electrical characteristics were measured by using a vacuum chamber equipped with a prober and appropriately storing the diamond power element 1 in the chamber.

Referring to FIG. 5, it can be seen that even when the drain voltage V _DS (−10V) is applied, no current flows when the gate voltage V _GS is 0V. That is, it was also confirmed in actual measurement that the diamond power element 1 operates in the normally-off mode. Further, when the gate voltage V _GS becomes lower than about −0.9 V, the drain current I _DS rises steeply. That is, the threshold voltage of the diamond power element 1 is about −0.9 V, and this value substantially matches the standard value −0.8 V to −1.0 V of the p-FET 20 used. In addition, also when said SJ410 was used as p-FET20, the threshold voltage of the diamond power element 1 was settled in the range of the threshold voltage rating value of 2SJ410. From this result, it can be seen that the threshold voltage of the diamond power element 1 is determined by the threshold voltage of the p-FET 20.

In the graph of FIG. 5, the drain current _{I DS} is saturated at about -13mA / mm. This is because when the diamond power element 1 is on, the diamond FET 10 functions as a constant current source, and even if the gate voltage of the p-FET 20 increases, the current flowing into the p-FET 20 is constant.

Next, the current-voltage characteristics (drain voltage-drain current characteristics) of the diamond power element 1 will be described with reference to FIG. FIG. 6 shows the result of measuring the drain current I _DS while changing the drain voltage V _DS from 0V to −30V. At this time, the gate voltage V _GS was changed to -1.2 V in increments of -0.02 V using the parameter as a parameter. As the drain voltage V _DS increases in the negative direction, the drain current I _DS also increases. When the drain current I _DS is V _GS = −1.2 V and V _DS = −30 V, it is about −20. The current was 8 mA / mm. Thereby, it was confirmed that the diamond power element 1 can be used as a power element. In this graph as well, the drain current _IDS is saturated, and particularly when the gate voltage _VGS is low, the drain current _IDS is saturated at a low value. This is because the current flowing through the p-FET 20 is limited by the gate voltage _{V GS.}

Next, for comparison, the current-voltage characteristics in the diamond FET 10 of the diamond power element 1 were measured. That is, the gate voltage V _gs applied between the gate 10g and the source 10s is changed while the drain voltage V _ds (−10 V) is applied between the drain (drain terminal D) and the source 10s of the diamond FET 10 in FIG. The drain current I _ds was measured. As shown in FIG. 7, even when the gate voltage V _gs is 0 V, a drain current of about −13 mA / mm flows. That is, it can be seen that the diamond FET 10 operates in the normally-on mode. By comparing this result with the result shown in FIG. 5, it is found that the diamond power element 1 according to the present embodiment operates in the normally-off mode while using the diamond FET 10 that operates in the normally-on mode.

Next, the withstand voltage characteristics of the diamond power element 1 will be described. FIG. 8 is a graph showing current-voltage characteristics when the gate voltage V _GS is not applied (that is, when off). In this graph, both the drain current _IDS and the gate current _IGS are plotted. As shown in this graph, even when the drain voltage V _DS is changed from 0 V to about −1.5 kV, the drain current I _DS is generally within a very low range from 10 ⁻⁸ A to 10 ⁻⁹ A, The current I _GS is generally within a very low range from 10 ⁻¹² A to 10 ⁻¹⁰ A. The dielectric breakdown occurred when the drain voltage V _DS was −1735 V. From this result, it can be seen that the diamond power element 1 can be suitably used as a high voltage power element.

Further, when the drain voltage V _DS is −200 V (gate voltage V _GS = 0 V), the voltage (voltage division) applied to each of the diamond FET 10 and the p-FET 20 is measured, and is applied to the p-FET 20. The voltage was -24.2V. In other words, the voltage applied to the p-FET20 is only about 12 percent of the drain voltage _{V DS.} Regarding the withstand voltage of the diamond power element 1, it was found that the diamond FET 10 plays a major role.

Even when applying the 1.7kV as the drain voltage V _DS, without p-FET 20 is destroyed, to work properly has been confirmed experimentally.

(Second Embodiment)
Next, the inverter according to the second embodiment will be described with reference to FIG. As illustrated, the inverter 100 includes a diamond power element 1 described above and an n-channel field effect transistor (hereinafter, n-FET) 30 having a drain connected to the drain terminal D (FIG. 1) of the diamond power element 1. And have. In other words, the inverter 100 is an inverter composed of the diamond power element 1 as a p-channel FET and the n-FET 30 as an n-channel FET. As the n-FET 30, a commercially available Si n-FET having a high withstand voltage can be used. Here, TK20A60 (manufactured by Toshiba) was used.

Further, in the inverter 100, the input terminal _{V in} is electrically connected to the gate of n-FET 30 and the gate terminal G of the diamond power element 1 (FIG. 1), the output terminal _{V out} is the diamond power devices 1 and n-FET 30 Conducted to drain.

Terminal V _dd to a predetermined voltage of the inverter 100 (for convenience of explanation, that voltage V) is applied to, in case where the ground terminal V _ss, when a voltage V is applied to the input terminal V _in, the diamond power element 1 is turned off The n-FET 30 is turned on. Therefore, the voltage at the output terminal _Vout is 0V. When no input voltage is applied to the input terminal V _in is diamond power element 1 is turned on, n-FET 30 is turned off. Therefore, the voltage V is output to the output terminal _Vout .

  FIG. 10 is a graph showing the operating characteristics of the inverter 100. In this graph, the solid line indicates the input voltage, and the broken line indicates the output voltage. It can be seen that when the input voltage is “low” (0 V), the output voltage is “high” (in this case, approximately 20 V), and when the input voltage is “high”, the output voltage is “low”. That is, it was confirmed that the inverter 100 operates as an inverter.

  The output voltage had a delay of about 215 ns when falling with respect to 1 ms per cycle. On the other hand, a delay DL of about 290 μs occurs during the rise. This delay DL is presumed to be caused by the fact that the gate length of the diamond FET 10 in the diamond power element 1 is smaller than the gate length of the n-FET 30. Adjustment of these is expected to reduce the delay DL.

  As described above, the diamond power element 1 functions as a high withstand voltage p-channel FET that operates in a normally-off mode. By using such a diamond power element 1 together with an n-FET 30 that operates in a normally-off mode with a high withstand voltage, an inverter 100 with a high withstand voltage is provided.

  Although the present invention has been described above with reference to some embodiments, the present invention is not limited to these embodiments and can be variously changed or modified.

  For example, in the above embodiment, the single crystal diamond substrate 11a is used, but a black polycrystalline diamond substrate may be used. In this case, a polycrystalline diamond layer may or may not be deposited on the surface.

  Moreover, in said embodiment, although Si-made FET was illustrated as p-FET20, you may use enhancement type p-FET comprised with the other material. For example, a p-channel FET composed of germanium (Ge) (including an FET employing Ge or SiGe as a channel layer) can be used, and a p-channel FET composed of a III-V group compound semiconductor is used as p. -You may use as FET20. For example, an FET having an indium gallium arsenide (InGaAs) layer as a channel layer may be used.

  In the diamond power element 1 according to the above embodiment, the gate 10g of the diamond FET 10 and the source 20s of the p-FET 20 are connected to each other, but each may be grounded.

  Furthermore, the n-FET 30 in the inverter 100 is not limited to a Si FET, and an n-FET made of other materials can be used. For example, an element using an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) n-FET may be used as the n-FET 30. Specifically, this element can have an AlGaN / GaN-based n-FET (depletion type) and an enhancement type n-FET. The source of the AlGaN / GaN n-FET and the drain of the enhancement type n-FET are connected, and the gate of the AlGaN / GaN n-FET and the source of the enhancement type n-FET are connected. Thus, this element operates in a normally-off mode. According to this, the diamond power element 1, the first n-channel field effect transistor made of a semiconductor containing gallium and nitrogen, and the enhancement type first connected in series to the first n-channel field effect transistor. An inverter including two n-channel field effect transistors and connected in series to the diamond power element 1 is provided.

  When such an element is used, the AlGaN / GaN-based n-FET may be formed on the substrate 11 on which the diamond FET 10 is formed.

[Example 1]
Embodiment 1 of the present invention will be described with reference to FIG. In the drawing, symbol D represents a drain, symbol S represents a source, and symbol G represents a gate.

  The complementary inverter 200 of the first embodiment includes a cascode p-FET 210 in which a depletion type diamond FET 211 and an enhancement type Si p-FET 212 are cascode-connected, a depletion type AlGaN / GaN n-FET 221 and an enhancement type Si. The drain of the cascode p-FET 210 and the drain of the cascode n-FET 220 are connected to each other so that the cascode n-FET 220 in which the n-FET 222 is cascode-connected constitutes a complementary inverter.

  In the cascode p-FET 210, the drain of the Si p-FET 212 is connected to the source of the diamond FET 211, and the source of the Si p-FET 212 is connected to the gate of the diamond FET 211. The source of the Si p-FET 212 (corresponding to the source terminal of the cascode p-FET 210) is connected to the DC power supply 260a. The drain of the diamond FET 211 (corresponding to the drain terminal of the cascode p-FET 210) is connected to the drain of the AlGaN / GaN n-FET 221 (corresponding to the drain terminal of the cascode n-FET 220).

  On the other hand, in the cascode n-FET 220, the drain of the Si n-FET 222 is connected to the source of the AlGaN / GaN n-FET 221, and the source of the Si n-FET 222 is connected to the gate of the AlGaN / GaN n-FET 221. Has been. The source of the Si p-FET 222 (corresponding to the source terminal of the cascode n-FET 220) is connected to the DC power supply 260b. The drain of the AlGaN / GaN-based n-FET 221 (corresponding to the drain terminal of the cascode n-FET 220) is connected to the drain electrode of the diamond FET 211 (corresponding to the drain terminal of the cascode p-FET 210).

  The signal line extending from the signal source 250 is branched into two, respectively, the gate of the Si p-FET 212 (corresponding to the gate terminal of the cascode p-FET 210) and the gate of the Si p-FET 222 (cascode p). -Corresponding to the gate terminal of the FET 220).

  In the present embodiment, using the complementary inverter 200 configured as described above, a voltage +10 V is applied from the DC power supply 260 a to the source terminal of the cascode p-FET 210, and the DC power supply 260 b is applied to the source terminal of the cascode n-FET 220. A voltage of −10 V is applied, and a rectangular pulse having an input voltage level of 0 V, an amplitude of 10 V, a period of 1000 Hz, and a duty ratio of 50% is input from the signal source 250 to the gate terminals of the cascode p-FET 210 and the cascode n-FET 220. A rectangular pulse with an amplitude of 10 V obtained by inverting the waveform from the midpoint connecting the drain terminal of the FET 210 and the drain terminal of the cascode n-FET 220 was obtained as an output.

[Example 2]
A second embodiment of the present invention will be described with reference to FIG. Also in the figure, symbol D represents a drain, symbol S represents a source, and symbol G represents a gate.

  The complementary inverter 300 according to the second embodiment includes a first-stage circuit 330 that functions as a level shifter of an input voltage, and a second-stage circuit 340 that functions as a complementary inverter.

  First, the second stage circuit 340 will be described. The second stage circuit 340 includes a cascode p-FET 310 in which a depletion type diamond FET 311 and an enhancement type Si p-FET 312 are cascode-connected, a depression type AlGaN / GaN n-FET 321 and an enhancement type Si n-type. The cascode n-FET 320 having the cascode-connected FET 322 constitutes a complementary inverter, so that the drain of the cascode p-FET 310 and the drain of the cascode n-FET 320 are connected to each other.

  In the cascode p-FET 310, the drain of the Si p-FET 312 is connected to the source of the diamond FET 311, and the source of the Si p-FET 312 is connected to the gate of the diamond FET 311. The source of the Si p-FET 312 (corresponding to the source terminal of the cascode p-FET 310) is connected to the DC power supply 360a. The drain of the diamond FET 311 (corresponding to the drain terminal of the cascode p-FET 310) is connected to the drain of the AlGaN / GaN n-FET 321 (corresponding to the drain terminal of the cascode n-FET 320).

  On the other hand, in the cascode n-FET 320, the drain of the Si n-FET 322 is connected to the source of the AlGaN / GaN n-FET 321, and the source of the Si n-FET 322 is connected to the gate of the AlGaN / GaN n-FET 321. Has been. The source of the Si p-FET 322 (corresponding to the source terminal of the cascode n-FET 320) is connected to the DC power supply 360b. The drain of the AlGaN / GaN n-FET 321 (corresponding to the drain terminal of the cascode n-FET 320) is connected to the drain of the diamond FET 311 (corresponding to the drain terminal of the cascode p-FET 310).

  Next, the first-stage circuit 330 will be described. The first stage circuit 330 includes a gate of the Si p-FET 312 (corresponding to the gate terminal of the cascode p-FET 310) and a gate of the Si n-FET 322 (the gate of the cascode n-FET 320) of the second stage circuit 340. This is a circuit for level-shifting the voltage level of the signal input from the signal source 350 such that the voltage level of the input signal input to the terminal corresponds to a predetermined voltage level. A switch circuit operating in a complementary manner is formed by connecting the source of the Si n-FET 331 and the source of the Si p-FET 332, and the source is grounded. The signal line of the signal source 350 branches into two and is connected to the gates of the Si n-FET 331 and the Si p-FET 332, respectively.

  A resistor 333 is connected to the drain of the Si n-FET 331, and a resistor 334 is connected in series to the tip of the resistor 333. The resistor 333 and the resistor 334 form a resistor voltage divider. The end of the resistor 334 opposite to the end connected to the resistor 333 is connected to the DC power source 360a. The midpoint between the resistors 333 and 334 is connected to the gate of the p-FET 312 made of Si, and the voltage divided by the resistors 333 and 334 and level-shifted to a predetermined voltage level is cascode. A signal can be input to the gate terminal of the p-FET 310. In this embodiment, the resistance ratio between the resistor 333 and the resistor 334 is 4: 1.

  On the other hand, a resistor 335 is connected to the drain of the p-FET 332 made of Si, a resistor 336 is connected in series to the tip of the resistor 335, and the resistor 335 and the resistor 336 form a resistor voltage divider. The end of the resistor 336 opposite to the end connected to the resistor 335 is connected to the DC power supply 360b. The middle point between the resistor 335 and the resistor 336 is connected to the gate of the Si n-FET 322, and the voltage divided by the resistors 335 and 336 is level-shifted to a predetermined voltage level. A signal can be input to the gate terminal of the p-FET 320. In this embodiment, the resistance ratio between the resistor 335 and the resistor 336 is 4: 1.

  In this embodiment, using the complementary inverter 300 configured as described above, a voltage +100 V is applied from the DC power supply 360 a to the source terminal of the cascode p-FET 310, and from the DC power supply 360 b to the source terminal of the cascode n-FET 320. A voltage of −100 V was applied, and a rectangular pulse having an input voltage level of 0 V and an amplitude of 5 V was input from the signal source 350 to the gates of the Si n-FET 331 and the Si p-FET 332 of the first-stage circuit 330.

  Since the resistance ratio between the resistor 333 and the resistor 334 is set to 4: 1, when the Si n-FET 331 of the first-stage circuit 330 is turned on, a current flows through the resistor 333 and the resistor 334, and the signal source 350 Since the input signal is level-shifted to a voltage level 20V lower than the power supply voltage + 100V of the DC power supply 360a by the resistance voltage division, the voltage between the gate and the source of the cascode p-FET 310 is opened by 20V, and the cascode p-FET 310 is Turn on. On the other hand, when the Si n-FET 331 of the first stage circuit 330 is turned off, no current flows through the resistor 333 and the resistor 334, so that the gate of the cascode p-FET 310 is pulled up to the power supply voltage + 100V of the DC power supply 360a. The voltage between the gate and the source of the cascode p-FET 310 becomes 0 V, and the cascode p-FET 310 is turned off.

  On the other hand, since the resistance ratio between the resistor 335 and the resistor 336 is set to 4: 1, when the Si p-FET 332 of the first-stage circuit 330 is turned on, a current flows through the resistor 335 and the resistor 336, and the signal source The input signal input from 350 is level-shifted to a voltage level 20V higher than the power supply voltage −100V of the DC power supply 360b by resistance voltage division, the voltage between the gate and the source of the cascode n-FET 320 is opened by 20V, and the cascode n-FET 320 Turns on. Conversely, when the Si p-FET 332 of the first-stage circuit 330 is turned off, no current flows through the resistor 335 and the resistor 336. Therefore, the gate electrode of the cascode n-FET 320 is pulled down to the power supply voltage −100V of the DC power supply 360b. As a result, the voltage between the gate and the source of the cascode n-FET 320 becomes 0 V, and the cascode n-FET 320 is turned off.

  Since the Si n-FET 331 and the Si p-FET 332 in the first stage circuit 330 operate in a complementary manner, the cascode p-FET 310 and the cascode n-FET 320 in the second stage circuit 340 also operate in a complementary manner. .

  FIG. 13A shows two output signals of the first-stage circuit 330 when a rectangular pulse (INPUT 1) having an input voltage level of 0 V, an amplitude of 5 V, a period of 1000 Hz, and a duty ratio of 50% is input from the signal source 350. That is, the gate input signal (INPUT2 ch1) of the cascode p-FET 310 and the gate input signal (INPUT2 ch2) of the cascode n-FET 320 are shown. As shown, the level is shifted to a predetermined voltage level. Then, the input signal to the first stage circuit 330 is shown in the lower part of FIG. 13B, and the output waveform of the second stage circuit 340 is shown in the upper part of FIG. 13B. As shown in the figure, a rectangular pulse having a voltage level of 0V and an amplitude of 100V is output.

  Note that the withstand voltage of the complementary inverter 300 described as an example in the second embodiment is limited by the withstand voltage of the first-stage circuit 330. In the first-stage circuit 330, the Si n-FET 331 is an cascode n-FET in which an AlGaN / GaN n-FET and an Si n-FET are cascode-connected, and an Si p-FET 332 is a diamond FET and Si. The p-FET may be replaced with a cascode p-FET having a cascode connection. In this way, the overall breakdown voltage of the complementary inverter 300 can be significantly improved.

  Further, the first-stage circuit 330 is not limited to the circuit configuration of the present embodiment as long as the input voltage level can be level-shifted to a predetermined voltage level, and may be another circuit. It is particularly preferable that the circuit be capable of outputting two synchronized signals with different voltage levels so that the cascode p-FET 310 and the cascode n-FET 320 constituting the stage circuit 340 are synchronized.

10 Diamond FET
DESCRIPTION OF SYMBOLS 11 Substrate 11a Diamond substrate 11b Diamond layer 12 Drain electrode 13 Source electrode 14 Gate electrode 15 Hydrogenation layer 16 Gate insulating film

Claims (8)

A diamond field effect transistor and an enhancement type p-channel field effect transistor connected in series with the diamond field effect transistor;
The diamond field effect transistor is
A drain electrode provided on the diamond substrate;
A source electrode provided on the diamond substrate apart from the drain electrode;
A hydrogenation layer provided on the surface of the diamond substrate between the drain electrode and the source electrode and having a carbon-hydrogen bond;
A gate insulating film covering the hydrogenation layer;
A diamond power element including a gate electrode provided on the gate insulating film.   The diamond power device according to claim 1, wherein the gate electrode of the diamond field effect transistor is connected to a source of the p-channel field effect transistor.   The diamond power device according to claim 1, wherein the p-channel field effect transistor is made of silicon. The diamond power element according to any one of claims 1 to 3,
And an n-channel field effect transistor connected in series to the diamond power element.   The inverter according to claim 4, wherein the n-channel field effect transistor is made of silicon.   The inverter according to claim 4, wherein the n-channel field effect transistor is formed of a group III-V compound semiconductor.   The inverter according to claim 6, wherein the III-V compound semiconductor is a semiconductor containing gallium and nitrogen. The inverter according to claim 7, wherein the n-channel field effect transistor including the semiconductor containing gallium and nitrogen is provided on the diamond substrate.