JP2018142672A - Semiconductor device and manufacturing method of the same - Google Patents
Semiconductor device and manufacturing method of the same Download PDFInfo
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Abstract
Description
本発明は、太陽電池、薄膜トランジスタ（ディスプレイ）、受光センサー等に用いる半導体装置と、その製造方法に関する。 The present invention relates to a semiconductor device used for a solar cell, a thin film transistor (display), a light receiving sensor, and the like, and a manufacturing method thereof.
絶縁体（ＳｉＯ２、ガラス、プラスティック）上に合成する半導体膜は、集積回路（ＬＳＩ）の３次元化や、情報端末・太陽電池の高性能化・低価格化を実現するための主要な構成要素として、盛んに研究されている。 A semiconductor film synthesized on an insulator (SiO 2 , glass, plastic) is a main component for realizing three-dimensional integrated circuits (LSIs) and high-performance and low-cost information terminals and solar cells. It has been actively studied as an element.
Ｓｉは代表的な半導体であり、あらゆる電子デバイスに用いられている。また、Ｓｉと同じＩＶ族半導体であるＧｅやＳｉＧｅは、既存の材料であるＳｉと親和性が高く、さらにＳｉより高いキャリア移動度および低い結晶化温度を有するため、次世代の半導体材料として期待されている。 Si is a typical semiconductor and is used in all electronic devices. In addition, Ge and SiGe, which are the same group IV semiconductors as Si, have high affinity with existing Si, and have higher carrier mobility and lower crystallization temperature than Si, so they are expected as next-generation semiconductor materials. Has been.
半導体膜を形成する場合、基材（基板）となるＬＳＩチップやガラス、プラスティックへの影響を考慮すると、プロセス温度は低くする必要がある。半導体膜の形成方法としては、転写法、化学気相成長法（ＣＶＤ法）、フラッシュランプアニール（ＦＬＡ）、金属誘起成長法（ＭＩＣ）、固相成長法等を用いることができる。転写法は、単結晶基板を薄膜上にカットし、絶縁体上に貼り合わせるものであるが、原材料となる単結晶基板が高価であること、プロセスが複雑であること、均一で大面積の転写が困難であることから、実用上の障壁が高いと考えられている（非特許文献１）。 In the case of forming a semiconductor film, it is necessary to lower the process temperature in consideration of the influence on an LSI chip, glass, or plastic that is a base material (substrate). As a method for forming the semiconductor film, a transfer method, a chemical vapor deposition method (CVD method), a flash lamp annealing (FLA), a metal induced growth method (MIC), a solid phase growth method, or the like can be used. In the transfer method, a single crystal substrate is cut onto a thin film and bonded onto an insulator. However, the single crystal substrate that is the raw material is expensive, the process is complicated, and the transfer is uniform and large in area. Therefore, it is considered that the practical barrier is high (Non-patent Document 1).
また、化学気相成長法は、絶縁体上に薄膜を合成する最も一般的な手法であるが、基板への成膜と結晶化を同時に行うものであり、合成される膜の構成粒子は小粒径（＜１μｍ）となってしまう。そのため、形成された半導体膜中でのキャリアの移動度は極めて低い（非特許文献２）。 Chemical vapor deposition is the most common method for synthesizing a thin film on an insulator. However, the film is formed on a substrate and crystallized at the same time. The particle size will be <1 μm. Therefore, the mobility of carriers in the formed semiconductor film is extremely low (Non-Patent Document 2).
また、フラッシュランプアニールは、絶縁体上に非晶質の半導体膜を形成した後、ランプ加熱して結晶化を促す方法であり、基板への熱的なダメージは少ないが、この場合にも、合成された半導体膜中でのキャリアの移動度は低い。この方法において、半導体膜の材料としてＧｅを用いた場合、得られる正孔移動度が２００ｃｍ２／Ｖ・ｓ程度であることが、これまでに報告されている（非特許文献３）。 In addition, flash lamp annealing is a method of forming an amorphous semiconductor film on an insulator and then heating the lamp to promote crystallization, and there is little thermal damage to the substrate. The mobility of carriers in the synthesized semiconductor film is low. In this method, when Ge is used as the material of the semiconductor film, it has been reported so far that the hole mobility obtained is about 200 cm 2 / V · s (Non-patent Document 3).
また、金属誘起成長法は、非晶質の半導体膜上に蒸着された触媒金属を核として、平面方向に結晶化を誘起させる方法である。この方法では、半導体膜の低温合成を可能とし、かつ、この半導体膜の構成粒子を５０μｍ以上に大粒径化するものとする。半導体膜の材料としてＧｅを用いた場合に、最大で２１０ｃｍ２／Ｖ・ｓの正孔移動度が得られることが、これまでに報告されている（非特許文献４）。 The metal-induced growth method is a method for inducing crystallization in a planar direction using a catalyst metal deposited on an amorphous semiconductor film as a nucleus. In this method, the semiconductor film can be synthesized at a low temperature, and the constituent particles of the semiconductor film are increased to 50 μm or more. It has been reported so far that a hole mobility of 210 cm 2 / V · s at the maximum can be obtained when Ge is used as the material of the semiconductor film (Non-patent Document 4).
また、固相成長法は、非晶質膜を電気炉で加熱して結晶化する非常に簡易な方法であり、構成粒子が比較的大粒径化した膜を得やすい。ただし、この方法でＳｉ、Ｇｅを固相成長させる場合、通常は、それぞれ６００℃以上、４００℃以上の熱処理が必要となる。Ｇｅを用いた場合において、これまでに報告されている最高の正孔移動度は、１４０ｃｍ２／Ｖ・ｓである（非特許文献５）。ＧｅにＳｎを添加することで、３２０ｃｍ２／Ｖ・ｓの正孔移動度が得られることも報告されており、これが、絶縁体上の低温合成薄膜の正孔移動度として、これまでに得られている中での最高値である（非特許文献６）。 The solid phase growth method is a very simple method of crystallizing an amorphous film by heating with an electric furnace, and it is easy to obtain a film in which constituent particles have a relatively large particle size. However, when solid phase growth of Si and Ge is performed by this method, heat treatment at 600 ° C. or higher and 400 ° C. or higher is usually required, respectively. In the case of using Ge, the highest hole mobility reported so far is 140 cm 2 / V · s (Non-patent Document 5). It has also been reported that hole mobility of 320 cm 2 / V · s can be obtained by adding Sn to Ge. This has been obtained as a hole mobility of a low-temperature synthetic thin film on an insulator so far. It is the highest value among these (Non-Patent Document 6).
本発明は、かかる事情に鑑みてなされたものであり、基材にダメージを与える熱負荷を低減し、デバイス動作させたときに、従来よりも高いキャリア移動度や発電効率を実現する半導体装置と、その製造方法を提供することを目的としている。 The present invention has been made in view of such circumstances, and a semiconductor device that achieves higher carrier mobility and power generation efficiency than conventional devices when the device is operated by reducing the thermal load that damages the base material. It aims at providing the manufacturing method.
本発明は、上記課題を解決するため、以下の手段を提供する。
（１）本発明の一態様に係る半導体装置は、基材と、基材の一面に形成された半導体膜とを有し、前記半導体膜は、平均粒径が１μｍ以上の結晶粒子からなる多結晶膜である。
（２）（１）に記載の半導体装置は、前記半導体膜の厚さが、５０ｎｍ以上であることが好ましい。
（３）（１）または（２）のいずれかに記載の半導体装置は、前記結晶粒子がＧｅからなることが好ましい。
（４）（１）または（２）のいずれかに記載の半導体装置は、前記結晶粒子がＳｉＧｅからなることが好ましい。
（５）（１）または（２）のいずれかに記載の半導体装置は、前記結晶粒子がＳｉからなることが好ましい。
（６）本発明の一態様に係る半導体装置の製造方法は、（１）〜（５）のいずれか一つに記載の半導体装置の製造方法であって、前記基材を加熱しながら、前記基材の一面に非晶質の半導体膜を形成する第一工程と、前記半導体膜を加熱して、前記半導体膜の固相成長を促す第二工程と、を有し、前記第一工程での加熱温度を、前記半導体膜に結晶核が発生する温度の５０％以上１００％未満となるように調整する。
（７）（６）に記載の半導体装置の製造方法は、前記第一工程での加熱温度を、前記半導体膜を構成する粒子の密度が、同じ材料の結晶における粒子の密度の９８％以上１０２％未満となるように調整することが好ましい。
（８）（６）または（７）のいずれかに記載の半導体装置の製造方法は、前記第一工程での加熱温度を、１００℃以上７００℃以下とすることが好ましい。
（９）（６）〜（８）のいずれか一つに記載の半導体装置の製造方法は、前記第二工程での加熱温度を、３５０℃以上８００℃以下とすることが好ましい。
The present invention provides the following means in order to solve the above problems.
(1) A semiconductor device according to one embodiment of the present invention includes a base material and a semiconductor film formed on one surface of the base material, and the semiconductor film includes a plurality of crystal grains having an average grain size of 1 μm or more. It is a crystal film.
(2) In the semiconductor device according to (1), the thickness of the semiconductor film is preferably 50 nm or more.
(3) In the semiconductor device according to any one of (1) and (2), the crystal particles are preferably made of Ge.
(4) In the semiconductor device according to any one of (1) and (2), the crystal particles are preferably made of SiGe.
(5) In the semiconductor device according to any one of (1) and (2), the crystal particles are preferably made of Si.
(6) A method for manufacturing a semiconductor device according to an aspect of the present invention is the method for manufacturing a semiconductor device according to any one of (1) to (5), wherein the substrate is heated while the substrate is heated. A first step of forming an amorphous semiconductor film on one surface of the substrate, and a second step of heating the semiconductor film to promote solid phase growth of the semiconductor film, The heating temperature is adjusted to 50% or more and less than 100% of the temperature at which crystal nuclei are generated in the semiconductor film.
(7) In the method for manufacturing a semiconductor device according to (6), the heating temperature in the first step is equal to or higher than 98% of the density of particles in a crystal of the same material as the density of particles constituting the semiconductor film. It is preferable to adjust so that it may be less than%.
(8) In the method for manufacturing a semiconductor device according to any one of (6) and (7), the heating temperature in the first step is preferably set to 100 ° C. or more and 700 ° C. or less.
(9) In the method for manufacturing a semiconductor device according to any one of (6) to (8), the heating temperature in the second step is preferably set to 350 ° C. or higher and 800 ° C. or lower.
本発明の半導体装置は、その製造過程において、結晶核が発生しない範囲で結晶に近い密度の非晶質膜を形成し、これを固相成長させることによって得られる半導体膜を有している。この半導体膜は、大粒径化した結晶粒子からなる多結晶膜であるため、本発明の半導体装置をデバイス動作させたときに、従来よりも高いキャリア移動度を実現することができる。 The semiconductor device of the present invention has a semiconductor film obtained by forming an amorphous film having a density close to a crystal within a range in which crystal nuclei are not generated and solid-phase growing the film in the manufacturing process. Since this semiconductor film is a polycrystalline film made of crystal grains having a large particle size, when the semiconductor device of the present invention is operated as a device, higher carrier mobility than before can be realized.
本発明での半導体膜は、固相成長に必要な加熱温度が低減するため、基材にダメージを与えるような熱的負荷を軽減することができる。 In the semiconductor film according to the present invention, the heating temperature necessary for solid phase growth is reduced, so that a thermal load that damages the substrate can be reduced.
以下、本発明について、図を適宜参照しながら詳細に説明する。以下の説明で用いる図は、本発明の特徴を分かりやすくするために、便宜上特徴となる部分を拡大して示している場合があり、各構成要素の寸法比率等は実際とは異なっていることがある。また、以下の説明において例示される材料、寸法等は一例であって、本発明はそれらに限定されるものではなく、本発明の効果を奏する範囲で適宜変更して実施することが可能である。 Hereinafter, the present invention will be described in detail with appropriate reference to the drawings. In the drawings used in the following description, in order to make the features of the present invention easier to understand, portions that become features may be shown in an enlarged form for convenience, and the dimensional ratios and the like of each component are different from actual ones. There is. In addition, the materials, dimensions, and the like exemplified in the following description are examples, and the present invention is not limited thereto, and can be implemented with appropriate modifications within the scope of the effects of the present invention. .
［半導体装置の構成］
図１は、本発明の一実施形態に係る半導体装置１００の断面図である。半導体装置１００は、基材１０１と、基材の一面１０１ａに形成（合成）された半導体膜（半導体薄膜）１０２とを有している。
[Configuration of semiconductor device]
FIG. 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a base material 101 and a semiconductor film (semiconductor thin film) 102 formed (synthesized) on one surface 101a of the base material.
基材１０１は、ＳｉＯ２、ガラス、プラスティック等の絶縁体、それらを搭載した基板、あるいはＬＳＩチップ等からなる。 The substrate 101 is made of an insulator such as SiO 2 , glass, or plastic, a substrate on which these are mounted, an LSI chip, or the like.
半導体膜１０２は、薄膜形成が可能なあらゆる材料、例えばＧｅ、ＳｉＧｅ、Ｓｉ、ＧｅＳｎ、ＳｉＣ、ＧａＡｓ、ＩｎＰ、ＧａＮ、ＺｎＳｅ、ＣｄＳ、ＺｎＯ等の大粒径化した結晶粒子からなる多結晶膜である。結晶粒子の平均粒径は、１μｍ以上であればよく、５μｍ以上３０μｍ以下であれば好ましく、３０μｍ程度であればより好ましい。 The semiconductor film 102 is a polycrystalline film made of any material capable of forming a thin film, such as Ge, SiGe, Si, GeSn, SiC, GaAs, InP, GaN, ZnSe, CdS, and ZnO. is there. The average particle size of the crystal particles may be 1 μm or more, preferably 5 μm or more and 30 μm or less, and more preferably about 30 μm.
半導体膜１０２の厚さは、５０ｎｍ以上であればよく、５０ｎｍ以上５０００ｎｍ以下であれば好ましい。 The thickness of the semiconductor film 102 may be 50 nm or more, and preferably 50 nm or more and 5000 nm or less.
［半導体装置の製造方法］
半導体装置１００を製造するための主要な２工程について、図２を用いて説明する。
[Method for Manufacturing Semiconductor Device]
Two main steps for manufacturing the semiconductor device 100 will be described with reference to FIG.
（第一工程）
基材１０１を加熱しながら、基材の一面１０１に対し、Ｇｅ、ＳｉＧｅ、Ｓｉ、ＧｅＳｎ、ＳｉＣ、ＧａＡｓ、ＩｎＰ、ＧａＮ、ＺｎＳｅ、ＣｄＳ、ＺｎＯ等の粒子１０２Ａを堆積させ、非晶質の半導体膜１０２Ｂを形成する（図２の左側）。
(First step)
While heating the base material 101, particles 102A such as Ge, SiGe, Si, GeSn, SiC, GaAs, InP, GaN, ZnSe, CdS, and ZnO are deposited on one surface 101 of the base material to form an amorphous semiconductor. A film 102B is formed (left side in FIG. 2).
加熱方法、堆積方法としては、特に限定されるものではなく、一般的な方法（分子線堆積法、ＣＶＤ法、スパッタリング法等）を用いることができる。分子線堆積法を用いる場合には、高真空中で粒子１０２Ａの分子線を発生させ、これを加熱中の基材の一面１０１ａに照射することにより、粒子１０２Ａを堆積させて非晶質の膜１０２Ｂを形成することになる。この方法では成膜温度を低く設定することができるため、プラスティック等の耐熱性が低い基材、ＬＳＩチップ等に対して成膜する場合に、好ましい方法となる。 The heating method and the deposition method are not particularly limited, and general methods (molecular beam deposition method, CVD method, sputtering method, etc.) can be used. When the molecular beam deposition method is used, a molecular beam of the particle 102A is generated in a high vacuum, and the surface 102a of the heated substrate is irradiated with the molecular beam, thereby depositing the particle 102A to form an amorphous film. 102B is formed. In this method, since the film formation temperature can be set low, it is a preferable method when forming a film on a substrate having low heat resistance such as plastic, an LSI chip, or the like.
第一工程での加熱温度は、形成される非晶質膜１０２Ｂが、できる限り結晶に近い粒子数密度（同じ材料の結晶における粒子の密度の９８％以上１０２％未満）であり、かつ、結晶核が発生していない状態となるように調整する。つまり、半導体膜１０２Ｂに結晶核が発生しない範囲で、可能な限り大きい温度となるように調整する。 The heating temperature in the first step is such that the amorphous film 102B to be formed has a particle number density as close as possible to the crystal (98% or more and less than 102% of the density of particles in the crystal of the same material) and the crystal Adjust so that no nucleus is generated. That is, the temperature is adjusted to be as high as possible without causing crystal nuclei in the semiconductor film 102B.
実際には、半導体膜１０２Ｂに結晶核が発生する温度の３０％以上１００％未満となるように調整すればよく、５０％以上１００％未満となるように調整すればより好ましい。具体的には、概ね１００℃以上７００℃以下となる。この温度は、形成する半導体膜１０２の材料と厚さに応じて調整する。例えば、Ｇｅからなる厚さ１００ｎｍの半導体膜１０２を形成する場合には、１００〜１５０℃とする。また、ＳｉＧｅ、Ｓｉからなる厚さ１００ｎｍの半導体膜１０２を形成する場合には、それぞれ１００〜６５０℃、５００〜６５０℃とする。 Actually, the temperature may be adjusted to be 30% or more and less than 100% of the temperature at which crystal nuclei are generated in the semiconductor film 102B, and more preferably 50% or more and less than 100%. Specifically, the temperature is approximately 100 ° C. or more and 700 ° C. or less. This temperature is adjusted in accordance with the material and thickness of the semiconductor film 102 to be formed. For example, when the semiconductor film 102 made of Ge and having a thickness of 100 nm is formed, the temperature is set to 100 to 150 ° C. In the case of forming the semiconductor film 102 made of SiGe and Si and having a thickness of 100 nm, the temperature is set to 100 to 650 ° C. and 500 to 650 ° C., respectively.
（第二工程）
熱処理（雰囲気は問わない）を行い、第一工程で形成された非晶質の半導体膜１０２Ｂの固相成長を促し、多結晶の半導体膜（多結晶膜）１０２Ｃを合成する（図２の右側）。第二工程において、加熱温度は３５０℃以上８００℃以下とすることが好ましく、加熱時間は０．１時間以上３００時間以下とすることが好ましい。
(Second step)
Heat treatment (regardless of atmosphere) is performed to promote solid phase growth of the amorphous semiconductor film 102B formed in the first step, and a polycrystalline semiconductor film (polycrystalline film) 102C is synthesized (right side of FIG. 2). ). In the second step, the heating temperature is preferably 350 ° C. or more and 800 ° C. or less, and the heating time is preferably 0.1 hours or more and 300 hours or less.
第一工程での加熱温度を上述したように調整することにより、形成される半導体膜１０２Ｃは、１μｍ以上の大粒径の粒子からなる多結晶膜となる。 By adjusting the heating temperature in the first step as described above, the formed semiconductor film 102C becomes a polycrystalline film made of particles having a large particle diameter of 1 μm or more.
第一工程および第二工程を経て得られた半導体装置１００は、その製造過程において、結晶核が発生しない範囲で結晶に近い密度の非晶質膜１０２Ｂを形成し、これを固相成長させることによって得られる多結晶の半導体膜１０２Ｃを有している。この半導体膜１０２Ｃは、１μｍ以上の大粒径化した結晶粒子からなる多結晶膜であるため、半導体装置１００をデバイス動作させたときに、従来よりも高いキャリア移動度を実現することができる。例えば、Ｇｅからなる厚さ１００ｎｍの半導体膜においては、正孔移動度を３４０ｃｍ２／Ｖ・ｓまで向上させることができる。また、Ｇｅからなる厚さ３００ｎｍの半導体膜においては、正孔移動度を３８０ｃｍ２／Ｖ・ｓまで向上させることができる。 The semiconductor device 100 obtained through the first step and the second step forms an amorphous film 102B having a density close to a crystal within a range in which crystal nuclei are not generated in the manufacturing process, and this is solid-phase grown. A polycrystalline semiconductor film 102C obtained by the above process. Since the semiconductor film 102C is a polycrystalline film made of crystal grains having a large particle size of 1 μm or more, when the semiconductor device 100 is operated as a device, higher carrier mobility than before can be realized. For example, in a semiconductor film made of Ge and having a thickness of 100 nm, hole mobility can be improved to 340 cm 2 / V · s. In addition, in a semiconductor film made of Ge and having a thickness of 300 nm, the hole mobility can be improved to 380 cm 2 / V · s.
半導体膜１０２を構成する結晶の粒径が１μｍより小さい場合、粒界によるキャリアの散乱が顕著となるため、本発明と同等の移動度を得ることはできない。 When the crystal grain size of the semiconductor film 102 is smaller than 1 μm, carrier scattering due to the grain boundary becomes significant, and thus mobility equivalent to that of the present invention cannot be obtained.
以上のように、本実施形態に係る半導体装置１００は、その製造過程において、結晶核が発生しない範囲で結晶に近い密度の非晶質膜１０２Ｂを形成し、これを固相成長させることによって得られる半導体膜１０２Ｃを有している。この半導体膜１０２Ｃは、１μｍ以上の大粒径化した結晶粒子からなる多結晶膜であるため、従来よりも高いキャリア移動度を実現することができる。 As described above, the semiconductor device 100 according to the present embodiment is obtained by forming the amorphous film 102B having a density close to a crystal within a range in which crystal nuclei are not generated and performing solid phase growth in the manufacturing process. The semiconductor film 102C is formed. Since the semiconductor film 102C is a polycrystalline film made of crystal grains having a large particle size of 1 μm or more, higher carrier mobility than conventional can be realized.
本実施形態での半導体膜１０２Ｃでは、固相成長に必要な加熱温度が低減する。例えばＧｅにおいては、基材１０１にダメージを与えるような５００℃以上の高温処理を行うことなく形成することができる。そのため、基材１０１として、ＬＳＩチップや耐熱性の低いガラス、プラスティック等を幅広く用いることができる。 In the semiconductor film 102C in this embodiment, the heating temperature necessary for solid phase growth is reduced. For example, in Ge, it can form without performing the high temperature process of 500 degreeC or more which damages the base material 101. FIG. Therefore, a wide variety of LSI chips, glass with low heat resistance, plastics, and the like can be used as the base material 101.
以下、実施例により本発明の効果をより明らかなものとする。なお、本発明は、以下の実施例に限定されるものではなく、その要旨を変更しない範囲で適宜変更して実施することができる。 Hereinafter, the effects of the present invention will be made clearer by examples. In addition, this invention is not limited to a following example, In the range which does not change the summary, it can change suitably and can implement.
（実施例１）
分子線堆積法により、石英ガラス基板上に、基板温度Ｔｄを５０℃〜２００℃の範囲で設定した状態で、ゲルマニウム（Ｇｅ）粒子を堆積させ、厚さ１００ｎｍのＧｅ薄膜を形成（蒸着）した（第一工程）。成膜レートを１ｎｍ／ｍｉｎとし、成膜時間を１００分間とした。
Example 1
With a molecular beam deposition method, germanium (Ge) particles are deposited on a quartz glass substrate in a state where the substrate temperature Td is set in the range of 50 ° C. to 200 ° C. to form a Ge thin film with a thickness of 100 nm (vapor deposition). (First step). The film formation rate was 1 nm / min, and the film formation time was 100 minutes.
その後、第一工程を経た試料を、窒素雰囲気とした電気炉内に導入し、第一工程で形成したＧｅ薄膜に対し、３７５℃で１４０時間、４００℃で６０時間、４５０℃で５時間の熱処理を行い、固相成長を促した（第二工程）。 Then, the sample which passed the 1st process was introduce | transduced in the electric furnace made into nitrogen atmosphere, with respect to Ge thin film formed at the 1st process, it is 140 hours at 375 degreeC, 60 hours at 400 degreeC, and 5 hours at 450 degreeC. Heat treatment was performed to promote solid phase growth (second step).
第一工程で形成したＧｅ薄膜に対し、Ｘ線反射率測定（ＸＲＲ）を行った結果を図３（ａ）のグラフに示す。グラフの横軸は試料の傾斜角（２θ）［ｄｅｇ］を示し、縦軸は反射光の強度［ａ．ｕ．］を示している。 The graph of FIG. 3A shows the results of X-ray reflectivity measurement (XRR) performed on the Ge thin film formed in the first step. The horizontal axis of the graph represents the tilt angle (2θ) [deg] of the sample, and the vertical axis represents the intensity of reflected light [a. u. ] Is shown.
この測定結果に基づいて、第一工程で設定した基板温度Ｔｄに対応する、Ｇｅ薄膜の粒子密度を算出した。算出結果を図３（ｂ）のグラフに示す。グラフの横軸は基板温度Ｔｄ［℃］を示し、縦軸は粒子密度［ｇ／ｃｍ３］を示している。Ｇｅが結晶化した場合の粒子密度は約５．３４［ｇ／ｃｍ３］と推定され、これを一点鎖線で示している。 Based on this measurement result, the particle density of the Ge thin film corresponding to the substrate temperature Td set in the first step was calculated. The calculation results are shown in the graph of FIG. The horizontal axis of the graph represents the substrate temperature T d [° C.], and the vertical axis represents the particle density [g / cm 3 ]. When Ge is crystallized, the particle density is estimated to be about 5.34 [g / cm 3 ], which is indicated by a one-dot chain line.
粒子密度に着目すると、Ｇｅ薄膜の構成粒子は、基板温度Ｔｄを低く設定して形成した場合には、低密度の非晶質の構造をとるが、設定温度を上げるにつれて緻密化し、１００℃以上とした場合には、粒子密度が結晶に漸近することが分かる。 Focusing on the particle density, the constituent particles of the Ge thin film have a low-density amorphous structure when formed at a low substrate temperature Td. In the case described above, it can be seen that the particle density is asymptotic to the crystal.
第二工程を経て得られた半導体装置に対し、ラマン分光測定を行ったところ、第一工程においてＴｄ＞１７５℃とした場合においては、堆積時の核発生が確認された。 When the Raman spectroscopic measurement was performed on the semiconductor device obtained through the second step, nucleation during deposition was confirmed when T d > 175 ° C. in the first step.
また、Ｇｅ薄膜の形成時に設定する基板温度Ｔｄを高くするほど、第二工程での核の成長速度は上昇する傾向にあり、例えば、Ｔｄを１００℃以上とした場合には、３７５℃、１４０時間程度の熱処理で結晶化することが確認された。この温度（３７５℃）は、プラスティック上での薄膜合成も可能とする温度である。 Further, as the substrate temperature Td set at the time of forming the Ge thin film is increased, the nucleus growth rate in the second step tends to increase. For example, when Td is set to 100 ° C. or higher, 375 ° C. It was confirmed that crystallization occurred by heat treatment for about 140 hours. This temperature (375 ° C.) is a temperature at which thin film synthesis on a plastic is possible.
第二工程を経て得られた多結晶Ｇｅ膜の構成粒子の粒径について、電子線後方散乱回折（ＥＢＳＤ）法を用いて評価した。 The particle diameter of the constituent particles of the polycrystalline Ge film obtained through the second step was evaluated using an electron beam backscatter diffraction (EBSD) method.
図４（ａ）〜（ｃ）は、基板温度Ｔｄを５０℃、１００℃、２００℃とした場合のＥＢＳＤ画像である。これらのＥＢＳＤ画像から、多結晶Ｇｅ膜の結晶方位は、Ｔｄを５０℃、２００℃とした場合にはランダムであるのに対し、Ｔｄを１００℃とした場合には特定の方向に優先配向していることが分かる。また、Ｔｄを１００℃とした場合には１μｍ以上の結晶粒が得られていることが分る。 4A to 4C are EBSD images when the substrate temperature Td is 50 ° C., 100 ° C., and 200 ° C. FIG. From these EBSD images, the crystal orientation of the polycrystalline Ge film is random when Td is 50 ° C. and 200 ° C., but priority is given to a specific direction when T d is 100 ° C. It can be seen that it is oriented. It can also be seen that when Td is 100 ° C., crystal grains of 1 μm or more are obtained.
図５は、多結晶Ｇｅ膜の構成粒子の粒径と、第一工程で設定した基板温度Ｔｄとの関係を示すグラフである。グラフの横軸は基板温度Ｔｄ［℃］を示し、縦軸は粒径［μｍ］を示している。ここには、第二工程の熱処理温度Ｔｇを３７５℃、４００℃、４５０℃とした場合の粒径を、それぞれ四角プロット、三角プロット、円プロットで示している。 FIG. 5 is a graph showing the relationship between the particle diameter of the constituent particles of the polycrystalline Ge film and the substrate temperature Td set in the first step. The horizontal axis of the graph represents the substrate temperature T d [° C.], and the vertical axis represents the particle size [μm]. Here shows the heat treatment temperature T g of the second step 375 ° C., 400 ° C., the particle size in the case of a 450 ° C., square plot respectively, triangular plot, a circle plot.
Ｇｅ薄膜の粒径は、基板温度Ｔｄに強く依存しており、基板温度Ｔｄが１２５℃のときに最大値（約５μｍ）となっている。この結果は、下記〔１〕、〔２〕の事項を示唆している。
〔１〕基板温度Ｔｄが１００〜１５０℃の範囲において、非晶質Ｇｅは、その密度を結晶レベルに近づけることにより、核成長が促進され、大粒径化する。
〔２〕基板温度Ｔｄが１５０℃より大きい範囲において、堆積時に発生した初期核は高密度であり、固相成長時に小粒径化を促す。
The particle size of the Ge thin film is strongly dependent on the substrate temperature T d, the substrate temperature T d is the maximum value (about 5 [mu] m) at 125 ° C.. This result suggests the following items [1] and [2].
[1] In the range where the substrate temperature Td is in the range of 100 to 150 ° C., the amorphous Ge has its density brought close to the crystal level, thereby promoting nucleus growth and increasing the particle size.
[2] In the range where the substrate temperature Td is higher than 150 ° C., the initial nuclei generated at the time of deposition are high density, and the particle size is promoted to be reduced during solid phase growth.
第二工程を経て得られた多結晶Ｇｅ膜の電気的特性について、van der Pauw法を用いて評価した。 The electrical characteristics of the polycrystalline Ge film obtained through the second step were evaluated using the van der Pauw method.
図６は、第一工程で設定した基板温度Ｔｄと、多結晶Ｇｅ膜の正孔移動度、および正孔密度との関係を示すグラフである。グラフの横軸は基板温度Ｔｄ［℃］を示し、縦軸は正孔移動度（左側）、正孔密度（右側）を示している。基板温度Ｔｄを１２５℃とした場合に、結晶粒径を反映し、多結晶Ｇｅ膜として最低レベルの正孔密度（３×１０１７ｃｍ−３）および最高の正孔移動度（３４０ｃｍ２／Ｖ・ｓ）が得られている。 FIG. 6 is a graph showing the relationship between the substrate temperature Td set in the first step, the hole mobility of the polycrystalline Ge film, and the hole density. The horizontal axis of the graph represents the substrate temperature T d [° C.], and the vertical axis represents the hole mobility (left side) and the hole density (right side). When the substrate temperature Td is 125 ° C., the crystal grain size is reflected, and the lowest hole density (3 × 10 17 cm −3 ) and the highest hole mobility (340 cm 2 / V · s) is obtained.
（実施例２）
分子線堆積法により、石英ガラス基板上に、基板温度Ｔｄを１５０℃で設定した状態で、ゲルマニウム（Ｇｅ）粒子を堆積させ、厚さ３００ｎｍのＧｅ薄膜を形成（蒸着）した（第一工程）。成膜レートを１ｎｍ／ｍｉｎとし、成膜時間を３００分間とした。
(Example 2)
With a molecular beam deposition method, germanium (Ge) particles were deposited on a quartz glass substrate with a substrate temperature Td set at 150 ° C. to form (evaporate) a Ge thin film having a thickness of 300 nm (first step). ). The film formation rate was 1 nm / min, and the film formation time was 300 minutes.
その後、第一工程を経た試料を、窒素雰囲気とした電気炉内に導入し、第一工程で形成したＧｅ薄膜に対し、４５０℃で５時間の熱処理を行い、固相成長を促した（第二工程）。 After that, the sample after the first step was introduced into an electric furnace in a nitrogen atmosphere, and the Ge thin film formed in the first step was subjected to heat treatment at 450 ° C. for 5 hours to promote solid phase growth (first step). Two steps).
第二工程を経て得られた多結晶Ｇｅ膜の電気的特性について、実施例１と同様に評価したところ、実施例１よりもさらに高い正孔移動度３８０ｃｍ２／Ｖ・ｓが得られた。 When the electrical characteristics of the polycrystalline Ge film obtained through the second step were evaluated in the same manner as in Example 1, a higher hole mobility of 380 cm 2 / V · s than in Example 1 was obtained.
本発明は、「高速、軽量かつフレキシブルな携帯型情報端末の開発」、「ＬＳＩの３次元化、多機能化」、「高効率と低コストを両立する多接合型太陽電池の開発」等に広く活用することができる。 The present invention includes "development of a high-speed, light-weight and flexible portable information terminal", "three-dimensional and multi-functional LSI", "development of a multi-junction solar cell that achieves both high efficiency and low cost", etc. Can be widely used.
１００・・・半導体装置、１０１・・・基材、１０１ａ・・・基材の一面、
１０２、１０２Ａ・・・粒子、１０２Ｂ、１０２Ｃ・・・半導体膜。
DESCRIPTION OF SYMBOLS 100 ... Semiconductor device, 101 ... Base material, 101a ... One surface of a base material,
102, 102A ... Particles, 102B, 102C ... Semiconductor films.
Claims (9)
基材の一面に形成された半導体膜とを有し、
前記半導体膜は、平均粒径が１μｍ以上の結晶粒子からなる多結晶膜であることを特徴とする半導体装置。 A substrate;
A semiconductor film formed on one surface of the substrate;
The semiconductor device according to claim 1, wherein the semiconductor film is a polycrystalline film made of crystal grains having an average grain size of 1 μm or more.
前記基材を加熱しながら、前記基材の一面に非晶質の半導体膜を形成する第一工程と、
前記半導体膜を加熱して、前記半導体膜の固相成長を促す第二工程と、を有し、
前記第一工程での加熱温度を、前記半導体膜に結晶核が発生する温度の５０％以上１００％未満となるように調整することを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 1,
A first step of forming an amorphous semiconductor film on one surface of the substrate while heating the substrate;
Heating the semiconductor film to promote solid phase growth of the semiconductor film, and
A method for manufacturing a semiconductor device, wherein the heating temperature in the first step is adjusted to be 50% or more and less than 100% of a temperature at which crystal nuclei are generated in the semiconductor film.
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