JP7360180B2 - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP7360180B2
JP7360180B2 JP2021007370A JP2021007370A JP7360180B2 JP 7360180 B2 JP7360180 B2 JP 7360180B2 JP 2021007370 A JP2021007370 A JP 2021007370A JP 2021007370 A JP2021007370 A JP 2021007370A JP 7360180 B2 JP7360180 B2 JP 7360180B2
Authority
JP
Japan
Prior art keywords
film
semiconductor film
semiconductor device
semiconductor
base material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2021007370A
Other languages
Japanese (ja)
Other versions
JP2021061451A (en
Inventor
薫 都甲
崇 末益
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Tsukuba NUC
Original Assignee
University of Tsukuba NUC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2017037505A external-priority patent/JP6985711B2/en
Application filed by University of Tsukuba NUC filed Critical University of Tsukuba NUC
Priority to JP2021007370A priority Critical patent/JP7360180B2/en
Publication of JP2021061451A publication Critical patent/JP2021061451A/en
Application granted granted Critical
Publication of JP7360180B2 publication Critical patent/JP7360180B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Recrystallisation Techniques (AREA)

Description

本発明は、太陽電池、薄膜トランジスタ(ディスプレイ)、受光センサー等に用いる半導体装置と、その製造方法に関する。 The present invention relates to a semiconductor device used for a solar cell, a thin film transistor (display), a light receiving sensor, etc., and a method for manufacturing the same.

絶縁体(SiO、ガラス、プラスティック)上に合成する半導体膜は、集積回路(LSI)の3次元化や、情報端末・太陽電池の高性能化・低価格化を実現するための主要な構成要素として、盛んに研究されている。 Semiconductor films synthesized on insulators (SiO 2 , glass, plastic) are the main components for realizing three-dimensional integrated circuits (LSIs) and higher performance and lower prices for information terminals and solar cells. This element is being actively researched.

Siは代表的な半導体であり、あらゆる電子デバイスに用いられている。また、Siと同じIV族半導体であるGeやSiGeは、既存の材料であるSiと親和性が高く、さらにSiより高いキャリア移動度および低い結晶化温度を有するため、次世代の半導体材料として期待されている。 Si is a typical semiconductor and is used in all kinds of electronic devices. In addition, Ge and SiGe, which are group IV semiconductors like Si, have a high affinity with the existing material Si, and also have higher carrier mobility and lower crystallization temperature than Si, so they are expected to be used as next-generation semiconductor materials. has been done.

半導体膜を形成する場合、基材(基板)となるLSIチップやガラス、プラスティックへの影響を考慮すると、プロセス温度は低くする必要がある。半導体膜の形成方法としては、転写法、化学気相成長法(CVD法)、フラッシュランプアニール(FLA)、金属誘起成長法(MIC)、固相成長法等を用いることができる。転写法は、単結晶基板を薄膜上にカットし、絶縁体上に貼り合わせるものであるが、原材料となる単結晶基板が高価であること、プロセスが複雑であること、均一で大面積の転写が困難であることから、実用上の障壁が高いと考えられている(非特許文献1)。 When forming a semiconductor film, it is necessary to keep the process temperature low in consideration of the effect on the LSI chip, glass, and plastic that serve as the base material (substrate). As a method for forming the semiconductor film, a transfer method, chemical vapor deposition method (CVD method), flash lamp annealing (FLA), metal induced growth method (MIC), solid phase growth method, etc. can be used. The transfer method involves cutting a single crystal substrate into a thin film and bonding it onto an insulator, but the single crystal substrate used as the raw material is expensive, the process is complicated, and it is difficult to transfer uniformly and over a large area. Since it is difficult, it is considered that there is a high practical barrier (Non-Patent Document 1).

また、化学気相成長法は、絶縁体上に薄膜を合成する最も一般的な手法であるが、基板への成膜と結晶化を同時に行うものであり、合成される膜の構成粒子は小粒径(<1μm)となってしまう。そのため、形成された半導体膜中でのキャリアの移動度は極めて低い(非特許文献2)。 In addition, chemical vapor deposition is the most common method for synthesizing thin films on insulators, but it simultaneously performs film formation on a substrate and crystallization, and the constituent particles of the synthesized film are small. The particle size becomes (<1 μm). Therefore, the mobility of carriers in the formed semiconductor film is extremely low (Non-Patent Document 2).

また、フラッシュランプアニールは、絶縁体上に非晶質の半導体膜を形成した後、ランプ加熱して結晶化を促す方法であり、基板への熱的なダメージは少ないが、この場合にも、合成された半導体膜中でのキャリアの移動度は低い。この方法において、半導体膜の材料としてGeを用いた場合、得られる正孔移動度が200cm/V・s程度であることが、これまでに報告されている(非特許文献3)。 In addition, flash lamp annealing is a method in which an amorphous semiconductor film is formed on an insulator and then heated with a lamp to promote crystallization. Although there is little thermal damage to the substrate, in this case as well, The mobility of carriers in the synthesized semiconductor film is low. In this method, it has been reported that when Ge is used as the material for the semiconductor film, the obtained hole mobility is about 200 cm 2 /V·s (Non-Patent Document 3).

また、金属誘起成長法は、非晶質の半導体膜上に蒸着された触媒金属を核として、平面方向に結晶化を誘起させる方法である。この方法では、半導体膜の低温合成を可能とし、かつ、この半導体膜の構成粒子を50μm以上に大粒径化するものとする。半導体膜の材料としてGeを用いた場合に、最大で210cm/V・sの正孔移動度が得られることが、これまでに報告されている(非特許文献4)。 Further, the metal-induced growth method is a method of inducing crystallization in a planar direction using a catalyst metal deposited on an amorphous semiconductor film as a nucleus. In this method, it is possible to synthesize a semiconductor film at a low temperature, and the particle size of the constituent particles of the semiconductor film is increased to 50 μm or more. It has been reported so far that when Ge is used as a material for a semiconductor film, a maximum hole mobility of 210 cm 2 /V·s can be obtained (Non-Patent Document 4).

また、固相成長法は、非晶質膜を電気炉で加熱して結晶化する非常に簡易な方法であり、構成粒子が比較的大粒径化した膜を得やすい。ただし、この方法でSi、Geを固相成長させる場合、通常は、それぞれ600℃以上、400℃以上の熱処理が必要となる。Geを用いた場合において、これまでに報告されている最高の正孔移動度は、140cm/V・sである(非特許文献5)。GeにSnを添加することで、320cm/V・sの正孔移動度が得られることも報告されており、これが、絶縁体上の低温合成薄膜の正孔移動度として、これまでに得られている中での最高値である(非特許文献6)。 Further, the solid phase growth method is a very simple method in which an amorphous film is crystallized by heating it in an electric furnace, and it is easy to obtain a film in which the constituent particles are relatively large in size. However, when Si and Ge are grown in solid phase using this method, heat treatment at 600° C. or higher and 400° C. or higher is usually required, respectively. In the case of using Ge, the highest hole mobility reported so far is 140 cm 2 /V·s (Non-Patent Document 5). It has also been reported that a hole mobility of 320 cm 2 /V・s can be obtained by adding Sn to Ge, which is the highest hole mobility ever obtained in a low-temperature synthetic thin film on an insulator. This is the highest value among those reported (Non-Patent Document 6).

G. Taraschi, A.J. Pitera, and E.A. Fitzgerald, Solid-State. Electronics. 48, 1297 (2004).G. Taraschi, A.J. Pitera, and E.A. Fitzgerald, Solid-State. Electronics. 48, 1297 (2004). T. Matsui, M. Kondo, K. Ogata, T. Ozawa, and M. Isomura, Appl. Phys. Lett. 89, 142115 (2006).T. Matsui, M. Kondo, K. Ogata, T. Ozawa, and M. Isomura, Appl. Phys. Lett. 89, 142115 (2006). K. Usuda, Y. Kamata, Y. Kamimuta, T. Mori, M. Koike, and T. Tezuka, Appl. Phys. Express 7, 56501 (2014).K. Usuda, Y. Kamata, Y. Kamimuta, T. Mori, M. Koike, and T. Tezuka, Appl. Phys. Express 7, 56501 (2014). K. Kasahara, Y. Nagatomi, K. Yamamoto, H. Higashi, M. Nakano, S. Yamada, D. Wang, H. Nakashima, and K. Hamaya, Appl. Phys. Lett. 107, 142102 (2015).K. Kasahara, Y. Nagatomi, K. Yamamoto, H. Higashi, M. Nakano, S. Yamada, D. Wang, H. Nakashima, and K. Hamaya, Appl. Phys. Lett. 107, 142102 (2015). K. Toko, I. Nakao, T. Sadoh, T. Noguchi, and M. Miyao, Solid-State. Electronics. 53, 1159 (2009).K. Toko, I. Nakao, T. Sadoh, T. Noguchi, and M. Miyao, Solid-State. Electronics. 53, 1159 (2009). T. Sadoh, Y. Kai, R. Matsumura, K. Moto, and M. Miyao, Appl. Phys. Lett. 109, 232106 (2016).T. Sadoh, Y. Kai, R. Matsumura, K. Moto, and M. Miyao, Appl. Phys. Lett. 109, 232106 (2016).

本発明は、かかる事情に鑑みてなされたものであり、基材にダメージを与える熱負荷を低減し、デバイス動作させたときに、従来よりも高いキャリア移動度や発電効率を実現する半導体装置と、その製造方法を提供することを目的としている。 The present invention has been made in view of the above circumstances, and provides a semiconductor device and a semiconductor device that reduce the heat load that damages the base material and achieve higher carrier mobility and power generation efficiency than before when the device is operated. , the purpose is to provide a manufacturing method thereof.

本発明は、上記課題を解決するため、以下の手段を提供する。
(1)本発明の一態様に係る半導体装置は、基材と、基材の一面に形成された半導体膜とを有し、前記半導体膜は、平均粒径が1μm以上の結晶粒子からなる多結晶膜である。
(2)(1)に記載の半導体装置は、前記半導体膜の厚さが、50nm以上であることが好ましい。
(3)(1)または(2)のいずれかに記載の半導体装置は、前記結晶粒子がGeからなることが好ましい。
(4)(1)または(2)のいずれかに記載の半導体装置は、前記結晶粒子がSiGeからなることが好ましい。
(5)(1)または(2)のいずれかに記載の半導体装置は、前記結晶粒子がSiからなることが好ましい。
(6)本発明の一態様に係る半導体装置の製造方法は、(1)~(5)のいずれか一つに記載の半導体装置の製造方法であって、前記基材を加熱しながら、前記基材の一面に非晶質の半導体膜を形成する第一工程と、前記半導体膜を加熱して、前記半導体膜の固相成長を促す第二工程と、を有し、前記第一工程での加熱温度を、前記半導体膜に結晶核が発生する温度の50%以上100%未満となるように調整する。
(7)(6)に記載の半導体装置の製造方法は、前記第一工程での加熱温度を、前記半導体膜を構成する粒子の密度が、同じ材料の結晶における粒子の密度の98%以上102%未満となるように調整することが好ましい。
(8)(6)または(7)のいずれかに記載の半導体装置の製造方法は、前記第一工程での加熱温度を、100℃以上700℃以下とすることが好ましい。
(9)(6)~(8)のいずれか一つに記載の半導体装置の製造方法は、前記第二工程での加熱温度を、350℃以上800℃以下とすることが好ましい。
The present invention provides the following means to solve the above problems.
(1) A semiconductor device according to one aspect of the present invention includes a base material and a semiconductor film formed on one surface of the base material, and the semiconductor film is composed of polycrystalline grains having an average grain size of 1 μm or more. It is a crystalline film.
(2) In the semiconductor device according to (1), it is preferable that the semiconductor film has a thickness of 50 nm or more.
(3) In the semiconductor device according to either (1) or (2), it is preferable that the crystal particles are made of Ge.
(4) In the semiconductor device according to either (1) or (2), it is preferable that the crystal particles are made of SiGe.
(5) In the semiconductor device according to either (1) or (2), it is preferable that the crystal particles are made of Si.
(6) A method for manufacturing a semiconductor device according to one aspect of the present invention is the method for manufacturing a semiconductor device according to any one of (1) to (5), wherein while heating the base material, a first step of forming an amorphous semiconductor film on one surface of a base material; a second step of heating the semiconductor film to promote solid phase growth of the semiconductor film; The heating temperature is adjusted to be 50% or more and less than 100% of the temperature at which crystal nuclei are generated in the semiconductor film.
(7) In the method for manufacturing a semiconductor device according to (6), the heating temperature in the first step is such that the density of particles constituting the semiconductor film is 98% or more of the density of particles in a crystal of the same material. It is preferable to adjust it so that it is less than %.
(8) In the method for manufacturing a semiconductor device according to any one of (6) and (7), the heating temperature in the first step is preferably 100°C or more and 700°C or less.
(9) In the method for manufacturing a semiconductor device according to any one of (6) to (8), the heating temperature in the second step is preferably 350° C. or more and 800° C. or less.

本発明の半導体装置は、その製造過程において、結晶核が発生しない範囲で結晶に近い密度の非晶質膜を形成し、これを固相成長させることによって得られる半導体膜を有している。この半導体膜は、大粒径化した結晶粒子からなる多結晶膜であるため、本発明の半導体装置をデバイス動作させたときに、従来よりも高いキャリア移動度を実現することができる。 The semiconductor device of the present invention has a semiconductor film obtained by forming an amorphous film with a density close to that of a crystal within a range in which crystal nuclei are not generated during the manufacturing process, and growing the amorphous film in a solid phase. Since this semiconductor film is a polycrystalline film made of crystal grains having a large grain size, when the semiconductor device of the present invention is operated as a device, it is possible to realize higher carrier mobility than in the past.

本発明での半導体膜は、固相成長に必要な加熱温度が低減するため、基材にダメージを与えるような熱的負荷を軽減することができる。 In the semiconductor film of the present invention, since the heating temperature required for solid phase growth is reduced, it is possible to reduce the thermal load that would damage the base material.

本発明の半導体装置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device of the present invention. 本発明の半導体装置の製造過程について説明する図である。FIG. 3 is a diagram illustrating a manufacturing process of a semiconductor device of the present invention. (a)、(b)本発明の半導体装置の製造方法において、第一工程での処理温度と、最終的に形成される半導体膜の粒子密度との関係を示すグラフである。(a), (b) are graphs showing the relationship between the processing temperature in the first step and the particle density of the semiconductor film finally formed in the method for manufacturing a semiconductor device of the present invention. (a)~(c)本発明の半導体装置の製造方法において、第一工程での処理温度に対応して、最終的に形成される半導体膜のEBSD画像である。(a) to (c) are EBSD images of semiconductor films finally formed in accordance with the processing temperature in the first step in the method for manufacturing a semiconductor device of the present invention. 本発明の半導体装置の製造方法において、第一工程での処理温度と、最終的に形成される半導体膜の粒子径との関係を示すグラフである。3 is a graph showing the relationship between the processing temperature in the first step and the particle size of the semiconductor film finally formed in the method for manufacturing a semiconductor device of the present invention. 本発明の半導体装置の製造方法において、第一工程での処理温度と、最終的に形成される半導体膜の正孔密度および正孔移動度との関係を示すグラフである。3 is a graph showing the relationship between the processing temperature in the first step and the hole density and hole mobility of the finally formed semiconductor film in the method for manufacturing a semiconductor device of the present invention.

以下、本発明について、図を適宜参照しながら詳細に説明する。以下の説明で用いる図は、本発明の特徴を分かりやすくするために、便宜上特徴となる部分を拡大して示している場合があり、各構成要素の寸法比率等は実際とは異なっていることがある。また、以下の説明において例示される材料、寸法等は一例であって、本発明はそれらに限定されるものではなく、本発明の効果を奏する範囲で適宜変更して実施することが可能である。 Hereinafter, the present invention will be described in detail with reference to the drawings as appropriate. In the figures used in the following explanation, characteristic parts of the present invention may be enlarged for convenience in order to make it easier to understand, and the dimensional ratios of each component may differ from the actual ones. There is. Further, the materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not limited thereto, and can be implemented with appropriate changes within the scope of achieving the effects of the present invention. .

[半導体装置の構成]
図1は、本発明の一実施形態に係る半導体装置100の断面図である。半導体装置100は、基材101と、基材の一面101aに形成(合成)された半導体膜(半導体薄膜)102とを有している。
[Semiconductor device configuration]
FIG. 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a base material 101 and a semiconductor film (semiconductor thin film) 102 formed (synthesized) on one surface 101a of the base material.

基材101は、SiO、ガラス、プラスティック等の絶縁体、それらを搭載した基板、あるいはLSIチップ等からなる。 The base material 101 is made of an insulator such as SiO 2 , glass, or plastic, a substrate on which the insulator is mounted, an LSI chip, or the like.

半導体膜102は、薄膜形成が可能なあらゆる材料、例えばGe、SiGe、Si、GeSn、SiC、GaAs、InP、GaN、ZnSe、CdS、ZnO等の大粒径化した結晶粒子からなる多結晶膜である。結晶粒子の平均粒径は、1μm以上であればよく、5μm以上30μm以下であれば好ましく、30μm程度であればより好ましい。 The semiconductor film 102 is a polycrystalline film made of large crystal grains of any material that can be formed into a thin film, such as Ge, SiGe, Si, GeSn, SiC, GaAs, InP, GaN, ZnSe, CdS, and ZnO. be. The average particle size of the crystal particles may be 1 μm or more, preferably 5 μm or more and 30 μm or less, and more preferably about 30 μm.

半導体膜102の厚さは、50nm以上であればよく、50nm以上5000nm以下であれば好ましい。 The thickness of the semiconductor film 102 may be 50 nm or more, and preferably 50 nm or more and 5000 nm or less.

[半導体装置の製造方法]
半導体装置100を製造するための主要な2工程について、図2を用いて説明する。
[Method for manufacturing semiconductor device]
Two main steps for manufacturing the semiconductor device 100 will be explained using FIG. 2.

(第一工程)
基材101を加熱しながら、基材の一面101に対し、Ge、SiGe、Si、GeSn、SiC、GaAs、InP、GaN、ZnSe、CdS、ZnO等の粒子102Aを堆積させ、非晶質の半導体膜102Bを形成する(図2の左側)。
(First step)
While heating the base material 101, particles 102A of Ge, SiGe, Si, GeSn, SiC, GaAs, InP, GaN, ZnSe, CdS, ZnO, etc. are deposited on one surface 101 of the base material to form an amorphous semiconductor. A film 102B is formed (left side in FIG. 2).

加熱方法、堆積方法としては、特に限定されるものではなく、一般的な方法(分子線堆積法、CVD法、スパッタリング法等)を用いることができる。分子線堆積法を用いる場合には、高真空中で粒子102Aの分子線を発生させ、これを加熱中の基材の一面101aに照射することにより、粒子102Aを堆積させて非晶質の膜102Bを形成することになる。この方法では成膜温度を低く設定することができるため、プラスティック等の耐熱性が低い基材、LSIチップ等に対して成膜する場合に、好ましい方法となる。 The heating method and deposition method are not particularly limited, and general methods (such as molecular beam deposition, CVD, and sputtering) can be used. When using the molecular beam deposition method, a molecular beam of the particles 102A is generated in a high vacuum and is irradiated onto one surface 101a of the substrate being heated, thereby depositing the particles 102A and forming an amorphous film. 102B will be formed. Since this method allows the film formation temperature to be set low, it is a preferred method when forming a film on a base material with low heat resistance such as plastic, an LSI chip, or the like.

第一工程での加熱温度は、形成される非晶質膜102Bが、できる限り結晶に近い粒子数密度(同じ材料の結晶における粒子の密度の98%以上102%未満)であり、かつ、結晶核が発生していない状態となるように調整する。つまり、半導体膜102Bに結晶核が発生しない範囲で、可能な限り大きい温度となるように調整する。 The heating temperature in the first step is such that the amorphous film 102B to be formed has a particle number density as close as possible to that of a crystal (98% or more and less than 102% of the particle density in a crystal of the same material), and Adjust so that no nuclei are generated. In other words, the temperature is adjusted to be as high as possible without generating crystal nuclei in the semiconductor film 102B.

実際には、半導体膜102Bに結晶核が発生する温度の30%以上100%未満となるように調整すればよく、50%以上100%未満となるように調整すればより好ましい。
具体的には、概ね100℃以上700℃以下となる。この温度は、形成する半導体膜102の材料と厚さに応じて調整する。例えば、Geからなる厚さ100nmの半導体膜102を形成する場合には、100~150℃とする。また、SiGe、Siからなる厚さ100nmの半導体膜102を形成する場合には、それぞれ100~650℃、500~650℃とする。
Actually, the temperature may be adjusted to be 30% or more and less than 100% of the temperature at which crystal nuclei are generated in the semiconductor film 102B, and more preferably adjusted to be 50% or more and less than 100%.
Specifically, the temperature is approximately 100°C or higher and 700°C or lower. This temperature is adjusted depending on the material and thickness of the semiconductor film 102 to be formed. For example, when forming the semiconductor film 102 made of Ge and having a thickness of 100 nm, the temperature is set at 100 to 150°C. Further, when forming a 100 nm thick semiconductor film 102 made of SiGe and Si, the temperature is 100 to 650° C. and 500 to 650° C., respectively.

(第二工程)
熱処理(雰囲気は問わない)を行い、第一工程で形成された非晶質の半導体膜102Bの固相成長を促し、多結晶の半導体膜(多結晶膜)102Cを合成する(図2の右側)。
第二工程において、加熱温度は350℃以上800℃以下とすることが好ましく、加熱時間は0.1時間以上300時間以下とすることが好ましい。
(Second process)
Heat treatment (in any atmosphere) is performed to promote solid phase growth of the amorphous semiconductor film 102B formed in the first step, and to synthesize a polycrystalline semiconductor film (polycrystalline film) 102C (see right side of FIG. 2). ).
In the second step, the heating temperature is preferably 350°C or more and 800°C or less, and the heating time is preferably 0.1 hour or more and 300 hours or less.

第一工程での加熱温度を上述したように調整することにより、形成される半導体膜102Cは、1μm以上の大粒径の粒子からなる多結晶膜となる。 By adjusting the heating temperature in the first step as described above, the formed semiconductor film 102C becomes a polycrystalline film made of particles with a large grain size of 1 μm or more.

第一工程および第二工程を経て得られた半導体装置100は、その製造過程において、結晶核が発生しない範囲で結晶に近い密度の非晶質膜102Bを形成し、これを固相成長させることによって得られる多結晶の半導体膜102Cを有している。この半導体膜102Cは、1μm以上の大粒径化した結晶粒子からなる多結晶膜であるため、半導体装置100をデバイス動作させたときに、従来よりも高いキャリア移動度を実現することができる。例えば、Geからなる厚さ100nmの半導体膜においては、正孔移動度を340cm/V・sまで向上させることができる。また、Geからなる厚さ300nmの半導体膜においては、正孔移動度を380cm/V・sまで向上させることができる。 In the manufacturing process of the semiconductor device 100 obtained through the first and second steps, an amorphous film 102B having a density close to that of a crystal is formed within a range where crystal nuclei are not generated, and this is grown in a solid phase. It has a polycrystalline semiconductor film 102C obtained by. Since this semiconductor film 102C is a polycrystalline film made of crystal grains with a large grain size of 1 μm or more, when the semiconductor device 100 is operated as a device, it is possible to achieve higher carrier mobility than in the past. For example, in a semiconductor film made of Ge and having a thickness of 100 nm, the hole mobility can be improved to 340 cm 2 /V·s. Further, in a semiconductor film made of Ge and having a thickness of 300 nm, the hole mobility can be improved to 380 cm 2 /V·s.

半導体膜102を構成する結晶の粒径が1μmより小さい場合、粒界によるキャリアの散乱が顕著となるため、本発明と同等の移動度を得ることはできない。 If the grain size of the crystals constituting the semiconductor film 102 is smaller than 1 μm, carrier scattering due to grain boundaries becomes significant, making it impossible to obtain a mobility equivalent to that of the present invention.

以上のように、本実施形態に係る半導体装置100は、その製造過程において、結晶核が発生しない範囲で結晶に近い密度の非晶質膜102Bを形成し、これを固相成長させることによって得られる半導体膜102Cを有している。この半導体膜102Cは、1μm以上の大粒径化した結晶粒子からなる多結晶膜であるため、従来よりも高いキャリア移動度を実現することができる。 As described above, the semiconductor device 100 according to the present embodiment is obtained by forming an amorphous film 102B with a density close to that of a crystal within a range in which crystal nuclei are not generated during its manufacturing process, and performing solid phase growth on the amorphous film 102B. It has a semiconductor film 102C. Since this semiconductor film 102C is a polycrystalline film made of crystal grains with a large grain size of 1 μm or more, it is possible to achieve higher carrier mobility than in the past.

本実施形態での半導体膜102Cでは、固相成長に必要な加熱温度が低減する。例えばGeにおいては、基材101にダメージを与えるような500℃以上の高温処理を行うことなく形成することができる。そのため、基材101として、LSIチップや耐熱性の低いガラス、プラスティック等を幅広く用いることができる。 In the semiconductor film 102C in this embodiment, the heating temperature required for solid phase growth is reduced. For example, Ge can be formed without performing high-temperature treatment of 500° C. or higher that would damage the base material 101. Therefore, as the base material 101, a wide variety of materials such as LSI chips, glass with low heat resistance, plastic, etc. can be used.

以下、実施例により本発明の効果をより明らかなものとする。なお、本発明は、以下の実施例に限定されるものではなく、その要旨を変更しない範囲で適宜変更して実施することができる。 Hereinafter, the effects of the present invention will be made clearer by way of Examples. It should be noted that the present invention is not limited to the following examples, and can be implemented with appropriate changes without changing the gist thereof.

(実施例1)
分子線堆積法により、石英ガラス基板上に、基板温度Tを50℃~200℃の範囲で設定した状態で、ゲルマニウム(Ge)粒子を堆積させ、厚さ100nmのGe薄膜を形成(蒸着)した(第一工程)。成膜レートを1nm/minとし、成膜時間を100分間とした。
(Example 1)
By molecular beam deposition, germanium (Ge) particles are deposited on a quartz glass substrate with the substrate temperature T d set in the range of 50°C to 200°C to form a 100 nm thick Ge thin film (evaporation). (first step). The film formation rate was 1 nm/min, and the film formation time was 100 minutes.

その後、第一工程を経た試料を、窒素雰囲気とした電気炉内に導入し、第一工程で形成したGe薄膜に対し、375℃で140時間、400℃で60時間、450℃で5時間の熱処理を行い、固相成長を促した(第二工程)。 After that, the sample that underwent the first step was introduced into an electric furnace with a nitrogen atmosphere, and the Ge thin film formed in the first step was heated at 375°C for 140 hours, at 400°C for 60 hours, and at 450°C for 5 hours. Heat treatment was performed to promote solid phase growth (second step).

第一工程で形成したGe薄膜に対し、X線反射率測定(XRR)を行った結果を図3(a)のグラフに示す。グラフの横軸は試料の傾斜角(2θ)[deg]を示し、縦軸は反射光の強度[a.u.]を示している。 The graph of FIG. 3(a) shows the results of X-ray reflectance measurement (XRR) performed on the Ge thin film formed in the first step. The horizontal axis of the graph shows the tilt angle (2θ) [deg] of the sample, and the vertical axis shows the intensity of reflected light [a. u. ] is shown.

この測定結果に基づいて、第一工程で設定した基板温度Tに対応する、Ge薄膜の粒子密度を算出した。算出結果を図3(b)のグラフに示す。グラフの横軸は基板温度Td[℃]を示し、縦軸は粒子密度[g/cm]を示している。Geが結晶化した場合の粒子密度は約5.34[g/cm]と推定され、これを一点鎖線で示している。 Based on this measurement result, the particle density of the Ge thin film corresponding to the substrate temperature T d set in the first step was calculated. The calculation results are shown in the graph of FIG. 3(b). The horizontal axis of the graph represents the substrate temperature Td [° C.], and the vertical axis represents the particle density [g/cm 3 ]. The particle density when Ge is crystallized is estimated to be about 5.34 [g/cm 3 ], and this is shown by the dashed line.

粒子密度に着目すると、Ge薄膜の構成粒子は、基板温度Tを低く設定して形成した場合には、低密度の非晶質の構造をとるが、設定温度を上げるにつれて緻密化し、100℃以上とした場合には、粒子密度が結晶に漸近することが分かる。 Focusing on particle density, the constituent particles of the Ge thin film assume a low-density amorphous structure when formed at a low substrate temperature Td , but become denser as the set temperature increases, and at 100°C In the above case, it can be seen that the particle density approaches asymptotically to the crystal.

第二工程を経て得られた半導体装置に対し、ラマン分光測定を行ったところ、第一工程においてT>175℃とした場合においては、堆積時の核発生が確認された。 When Raman spectroscopy was performed on the semiconductor device obtained through the second step, it was confirmed that nucleation occurred during deposition when T d >175° C. in the first step.

また、Ge薄膜の形成時に設定する基板温度Tdを高くするほど、第二工程での核の成長速度は上昇する傾向にあり、例えば、Tを100℃以上とした場合には、375℃、140時間程度の熱処理で結晶化することが確認された。この温度(375℃)は、プラスティック上での薄膜合成も可能とする温度である。 Furthermore, the higher the substrate temperature Td set at the time of forming the Ge thin film, the higher the growth rate of nuclei in the second step. For example, when Td is 100°C or higher, 375°C, It was confirmed that crystallization occurred after heat treatment for about 140 hours. This temperature (375° C.) is a temperature that also allows thin film synthesis on plastic.

第二工程を経て得られた多結晶Ge膜の構成粒子の粒径について、電子線後方散乱回折(EBSD)法を用いて評価した。 The particle size of the constituent particles of the polycrystalline Ge film obtained through the second step was evaluated using an electron beam backscatter diffraction (EBSD) method.

図4(a)~(c)は、基板温度Tdを50℃、100℃、200℃とした場合のEBSD画像である。これらのEBSD画像から、多結晶Ge膜の結晶方位は、Tを50℃、200℃とした場合にはランダムであるのに対し、Tを100℃とした場合には特定の方向に優先配向していることが分かる。また、Tを100℃とした場合には1μm以上の結晶粒が得られていることが分る。 FIGS. 4A to 4C are EBSD images when the substrate temperature Td is 50°C, 100°C, and 200°C. From these EBSD images, the crystal orientation of the polycrystalline Ge film is random when T d is 50℃ and 200℃, but when T d is 100℃, it has priority in a specific direction. It can be seen that it is oriented. Furthermore, it can be seen that when T d is 100° C., crystal grains of 1 μm or more are obtained.

図5は、多結晶Ge膜の構成粒子の粒径と、第一工程で設定した基板温度Tdとの関係を示すグラフである。グラフの横軸は基板温度T[℃]を示し、縦軸は粒径[μm]を示している。ここには、第二工程の熱処理温度Tを375℃、400℃、450℃とした場合の粒径を、それぞれ四角プロット、三角プロット、円プロットで示している。 FIG. 5 is a graph showing the relationship between the grain size of the constituent particles of the polycrystalline Ge film and the substrate temperature Td set in the first step. The horizontal axis of the graph shows the substrate temperature T d [°C], and the vertical axis shows the particle size [μm]. Here, the particle sizes when the heat treatment temperature T g of the second step is 375° C., 400° C., and 450° C. are shown as square plots, triangular plots, and circular plots, respectively.

Ge薄膜の粒径は、基板温度Tに強く依存しており、基板温度Tが125℃のときに最大値(約5μm)となっている。この結果は、下記〔1〕、〔2〕の事項を示唆している。
〔1〕基板温度Tが100~150℃の範囲において、非晶質Geは、その密度を結晶レベルに近づけることにより、核成長が促進され、大粒径化する。
〔2〕基板温度Tが150℃より大きい範囲において、堆積時に発生した初期核は高密度であり、固相成長時に小粒径化を促す。
The grain size of the Ge thin film strongly depends on the substrate temperature Td , and reaches its maximum value (approximately 5 μm) when the substrate temperature Td is 125°C. This result suggests the following points [1] and [2].
[1] When the substrate temperature T d is in the range of 100 to 150° C., the density of amorphous Ge is brought close to the crystal level, thereby promoting nucleus growth and increasing the grain size.
[2] In a range where the substrate temperature T d is higher than 150° C., the initial nuclei generated during deposition are dense and promote reduction in grain size during solid phase growth.

第二工程を経て得られた多結晶Ge膜の電気的特性について、van der Pauw法を用いて評価した。 The electrical properties of the polycrystalline Ge film obtained through the second step were evaluated using the van der Pauw method.

図6は、第一工程で設定した基板温度Tdと、多結晶Ge膜の正孔移動度、および正孔密度との関係を示すグラフである。グラフの横軸は基板温度T[℃]を示し、縦軸は正孔移動度(左側)、正孔密度(右側)を示している。基板温度Tを125℃とした場合に、結晶粒径を反映し、多結晶Ge膜として最低レベルの正孔密度(3×1017cm-3)および最高の正孔移動度(340cm/V・s)が得られている。 FIG. 6 is a graph showing the relationship between the substrate temperature Td set in the first step, the hole mobility of the polycrystalline Ge film, and the hole density. The horizontal axis of the graph indicates the substrate temperature T d [° C.], and the vertical axis indicates hole mobility (left side) and hole density (right side). When the substrate temperature T d is 125°C, it has the lowest hole density (3×10 17 cm -3 ) and highest hole mobility (340 cm 2 / V・s) is obtained.

(実施例2)
分子線堆積法により、石英ガラス基板上に、基板温度Tを150℃で設定した状態で、ゲルマニウム(Ge)粒子を堆積させ、厚さ300nmのGe薄膜を形成(蒸着)した(第一工程)。成膜レートを1nm/minとし、成膜時間を300分間とした。
(Example 2)
By molecular beam deposition, germanium (Ge) particles were deposited on a quartz glass substrate with the substrate temperature Td set at 150°C to form (evaporate) a Ge thin film with a thickness of 300 nm (first step). ). The film formation rate was 1 nm/min, and the film formation time was 300 minutes.

その後、第一工程を経た試料を、窒素雰囲気とした電気炉内に導入し、第一工程で形成したGe薄膜に対し、450℃で5時間の熱処理を行い、固相成長を促した(第二工程)。 Thereafter, the sample that had undergone the first step was introduced into an electric furnace with a nitrogen atmosphere, and the Ge thin film formed in the first step was heat-treated at 450°C for 5 hours to promote solid phase growth. 2 steps).

第二工程を経て得られた多結晶Ge膜の電気的特性について、実施例1と同様に評価したところ、実施例1よりもさらに高い正孔移動度380cm/V・sが得られた。 When the electrical properties of the polycrystalline Ge film obtained through the second step were evaluated in the same manner as in Example 1, a hole mobility of 380 cm 2 /V·s, which was even higher than in Example 1, was obtained.

本発明は、「高速、軽量かつフレキシブルな携帯型情報端末の開発」、「LSIの3次元化、多機能化」、「高効率と低コストを両立する多接合型太陽電池の開発」等に広く活用することができる。 The present invention is applicable to "development of high-speed, lightweight and flexible portable information terminals", "3D and multifunctional LSI", "development of multi-junction solar cells that achieve both high efficiency and low cost", etc. It can be used widely.

100・・・半導体装置、101・・・基材、101a・・・基材の一面、
102、102A・・・粒子、102B、102C・・・半導体膜。

100... Semiconductor device, 101... Base material, 101a... One side of base material,
102, 102A...Particles, 102B, 102C...Semiconductor film.

Claims (4)

基材と、
基材の一面に形成された半導体膜とを有し、
前記半導体膜は、電子線後方散乱回折法によって得られる平均粒径が1μm以上μm以下のGeからなる結晶粒子からなる多結晶Ge膜であり、
正孔移動度が250cm/V・s以上380cm/V・s以下であることを特徴とする半導体装置。
base material and
a semiconductor film formed on one surface of a base material,
The semiconductor film is a polycrystalline Ge film made of crystal grains made of Ge with an average grain size of 1 μm or more and 5 μm or less obtained by electron beam backscatter diffraction method,
A semiconductor device having a hole mobility of 250 cm 2 /V·s or more and 380 cm 2 /V·s or less.
基材と、基材の一面に形成された半導体膜とを有し、前記半導体膜は、電子線後方散乱回折法によって得られる平均粒径が1μm以上μm以下のGeからなる結晶粒子からなる多結晶膜である半導体装置の製造方法であって、
前記基材を加熱しながら、前記基材の一面に非晶質の半導体膜を形成する第一工程と、
前記半導体膜を加熱して、前記半導体膜の固相成長を促す第二工程と、を有し、
前記半導体膜はGe膜であり、
前記第一工程での加熱温度を、前記半導体膜に結晶核が発生する温度の50%以上100%未満となるように調整し、
前記第一工程での加熱温度を、前記半導体膜を構成する粒子数密度が、同じ材料の結晶における粒子の密度の98%以上102%未満となるように調整することを特徴とする半導体装置の製造方法。
It has a base material and a semiconductor film formed on one surface of the base material, and the semiconductor film is made of crystal grains made of Ge with an average grain size of 1 μm or more and 5 μm or less obtained by electron beam backscatter diffraction method. A method for manufacturing a semiconductor device that is a polycrystalline film, the method comprising:
a first step of forming an amorphous semiconductor film on one surface of the base material while heating the base material;
a second step of heating the semiconductor film to promote solid phase growth of the semiconductor film,
The semiconductor film is a Ge film,
Adjusting the heating temperature in the first step to be 50% or more and less than 100% of the temperature at which crystal nuclei are generated in the semiconductor film,
A semiconductor device characterized in that the heating temperature in the first step is adjusted so that the number density of particles constituting the semiconductor film is 98% or more and less than 102% of the density of particles in a crystal of the same material. Production method.
前記第一工程での加熱温度を、100℃以上150℃以下とすることを特徴とする請求項2に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 2, wherein the heating temperature in the first step is 100° C. or more and 150° C. or less. 前記第二工程での加熱温度を、350℃以上800℃以下とすることを特徴とする請求項2又は3のいずれかに記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 2, wherein the heating temperature in the second step is 350° C. or higher and 800° C. or lower.
JP2021007370A 2017-02-28 2021-01-20 Semiconductor device and its manufacturing method Active JP7360180B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2021007370A JP7360180B2 (en) 2017-02-28 2021-01-20 Semiconductor device and its manufacturing method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017037505A JP6985711B2 (en) 2017-02-28 2017-02-28 Manufacturing method of semiconductor device
JP2021007370A JP7360180B2 (en) 2017-02-28 2021-01-20 Semiconductor device and its manufacturing method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2017037505A Division JP6985711B2 (en) 2017-02-28 2017-02-28 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2021061451A JP2021061451A (en) 2021-04-15
JP7360180B2 true JP7360180B2 (en) 2023-10-12

Family

ID=88242087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021007370A Active JP7360180B2 (en) 2017-02-28 2021-01-20 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP7360180B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009182147A (en) 2008-01-30 2009-08-13 Sharp Corp Method of manufacturing semiconductor film and optical annealing apparatus
JP7169689B2 (en) 2018-12-12 2022-11-11 国立大学法人 東京大学 Measurement system, measurement method, and measurement program

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3178715B2 (en) * 1990-05-17 2001-06-25 セイコーエプソン株式会社 Method for manufacturing thin film semiconductor device
JPH07169689A (en) * 1993-09-29 1995-07-04 Tonen Corp Crystallization method of semiconductor film
JPH11145056A (en) * 1997-11-07 1999-05-28 Sony Corp Semiconductor material
JP2015056499A (en) * 2013-09-11 2015-03-23 東京エレクトロン株式会社 Substrate processing method and substrate processing apparatus
JP2015225962A (en) * 2014-05-28 2015-12-14 東京エレクトロン株式会社 Crystallization method of silicon layer and method of manufacturing semiconductor device
JP2017045974A (en) * 2015-01-29 2017-03-02 学校法人 芝浦工業大学 Production method for germanium layer, germanium layer, substrate with germanium layer, germanium nanodot, substrate with germanium nanowire, laminate, thin film transistor and semiconductor element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009182147A (en) 2008-01-30 2009-08-13 Sharp Corp Method of manufacturing semiconductor film and optical annealing apparatus
JP7169689B2 (en) 2018-12-12 2022-11-11 国立大学法人 東京大学 Measurement system, measurement method, and measurement program

Also Published As

Publication number Publication date
JP2021061451A (en) 2021-04-15

Similar Documents

Publication Publication Date Title
Alaskar et al. Towards van der Waals epitaxial growth of GaAs on Si using a graphene buffer layer
TWI783880B (en) High resistivity soi wafers
Yang et al. Novel solution processing of high‐efficiency earth‐abundant Cu2ZnSn (S, Se) 4 solar cells
US20060208257A1 (en) Method for low-temperature, hetero-epitaxial growth of thin film cSi on amorphous and multi-crystalline substrates and c-Si devices on amorphous, multi-crystalline, and crystalline substrates
KR20130016281A (en) Photoelectronically active, chalcogen-based thin film structures incorporating tie layers
US9873938B2 (en) Depositing calcium fluoride template layers for solar cells
JP2019524982A (en) IIIA nitride growth system and method
WO2016130725A1 (en) Epitaxial hexagonal materials on ibad-textured substrates
KR20130101069A (en) Microelectronic structures including cuprous oxide semiconductors and having improved p-n heterojunctions
US10600644B2 (en) Mono- and multilayer silicene prepared by plasma-enhanced chemical vapor deposition
JP6985711B2 (en) Manufacturing method of semiconductor device
JP7360180B2 (en) Semiconductor device and its manufacturing method
Kabacelik et al. Structural and electrical analysis of poly-Ge films fabricated by e-beam evaporation for optoelectronic applications
Ohmura et al. Mobility behavior of polycrystalline Si1-x-yGexSny grown on insulators
Hashim et al. Room-temperature deposition of silicon thin films by RF magnetron sputtering
Kumar et al. Optimization of controlled two-step liquid phase crystallization of Ge-on-Si
JP2017045974A (en) Production method for germanium layer, germanium layer, substrate with germanium layer, germanium nanodot, substrate with germanium nanowire, laminate, thin film transistor and semiconductor element
TWI827204B (en) Method for manufacturing crystallized laminated structure
Rahman et al. Influence of thermal annealing on CdTe thin film deposited by thermal evaporation technique
Imajo et al. Fabrication of SrGe 2 thin films on Ge (100),(110), and (111) substrates
KR102182519B1 (en) SnS Film Manufacturing Method, SnS Film, and Photovoltaic Device Using It
JP7232499B2 (en) Semiconductor device, manufacturing method thereof, and photoelectric conversion device
Chaurasia et al. High electron mobility large grain polycrystalline epitaxial Germanium on Silicon using liquid phase crystallization for III-V photovoltaic applications
Liu et al. Epitaxial Growth of Ge on Si by Magnetron Sputtering
Maximenko et al. Low temperature growth of Germanium buffer films by ion beam sputter process

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210219

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20211214

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220214

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20220214

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20220712

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221012

C60 Trial request (containing other claim documents, opposition documents)

Free format text: JAPANESE INTERMEDIATE CODE: C60

Effective date: 20221012

C11 Written invitation by the commissioner to file amendments

Free format text: JAPANESE INTERMEDIATE CODE: C11

Effective date: 20221025

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20221124

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20221214

C21 Notice of transfer of a case for reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C21

Effective date: 20221220

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20230120

C211 Notice of termination of reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C211

Effective date: 20230124

C22 Notice of designation (change) of administrative judge

Free format text: JAPANESE INTERMEDIATE CODE: C22

Effective date: 20230411

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230726

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230922

R150 Certificate of patent or registration of utility model

Ref document number: 7360180

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150