JP2018142664A - Nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device with long life span and high reliability.SOLUTION: A nitride semiconductor device 100c comprises: a laminate structure part 105; a first main electrode 110c and a second main electrode 120 extended to a first direction; and a lead-out wiring that is connected to the second main electrode 120, and is extended to one direction in a first direction on the second main electrode 120. The first main electrode 110c includes a first tip 111c in an end part on the side where the lead-out wiring is extended, and the second main electrode 120 includes a second tip 121 on an end part of the side where the lead-out wiring is extended and an inclined part 123 in which a width in the second direction is reduced as it approaches to the second tip 121 on the second tip 121 side in the first direction. The lead-out wiring includes a region 165 projected from the inclined part 123 to the second direction, and an end on a central side of the second main electrode 120 of the inclined part 123 is arranged on the second tip 121 side in the first direction from the first tip 111c.SELECTED DRAWING: Figure 1G

Description

  The present disclosure relates to a nitride semiconductor device, and more particularly, to a nitride semiconductor device such as a transistor or a diode used in an inverter, a power conditioner, a power supply circuit, or the like.

  In recent years, field effect transistors (FETs) have been actively developed as high-frequency, high-power devices using gallium nitride (GaN) -based nitride semiconductors.

  By using GaN and the same nitride semiconductors, aluminum nitride (AlN) and indium nitride (InN), various mixed crystals can be formed. In these nitride semiconductor heterojunctions, a high-mobility and high-concentration two-dimensional electron gas (2-Dimensional Electron Gas, 2DEG) layer is generated at the junction interface by spontaneous polarization or piezo-polarization even without impurity doping. There is a feature to do. FETs and Schottky Barrier Diodes (SBD) using the 2DEG layer as carriers are attracting attention as high-frequency and high-power devices.

  A GaN-FET using a 2DEG layer is a lateral device in which current flows in a horizontal direction with respect to a semiconductor substrate. On the other hand, currently widely used power MOS (Metal-Oxide Semiconductor) transistors and IGBTs (Insulated Gate Bipolar Transistors) using Si semiconductors are vertical devices in which current flows in a direction perpendicular to the semiconductor substrate. . In a horizontal device, unlike a vertical device, a source electrode that is a ground electrode and a drain electrode to which a high voltage is applied exist on the same surface side, so that a high voltage is applied over a short distance. Therefore, attention must be paid to the breakdown voltage design of the device more than the vertical device. Furthermore, in the case of a GaN-FET using a 2DEG layer, this 2DEG layer is generally composed of a GaN channel layer without impurity doping and an AlGaN layer with a thickness of about 10 nm to 100 nm formed thereon without impurity doping. Formed at the interface. Therefore, in the GaN-FET, a large current flows from the semiconductor surface to a very shallow region of about 10 nm to 100 nm. For this reason, in the power transistor (GaN power transistor) having a large gate width in the GaN-FET, it is important to design a device for ensuring reliability such as a heat dissipation design, a design in which current flows uniformly, and a design in which electric field concentration does not occur. It becomes.

  One of the major problems related to reliability in the GaN-FET is a phenomenon called current collapse in which electrons trapped on the semiconductor surface reduce the number of electrons in the channel and increase the on-resistance. So far, as a method of suppressing this current collapse, a method of disposing trapped electrons by disposing a hole injection electrode in the periphery of the drain electrode has been disclosed (Patent Document 1). .

  As another reliability-related problem in GaN-FETs, it has been reported that the dynamic breakdown voltage when a single on-pulse is applied to the gate is significantly lower than the static off-breakdown voltage (patent) Reference 2). Patent Document 2 discloses a structure in which current does not concentrate at the tip of the drain electrode, considering that the cause of the dynamic breakdown voltage drop is current concentration at the tip of the drain electrode.

International Publication No. 2014/174810 JP 2013-021361 A

  The inventors conducted a test for continuous hard switching operation in order to investigate the reliability of the GaN-FET assuming a long-term actual use state. The test will be described with reference to the drawings. FIG. 7 is a circuit diagram showing a configuration of a circuit used in a continuous hard switching test of a GaN-FET. FIG. 8 is a graph showing a locus (locus) of voltage and current applied to the GaN-FET in the continuous hard switching test. FIG. 8 shows the drain current and the drain voltage locus (locus) in the switching operation of the GaN-FET. FIG. 9 is a plan view showing a layout of a conventional GaN-FET used in this test.

  As shown in FIG. 7, since the inductance L is used as a load in the circuit, a high voltage and a high current are simultaneously applied to the GaN-FET during switching. For this reason, as shown in a region surrounded by a dotted line in FIG. 8, a high voltage and a high current are simultaneously applied to the GaN-FET at the time of turn-on and turn-off.

  As shown in FIG. 9, in this GaN-FET, source electrodes 1011 and drain electrodes 1005 are alternately arranged. The source electrode 1011 and the drain electrode 1005 are connected to the source electrode wiring 1012 and the drain electrode wiring 1006, respectively. A gate electrode 1010 is disposed between the source electrode 1011 and the drain electrode 1005. Furthermore, a hole injection portion 1007 composed of p-GaN and an electrode is disposed around the drain electrode 1005. At the time of switching in which a high voltage and a high current are applied simultaneously, holes are injected from the hole injection portion 1007 and electrons trapped around the drain electrode 1005 are extinguished to suppress current collapse.

  When continuous hard switching was performed using this GaN-FET, destruction of the GaN-FET occurred about 20 minutes after the start of the test. When the broken GaN-FET was examined, the drain electrode wiring 1006 shown in FIG. 9 is located near the drain electrode 1005 in the electrode vicinity region 1030 located in the vicinity of the protruding (protruded) portion, particularly near the drain electrode 1005. It was confirmed that the breakage occurred at the position (marked with X in FIG. 9). The tip of the drain electrode 1005 has a substantially semicircular shape in which the electrode width (lateral width in FIG. 9) is continuously narrowed in order to alleviate the electric field concentration, but the breakdown occurred in the vicinity of this tip. For this reason, the conventional GaN-FET has a short life and is not sufficiently reliable.

  Accordingly, the present disclosure provides a long-life and high-reliability nitride semiconductor device.

  In order to solve the above-described problem, an aspect of the nitride semiconductor device according to the present disclosure includes a substrate, a first nitride semiconductor layer disposed above the substrate, and the first nitride semiconductor layer. And a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer, and the first nitride semiconductor layer and the second nitride semiconductor layer. A laminated structure having an active region in which a two-dimensional electron gas induced at the interface exists; a first main electrode disposed above the active region and extending in a first direction in a plan view with respect to the substrate; A second main electrode disposed in a position above the active region spaced from the first main electrode in a second direction perpendicular to the first direction in plan view with respect to the substrate and extending in the first direction; And disposed above the second main electrode, A lead wire electrically connected to the second main electrode, the lead wire extending from above the second main electrode to one side in the first direction, the first main electrode comprising: The second main electrode has a first tip at an end portion on the side where the lead-out wiring extends among both end portions in the first direction, and the second main electrode has the first end in the first direction. A width in the second direction is closer to the second front end on the second front end side in the first direction and has a second front end at the end on the side where the lead wiring extends. The lead-out wiring has a region that protrudes in a second direction from the inclined portion in a plan view with respect to the substrate, and has a region that is included in the active region at a lower portion; The center side of the second main electrode in the first direction End, from the first tip, is disposed in the second distal end side in the first direction.

  According to one embodiment of the present disclosure, it is possible to provide a nitride semiconductor device having a long lifetime and high reliability.

1A is a plan view showing a layout of the nitride semiconductor device according to the first embodiment. FIG. 1B is a cross-sectional view showing the 1B-1B cross section in FIG. 1A of the nitride semiconductor device according to the first embodiment. 1C is a cross-sectional view showing the 1C-1C cross section in FIG. 1A of the nitride semiconductor device according to the first exemplary embodiment. FIG. 1D is a plan view showing a layout of a nitride semiconductor device including a control electrode having a configuration different from that of the control electrode according to the first embodiment. FIG. 1E is a graph showing the continuous hard switching operation lifetime of the nitride semiconductor device according to the first embodiment and the nitride semiconductor device according to the comparative example. 1F is a plan view showing another configuration example of the first main electrode according to Embodiment 1. FIG. 1G is a plan view showing still another configuration example of the first main electrode according to Embodiment 1. FIG. FIG. 1H is a plan view showing a layout of the nitride semiconductor device according to the modification of the first embodiment. 1I is a cross-sectional view showing a 1I-1I cross section in FIG. 1H of a nitride semiconductor device according to a modification of the first embodiment. 1J is a cross sectional view showing a 1J-1J cross section in FIG. 1H of a nitride semiconductor device according to a modification of the first embodiment. FIG. 2A is a plan view showing a layout of the nitride semiconductor device according to the second embodiment. 2B is a cross-sectional view showing the 2B-2B cross section in FIG. 2A of the nitride semiconductor device according to the second embodiment. 2C is a cross-sectional view showing the 2C-2C cross section in FIG. 2A of the nitride semiconductor device according to the second embodiment. FIG. 2D is a cross-sectional view perpendicular to the first direction of the nitride semiconductor device used for examining an appropriate positional relationship between the hole injection portion and the second lead-out wiring according to the second embodiment. FIG. 2E is a graph showing the relationship between the XY distance and the voltage at which the current collapse phenomenon occurs. FIG. 3A is a plan view showing a layout of the nitride semiconductor device according to the third embodiment. 3B is a cross-sectional view showing the 3B-3B cross section in FIG. 3A of the nitride semiconductor device according to the third embodiment. 3C is a cross-sectional view showing the 3C-3C cross section in FIG. 3A of the nitride semiconductor device according to the third embodiment. FIG. 4A is a plan view showing a layout of the nitride semiconductor device according to the fourth embodiment. 4B is a cross-sectional view showing the 4B-4B cross section in FIG. 4A of the nitride semiconductor device according to the fourth embodiment. FIG. 4C is a cross sectional view showing a 4C-4C cross section in FIG. 4A of the nitride semiconductor device according to the fourth embodiment. FIG. 4D is a cross-sectional view of an electrode structure having a recess used in a comparative experiment. FIG. 4E is a cross-sectional view of an electrode structure having no recess used in a comparative experiment. FIG. 4F is a graph showing the results of a comparative experiment of the hole injection effect with and without the recess. FIG. 5A is a plan view showing a layout of the nitride semiconductor device according to the fifth embodiment. FIG. 5B is a cross sectional view showing a 5B-5B cross section in FIG. 5A of the nitride semiconductor device according to the fifth embodiment. FIG. 5C is a cross sectional view showing the 5C-5C cross section in FIG. 5A of the nitride semiconductor device according to the fifth embodiment. FIG. 6A is a plan view showing a layout of the nitride semiconductor device according to the sixth embodiment. 6B is a cross-sectional view showing the 6B-6B cross section in FIG. 6A of the nitride semiconductor device according to the sixth embodiment. FIG. 6C is a cross-sectional view of the nitride semiconductor device according to the modification of the sixth embodiment. FIG. 7 is a circuit diagram showing a configuration of a circuit used in a continuous hard switching test of a GaN-FET. FIG. 8 is a graph showing the locus of voltage and current applied to the GaN-FET in the continuous hard switching test. FIG. 9 is a plan view showing a layout of a conventional GaN-FET used in the continuous hard switching test. 10 is a cross-sectional view showing a 10-10 cross section of the conventional GaN-FET shown in FIG.

(Knowledge that became the basis of this disclosure)
The inventors of the present invention conducted intensive studies on the breakdown generated near the tip of the drain electrode in the continuous hard switching test of the GaN-FET. First, as a result of observing the temperature and on-resistance of the GaN-FET performing the continuous hard switching test during the test, a rapid increase in temperature and on-resistance immediately before the breakdown was not observed. That is, it was found that current collapse as shown in Patent Document 1 did not occur in the GaN-FET. Furthermore, it was found that the moment when the breakdown occurs is at the time of switching at the turn-on or turn-off moment, and not the period during which the GaN-FET is on or off. That is, it has been found that the occurrence of breakdown is a phenomenon that occurs when a high voltage and a high current shown in a region surrounded by a dotted line in FIG. 8 are simultaneously applied to the GaN-FET.

  Therefore, when electrons flow from the source electrode toward the drain electrode, if a high voltage is applied from the upper drain electrode wiring in the middle, a part of the flowing electrons are drained to which the high voltage is applied. It was considered that a phenomenon of jumping to the trap level existing on the semiconductor surface occurred, not the drain electrode that was attracted to the electrode wiring and originally flowed in.

  A phenomenon in which breakdown occurs at the tip of the drain electrode by this mechanism will be described with reference to FIGS. 10 is a cross-sectional view showing a 10-10 cross section of the conventional GaN-FET shown in FIG.

  As shown in FIG. 10, in a conventional GaN-FET, a drain electrode 1005 and a hole injection part 1007 are formed on a stacked structure including a GaN layer 1004 and an AlGaN layer 1003. An electron flow 1060 that flows from the source electrode 1011 (see FIG. 9) to the drain electrode 1005 exists at the junction interface between the AlGaN layer 1003 and the GaN layer 1004.

  A drain electrode wiring 1006 is formed on the drain electrode 1005. Here, the drain electrode wiring 1006 protrudes from the drain electrode 1005 toward the hole injection portion 1007 and covers the electrode vicinity region 1030.

  As shown in FIG. 9, the density of the electron flow 1060 from the source electrode 1011 toward the drain electrode 1005 is substantially uniform in the facing region where the source electrode 1011 and the drain electrode 1005 face each other. On the other hand, when the source electrode 1011 is longer than the drain electrode 1005, the electron flow 1060 converges at the tip of the drain electrode 1005, so that the density of the electron flow 1060 is higher in the vicinity of the tip of the drain electrode 1005 than the counter region. Further, the surface of the AlGaN layer 1003 in the electrode vicinity region 1030 of the drain electrode 1005 and immediately below the drain electrode wiring 1006 is directly affected by the potential of the drain electrode wiring 1006. As a result, when a high voltage and a high current shown in a region surrounded by a dotted line in FIG. 8 are applied simultaneously, many electrons 1061 are attracted to the surface of the AlGaN layer 1003 having a high potential, and FIG. Trapped as shown.

  That is, electrons 1061 trapped on the surface of the AlGaN layer 1003 immediately below the drain electrode wiring 1006 are gradually accumulated in the electrode vicinity region 1030 of the drain electrode 1005 during the continuous hard switching operation. The potential of the surface of the AlGaN layer 1003 formed by the trapped electrons 1061 and the potential of the 2DEG layer in the vicinity of the drain electrode 1005, the drain electrode wiring 1006, or the drain electrode 1005 are separated at the time of switching, so that the AlGaN layer It can be estimated that dielectric breakdown has occurred in an insulating film (not shown) formed on 1003 or the AlGaN layer 1003. For such a countermeasure against destruction by an electron trap in the vicinity of the tip of the drain electrode 1005 and immediately below the drain electrode wiring 1006, it is not sufficient to dispose the hole injection portion 1007 as disclosed in Patent Document 1. Met.

  Further, the layout design that suppresses the current concentration at the tip of the drain electrode as disclosed in Patent Document 2 is not sufficient as a countermeasure against the breakdown by the electron trap. That is, the layout design of the GaN-FET including the source electrode, the drain electrode, the drain electrode wiring, and the active region where 2DEG exists is important.

  Based on the above knowledge and considerations, the nitride semiconductor device according to the present disclosure that improves the lifetime of continuous hard switching operation by reducing the number of electrons trapped at the tip of the finger-like (long) drain electrode I came up with it.

  Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Each of the embodiments described below shows a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, component arrangement positions, connection forms, and the like shown in the following embodiments are merely examples, and are not intended to limit the present disclosure. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present disclosure are described as arbitrary constituent elements.

  Each figure is a schematic diagram and is not necessarily illustrated strictly. Moreover, in each figure, the same code | symbol is attached | subjected to the substantially same structure, The overlapping description is abbreviate | omitted or simplified.

  In addition, in this specification, the terms “upper” (or “upper”) and “lower” (or “lower”) refer to the upper direction (vertically upper) and the lower direction (vertically lower) in absolute space recognition. It is not intended to indicate, but is used as a term defined by a relative positional relationship based on the stacking order in the stacking configuration. In addition, the terms “upper” and “lower” are used not only when two components are spaced apart from each other and there is another component between the two components. It is also applied to the case where they are arranged in close contact with each other.

(Embodiment 1)
The nitride semiconductor device according to the first embodiment will be described below with reference to the drawings.

  FIG. 1A is a plan view showing a layout of nitride semiconductor device 100 according to the present embodiment. FIG. 1B is a cross-sectional view showing a 1B-1B cross section in FIG. 1A of nitride semiconductor device 100 according to the present embodiment. FIG. 1C is a cross-sectional view showing a 1C-1C cross section in FIG. 1A of nitride semiconductor device 100 according to the present embodiment.

  Hereinafter, the configuration of nitride semiconductor device 100 will be described with reference to FIGS. 1A to 1C.

  The nitride semiconductor device 100 is a nitride semiconductor device using a nitride semiconductor. As shown in FIG. 1C, the substrate 101, the buffer layer 102, the stacked structure portion 105, the first main electrode 110, and the first 2 main electrodes 120, a control electrode 130, an insulating film 140, a first lead wire 150, and a second lead wire 160. As shown in FIG. 1A, the nitride semiconductor device 100 further includes a first aggregated wiring 170 and a second aggregated wiring 180.

  Note that, in each drawing, only a pair of the first main electrode 110 and the second main electrode 120 are shown for the nitride semiconductor device according to the present embodiment and each of the following embodiments. The nitride semiconductor device according to the embodiment has a repeated structure in which a plurality of first main electrodes 110 and a plurality of second main electrodes 120 are alternately arranged.

  The substrate 101 is a base of the nitride semiconductor device 100, and other components of the nitride semiconductor device 100 are formed above the substrate 101. The material for forming the substrate 101 is not particularly limited. In this embodiment mode, the material for forming the substrate 101 is silicon.

  The buffer layer 102 is a layer disposed between the substrate 101 and the first nitride semiconductor layer 103, and is a first layer associated with a lattice mismatch between the substrate 101 and the first nitride semiconductor layer 103. The lattice strain of the nitride semiconductor layer 103 is reduced. The configuration of the buffer layer 102 is not particularly limited as long as the lattice distortion of the first nitride semiconductor layer 103 can be reduced. In the present embodiment, the buffer layer 102 has a multilayer structure including an AlN layer and an AlGaN layer. The buffer layer 102 may have a superlattice structure. The buffer layer 102 is formed by, for example, a metal organic chemical vapor deposition (MOCVD) method (MOCVD: Metal Organic Chemical Vapor Deposition).

  The stacked structure unit 105 includes a first nitride semiconductor layer 103 and a second nitride that is stacked above the first nitride semiconductor layer 103 and has a larger band gap than the first nitride semiconductor layer 103. A semiconductor layer 104.

  The first nitride semiconductor layer 103 is a nitride semiconductor layer disposed above the substrate 101. In the present embodiment, the first nitride semiconductor layer 103 is stacked above the substrate 101 with the buffer layer 102 interposed therebetween. The configuration of the first nitride semiconductor layer 103 is not particularly limited as long as it is a nitride semiconductor layer having a band gap smaller than that of the second nitride semiconductor layer 104. In the present embodiment, the first nitride semiconductor layer 103 is made of a GaN layer having a thickness of about 2 μm.

  The second nitride semiconductor layer 104 is a nitride semiconductor layer that is disposed above the first nitride semiconductor layer 103 and has a larger band gap than the first nitride semiconductor layer 103. The configuration of the second nitride semiconductor layer 104 is not particularly limited as long as it is a nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer 103. In the present embodiment, the second nitride semiconductor layer 104 is made of an AlGaN layer having a thickness of about 50 nm.

  The first nitride semiconductor layer 103 and the second nitride semiconductor layer 104 are formed by, for example, MOCVD.

  As described above, in the multilayer structure unit 105, the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104 are sequentially formed, that is, a multilayer structure composed of an AlGaN layer / GaN layer is formed. Has been. A two-dimensional electron gas (2DEG) 106 is formed at the interface near the second nitride semiconductor layer 104 in the first nitride semiconductor layer 103 due to a polarization effect and a band gap difference generated between the GaN layer and the AlGaN layer. ing. In the present embodiment, as shown in FIG. 1A, the stacked structure portion 105 has a two-dimensional electron gas 106 induced at the interface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104. Active region 107 to be separated, and element isolation region 108 in which the two-dimensional electron gas 106 does not exist. The element isolation region 108 is formed by increasing the resistance of a two-dimensional electron gas by ion implantation of He, B, Ar, or the like, for example. The element isolation region 108 may be formed by etching away the second nitride semiconductor layer 104 made of an AlGaN layer.

  As shown in FIG. 1A, the first main electrode 110 is an electrode that is disposed above the active region 107 and extends in the first direction in a plan view with respect to the substrate 101. The first main electrode 110 is a finger-like electrode made of a laminate including, for example, Ti, Al and the like.

  The first main electrode 110 has a first end at the end of the both ends in the first direction on the side where the second lead wiring 160 extends (that is, the side opposite to the side on which the first lead wiring 150 extends). A tip 111 is provided, and a first opposite tip 112 is provided at an end on the side where the first lead-out wiring 150 extends.

  The second main electrode 120 is a finger-like electrode that is applied with a higher voltage than the first main electrode 110 in the off state, and is configured of, for example, a laminate including Ti, Al, and the like. As shown in FIG. 1A, the second main electrode 120 is positioned above the active region 107 spaced from the first main electrode 110 in a second direction perpendicular to the first direction in plan view with respect to the substrate 101. Arranged and extending in a first direction.

  The 2nd main electrode 120 has the 2nd front-end | tip 121 in the edge part by which the 2nd extraction wiring 160 is extended among the both ends in a 1st direction. Furthermore, the second main electrode 120 has an inclined portion 123 on the second tip 121 side in the first direction, the width of which decreases in the second direction as it approaches the second tip 121. The second main electrode 120 has a second opposite end 122 at the end opposite to the side from which the second lead wiring 160 extends out of both ends in the first direction. Furthermore, the second main electrode 120 has an inclined portion 124 on the second opposite tip 122 side in the first direction, the width of which decreases in the second direction as it approaches the second opposite tip 122. . With respect to the inclined portions 123 and 124, in other words, the electrode width (width in the second direction) of the second main electrode 120 is continuously narrowed at both ends in the first direction in plan view with respect to the substrate 101. It has the inclination parts 123 and 124 which have a shape. Further, the second main electrode 120 has a uniform width portion 126 having the same width in the second direction between both end portions in the first direction.

  The first main electrode 110 and the second main electrode 120 are formed by sputtering, for example, and are patterned using photolithography and dry etching.

  The insulating film 140 is an electrically insulating film formed above the laminated structure portion 105. The insulating film 140 is thicker than the first main electrode 110 and the second main electrode 120, and has an opening on almost the entire surface inside the periphery of the first main electrode 110 in a plan view with respect to the substrate 101. Through this opening, the first main wiring 110 and the first lead wiring 150 formed on the insulating film 140 are electrically connected. Similarly, the insulating film 140 has an opening on almost the entire surface inside the periphery of the second main electrode 120 in a plan view with respect to the substrate 101. Through this opening, the second main electrode 120 and the second lead wiring 160 formed on the insulating film 140 are electrically connected. The material for forming the insulating film 140 is not particularly limited as long as it is electrically insulating, and is, for example, SiN. The insulating film 140 is formed by, for example, a chemical vapor deposition (CVD) method. Each opening of the insulating film 140 is patterned using, for example, photolithography and dry etching.

  The first lead wiring 150 is a lead wiring that is disposed above the first main electrode 110 and is electrically connected to the first main electrode 110. The first lead wiring 150 is connected to the first main electrode 110 from the first main electrode 110. It extends to one side (the lower side in FIG. 1A) in the direction of. The first lead-out wiring 150 extends from the active region 107 to one element isolation region 108 (the lower side in FIG. 1A). The first lead wiring 150 is electrically connected to the first aggregate wiring 170 formed in the element isolation region 108.

  The second lead wiring 160 is a lead wiring that is disposed above the second main electrode 120 and is electrically connected to the second main electrode 120. The second lead wiring 160 is connected to the first main electrode 120 from the first main electrode 120. It extends to one side (upper side in FIG. 1A) in the direction of. The second lead wiring 160 extends from the active region 107 to one of the element isolation regions 108 (upper side in FIG. 1A). The second lead wiring 160 is electrically connected to the second aggregate wiring 180 formed in the element isolation region 108.

  The material for forming the first lead wiring 150 and the second lead wiring 160 is not particularly limited as long as it is a conductive member. The first lead wiring 150 and the second lead wiring 160 are formed by sputtering, for example, using Cu. Further, the first lead wiring 150 and the second lead wiring 160 are patterned using, for example, photolithography and dry etching. Alternatively, the first lead wiring 150 and the second lead wiring 160 may be made of Au using photolithography and electrolytic plating.

  The first aggregated wiring 170 and the second aggregated wiring 180 are lines that are electrically connected to the plurality of first lead-out lines 150 and the plurality of second lead-out lines 160, respectively. , Extending in the second direction. The first aggregated wiring 170 and the second aggregated wiring 180 are respectively connected to the plurality of first main electrodes 110 and the plurality of first interconnects via the plurality of first lead-out lines 150 and the plurality of second lead-out lines 160, respectively. A voltage is applied to the second main electrode 120.

  The material forming the first aggregated wiring 170 and the second aggregated wiring 180 is not particularly limited as long as it is a conductive member. The first aggregated wiring 170 and the second aggregated wiring 180 are formed by sputtering, for example, using Cu. The first aggregated wiring 170 and the second aggregated wiring 180 are patterned using, for example, photolithography and dry etching. The first aggregated wiring 170 and the second aggregated wiring 180 may be formed at the same time as the first extraction wiring 150 and the second extraction wiring 160.

  The control electrode 130 is an electrode that controls the amount of current flowing between the first main electrode 110 and the second main electrode 120. The control electrode 130 is disposed above the active region 107 and between the first main electrode 110 and the second main electrode 120. In this embodiment, as shown in FIGS. 1A and 1C, the control electrode 130 is between the first main electrode 110 and the second main electrode 120, and the first main electrode 110 and the second main electrode 120. It extends in the first direction at a position closer to the first main electrode 110 than the middle of the main electrode 120. As shown in FIG. 1A, the control electrode 130 is formed so as to cross the active region 107 in the first direction when the substrate 101 is viewed from above. The control electrode 130 is composed of a laminated body containing, for example, Ni, Pd, or the like. The control electrode 130 is formed by sputtering, for example, and is patterned using photolithography and dry etching. The control electrode 130 may be formed by electron beam evaporation and a lift-off method.

  Note that the configuration of the control electrode according to the present embodiment is not limited to the configuration illustrated in FIG. 1A, and may be another configuration. FIG. 1D is a plan view showing a layout of nitride semiconductor device 100a including control electrode 130a having a different configuration from control electrode 130 according to the present embodiment. As shown in FIG. 1D, the control electrode 130 a may be formed so as to surround the first main electrode 110.

  In the present embodiment, a normally-on transistor that conducts even when no bias voltage is applied to control electrode 130 or 130a is assumed. However, nitride semiconductor device 100 applies a bias voltage to control electrode 130 or 130a. If not, a normally-off transistor that is not conductive may be used.

  The control electrode 130 or 130a may be an electrode composed of a laminate including a p-type GaN layer and a metal layer such as Ni or Pd thereon. If p-type GaN is used, the effect of depleting 2DEG is great, so that a normally-off transistor can be easily obtained.

  As described above, the first main electrode 110 has the first tip 111 at the end of the first main electrode 110 in the first direction on the side where the second lead wiring 160 extends. . The second main electrode 120 has a second tip 121 at the end on the side where the second lead-out wiring 160 extends out of both ends of the second main electrode 120 in the first direction. At this time, in the present embodiment, the first tip 111 does not protrude from the second tip 121 in the first direction.

  The effect of nitride semiconductor device 100 according to the present embodiment having the above configuration will be described below with reference to the drawings. FIG. 1E is a graph showing the continuous hard switching operation lifetime of the nitride semiconductor device 100 according to the present embodiment and the nitride semiconductor device according to the comparative example. In the continuous hard switching test shown in FIG. 1E, the nitride semiconductor device used as a comparative example is the nitride semiconductor device 100 except that the first tip 111 protrudes in the first direction from the second tip 121. Has the same configuration.

  When the results of the continuous hard switching test were compared between the comparative example and the present embodiment, the life of the comparative example was 20 minutes (0.33 hours) as shown in FIG. In form, it was 500 hours. That is, in the nitride semiconductor device 100 according to the present embodiment, it is confirmed that the lifetime is improved by about 1500 times by applying a configuration in which the first tip 111 does not protrude from the second tip 121 in the first direction. did it. The continuous hard switching test is performed under acceleration conditions in which the current value and the voltage value are higher than the normal use conditions. The life of 500 hours obtained in this test corresponds to a life of 100 years or more under normal use conditions, and achieves a general life target value.

  The breakdown portion of the nitride semiconductor device of the comparative example is the tip of the second main electrode 120, whereas the breakdown portion of the nitride semiconductor device 100 according to the present embodiment is the second main electrode. It was a random position of 120 equal width portions 126. That is, by applying the configuration of the nitride semiconductor device 100 according to the present embodiment, the breakdown due to the electron trap at the tip of the second main electrode 120 as described above with reference to FIGS. 9 and 10 occurs. Suppressed. This result demonstrates that, in the nitride semiconductor device 100 according to the present embodiment, the lifetime of continuous hard switching is significantly improved by suppressing the electron trap at the tip of the second main electrode 120. ing.

  As shown in FIG. 1A, in the first main electrode 110 in the first direction, the first tip 111 does not protrude from the second tip 121 in the first direction, and the nitride semiconductor device 100 according to the present embodiment. Then, the electron flow starting from the first main electrode 110 is directed to the second main electrode 120 facing in the second direction, with a uniform electron flow density at the equal width portion 126 and equal at the inclined portion 123. It flows at a density equal to or lower than the electron flow density of the width portion 126. As a result, when a high voltage and a high current shown in a region surrounded by a dotted line in FIG. 8 are applied simultaneously, electrons having a density higher than the electron flow density of the equal width portion 126 immediately below the second lead-out wiring 160. It is considered that no current flows and electron traps in the second nitride semiconductor layer 104 can be suppressed. As a result, it is considered that the destruction does not occur in the vicinity of the second tip 121.

  The configuration of each main electrode of nitride semiconductor device 100 according to the present embodiment is not limited to the configuration shown in FIGS. 1A to 1C. Hereinafter, another configuration example of each main electrode according to the present embodiment will be described with reference to the drawings.

  FIG. 1F is a plan view showing another configuration example of the first main electrode according to the present embodiment. FIG. 1G is a plan view showing still another configuration example of the first main electrode according to the present embodiment.

  Like the nitride semiconductor device 100b including the first main electrode 110b shown in FIG. 1F, the second tip 121 protrudes in the first direction from the first tip 111b, and the second opposite tip 122. May be formed so as to protrude in the first direction from the first opposite end 112b. In this case, the electron current flowing immediately below the region 165 of the second lead-out wiring 160 extending in the second direction from the inclined portion 123 of the second main electrode 120 is the first tip as shown in FIG. 1A. It becomes smaller than the case where 111 is formed so as not to protrude from the second tip 121 in the first direction. For this reason, in the nitride semiconductor device 100 b, electron traps can be suppressed more than in the nitride semiconductor device 100.

  Further, like the nitride semiconductor device 100c having the first main electrode 110c shown in FIG. 1G, the first tip 111c of the first main electrode 110c is the first of the inclined portion 123 on the second tip 121 side. The first opposite tip 112c does not protrude in the first direction from the center end of the second main electrode 120 in the first direction, and the first direction of the inclined portion 124 on the second opposite tip 122 side The second main electrode 120 may be formed so as not to protrude in the first direction from the center end of the second main electrode 120. Furthermore, the center-side end of the second main electrode 120 in the first direction of the inclined portion 123 may be disposed closer to the second tip 121 side in the first direction than the first tip 111c. The central end of the second main electrode 120 in the first direction of the inclined portion 124 is disposed closer to the second opposite tip 122 side in the first direction than the first opposite tip 112c. Also good. In this case, the electron current flowing in the region 165 of the second lead-out wiring 160 extending in the second direction from the inclined portion of the second main electrode 120 has a second tip 121 as shown in FIG. 1F. It protrudes from one tip 111b, and the second opposite tip 122 is smaller than the case where it is formed to protrude from the first opposite tip 112b. Therefore, in the nitride semiconductor device 100c, electron traps can be suppressed more than in the nitride semiconductor device 100b.

  The portion of the second lead-out wiring 160 located above the portion of the equal width portion 126 of the second main electrode 120 that protrudes in the first direction from the first tip 111 c is the first width of the equal width portion 126. It is preferable that the second electrode does not protrude in the second direction from the end facing the main electrode 110c. Similarly, the portion of the second lead-out wiring 160 located above the portion of the equal width portion 126 of the second main electrode 120 protruding in the first direction from the first opposite end 112c is the equal width portion 126. It is preferable that the first main electrode 110c does not protrude in the second direction from the end facing the first main electrode 110c. In these cases, an electron trap due to a high voltage can be avoided in a portion immediately above the 2DEG in a portion closer to the first main electrode 110c than the equal width portion 126 of the second main electrode 120.

  In addition, a portion of the second lead-out wiring 160 where the position in the first direction coincides with the inclined portions 123 and 124 protrudes closer to the first main electrode 110 than the uniform width portion 126 in the second direction. You may form so that it may not. In this case, the position in the first direction in the region directly above 2DEG coincides with the inclined portions 123 and 124, and the position in the second direction is closer to the first main electrode 110c side than the equal width portion 126. Electron traps due to high voltage can be avoided in the portion.

  In addition, the portion of the second lead-out wiring 160 located on the active region 107 has a portion closer to the second aggregated electrode 180 than the second tip 121 in the second direction than the equal-width portion 126. It may be formed without protruding toward the main electrode 110 side. In this case, in the portion of the second lead-out wiring 160 that is closer to the second aggregated electrode 180 than the second tip 121 in the first direction and whose position in the second direction is equal to the equal width portion 126. , Avoid electronic traps. Further, the portion of the second lead-out wiring 160 located on the active region 107 may be formed without protruding in the first direction from the second opposite end 122.

(Modification of Embodiment 1)
A nitride semiconductor device according to a modification of the first embodiment will be described below with reference to the drawings.

  FIG. 1H is a plan view showing a layout of the nitride semiconductor device 100d according to the present modification. FIG. 1I is a cross-sectional view showing a 1I-1I cross section in FIG. 1H of a nitride semiconductor device 100d according to this modification. FIG. 1J is a cross-sectional view showing a 1J-1J cross section in FIG. 1H of a nitride semiconductor device 100d according to this modification.

Since the nitride semiconductor device 100d according to this modification has the same configuration as the nitride semiconductor device 100c described above with reference to FIG. 1G except for the insulating film 140d and the second lead wiring 160d, the description thereof is omitted. . In the present modification, the thickness of the insulating film 140d needs to be increased so that the potential of the second lead wiring 160d does not generate an electron trap on the surface of the second nitride semiconductor layer 104. As a result of examination by the inventors, when the insulating film 140d is SiN (relative dielectric constant 7.5), the thickness is required to be 2 μm or more. Since the necessary thickness of the insulating film is considered to be proportional to the relative dielectric constant of the insulating film, for example, when the insulating film 140d is SiO ₂ (relative dielectric constant 3.9), the thickness is 1 μm or more, polyimide (relative dielectric constant) In the case of 3.5), a thickness of 0.9 μm or more is necessary. In such a case, since the insulating film 140d has a sufficient thickness, the influence of a high voltage just above 2DEG can be ignored.

  As shown in FIG. 1H, in the second lead-out wiring 160d, at least a part of the regions 166a and 166b that do not protrude from the equal width portion 126 in the first direction and protrude from the first main electrode 110 is formed. , And may protrude toward the first main electrode 110 in the second direction. In other words, in the second lead-out wiring 160d, the portion (region 166a) located above the portion of the equal width portion 126 that protrudes in the first direction from the first tip 111c is second from the equal width portion 126. It may protrude in the direction of. In the second lead-out wiring 160 d, a portion (region 166 b) located above the portion of the equal width portion 126 that protrudes in the first direction from the first opposite end 112 c is the first width portion 126 d from the equal width portion 126. You may protrude in the direction of 2. In this case, the second lead wiring 160d functions as a drain field plate. That is, the second lead wiring 160d having the same potential as the second main electrode 120 protrudes toward the first main electrode 110 in the second direction, so that the second main wiring 110d from the first main electrode 110 side. Since a part of the lines of electric force directed to the electrode 120 side are directed to the second lead wiring 160d, electric field concentration at the end of the second main electrode 120 on the first main electrode 110 side can be reduced. Thereby, destruction of the edge part of the 2nd main electrode 120 can be suppressed.

  As shown in FIG. 1H, in the second lead-out wiring 160d, the regions 167a and 167b whose positions in the first direction coincide with the inclined portions 123 and 124 are larger than the equal-width portion 126 in the second direction. It may protrude toward the first main electrode 110 side. In this case, the portion from which the second lead-out wiring 160d protrudes functions as a drain field plate, so that an electric field relaxation effect can be obtained at the end of the second main electrode 120 on the first main electrode 110 side. Thereby, destruction of the edge part of the 2nd main electrode 120 can be suppressed.

  Further, as shown in FIG. 1H, in the first embodiment, a portion of the second lead-out wiring 160d located on the active region 107 is away from the second main electrode 120 (upward in FIG. 1H). A region 168a extending from the second tip 121 may be formed so as to protrude toward the first main electrode 110 with respect to the equal width portion 126 in the second direction. Further, as shown in FIGS. 1H and 1I, the second lead-out wiring 160d has a second position in a direction away from the second main electrode 120 (downward in FIG. 1H) in a portion located on the active region 107. A region 168b extending from the opposite-side tip 122 may be formed, and the region 168b may be formed so as to protrude toward the first main electrode 110 with respect to the equal width portion 126 in the second direction. By adopting such a structure, each region in which the second lead-out wiring 160 d protrudes from the second main electrode 120 functions as a drain field plate, and therefore the first main electrode 110 of the second main electrode 120. An electric field relaxation effect at the end portion on the side can be obtained. Thereby, destruction of the edge part of the 2nd main electrode 120 can be prevented.

(Embodiment 2)
The nitride semiconductor device according to the second embodiment will be described below. Nitride semiconductor device according to the present embodiment is different from nitride semiconductor device 100 according to the first embodiment in that it includes a hole injection portion for reducing electrons trapped on the surface of stacked structure portion 105. To do. Hereinafter, the nitride semiconductor device according to the present embodiment will be described with reference to the drawings with a focus on differences from the nitride semiconductor device 100 according to the first embodiment.

  FIG. 2A is a plan view showing a layout of nitride semiconductor device 200 according to the present embodiment. 2B is a cross-sectional view showing a 2B-2B cross section in FIG. 2A of nitride semiconductor device 200 according to the present embodiment. 2C is a cross-sectional view showing a 2C-2C cross section in FIG. 2A of nitride semiconductor device 200 according to the present embodiment.

  As shown in FIGS. 2A to 2C, the nitride semiconductor device 200 according to the present embodiment is similar to the nitride semiconductor device 100 in that the substrate 101, the buffer layer 102, the stacked structure unit 105, The main electrode 110, the second main electrode 120, the control electrode 130, the insulating film 140, the first lead wiring 150, the second lead wiring 162, the first aggregate wiring 170, the second Aggregation wiring 180 is provided. As shown in FIGS. 2A and 2B, the nitride semiconductor device 200 further injects holes into the stacked structure portion 105 above the active region 107 and in the vicinity of the second main electrode 120. Injecting portions 201 and 211 are provided.

  The hole injection portions 201 and 211 are disposed in the vicinity of the second main electrode 120 between the first main electrode 110 and the second main electrode 120. Here, the vicinity of the second main electrode 120 means that the distance from the second main electrode 120 to the edge of the hole injection portions 201 and 211 near the second main electrode 120 is within 1 μm, as will be described later. It means that. As shown in FIG. 2B, the hole injection portions 201 and 211 include p-type third nitride semiconductor layers 202 and 212 formed at predetermined positions on the second nitride semiconductor layer 104, respectively. It consists of both hole injection electrodes 203 and 213 formed thereon. Note that the hole injection portions 201 and 211 may be configured only by the p-type third nitride semiconductor layers 202 and 212 formed at predetermined positions on the second nitride semiconductor layer 104, respectively. .

The third nitride semiconductor layers 202 and 212 are, for example, GaN layers doped with Mg. The Mg concentration is about 1 × 10 ¹⁹ cm ⁻³ and the carrier concentration is about 1 × 10 ¹⁸ cm ⁻³ . The third nitride semiconductor layers 202 and 212 are formed by, for example, MOCVD and patterned using photolithography and dry etching.

  The hole injection electrodes 203 and 213 are made of a laminate including, for example, Ni, Pd, Ti, Al, etc., and are in ohmic contact with the third nitride semiconductor layers 202 and 212, respectively. The hole injection electrodes 203 and 213 are formed below the insulating film 140. The insulating film 140 has openings (not shown) at least partially on the formed hole injection electrodes 203 and 213, and the upper surfaces (see FIG. 5) of the hole injection electrodes 203 and 213 through the openings. At least a part of the upper side surface of 2B is connected to the second lead wiring 160. The hole injection electrodes 203 and 213 are formed by sputtering, for example, and are patterned using photolithography and dry etching.

  The hole injection portion 211 on the second opposite end 122 side is formed so as to be positioned closer to the second main electrode 120 than the end portion of the second lead-out wiring 162 in the first direction.

  In the nitride semiconductor device 200 having the above configuration, when a high voltage is applied to the second lead-out wiring 162, that is, the second main electrode 120 and the hole injection portions 201 and 211, the hole injection portion. Holes are injected from 201 and 211 into the multilayer structure portion 105, and electrons trapped at the surface level of the multilayer structure portion 105 disappear due to recombination with the holes. As described above, by forming the hole injection portions 201 and 211, trapped electrons can be reduced. As a result, the lifetime of the continuous hard switching operation can be further improved as compared with the first embodiment.

  A positional relationship between the above-described hole injection portions 201 and 211 and the second lead-out wiring 162 will be described with reference to the drawings.

  FIG. 2D shows a cross section perpendicular to the first direction of the nitride semiconductor device 200a used for examining the proper positional relationship between the hole injection portions 201 and 211 and the second lead-out wiring 162 according to this embodiment. The figure is shown. 2D is far from the edge of the second lead-out wiring 162a on the first lead-out wiring 150 side and the second main electrode 120 of the hole injection portion 201 (third nitride semiconductor layer 202). It represents the distance in the second direction from the side edge. FIG. 2E is a graph showing the relationship between the XY distance and the voltage at which the current collapse phenomenon occurs. In FIG. 2E, the edge of the third nitride semiconductor layer 202 far from the second main electrode 120 is farther from the second main electrode 120 than the edge of the second lead-out wiring 162a. The inter-XY distance is shown as a negative value.

  As can be seen from FIG. 2E, a collapse voltage of 900 V or more is obtained when the distance between XY is 1 μm or less. On the other hand, when the distance between XY exceeds 3 μm, the voltage at which the current collapse phenomenon occurs rapidly decreases. From this result, in order to reduce the trapped electrons by the hole injection portions 201 and 211, the edge of the second lead wiring 162 and the side farther from the second main electrode 120 of the hole injection portions 201 and 211 are used. It has been demonstrated that it is necessary to keep the distance to the edge of the film within 1 μm. From this result, it can be estimated that the holes are diffused from the hole injection portions 201 and 211 to about 1 μm in the horizontal direction (first direction and second direction).

  When this result is applied to the present embodiment, the hole injection portions 201 and 211 are formed so that the edges close to the second main electrode 120 are within 1 μm from the inclined portions 123 and 124, respectively. It is preferable.

(Embodiment 3)
The nitride semiconductor device according to the third embodiment will be described below. The nitride semiconductor device according to the present embodiment is different from nitride semiconductor device 200 according to the second embodiment in that the hole injection portion surrounds second main electrode 120. Hereinafter, the nitride semiconductor device according to the present embodiment will be described with reference to the drawings with a focus on differences from the nitride semiconductor device 200 according to the second embodiment.

  FIG. 3A is a plan view showing a layout of nitride semiconductor device 300 according to the present embodiment. 3B is a cross-sectional view showing a 3B-3B cross section in FIG. 3A of nitride semiconductor device 300 according to the present embodiment. 3C is a cross-sectional view showing a 3C-3C cross section in FIG. 3A of nitride semiconductor device 300 according to the present embodiment.

  Similar to nitride semiconductor device 200 according to the second embodiment, nitride semiconductor device 300 according to the present embodiment includes hole injection unit 301.

  The hole injection part 301 is disposed in the vicinity of the second main electrode 120 between the first main electrode 110 and the second main electrode 120. The hole injection portion 301 includes a p-type third nitride semiconductor layer 302 formed at a predetermined position on the second nitride semiconductor layer 104, and a hole injection electrode 303 formed thereon. Consists of both. Note that the hole injection portion 301 may be configured only by the p-type third nitride semiconductor layer 302 formed at a predetermined position on the second nitride semiconductor layer 104. The third nitride semiconductor layer 302 and the hole injection electrode 303 have the same structure as the third nitride semiconductor layer 202 and the hole injection electrode 203 in Embodiment 2, respectively.

  In the present embodiment, as shown in FIGS. 3A to 3C, the hole injection part 301 surrounds the second main electrode 120. More specifically, as shown in FIG. 3A, in the plan view of the substrate 101, the hole injection part 301 surrounds the entire second main electrode 120 in the vicinity of the second main electrode 120. Further, the connection configuration between the second lead-out wiring 163 and the hole injection portion 301 is not particularly limited. However, in the present embodiment, the second lead-out wiring 163 has a positive connection as shown in FIGS. 3B and 3C. It is connected to the hole injection part 301 only at one place. In nitride semiconductor device 300 having the above-described configuration, the contact area between hole injection portion 301 and stacked structure portion 105 is increased, and hole injection can be performed over second main electrode 120 as a whole. Therefore, trapped electrons can be further reduced as compared with nitride semiconductor device 200 according to the second embodiment.

  Furthermore, as described above, the width of the second lead-out wiring 163 in the second direction is set to 1 μm from the edge of the hole injection portion 301 on the side far from the second main electrode 120 without reducing the collapse voltage. Can be expanded. For this reason, there is an effect that the resistance of the second lead wiring 163 can be lowered.

(Embodiment 4)
The nitride semiconductor device according to the fourth embodiment will be described below. The nitride semiconductor device according to the present embodiment differs from nitride semiconductor device 300 according to the third embodiment in the configuration of the hole injection portion. Hereinafter, the nitride semiconductor device according to the present embodiment will be described with reference to the drawings with a focus on differences from the nitride semiconductor device 300 according to the third embodiment.

  FIG. 4A is a plan view showing a layout of nitride semiconductor device 400 according to the present embodiment. 4B is a cross-sectional view showing a 4B-4B cross section in FIG. 4A of nitride semiconductor device 400 according to the present embodiment. 4C is a cross-sectional view showing a 4C-4C cross section in FIG. 4A of nitride semiconductor device 400 according to the present embodiment.

  Similar to nitride semiconductor device 300 according to the third embodiment, nitride semiconductor device 400 according to the present embodiment includes hole injection portion 401 that surrounds second main electrode 120.

  The hole injection portion 401 is disposed in the vicinity of the second main electrode 120 between the first main electrode 110 and the second main electrode 120. The hole injection portion 401 includes both a p-type third nitride semiconductor layer 402 formed at a predetermined position on the second nitride semiconductor layer 104 and a hole injection electrode 403 formed thereon. Consists of. Note that the hole injection portion 401 may be composed of only the p-type third nitride semiconductor layer 402 formed at a predetermined position on the second nitride semiconductor layer 104. Third nitride semiconductor layer 402 and hole injection electrode 403 have the same structure as third nitride semiconductor layer 302 and hole injection electrode 303 in Embodiment 3, respectively.

  In the present embodiment, as shown in FIGS. 4A and 4B, concave recess portions 104 a and 104 b are formed in at least a part of the second nitride semiconductor layer 104 located immediately below the hole injection portion 401. A part of the hole injection part 401 is arranged in the recesses 104a and 104b. As shown in FIG. 4A, the recess portions 104a and 104b are formed so as to surround the inclined portions 123 and 124, respectively. In other words, from the position in the first direction at the end of the inclined portion 123 on the center side of the second main electrode 120 in the third nitride semiconductor layer 402, from the equal width portion 126 of the second main electrode 120. The part on the far side (the upper side in FIG. 4A) is formed on the recess 104 a formed in the second nitride semiconductor layer 104. An in-recess arrangement portion 404 of the third nitride semiconductor layer 402 is arranged in the recess portion 104a. Similarly, from the position in the first direction at the end of the inclined portion 124 on the center side of the second main electrode 120 in the third nitride semiconductor layer 402, from the equal width portion 126 of the second main electrode 120. The portion on the far side (the lower side in FIG. 4A) is formed on the recess portion 104 b formed in the second nitride semiconductor layer 104. An in-recess arrangement portion 405 of the third nitride semiconductor layer 402 is arranged in the recess portion 104b.

  The depth of the recesses 104 a and 104 b formed in the second nitride semiconductor layer 104 is greater than 0 and smaller than the thickness of the second nitride semiconductor layer 104. The third nitride semiconductor layer 402 in the hole injection portion 401 on the recess portions 104a and 104b has in-recess arrangement portions 404 and 405, respectively. The hole injection part 401 on the recesses 104a and 104b has a higher hole injection effect than the other hole injection parts 401, and is trapped because hole injection can be strengthened more than in the third embodiment. Electrons can be further reduced.

  The result of the comparative experiment of the hole injection effect with and without the recess structure is shown below.

  FIG. 4D is a cross-sectional view of an electrode structure having a recess used in a comparative experiment. FIG. 4E is a cross-sectional view of an electrode structure having no recess used in a comparative experiment.

  The electrode structure shown in FIG. 4D includes a laminated structure portion, a hole injection portion formed on the recess portion of the laminated structure portion, and a low potential electrode formed in the vicinity thereof. The electrode structure shown in FIG. 4E is different from the electrode structure shown in FIG. 4D in that the recess portion is not formed in the stacked structure portion, and is identical in other points.

  A result obtained by applying a voltage to the hole injection portion of each electrode structure shown in FIGS. 4D and 4E and comparing the applied voltages when a constant current flows will be described with reference to the drawings. FIG. 4F is a graph showing the results of a comparative experiment of the hole injection effect with and without the recess. As shown in FIG. 4F, the value of the electrode structure shown in FIG. 4D was smaller than that of the electrode structure shown in FIG. 4E. As described above, when the recess portion is formed immediately below the hole injection portion, a larger current can be supplied with a smaller applied voltage. That is, it can be seen that more holes can be injected when there is a recess portion for a predetermined applied voltage than when there is no recess portion.

  Such an effect of the recess portion is considered to be caused by an increase in the contact area between the hole injection portion and the second nitride semiconductor layer. That is, if the current amount per unit area (hole injection amount) in the contact area is constant, it is considered that the current amount increases as the contact area increases.

(Embodiment 5)
The nitride semiconductor device according to the fifth embodiment will be described below. The nitride semiconductor device according to the present embodiment is different from nitride semiconductor device 400 according to the fourth embodiment in the configuration of the recess portion. Hereinafter, the nitride semiconductor device according to the present embodiment will be described with reference to the drawings with a focus on differences from the nitride semiconductor device 400 according to the fourth embodiment.

  FIG. 5A is a plan view showing a layout of nitride semiconductor device 500 according to the present embodiment. FIG. 5B is a cross-sectional view showing a 5B-5B cross section in FIG. 5A of nitride semiconductor device 500 according to the present embodiment. FIG. 5C is a cross-sectional view showing a 5C-5C cross section in FIG. 5A of nitride semiconductor device 500 according to the present embodiment.

  Similar to nitride semiconductor device 400 according to the fourth embodiment, nitride semiconductor device 500 according to the present embodiment includes hole injection portion 501 that surrounds second main electrode 120.

  The hole injection portion 501 is disposed in the vicinity of the second main electrode 120 between the first main electrode 110 and the second main electrode 120. The hole injection portion 501 includes a p-type third nitride semiconductor layer 502 formed at a predetermined position on the second nitride semiconductor layer 104, and a hole injection electrode 503 formed thereon. Consists of both. Note that the hole injection portion 501 may be configured only by the p-type third nitride semiconductor layer 502 formed at a predetermined position on the second nitride semiconductor layer 104. The third nitride semiconductor layer 502 and the hole injection electrode 503 have the same structure as the third nitride semiconductor layer 202 and the hole injection electrode 203 in Embodiment 2.

  In the present embodiment, as shown in FIGS. 5A and 5B, the second nitride semiconductor layer 104 is formed on at least a part of the second nitride semiconductor layer 104 located immediately below the hole injection portion 501. Penetrating recess portions 104c and 104d are formed, and a part of the hole injection portion 501 is disposed in the through recess portions 104c and 104d. As shown in FIG. 5A, the through recess portions 104c and 104d are formed so as to surround the inclined portions 123 and 124, respectively. In other words, from the position in the first direction at the end of the inclined portion 123 on the center side of the second main electrode 120 in the third nitride semiconductor layer 502, from the equal width portion 126 of the second main electrode 120. The part on the far side (the upper side in FIG. 5A) is formed on the through recess 104 c formed in the second nitride semiconductor layer 104. An in-recess placement portion 504 of the third nitride semiconductor layer 502 is disposed in the through recess portion 104c. Similarly, in the third nitride semiconductor layer 502, from the position in the first direction at the end of the inclined portion 124 on the center side of the second main electrode 120, from the equal width portion 126 of the second main electrode 120. The portion on the far side (the lower side in FIG. 5A) is formed on the through recess 104 d formed in the second nitride semiconductor layer 104. An in-recess placement portion 505 of the third nitride semiconductor layer 502 is disposed in the through recess portion 104d. The through recesses 104c and 104d are formed by completely etching away the second nitride semiconductor layer 104, for example. By forming the hole injection portion 501 in the through-recess portions 104c and 104d, the second nitride semiconductor layer 104 and the third nitride semiconductor layer are compared with the fourth embodiment in this embodiment. Since the contact area with 502 becomes wider and hole injection can be further strengthened, trapped electrons can be further reduced.

  Further, in the through recess region, 2DEG disappears in a non-biased state, so that the electron flow does not flow, and it is considered that the electron flow is greatly reduced even at the time of switching indicated by the dotted line in FIG. Therefore, the breakage in the vicinity of the tip of the second main electrode 120 is less likely to occur.

(Embodiment 6)
The nitride semiconductor device according to the sixth embodiment will be described below. Nitride semiconductor device according to the present embodiment is different from nitride semiconductor device 100 according to the first embodiment in that it does not have a control electrode and can be operated as a diode. Hereinafter, the nitride semiconductor device according to the present embodiment will be described with reference to the drawings.

  FIG. 6A is a plan view showing a layout of nitride semiconductor device 600 according to the present embodiment. FIG. 6B is a cross-sectional view showing a 6B-6B cross section in FIG. 6A of nitride semiconductor device 600 according to the present embodiment.

  As shown in FIG. 6A, nitride semiconductor device 600 according to the present embodiment is different from nitride semiconductor device 100 according to Embodiment 1 in that control electrode 130 is mainly not provided.

  Since the configuration from the substrate 101 to the second opposite end 122 is the same as that of the first embodiment, description thereof is omitted.

  In the present embodiment, the first main electrode 110 in the first embodiment is made of a metal that forms a Schottky junction with the second nitride semiconductor, for example, instead of being composed of a laminated body containing, for example, Ti, Al, or the like. It is composed of a laminate including Ni, TiN, W and the like.

  With such a configuration, the nitride semiconductor device 600 can operate as a Schottky barrier diode having the first main electrode 110 as an anode and the second main electrode 120 as a cathode.

  In the sixth embodiment, instead of changing the electrode material of the first main electrode 110 in order to realize the function as a pn junction diode, the second nitride semiconductor layer 104 and the first main electrode 110 are changed. A p-type semiconductor layer 601 may be formed therebetween. FIG. 6C shows a cross-sectional view of nitride semiconductor device 600a according to such a modification of the sixth embodiment. 6C shows a cross section corresponding to the 6B-6B cross section in FIG. 6A of nitride semiconductor device 600a.

  With such a configuration, the nitride semiconductor device 600a can operate as a pn junction diode having the first main electrode 110 as an anode and the second main electrode 120 as a cathode.

  In the diode, electrons are trapped in the vicinity of the tip of the cathode electrode due to an electron flow flowing from the anode to the cathode when the diode is off, which may cause destruction. By using this embodiment, destruction near the tip of the cathode electrode is suppressed, and a long-life diode can be realized. In particular, since the density of the electron flow flowing from the anode to the cathode of the diode is generally larger than the density of the electron flow flowing from the source electrode to the drain electrode in the FET, the nitride semiconductor device 600 according to the present embodiment has the case of the FET. The effect of suppressing destruction by trapped electrons becomes more remarkable.

(Variations, etc.)
Although the nitride semiconductor device according to the present disclosure has been described based on the embodiments, the present disclosure is not limited to the above-described embodiments.

  For example, in the nitride semiconductor device 100d according to the modification of the first embodiment or the nitride semiconductor device 600 according to the sixth embodiment, the hole injection unit according to the second to fifth embodiments is applied. Good.

  Each nitride semiconductor device according to the first to fifth embodiments assumes a normally-on transistor that conducts even when no bias voltage is applied to control electrode 130, but when no bias voltage is applied to control electrode 130. A normally-off transistor that is not conductive may be used. Note that a normally-on transistor has a higher electron flow density from the first main electrode to the second main electrode than a normally-off transistor. For this reason, when the nitride semiconductor device according to each embodiment is applied to a normally-on transistor, the effect of suppressing the breakdown due to trapped electrons becomes more remarkable.

  In the inventions according to Embodiments 3 to 5, the hole injection part continuously surrounds the entire second main electrode 120, but the hole injection part may be partially interrupted. You may interrupt about 1 micrometer which is the distance which a hole diffuses. In addition, the hole injection portion may not be formed in a portion located in the first direction with respect to the second main electrode 120. Further, the position where the recess portion and the through recess portion are formed is not particularly limited. For example, the recess portion and the through recess portion may be formed at a position corresponding to the entire hole injection portion of the third nitride semiconductor layer.

  Moreover, in each figure, although the shape in planar view of the 1st main electrode is made into the ellipse shape, the shape of the 1st main electrode is not specifically limited, For example, a rectangle may be sufficient. Moreover, in each figure, although the 2nd main electrode is provided with the inclination part 124 in one edge part, it does not necessarily need to be provided with the inclination part 124. FIG. For example, the second main electrode may include a rectangular end portion instead of the inclined portion 124.

  In addition, it is realized by arbitrarily combining the components and functions in each embodiment without departing from the spirit of the present disclosure, or forms obtained by subjecting each embodiment to various modifications conceived by those skilled in the art. Forms are also included in the present disclosure.

  The nitride semiconductor device according to the present disclosure is useful as a transistor or a diode used in an inverter, a power conditioner, a power supply circuit, or the like.

100, 100a, 100b, 100c, 100d, 200, 200a, 300, 400, 500, 600, 600a Nitride semiconductor device 101 Substrate 102 Buffer layer 103 First nitride semiconductor layer 104 Second nitride semiconductor layer 104a, 104b Recessed portion 104c, 104d Through-recessed portion 105 Laminated structure portion 106 Two-dimensional electron gas 107 Active region 108 Element isolation region 110, 110b, 110c First main electrode 111, 111b, 111c First tip 112, 112b, 112c First 1 opposite tip 120 second main electrode 121 second tip 122 second opposite tip 123, 124 inclined portion 126 equal width portion 130, 130a control electrode 140, 140d insulating film 150 first lead wiring 160, 160d, 162, 162a, 163 Second pull 165, 166a, 166b, 167a, 167b, 168a, 168b region 170 first aggregated wiring 180 second aggregated wiring 201, 211, 301, 401, 501, 1007 hole injection portions 202, 212, 302, 402 , 502 Third nitride semiconductor layer 203, 213, 303, 403, 503 Hole injection electrode 404, 405, 504, 505 In-recess arrangement portion 601 p-type semiconductor layer 1003 AlGaN layer 1004 GaN layer 1005 drain electrode 1006 drain electrode Wiring 1010 Gate electrode 1011 Source electrode 1012 Source electrode wiring 1030 Electrode vicinity region 1060 Electron current 1061 Electron

Claims (11)

A substrate,
A first nitride semiconductor layer disposed above the substrate; and a second nitride layer stacked above the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer. A stacked structure portion having an active region in which a two-dimensional electron gas induced at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer exists,
A first main electrode disposed above the active region and extending in a first direction in plan view with respect to the substrate;
A second main main body disposed at a position above the active region spaced from the first main electrode in a second direction perpendicular to the first direction in plan view with respect to the substrate, and extending in the first direction; Electrodes,
A lead-out wiring disposed above the second main electrode and electrically connected to the second main electrode, and extending from the second main electrode to one side in the first direction. With lead-out wiring,
The first main electrode has a first tip at the end on the side where the lead-out wiring extends, of both ends in the first direction,
The second main electrode has a second tip at the end on the side where the lead-out wiring extends, out of both ends in the first direction, and the second tip in the first direction. On the side, having an inclined portion whose width in the second direction decreases as it approaches the second tip,
The lead-out wiring has a region that protrudes in the second direction from the inclined portion in a plan view with respect to the substrate, and a lower portion includes a region included in the active region,
An end of the inclined portion on the center side of the second main electrode in the first direction is disposed closer to the second tip side in the first direction than the first tip. . The second main electrode has an equal width portion between both end portions in the first direction and having the same width in the second direction,
2. The nitride semiconductor device according to claim 1, wherein a portion of the lead-out wiring that is located above the equal width portion does not protrude from the equal width portion toward the first main electrode in the second direction. . The second main electrode has an equal width portion between both end portions in the first direction and having the same width in the second direction,
The portion of the lead-out wiring whose position in the first direction coincides with the inclined portion does not protrude from the constant width portion toward the first main electrode in the second direction. The nitride semiconductor device described in 1. The second main electrode has an equal width portion between both end portions in the first direction and having the same width in the second direction,
The portion of the lead-out wiring that extends in a direction away from the second main electrode from the second tip, the portion covering the active region is the first width portion from the constant width portion in the second direction. Without projecting to the main electrode side of
The nitride semiconductor device according to any one of claims 1 to 3, wherein the lead-out wiring does not protrude in the first direction from a tip opposite to the first tip of the second main electrode. The second main electrode has an equal width portion between both end portions in the first direction and having the same width in the second direction,
At least a part of the portion of the lead-out wiring that does not protrude from the equal width portion in the first direction and protrudes from the first main electrode is in the second direction. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device protrudes toward the electrode side. The second main electrode has an equal width portion between both end portions in the first direction and having the same width in the second direction,
At least a part of the portion of the lead-out wiring that protrudes from the equal width portion and does not protrude from the second main electrode in the first direction is the first main electrode in the second direction. The nitride semiconductor device according to claim 1, which protrudes to the side. At least a part of a portion of the lead-out wiring that is above the active region and protrudes from the second main electrode in the first direction is the first main line in the second direction. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device protrudes toward the electrode side. further,
8. The nitride semiconductor according to claim 1, further comprising a hole injection part that injects holes into the stacked structure part in the vicinity of the second main electrode and above the active region. apparatus. The nitride semiconductor device according to claim 8, wherein the hole injection portion surrounds the second main electrode in a plan view of the substrate. At least a part of the second nitride semiconductor layer located immediately below the hole injection part is formed with a recessed recess part,
The nitride semiconductor device according to claim 8, wherein a part of the hole injection part is disposed in the recess part. A through recess portion penetrating the second nitride semiconductor layer is formed in at least a part of the second nitride semiconductor layer located immediately below the hole injection portion,
The nitride semiconductor device according to claim 8, wherein a part of the hole injection part is disposed in the through recess part.

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