JP2018142112A - Clock device, central processing unit, counting device, counting method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock device for counting in accordance with an operation speed when the operation speed of a semiconductor circuit changes.SOLUTION: A central processing unit 100 incorporates an operation clock device and operates on the basis of an operation clock signal generated by itself. An operation clock control part 120 generates the operation clock signal and supplies it to an instruction processing part 110. An environment information control part 121 determines an operation clock frequency on the basis of environment information indicating an operation environment of the central processing unit, such as temperature or electric power. A frequency setting register 123 stores operation clock information acquired from the environmental information control part. A clock output part 124 refers to the operation clock information stored by the frequency setting register to generate the operation clock signal at a frequency indicated by the operation clock information and output it to the instruction processing part. An operation frequency history totaling part 130 counts an index value indicating a clock number of the operation clock signal output by the clock output part for each frequency determined by the environment information control part.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a clock device, a central processing unit, a counting device, a counting method, and a program.

  There is an apparatus having a function of changing an operating frequency of a semiconductor circuit such as a power saving control function. In relation to such a change in operating frequency, Patent Document 1 discloses a multiprocessor count correction device that corrects the count value of a clock cycle counter prepared for each processor in the multiprocessor to an elapsed time common to the processors. Has been. When detecting a change in the operating frequency for each processor, the multiprocessor count correction apparatus derives a virtual time based on the operating frequency after the frequency change and the clock cycle count value at the time of the frequency change.

Japanese Patent No. 5267656

  By changing the operating frequency of the semiconductor circuit, the operating speed of the semiconductor circuit changes. For example, when a service is provided with a pay-per-use charge based on the usage time of the server device, it is preferable from the viewpoint of fairness that the change in operation speed can be reflected in the fee. Thus, when the operation speed of the semiconductor circuit changes, it is preferable that processing corresponding to the operation speed can be performed.

  An object of the present invention is to provide a clock device, a central processing unit, a counting device, a counting method, and a program that can solve the above-described problems.

  According to the first aspect of the present invention, the clock device includes a frequency determining unit that determines the clock frequency to be one of a plurality of frequencies, and a clock output unit that outputs a clock signal having a frequency determined by the frequency determining unit. A counting unit that counts an index value indicating the number of clocks of the clock signal output by the clock output unit for each frequency determined by the frequency determination unit.

  According to the second aspect of the present invention, the counting device determines the clock frequency to be one of a plurality of frequencies, and the index indicating the number of clocks of the clock signal output by the clock device that outputs the clock signal of the determined frequency A counter for counting the value for each frequency determined by the clock device;

  According to the third aspect of the present invention, in the counting method, the clock frequency is determined as one of a plurality of frequencies, and the index indicating the number of clocks of the clock signal output by the clock device that outputs the clock signal of the determined frequency Counting values for each frequency determined by the clock device.

  According to the fourth aspect of the present invention, the program determines the clock frequency of the clock signal output from the clock device that outputs the clock signal having the determined frequency to the computer and determines the clock frequency to one of the plurality of frequencies. This is a program for counting the indicated index value for each frequency determined by the clock device.

  According to the present invention, when the operating speed of the semiconductor circuit changes, processing according to the operating speed can be performed.

It is a schematic block diagram which shows the function structure of the central processing unit which concerns on embodiment of this invention. It is a schematic block diagram which shows the function structure of the central processing unit which counts the number of clocks, without distinguishing an operation clock frequency. It is a figure which shows the example of the clock number which the clock counter which concerns on embodiment of this invention counts. It is a figure which shows the example of the cycle number which the central processing unit which concerns on embodiment of this invention counts. It is a schematic block diagram which shows the function structure of the central processing unit which can set the upper limit of the operation clock frequency which concerns on embodiment of this invention. It is a figure which shows the example of the minimum structure of the clock apparatus based on this invention. It is a figure which shows the example of the minimum structure of the counting device which concerns on this invention.

Hereinafter, although embodiment of this invention is described, the following embodiment does not limit the invention concerning a claim. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.
FIG. 1 is a schematic block diagram showing a functional configuration of a central processing unit (CPU) according to an embodiment of the present invention. As shown in FIG. 1, the central processing unit 100 includes an instruction processing unit 110, an operation clock control unit 120, and an operation frequency history control unit 130. The operation clock control unit 120 includes an environment information control unit 121, a clock control unit 122, a frequency setting register 123, and a clock output unit 124. The operating frequency history control unit 130 includes a counter control unit 131, an integration counter unit 132, an integration counter 133, an integration counter 134, and an integration counter 135.

The central processing unit 100 incorporates an operation clock device. The central processing unit 100 is mounted on, for example, a computer and operates based on an operation clock signal generated by the central processing unit 100 itself, and reads and executes a program from a storage device.
The operation clock signal here is a clock signal used as a signal indicating the operation timing of the semiconductor circuit. The operation clock signal is also simply referred to as a clock signal.
The instruction processing unit 110 has a function of executing a program (instruction sequence).

The operation clock control unit 120 generates an operation clock signal and supplies it to the instruction processing unit 110.
In the present embodiment, a case where the operation clock frequency (frequency of the operation clock signal) of the central processing unit 100 can be switched in three stages will be described as an example. The operation clock frequencies of the central processing unit 100 are referred to as “standard”, “low”, and “very low” in descending order of frequency. However, the operation clock frequency of the central processing unit 100 is not limited to three stages, but may be switched to two or more stages.

The environment information control unit 121 acquires environment information indicating the operation environment of the central processing unit 100 such as temperature or power, and determines an operation clock frequency based on the environment information. The environment information control unit 121 corresponds to an example of a frequency determination unit, and determines the operation clock frequency to be one of the above three stages of frequencies.
When the temperature information or the power consumption information exceeds the threshold during the operation of the central processing unit 100, the environment information control unit 121 reduces the operation clock to suppress the temperature rise or the power consumption.

For example, the environment information control unit 121 acquires information indicating the temperature of the central processing unit 100 as environment information, and the first threshold value and the two-level threshold values that are higher than the first threshold value and the central calculation value. The temperature of the processing apparatus 100 is compared. When the temperature of the central processing unit 100 is equal to or lower than the first threshold, the environment information control unit 121 determines the operation clock frequency to be “standard”. When the temperature of the central processing unit 100 is higher than the first threshold and lower than or equal to the second threshold, the environment information control unit 121 sets the operation clock frequency to “low”. When the temperature of the central processing unit 100 is higher than the second threshold, the environment information control unit 121 determines the operation clock frequency to be “very low”.
The environment information control unit 121 outputs operation clock information indicating the determined frequency to the clock control unit 122.

The clock control unit 122 generates an operation clock signal having a frequency determined by the environment information control unit 121 and supplies the generated operation clock signal to the instruction processing unit 110.
The frequency setting register 123 stores operation clock information acquired from the environment information control unit 121.
The clock output unit 124 refers to the operation clock information stored in the frequency setting register 123 and generates an operation clock signal having a frequency indicated by the operation clock information. As a result, the clock output unit 124 outputs an operation clock signal having a frequency determined by the environment information control unit 121.
The clock output unit 124 outputs the generated operation clock signal to the instruction processing unit 110.

The environment information control unit 121 supports the frequency “low” while the frequency setting register 123 stores the operation clock information of the frequency “standard” and the clock output unit 124 outputs the operation clock signal of the frequency “standard”. When the environment information to be acquired is acquired, the environment information control unit 121 outputs the operation clock information having the frequency “low” to the clock control unit 122. The clock control unit 122 updates the operation clock information of the frequency “standard” stored in the frequency setting register 123 to the operation clock information of the frequency “low”. The clock output unit 124 outputs an operation clock signal having a frequency “low” in accordance with the updated operation clock information.
Similarly, the operation clock control unit 120 starts from the frequency “low” to “very low”, “very low” to “low”, “low” to “standard”, “standard” to “very low”, and “very low”. Corresponds to the “standard” switching.

  The operating frequency history control unit 130 corresponds to an example of a counting unit, and counts an index value indicating the number of operating clock signals output from the clock output unit 124 for each frequency determined by the environment information control unit 121. The index value indicating the number of clocks here is a value capable of calculating the number of clocks. For example, the operating frequency history control unit 130 may count the number of clocks or the number of cycles.

The cycle here is a cycle of the clock signal that is a reference of the operation clock signal, and specifically, is a cycle of the operation clock signal when the frequency is “standard”. In this embodiment, the period of the operation clock signal when the frequency is “low” and “extremely low” is twice or four times that of the operation clock signal when the frequency is “standard”. . Therefore, when the frequency is “standard”, the number of cycles is equal to the number of clocks. When the frequency is “low”, the quotient obtained by dividing the number of cycles by 2 is equal to the number of clocks. When the frequency is “very low”, the quotient obtained by dividing the number of cycles by 4 is equal to the number of clocks.
Hereinafter, a case where the operating frequency history control unit 130 counts the number of cycles will be described as an example.

The counter control unit 131 operates at a constant clock to control the integration counter unit 132, and the frequency determined by the environment information control unit 121 is used as an index value for the number of clocks of the operation clock signal output from the clock output unit 124. Let each count.
The accumulation counter unit 132 counts the number of cycles as an index value of the number of clocks of the operation clock signal output from the clock output unit 124 for each frequency determined by the environment information control unit 121 according to the control of the counter control unit 131.

The integration counter 133 counts the number of cycles when the frequency is “standard” among the number of cycles corresponding to the operation clock signal output from the clock output unit 124. The integration counter 134 counts the number of cycles when the frequency is “low” among the number of cycles corresponding to the operation clock signal output from the clock output unit 124. The integration counter 135 counts the number of cycles when the frequency is “extremely low” among the number of cycles corresponding to the operation clock signal output from the clock output unit 124.
The integration counter 133, the integration counter 134, and the integration counter 135 may be software visible registers. The software visible register mentioned here is a register that can be read from software.

  As described above, the operation frequency history control unit 130 aggregates the index values indicating the number of clocks of the operation clock signal of the central processing unit 100 for each frequency, thereby enabling processing for each frequency. For example, when charging according to the user of the server apparatus including the central processing unit 100, the charging is performed according to the usage time for each frequency, so that the fairness can be improved as compared with the case of charging according to the simple usage time. Can be increased.

Here, for comparison with the central processing unit 100, a central processing unit that counts the number of clocks without distinguishing the operation clock frequency will be described.
FIG. 2 is a schematic block diagram showing a functional configuration of a central processing unit that counts the number of clocks without distinguishing between operation clock frequencies. As shown in FIG. 2, the central processing unit 900 includes an instruction processing unit 910 and an operation clock control unit 920. The instruction processing unit 910 includes a clock counter 911. The operation clock control unit 920 includes an environment information control unit 921 and a clock control unit 922. The clock control unit 922 includes a frequency setting register 923 and a clock output unit 924.

The central processing unit 100 counts the number of cycles for each operation clock frequency, whereas the central processing unit 900 counts the number of clocks without distinguishing the operation clock frequency. In other respects, the central processing unit 900 is the same as the central processing unit 100.
Similar to the operation clock control unit 120, the operation clock control unit 920 generates an operation clock signal and supplies it to the instruction processing unit 910. The function of each part of the operation clock control unit 920 is the same as the function of each part of the operation clock control unit 120.
The instruction processing unit 910 has a function of executing a program, like the instruction processing unit 110. On the other hand, the instruction processing unit 910 is different from the instruction processing unit 110 in that it includes a clock counter 911.

The clock counter 911 counts the number of operating clock signals output from the clock output unit 924. The clock output unit 924 outputs the operation clock signal at three stages of frequencies in the same manner as the clock output unit 124, whereas the clock counter 911 counts up every cycle of the operation clock signal without distinguishing the frequencies. To count the number of clocks.
The clock counter 911 may be a software visible register.
The number of clocks counted by the clock counter 911 is used, for example, for billing a user of a server device including the central processing unit 900 or for a performance monitor.

  FIG. 3 is a diagram illustrating an example of the number of clocks counted by the clock counter 911. The upper side of FIG. 3 shows an example in which the clock output unit 924 outputs the clock signal with the “standard” frequency. On the lower side, an example in which the clock output unit 924 switches the frequency from “standard” to “low” and further to “very low” is shown. In this example, the operation clock frequency is switched from “standard” to “low” at time t4. Further, at time t10, the operating clock frequency is switched from “low” to “very low”.

Comparing the upper example with the lower example, the number of clocks is 9 (0 to 8). On the other hand, the operation time required for 9 clocks is 9 unit time (time t0 to time t8) in the upper example, whereas 18 unit time (time t0 to time t17) in the lower example, It takes twice as long as the example.
When the central processing unit 900 performs the same processing in the upper example and the lower example, the upper example has a higher processing speed (operation speed). From this point, it is considered that the fairness is high when the charge in the upper example is set higher than the charge in the lower example.
However, in the configuration shown in FIG. 2, the central processing unit 900 counts the number of clocks as 9 in both the upper example and the lower example. For this reason, it is not possible to make a difference in charging between the upper example and the lower example.

FIG. 4 is a diagram illustrating an example of the number of cycles counted by the central processing unit 100. FIG. 4 shows an example in which the operation clock frequency is switched from “standard” to “low”, “standard”, “low”, “extremely low”.
For example, the integration counter 133 is counted up in the next cycle (time t1) after the time t0 when the frequency setting register 123 indicates “standard”. In the next cycle (time t5) of time t4 when the frequency setting register 123 indicates “low”, the integration counter 134 is counted up. The integration counter 135 is counted up in the cycle following the time t11 (time t12) when the frequency setting register 123 indicates “extremely low”.

  As described above, the integration counters 133 to 135 are software visible registers. By looking at the difference between the start timing (time t0) and the end timing (time t15) of the user's execution program, it is possible to know how many cycles the execution program was operating at which operation clock frequency. In the example of FIG. 4, the final difference of the integration counter 133 is “7”, the difference of the integration counter 134 is “5”, and the difference of the integration counter 135 is “4”. From these values, it can be known that there are 7 cycles with a frequency of “standard” and 9 cycles with a total performance of the integration counter 134 and the integration counter 135 that have degraded performance due to power control.

  As described above, the environment information control unit 121 determines the clock frequency as one of a plurality of frequencies. The clock output unit 124 outputs a clock signal having a frequency determined by the environment information control unit 121. The operating frequency history control unit 130 counts an index value indicating the number of clocks of the clock signal output from the clock output unit 124 for each frequency determined by the environment information control unit 121.

  As described above, the operating frequency history control unit 130 counts the index value indicating the number of clocks for each frequency, so that processing corresponding to the operating speed can be performed when the operating speed of the semiconductor circuit changes. The semiconductor circuit here may be any circuit that operates based on a clock signal and can cope with a change in the clock signal. For example, the semiconductor circuit here may be a CPU, but is not limited thereto.

  As an example of the processing according to the operation speed of the semiconductor circuit, there is a program performance measurement in consideration of the influence of power saving control. The user can obtain information on the operation level at the time of program execution, and the information on the operation level can be used as an evaluation index together with the performance value at the time of program execution. As the performance value at the time of execution of the program, for example, the calculation amount per unit time and the execution time can be used.

The operation level here is a candidate for the operation clock frequency set by the environment information control unit 121. For example, when the environment information control unit 121 sets the operation clock frequency to three levels of “standard”, “low”, and “very low”, each of these three levels corresponds to the operation level.
For example, if the tuned programs A and B have the same execution time but the operation level is lower in A, it can be determined that the tuning of the program A is better.

  Another example of processing according to the operating speed of a semiconductor circuit is a charging method that takes into account the influence of power saving control. In a system that operates with a fixed-rate billing method based on time, if performance degradation occurs due to the effect of power saving control, it is assumed that the charge will change even if the same program is executed. A charging method with high equality can be realized by taking account of the operation level in addition to time.

For example, the billing count value can be calculated using equation (1).
Billing count value = A x (number of cycles when the frequency is "standard")
+ B x (number of cycles when frequency is low)
+ C x (number of cycles when the frequency is “low”) (1)
Here, A, B, and C are all coefficients, and A>B> C.

As described above, the operation clock frequency is not limited to three stages and may be two or more stages. The operation clock frequency may also be set in a direction in which the frequency is higher than the standard, such as “extremely high”, “high”, “standard”, “low”, “extremely low”.
Note that the integration counter unit 132 may be implemented using a hardware counter, or may be realized by software. When the integration counter unit 132 is realized by software, the frequency setting register 123 of the operation clock control unit 120 is a software visible register, and the value of the frequency setting register 123 is periodically read by a program. The integration counter unit 132 can be realized by counting the value in the variable corresponding to the value of the frequency setting register 123 at the count timing linked to the system timer.

The user may be allowed to set the upper limit value of the operation clock frequency.
FIG. 5 is a schematic block diagram showing a functional configuration of the central processing unit capable of setting an upper limit value of the operation clock frequency. As shown in FIG. 5, the central processing unit 200 includes an instruction processing unit 110, an operation clock control unit 220, and an operation frequency history control unit 130. The operation clock control unit 220 includes an environment information control unit 121, a clock control unit 122, a frequency setting register 123, a clock output unit 124, and an operation level upper limit setting register 225. The operating frequency history control unit 130 includes a counter control unit 131, an integration counter unit 132, an integration counter 133, an integration counter 134, and an integration counter 135.

5 that have the same functions corresponding to those in FIG. 1 are assigned the same reference numerals (110, 121 to 124, 130 to 135), and descriptions thereof are omitted.
The central processing unit 200 is different from the central processing unit 100 in that the operation clock control unit 220 includes an operation level upper limit setting register 225. The other points are the same as those of the central processing unit 100.
The operation level upper limit setting register 225 corresponds to an example of an upper limit value setting unit, and sets an upper limit value of the operation clock frequency (frequency of the operation clock signal). For example, the operation level upper limit setting register 225 sets the frequency input by the user operation as the upper limit value of the operation clock frequency.

In response to the setting of the upper limit value by the operation level upper limit setting register 225, the environment information control unit 121 determines the operation clock frequency to a frequency equal to or lower than the upper limit value. Specifically, when the operation clock frequency determined based on the environment information is equal to or lower than the upper limit value, the environment information control unit 121 adopts the determined operation clock frequency as it is. On the other hand, when the operation clock frequency determined based on the environment information is higher than the upper limit value, the environment information control unit 121 sets the upper limit value (or the closest operation clock frequency selection candidate equal to or lower than the upper limit value to the upper limit value). Adopted as operating clock frequency.
Alternatively, the environment information control unit 121 sets the operation clock frequency at the start of the operation to the upper limit value, and sets the operation clock frequency equal to or lower than the upper limit value based on the environment information as described above at the subsequent update timing. May be.

As described above, the operation level upper limit setting register 225 sets the upper limit value of the operation clock frequency. The environment information control unit 121 determines the operation clock frequency to be a frequency equal to or lower than the upper limit value set by the operation level upper limit setting register 225.
As a result, the user can more easily compare the performance of programs and the like. For example, when it is desired to compare performance in a stable environment for applications such as confirmation of program tuning, the user sets the lowest operation level to the upper limit value so that the central processing unit 200 can be programmed with a constant operation clock frequency. Can be executed. This allows the central processing unit 200 to execute a plurality of programs at the same operation clock frequency, and the performance of the programs can be easily compared in this respect.

  In addition, the user can select the processing speed and billing according to the use of the central processing unit 200 by setting the upper limit value of the operation clock frequency. When obtaining the processing speed, the user can be provided with high-speed processing at a high operation clock frequency by setting the upper limit value high. On the other hand, when the processing speed is not obtained, the user can keep charging relatively low by setting the upper limit value low.

Next, the minimum configuration of the present invention will be described with reference to FIGS.
FIG. 6 is a diagram showing an example of the minimum configuration of the clock device according to the present invention. The clock device 10 illustrated in FIG. 6 includes a frequency determination unit 11, a clock output unit 12, and a counting unit 13.
With this configuration, the frequency determination unit 11 determines the clock frequency as one of a plurality of frequencies. The clock output unit 12 outputs a clock signal having a frequency determined by the frequency determination unit. The counting unit 13 counts an index value indicating the number of clocks of the clock signal output from the clock output unit 12 for each frequency determined by the frequency determination unit 11.
As described above, the counting unit 13 counts the index value indicating the number of clocks for each frequency, so that processing according to the operation speed can be performed when the operation speed of the semiconductor circuit changes.

FIG. 7 is a diagram showing an example of the minimum configuration of the counting device according to the present invention. The counting device 20 illustrated in FIG. 6 includes a counting unit 21.
With this configuration, the counting unit 21 determines the clock frequency to be one of a plurality of frequencies, and displays an index value indicating the number of clocks of the clock signal output from the clock device that outputs the clock signal having the determined frequency as the clock device. Is counted for each frequency determined.
As described above, the counting unit 21 counts the index value indicating the number of clocks for each frequency, so that processing according to the operation speed can be performed when the operation speed of the semiconductor circuit changes.

A program for realizing all or part of the functions of the central processing units 100 and 200 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system and executed. By doing so, the functions of the central processing units 100 and 200 may be processed. Here, the “computer system” includes an OS and hardware such as peripheral devices.
The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. The program may be a program for realizing a part of the functions described above, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

100, 200 Central processing unit 110 Instruction processing unit 120, 220 Operation clock control unit 121 Environmental information control unit 122 Clock control unit 123 Frequency setting register 124 Clock output unit 130 Operating frequency history control unit 131 Counter control unit 132 Integration counter unit 133 , 134, 135 Integration counter 225 Operation level upper limit setting register

Claims (6)

A frequency determining unit that determines the clock frequency as one of a plurality of frequencies;
A clock output unit for outputting a clock signal having a frequency determined by the frequency determination unit;
A counting unit that counts an index value indicating the number of clocks of the clock signal output by the clock output unit for each frequency determined by the frequency determination unit;
A clock device comprising: An upper limit setting unit for setting an upper limit of the clock frequency;
The frequency determining unit determines the clock frequency to a frequency equal to or less than the upper limit;
The clock device according to claim 1.   A central processing unit comprising the clock device according to claim 1.   The clock frequency is determined as one of a plurality of frequencies, and an index value indicating the number of clocks of the clock signal output by the clock device that outputs the clock signal of the determined frequency is counted for each frequency determined by the clock device. A counting device comprising a unit.   The clock frequency is determined as one of a plurality of frequencies, and an index value indicating the number of clocks of the clock signal output by the clock device that outputs the clock signal of the determined frequency is counted for each frequency determined by the clock device. Including a counting method. On the computer,
The clock frequency is determined as one of a plurality of frequencies, and an index value indicating the number of clocks of the clock signal output by the clock device that outputs the clock signal of the determined frequency is counted for each frequency determined by the clock device. Program.

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