JP2018137733A - Detection device, controller, and image formation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of signal lines that transmit zero cross and AC voltage.SOLUTION: A detection device generates a superposition signal on which information indicating timing of zero cross of AC voltage and information indicating a voltage level of the AC voltage are superposed. For example, the detection device generates, as a superposition signal, a pulse signal including a first edge indicating timing of zero cross of AC voltage and a second edge of which a time interval from the first edge changes according to a voltage level of the AC voltage.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a detection device, a controller, and an image forming apparatus that detect a voltage level of an alternating voltage and a zero cross timing.

  In general, an image forming apparatus uses a commercial AC power source as a power supply source. The image forming apparatus may control the power supplied to the load with reference to an alternating zero cross. A detection circuit for detecting such a zero cross is proposed in Patent Document 1.

  In some countries, there are many variations in the AC voltage supplied from commercial AC power. In order to protect the power supply device and the load from such variations, the load may be appropriately controlled according to the AC voltage detected by the detection circuit. According to Patent Document 2, an AC voltage detection circuit is proposed.

JP 2006-216657 A JP 2003-098860 A

  A control device such as a microcomputer can control the image forming apparatus by acquiring a zero-cross signal output from the zero-cross detection circuit and a voltage signal output from the AC voltage detection circuit. However, since the two detection circuits are independent, the control device requires many circuit components such as two signal lines and two input ports. Therefore, an object of the present invention is to reduce the number of signal lines that transmit a zero cross and an AC voltage.

  According to the present invention, a detection device is provided that generates a superimposed signal in which information indicating the timing of zero crossing in an AC voltage and information indicating the voltage level of the AC voltage are superimposed.

  According to the present invention, the number of signal lines for transmitting the zero cross and the AC voltage is reduced.

The figure which shows the detection apparatus of Example 1. Diagram explaining the principle of pulse signal generation Diagram explaining functions of microcomputer Figure showing the voltage table The figure which shows the detection apparatus of Example 2. Diagram explaining the principle of pulse signal generation The figure which shows the detection apparatus of Example 3. Diagram explaining the principle of pulse signal generation The figure which shows the detection apparatus of Example 4. Diagram explaining the principle of pulse signal generation The figure which shows the detection apparatus of Example 5. Diagram explaining the principle of pulse signal generation The figure which shows the detection apparatus of Example 6. Diagram explaining the principle of pulse signal generation Diagram showing image forming apparatus

  ADVANTAGE OF THE INVENTION According to this invention, the detection apparatus which produces | generates the superimposition signal which superimposed the information which shows the timing of the zero cross in an alternating voltage, and the information which shows the voltage level of an alternating voltage is provided. This reduces the number of signal lines. More specifically, a detection device that generates a pulse signal including a first edge indicating the timing of zero crossing in an AC voltage and a second edge whose time interval with respect to the first edge changes according to the voltage level of the AC voltage. Provided.

<Example 1>
In the first embodiment, the first edge indicating the zero-crossing timing is generated when the forward voltage applied to the diode drops below a threshold value. When the voltage correlated to the AC voltage applied to the gate of the FET connected in series with the diode exceeds the threshold, the FET conducts and the diode conducts, generating a second edge indicating the voltage level of the AC voltage. This utilizes the property that when the voltage level of the AC voltage is high, the timing at which the voltage level exceeds the threshold is advanced, and when the voltage level is low, the timing at which the voltage level exceeds the threshold is delayed. FET is an abbreviation for field effect transistor. The microcomputer recognizes the temporal position of the first edge as a zero cross point of the AC voltage. Further, the microcomputer recognizes the time interval from the second edge to the first edge as the voltage level of the AC voltage.

  FIG. 1 is a circuit diagram of a detection device 100 that detects the voltage level and zero crossing of an AC voltage according to the first embodiment. The zero cross detection unit 101a is a circuit that detects the zero cross timing of the AC voltage supplied from the commercial AC power supply AC. The AC voltage supplied from the commercial AC power supply AC is input to the input unit 110 such as an input terminal. The voltage detection unit 106a is a circuit that detects the voltage level (effective value) of the AC voltage supplied from the commercial AC power supply AC.

  The photocoupler PC includes a light emitting diode D1 and a phototransistor Q1, and is an insulating element that insulates the primary side and the secondary side of the photocoupler PC. In FIG. 1, a commercial AC power source AC is connected to the primary side. A microcomputer 105 is connected to the secondary side. The light emitting diode D1 is turned on and off according to the information on the primary side. The phototransistor Q1 receives light from the light emitting diode D1 and outputs a signal corresponding to the received light. The diode D2 is provided in parallel with the light emitting diode D1. The diode D2 is conductive when the AC voltage supplied from the commercial AC power supply AC is negative, and is not conductive when positive. Thereby, the both-ends voltage of the light emitting diode D1 of the photocoupler PC is suppressed below the withstand voltage of the light emitting diode D1. The resistor R1 is a current limiting resistor that protects the light emitting diode D1 by limiting the current that flows to the light emitting diode D1.

  The voltage detection unit 106a is connected in series to the light emitting diode D1. The voltage detection unit 106a includes a level detection unit 107 that detects the voltage level of the AC voltage supplied from the commercial AC power supply AC, and an FET Q2 that is turned on or off according to the voltage level. The level detection unit 107 includes a resistor R3 and a capacitor C1 that form a low-pass filter (LPF), applies a phase delay to a voltage correlated with an AC voltage, and applies the voltage to the FET Q2. When the gate voltage of the FET Q2 exceeds the gate threshold value of the FET Q2, the drain-source of the FET Q2 becomes conductive. When the voltage applied to the light emitting diode D1 exceeds the forward voltage VF, if the FET Q2 becomes conductive, a forward current flows through the light emitting diode D1. The collector of the phototransistor Q1 is pulled up to the power supply voltage Vcc (eg, 3.3 V) by the resistor R2. Therefore, the phototransistor Q1 generates a pulse signal having binary voltage levels of H (approximately 3.3 V) and L (approximately 0 V) and inputs the pulse signal to the input port 104 of the microcomputer 105. H is an abbreviation for high level. L is an abbreviation for low level. The phototransistor Q1 is turned on when the light emitting diode D1 is turned on, and the pulse signal is set to L. The phototransistor Q1 does not conduct when the light emitting diode D1 is turned off, and sets the pulse signal to H.

  FIG. 2A shows a voltage waveform W1 of the commercial AC power supply AC, a voltage waveform W2 of the gate terminal of the FET Q2, and a voltage waveform W3 of the pulse signal. The horizontal axis indicates time. The vertical axis represents voltage. Assume that the voltage of the commercial AC power supply AC is 100 Vrms. The other waveform voltages are in the range of several volts. Here, in order to represent all waveforms in the same graph, the voltage of the commercial AC power supply AC is shown compressed to 1/20 for convenience. Overlaid on these voltage waveforms, the operating state W4 of the light emitting diode D1 of the photocoupler PC and the operating state W5 of the FET Q2 are also shown. The reverse direction indicates that a reverse voltage is applied to the light emitting diode D1. The forward direction indicates that a forward voltage is applied to the light emitting diode D1. ON indicates a conductive state. OFF indicates a non-conductive state.

  The light emitting diode D1 becomes conductive when the voltage of the commercial AC power supply AC exceeds a predetermined value (generally about 1.0 V which is the forward voltage VF of the light emitting diode of the photocoupler PC). Thus, the forward voltage VF is much smaller than 100 Vrms, which is the effective value of the AC voltage of the commercial AC power supply AC. Therefore, the timing at which the light-emitting diode D1 is switched between conduction and non-conduction substantially indicates the zero-cross timing of the commercial AC power supply AC.

  In Example 1, the light emitting diode D1 is connected in series with the FET Q2. Therefore, the zero cross timing can be detected only when the FET Q2 is conductive. As shown in FIG. 2A, the light emitting diode D1 is switched from the conductive state to the non-conductive state when the FET Q2 is conductive and the zero cross timing of the commercial AC power supply AC arrives. As a result, the rising edge of the pulse signal (the timing at which the level of the pulse signal changes from L to H) is generated.

  On the other hand, the voltage of the commercial AC power supply AC is input to the LPF formed by the resistor R3 and the capacitor C1. The cut-off frequency of the LPF is set so that the phase of the voltage is delayed by several tens of degrees to 90 degrees or less in the range from 50 Hz to 60 Hz, which is the frequency of the commercial AC power supply AC. Due to the action of the LPF, the waveform of the gate voltage of the FET Q2 becomes a voltage waveform W2 as shown by a broken line in FIG. 2A. For example, the gate threshold of the FET Q2 may be 3V. In this case, the FET Q2 transitions to a conductive state when the gate voltage exceeds 3V. Due to the influence of the phase delay due to the LPF, the conduction timing and non-conduction timing of the FET Q2 are delayed from those of the photocoupler PC. The photocoupler PC and the FET Q2 are connected in series with the commercial AC power supply AC. Therefore, information is transmitted to the secondary side only when the photocoupler PC and the FET Q2 are both conductive. The falling edge of the pulse signal, which is the timing at which information transmission is started to the secondary side, is generated when the FET Q2 becomes conductive. The rising edge, which is the timing at which information transmission to the secondary side is completed, is generated when the light emitting diode D1 is switched from conduction to non-conduction.

  FIG. 2B shows voltage waveforms W1 to W3 when the voltage of the commercial AC power supply AC is changed in four steps in increments of 20V in the range from 80V to 140V. The temporal position of the rising edge generated by the non-conduction of the light emitting diode D1 remains almost unchanged even when the voltage of the commercial AC power supply AC changes. The forward voltage VF of the light emitting diode D1 is sufficiently smaller than the voltage of the commercial AC power supply AC. Therefore, the position of the rising edge is hardly affected by the difference in slope (dv / dt) due to the voltage change of the commercial AC power supply AC.

  On the other hand, the falling edge generated by the conduction of the FET Q2 changes greatly according to the voltage change of the commercial AC power supply AC. This is because the gate threshold value (3V) of the FET Q2 and the gate voltage (about 4Vpeak and about 5Vpeak) are close to each other. Therefore, the position of the falling edge is affected by the difference in the slope (dv / dt) of the gate voltage of the FET Q2 due to the voltage change of the commercial AC power supply AC. As shown in FIG. 2B, the time when the gate voltage of the FET Q2 exceeds the gate threshold value of the FET Q2 varies greatly depending on the voltage of the commercial AC power supply AC. For this reason, the generation timing of the falling edge varies greatly depending on the voltage of the commercial AC power supply AC. The timing at which the FET Q2 is turned off also varies greatly depending on the voltage of the commercial AC power supply AC, as in the case of conduction. However, the LPF is designed so that the light emitting diode D1 is always non-conductive at the timing when the FET Q2 is non-conductive. Thereby, the pulse signal does not depend on the timing when the FET Q2 becomes non-conductive.

  FIG. 2C shows the relationship between the pulse width of the pulse signal and the voltage. The pulse width is the time from the timing when the falling edge is detected to the timing when the rising edge is detected. The horizontal axis represents the effective value of the AC voltage supplied from the commercial AC power supply AC. The vertical axis indicates the pulse width of the pulse signal. PW2 indicates the pulse width in a typical case where there is no variation in circuit components. PW1 indicates the characteristics in the case where the pulse width is maximized due to variations in circuit components. PW3 indicates characteristics in a case where the pulse width is minimized due to variations in circuit components. The variation of the resistance R3 is ± 1%. The variation of the capacitor C1 is ± 10%. The variation of the gate threshold value of the FET Q2 is ± 3%. In the first embodiment, the variation of the capacitor C1 has a great influence on the pulse width. Therefore, by adopting a variable resistor as the resistor R3 and setting an appropriate resistance value with respect to variations in the capacitor C1, the voltage of the commercial AC power supply AC can be detected with high accuracy.

  FIG. 3 shows the functions of the microcomputer 105. The microcomputer 105 may be realized by a CPU, an ASIC, an FPGA, or the like, or a combination thereof. ASIC is an abbreviation for application specific integrated circuit. FPGA is an abbreviation for field programmable gate array. The storage device 310 may store a control program. Here, it is assumed that the following functions are realized by the CPU executing the control program.

  The load control unit 301 can recognize the zero-cross timing of the AC voltage of the commercial AC power supply AC by detecting the rising edge of the pulse signal input to the input port 104. The first counter 302 measures the time between adjacent rising edges in the pulse signal. This time corresponds to one cycle. The reciprocal of one cycle is the frequency. Note that the time between adjacent falling edges may be measured. The frequency determination unit 303 converts the count value of the first counter 302 into a frequency with reference to the frequency table 311 stored in the storage device 310. A function may be used instead of the frequency table 311. The second counter 304 measures the time (pulse width) from the falling edge to the rising edge of the pulse signal. The voltage determination unit 305 converts the count value of the second counter 304 into a voltage value with reference to the voltage table 312 stored in the storage device 310. Note that a function (approximate expression) may be used instead of the voltage table 312.

  FIG. 4 shows a voltage table 312 for converting the pulse width measured by the second counter 304 into a voltage value. Here, 50 Hz is assumed as the frequency of the AC voltage, but there is an area where a frequency of 60 Hz is used. Therefore, the storage device 310 may have a voltage table 312 for each frequency. In this case, the voltage determination unit 305 may select the voltage table 312 based on the frequency determined by the frequency determination unit 303. Alternatively, the storage device 310 may store a single normalized voltage table 312 and a correction coefficient for each frequency. The voltage determination unit 305 may select a correction coefficient based on the frequency determined by the frequency determination unit 303 and correct the voltage value obtained from the count value and the voltage table 312 with the correction coefficient. The voltage table 312 shown in FIG. 4 is a table for acquiring voltage values in increments of 5V. However, when it is desired to detect the voltage of the commercial AC power supply AC with higher resolution, a conversion table with higher resolution may be employed. Alternatively, a voltage value with higher resolution may be calculated by using a function such as an approximate expression.

  In FIG. 3, the load control unit 301 controls the load 320 by using the voltage value determined by the voltage determination unit 305 or the zero cross timing as a trigger. For example, if the load 320 is a fixing device of an electrophotographic image forming apparatus, the load control unit 301 can control the power supplied to the heater of the fixing device by wave number control. The wave number control refers to adjusting the electric power applied to the heater in units of wave number (half cycle of alternating current). The load control unit 301 can recognize the start position of the half cycle based on the zero cross timing. In addition, since the load control unit 301 can also acquire the voltage level of the AC voltage, the power to be supplied to the heater is determined from the voltage level, and the AC having the wave number necessary for the zero cross timing is supplied to the load 320. Note that the image forming apparatus is merely an example, and the first embodiment can be applied to any electrical device provided with a load that operates by being supplied with alternating current.

  As described above, according to the first embodiment, the information signal in which the information indicating the timing of the zero crossing and the information indicating the voltage level of the AC voltage are superimposed is generated and transmitted. Therefore, the number of signal lines and input ports 104 for transmitting information signals can be reduced. That is, it is possible to detect the zero crossing and the AC voltage while reducing circuit components.

  In particular, in the first embodiment, the zero cross timing is expressed by the time position of the rising edge of the pulse signal. Further, the AC voltage of the commercial AC power supply AC is expressed by the time interval between the rising edge and the falling edge of the pulse signal. Therefore, the microcomputer 105 can recognize the zero cross timing and the AC voltage from the pulse signal input from one input port 104. Note that the time interval between rising edges and the time interval between falling edges are both constant. Therefore, the microcomputer 105 can also obtain the frequency of the AC voltage from any time interval.

  In the first embodiment, it is assumed that the voltage waveform of the commercial AC power supply AC is a sine wave. The conversion table stored in the storage device 310 is also created assuming a sine wave. Here, a voltage other than a sine wave such as a rectangular wave may be supplied from the commercial AC power supply AC. In this case, the microcomputer 105 can detect that a rectangular wave or the like has been input. The slope of the rectangular wave voltage (dv / dt) is very large compared to the slope of the sinusoidal voltage. Therefore, the pulse width for the rectangular wave is much longer than that of the sine wave. Therefore, the microcomputer 105 may determine that the waveform of the AC voltage is not a sine wave when the pulse width measured by the second counter 304 exceeds a predetermined threshold. This determination may be handled by the voltage determination unit 305. When the load control unit 301 receives a determination signal from the voltage determination unit 305 that the AC voltage waveform is not a sine wave, the load control unit 301 stops the supply of AC to the load 320. For example, the load control unit 301 stops the supply of alternating current by switching off a switching element such as a triac. Thereby, the load 320 can be protected.

  For Example 1, it is not essential that the waveform of the AC voltage is a sine wave. Embodiment 1 can be applied to any AC voltage whose slope (dv / dt) changes according to the effective value.

  In FIG. 1, the LPF is formed using a resistor R3 and a capacitor C1. An FET Q2 is employed as the switch element. However, a circuit that can appropriately adjust the phase of the AC voltage is sufficient. Instead of the FET Q2, any switch element that switches between a conductive state and a non-conductive state according to the voltage level of the control signal, such as a semiconductor switch such as a transistor or a relay, can be used.

  In FIG. 1, a photocoupler PC that insulates the primary side and the secondary side is employed, but this is not essential. Instead of the photocoupler PC, a switch element such as a semiconductor switch or a relay may be employed. Alternatively, the photocoupler PC may be eliminated and the drain terminal of the FET Q2 may be directly connected to the input port 104.

<Example 2>
In the second embodiment, the detection device 100 of the first embodiment is improved so that the detection accuracy of the voltage level is improved. Specifically, the dynamic range of the voltage level is expanded by increasing the change in pulse width according to the difference in voltage level. That is, the amount of change in the position of the second edge with respect to the amount of change in the voltage level of the AC voltage increases.

  FIG. 5 shows a detection device 100 according to the second embodiment. In the second embodiment, the same reference numerals are assigned to the same circuit elements as in the first embodiment, and the description of the first embodiment is used. In the second embodiment, the voltage detection unit 106a is replaced with a voltage detection unit 106b. The voltage detection unit 106b includes a level detection unit 501, a timing adjustment unit 502, and a voltage generation unit 503. The AC voltage supplied from the commercial AC power supply AC is input to the level detection unit 501. The level detection unit 501 is a voltage dividing circuit formed by a resistor R4 and a resistor R5, and converts an AC voltage supplied from a commercial AC power supply AC into an AC voltage proportional to the AC voltage and outputs the AC voltage.

  The AC voltage of the commercial AC power supply AC is also input to the timing adjustment unit 502. The timing adjustment unit 502 is a circuit that adjusts the timing at which the FET Q3 switches from on (conducting) to off (non-conducting). The timing adjustment unit 502 is an LFP composed of a resistor R6 and a capacitor C2. That is, the timing adjustment unit 502 outputs the AC voltage with a delayed phase. The diode D3 is arranged for the purpose of separating the level detection unit 501 and the timing adjustment unit 502. Both the current output from the level detection unit 501 and the current output from the timing adjustment unit 502 flow into the resistor R7. That is, the resistor R7 functions as an adder that adds these currents and converts the sum of the currents into a voltage. In this way, the resistor R7 adds the voltage detected by the level detection unit 501 and the voltage output from the timing adjustment unit 502.

  The voltage generator 503 is a circuit that generates a DC voltage from an AC voltage supplied from a commercial AC power supply AC. The resistors R8 and R9 of the voltage generator 503 form a voltage dividing circuit, which divides and outputs an AC voltage. The diode D4 is a rectifying element that half-wave rectifies the AC voltage generated by the voltage dividing circuit. The capacitor C3 is a smoothing element that smoothes the pulsating current output from the diode D4 and generates a direct current. The voltage generated by the voltage generator 503 is divided by a voltage dividing circuit formed by the resistors R10 and R11, and is applied to the gate of the FET Q3. Similarly, the voltage across resistor R7 is applied to the gate of FET Q3 via capacitor C4. That is, the voltage across the resistor R7 and the DC voltage from the voltage generator 503 are superimposed and applied to the gate of the FET Q3. Note that the capacitor C4 has a role of cutting the DC component of the voltage across the resistor R7. In the case where the direct current component hardly affects the operation of the FET Q3, the capacitor C4 may be omitted. The reason why the DC voltage from the voltage generator 503 is divided by the resistors R10 and R11 and applied to the gate of the FET Q3 is to reduce the influence of the diode D4 and the capacitor C3 of the voltage generator 503. This improves the voltage detection accuracy.

  FIG. 6A shows an AC voltage waveform W1, a voltage waveform W2 applied to the gate of the FET Q3, and a pulse signal waveform W3 in the second embodiment. The AC voltage divided by the level detection unit 501 and the output voltage of the timing adjustment unit 502 are added by a resistor R7. As shown by the waveform W2, the waveform of the voltage applied to the gate is a waveform in which the amplitude of a part of the sine wave is increased. By adding the output voltage of the timing adjustment unit 502 to the output voltage of the level detection unit 501, the timing at which the FET Q3 becomes non-conductive is adjusted after the timing at which the light-emitting diode D1 becomes non-conductive. Since the light emitting diode D1 and the FET Q3 are connected in series, the rising edge of the pulse signal is generated by the non-conduction of the light emitting diode D1, and the falling edge is generated by the conduction of the FET Q3.

  FIG. 6B shows voltage waveforms W1 to W3 when the voltage of the commercial AC power supply AC is changed in four steps in increments of 20V in the range from 80V to 140V. The timing of the rising edge generated when the light emitting diode D1 becomes non-conductive does not change even if the voltage level of the commercial AC power supply AC changes. On the other hand, the timing at which the gate voltage of the FET Q3 exceeds the gate threshold value of the FET Q3 varies greatly depending on the voltage level of the commercial AC power supply AC. That is, the falling edge timing varies greatly depending on the voltage level of the commercial AC power supply AC. Further, since the pulse width varies greatly depending on the voltage level of the commercial AC power supply AC, the dynamic range of the detected voltage is expanded.

  FIG. 6C shows the relationship between the effective value of the AC voltage and the pulse width. In the second embodiment, the voltage applied to the gate terminal of the FET Q3 is designed so as to substantially depend only on the resistance. As can be seen from the difference between PW1, PW2 and PW3, the variation in the voltage detection result due to the circuit components is significantly suppressed in the second embodiment compared to the first embodiment. Further, the voltage level difference of the commercial AC power supply AC is expressed by the sum of two pieces of information, that is, the voltage gradient (dv / dt) and the DC voltage generated by the voltage generator 503. Therefore, the amount of change in the pulse width with respect to the voltage change of the commercial AC power supply AC in the second embodiment is larger than that in the first embodiment.

  Thus, the voltage generation unit 503 plays a role of improving the voltage detection accuracy by increasing the amount of change in the pulse width with respect to the voltage change of the commercial AC power supply AC. However, the voltage generation unit 503 is not essential and may be omitted. The necessity of the voltage generator 503 can be determined according to how much the dynamic range of voltage detection is necessary.

<Example 3>
In the third embodiment, an edge indicating the zero cross and an edge indicating the voltage level of the AC voltage are generated by the FET, respectively. That is, by making the rising edge a steeper edge, the zero-cross detection accuracy is improved.

  FIG. 7 shows a detection device 100 according to the third embodiment. The AC voltage of the commercial AC power supply AC is applied to the rectifying / smoothing circuit 701. In the rectifying / smoothing circuit 701, the alternating current is half-wave rectified by the resistor R12 and the diode D5 to become a pulsating current, and the pulsating current is smoothed by the capacitor C5 and converted into a direct current. The DC voltage generated across the capacitor C5 functions as a voltage source for the photocoupler PC. The DC voltage is applied to the anode of the light emitting diode D1 of the photocoupler PC via the current limiting resistor R1 and the FET Q4. Therefore, the light-emitting diode D1 of Example 3 is always maintained in a conductive state and does not function as a direct switch element for creating an edge. That is, the conduction / non-conduction of the FET Q4 connected in series with the diode Q4 controls the conduction / non-conduction of the light emitting diode D1. The transient response for the conduction / non-conduction of the FET Q4 is generally faster than the transient response of the light emitting diode D1. Therefore, the rising edge of the pulse signal is steeper in the third embodiment than in the first embodiment. Since the rising edge becomes a steep edge, the influence of the variation in the voltage detection threshold at the input port 104 on the edge detection is reduced. As a result, the accuracy of zero cross detection is increased.

  The resistors R13 and R14 form a voltage dividing circuit that divides the AC voltage supplied from the commercial AC power supply AC. The voltage generated by the resistors R13 and R14 is applied to the gate of the FET Q4. The FET Q4 operates so as to form a rising edge indicating the zero cross timing of the AC voltage of the commercial AC power supply AC. Therefore, the FET Q4 whose gate voltage is about several volts is selected.

  Zener diode D6 conducts when a forward current flows when the AC voltage from commercial AC power supply AC is a negative voltage. Thereby, the negative voltage of the capacitor C5 can be suppressed to the forward voltage of the Zener diode D6. When the AC voltage of the commercial AC power supply AC is a positive voltage, the Zener diode D6 suppresses the positive voltage of the capacitor C5 to the breakdown voltage. This will be particularly useful when a high voltage outside the specification is output from the commercial AC power supply AC. The voltage detection unit 106c includes a high-pass filter (HPF) 703 and an FET Q5. The HPF 703 includes a capacitor C6 and a resistor R15. The HPF 703 generates a voltage that is correlated with the AC voltage and has a phase that is more advanced than the phase of the AC voltage. Since the FET Q5 is connected in parallel with the light emitting diode D1, the light emitting diode D1 can be forcibly turned off. The voltage detector 106c forms a rising edge when the FET Q5 conducts in accordance with the voltage level of the AC voltage.

  FIG. 8A shows the voltage waveforms W1 to W3 and the state of the FET Q5 in the third embodiment. W2 is a voltage waveform of a voltage applied to the FET Q5. W6 indicates conduction (ON) and non-conduction (OFF) of the FET Q5. The FET Q4 becomes conductive when the voltage of the commercial AC power supply AC exceeds a predetermined voltage. Therefore, when the FET Q4 is switched from conduction to non-conduction at the zero cross timing, the light emitting diode D1 is turned off and a rising edge is formed.

  The FET Q4 is connected in parallel with the FET Q5. Therefore, only when the FET Q5 is in a non-conducting state, a forward voltage is applied to the light emitting diode D1, and the FET Q4 can form a rising edge. As shown in FIG. 8A, when the zero crossing occurs in the voltage waveform W1 when the FET Q5 is in the non-conduction state (OFF), the FET Q4 is switched from the conduction state to the non-conduction state, and a rising edge is formed. As shown in FIG. 8A, when the FET Q5 is in the conductive state (ON), a rising edge is not formed even if a zero cross occurs.

  As described above, the phase of the AC voltage of the commercial AC power supply AC advances by passing through the HPF 703. The cutoff frequency of the HPF 703 is set to advance the phase of the AC voltage by several tens of degrees and 90 degrees or less in the range from 50 Hz to 60 Hz which is the frequency of the AC voltage. The waveform of the AC voltage of the commercial AC power supply AC becomes a voltage waveform W2 by passing through the HPF 703. When the gate voltage whose phase has advanced through the HPF 703 exceeds the gate threshold (eg, 3 V), the drain and source of the FET Q5 transition from the non-conductive state to the conductive state. As the HPF 703 advances the voltage phase, the conduction timing and non-conduction timing of the FET Q5 advance more than those of the FET Q4. In the third embodiment, when the FET Q4 transitions from the conductive state to the non-conductive state, the diode D1 is turned off and a rising edge indicating a zero cross is formed. Therefore. At the timing when the FET Q4 transitions from the conductive state to the non-conductive state, the state of the FET Q5 must be a non-conductive state. Therefore, the timing at which the FET Q5 transitions to the non-conduction state is advanced by the HPF 703 earlier than the timing at which the FET Q4 transitions to the non-conduction state. Further, the falling edge for notifying the voltage level is formed by turning on the light emitting diode D1 by switching the FET Q5 from the conductive state to the nonconductive state. Therefore, when the FET Q5 transitions from the conductive state to the non-conductive state, the state of the FET Q4 must be a conductive state. Since the timing at which the FET Q5 transitions to the non-conducting state is advanced by the HPF 703 earlier than the timing at which the FET Q4 transitions to the non-conducting state, this condition is also satisfied.

  FIG. 8B shows voltage waveforms W1 to W3 when the voltage of the commercial AC power supply AC is changed in four steps in increments of 20V within a range from 80V to 140V. The timing of the rising edge generated when the FET Q4 becomes non-conductive does not change substantially even when the voltage of the commercial AC power supply AC changes. On the other hand, the timing at which the gate voltage of the FET Q5 exceeds the gate threshold varies greatly depending on the voltage of the commercial AC power supply AC. That is, the timing of the falling edge generated when the FET Q5 becomes non-conductive varies greatly depending on the voltage of the commercial AC power supply AC. It should be noted that the timing at which the FET Q5 starts to conduct also varies greatly depending on the voltage of the commercial AC power supply AC. Since the HPF 703 is designed so that the FET Q4 is non-conductive whenever the FET Q5 starts to conduct, the pulse signal does not depend on the timing when the FET Q5 starts to conduct.

  In the third embodiment, a capacitor C5 is used for the voltage detection unit 106c as in the first embodiment. Therefore, the voltage detection result is easily affected by variations in the capacitor C5. Therefore, a variable resistor may be employed as the resistor R15. By setting the resistance value of the variable resistor so as to reduce the variation in the capacitance of the capacitor C5, the voltage detection accuracy is improved.

<Example 4>
The fourth embodiment improves the voltage detection accuracy by combining the zero cross detection unit of the third example and the voltage detection unit of the second example. In the third embodiment, since the HPF 703 of the voltage detection unit 106c is interposed in the gate of the FET Q5, the falling edge is affected by the HPF 703. Therefore, in the fourth embodiment, a voltage detection unit similar to the voltage detection unit 106b of the second embodiment is employed instead of the voltage detection unit 106c.

  FIG. 9 shows a detection device 100 according to the fourth embodiment. The zero cross detection unit 101c is the same as the zero cross detection unit used in the third embodiment. The voltage detection unit 106d is formed by changing a part of the voltage detection unit 106b of the second embodiment. As illustrated in FIG. 9, the zero-cross detection unit 101 c includes a rectifying and smoothing circuit 701 that functions as a voltage generation unit that generates a DC voltage. Therefore, the voltage generator 503 shown in FIG. 5 is not necessary. The DC voltage generated by the rectifying / smoothing circuit 701 is applied to the gate terminal of the FET Q6 via the resistor R16. Since this DC voltage is a voltage exceeding the gate threshold value of the FET Q6, the FET Q6 is always maintained in a conductive state. The drain terminal of the FET Q3 is connected to the gate terminal of the FET Q6 via the current limiting resistor R17. The FET Q3 and the FET Q6 substantially form an inverting circuit. If FET Q3 is in the conducting state, the gate voltage of FET Q6 is less than or equal to the gate threshold, and the state of FET Q6 is in the non-conducting state. On the other hand, if the state of the FET Q3 is non-conductive, the gate voltage of the FET Q6 exceeds the gate threshold value, so that the state of the FET Q6 becomes conductive. Thus, since the FET Q6 is connected in parallel to the light emitting diode D1 and the FET Q4, it contributes to the formation of the falling edge in the same manner as the FET Q5 of the fourth embodiment.

  FIG. 10A shows a voltage waveform in the fourth embodiment. W2 is a voltage waveform of the gate voltage of the FET Q3. W10 is a voltage waveform of the gate voltage of the FET Q6. As shown in FIG. 9, the FET Q4 and the FET Q6 are connected in parallel to the commercial AC power supply AC. When the FET Q4 is in the conductive state, the light emitting diode D1 is lit by the FET Q6 transitioning from the conductive state to the non-conductive state, and a falling edge is generated. Thereby, the voltage level of the AC voltage is transmitted to the microcomputer 105. The FET Q6 is always kept in a conductive state. Therefore, the state of the FET Q6 is controlled by the FET Q3. During the period when the FET Q3 is in the conductive state, the FET Q6 is maintained in the non-conductive state. That is, as indicated by the voltage waveforms W2 and W3, when the gate voltage of the FET Q3 exceeds the gate threshold, the FET Q6 transitions to a non-conduction state. Further, when the gate voltage of the FET Q3 becomes equal to or lower than the gate threshold, the FET Q6 transitions to a conductive state.

  When FET Q6 is in a non-conductive state, the gate voltage of FET Q4 is less than or equal to the gate threshold, so that FET Q4 transitions from a conductive state to a non-conductive state, the light emitting diode D1 is turned off, and a rising edge is formed. Is done. As a result, the zero cross timing of the AC voltage is transmitted to the microcomputer 105.

  FIG. 10B shows voltage waveforms W1, W2, and W10 when the voltage of the commercial AC power supply AC is changed in four steps in increments of 20V in the range from 80V to 140V. The position of the rising edge generated by the FET Q4 becoming non-conductive does not change substantially even when the voltage of the commercial AC power supply AC changes. On the other hand, the timing at which the gate voltage of the FET Q6 becomes equal to or lower than the gate threshold varies greatly depending on the voltage of the commercial AC power supply AC. The position of the falling edge generated when the FET Q6 transitions from the conducting state to the non-conducting state varies greatly depending on the voltage of the commercial AC power supply AC. In the fourth embodiment, the timing at which the gate voltage of the FET Q6 becomes equal to or lower than the gate threshold depends substantially only on the resistance. Resistors are generally circuit elements with little variation in resistance value, but capacitors and coils are circuit elements with large variations in capacitance value and inductance value. Such variations in circuit elements lower the voltage detection accuracy. In Example 4, only a resistor is interposed, and no capacitor, coil, or the like is interposed. Therefore, the fourth embodiment can detect the voltage of the commercial AC power supply AC with higher accuracy than the third embodiment.

<Example 5>
In the fifth embodiment, the drive source of the photocoupler PC in the fourth embodiment is changed from a DC voltage to an AC voltage. FIG. 11 shows a detection device 100 according to the fifth embodiment. The zero cross detector 101a is the same as the zero cross detector used in the first and second embodiments. The voltage detection unit 106e is formed by combining the voltage detection unit 106d of the fourth embodiment with the voltage generation unit 503 of the second embodiment. That is, the DC voltage generated by the voltage generator 503 is applied to the gate terminal of the FET Q6 via the resistor R16. The DC voltage generated by the voltage generator 503 is set to a voltage higher than the gate threshold value of the FET Q6. Therefore, the FET Q6 is always in a conductive state. The drain of the FET Q3 is connected to the gate terminal of the FET Q6 via the current limiting resistor R17. Therefore, when the FET Q3 transitions to the conductive state, the gate voltage of the FET Q6 becomes lower than the gate threshold value, and the FET Q6 transitions to the non-conductive state.

  FIG. 12A shows voltage waveforms W1, W2, and W10 according to the fifth embodiment. Compared to FIG. 10A, it can be seen that the voltage waveforms W1, W2, and W10 are the same in FIG. 12A. That is, the circuit configuration of the zero cross detection unit 101a does not affect the operation of the voltage detection unit 106e.

  In the fifth embodiment, the light emitting diode D1 itself controls the conduction and non-conduction of the light emitting diode D1 of the photocoupler PC. For this reason, the slope of the rising edge of the pulse signal of the fifth embodiment is gentler than the slope of the rising edge of the fourth embodiment.

  FIG. 12B shows voltage waveforms W1, W2, and W10 when the voltage of the commercial AC power supply AC is changed in four steps in increments of 20V within a range from 80V to 140V. In the first and second embodiments, the FETs Q2 and Q3 that generate the falling edge of the pulse signal are connected to the commercial AC power supply AC. On the other hand, in the fifth embodiment, the gate of the FET Q3 that controls the timing of the falling edge is connected to the output (several V to several tens V) of the voltage generator 503. Therefore, an FET having a lower withstand voltage than the FETs of the first and second embodiments can be used as the FET Q3. Instead of the FET Q3, a shunt regulator or the like having a low breakdown voltage and a small variation in threshold voltage may be employed. This will further improve the voltage detection accuracy of the commercial AC power supply AC.

<Example 6>
The sixth embodiment employs a configuration in which the zero cross detection unit 101c used in the third and fourth embodiments is combined with a voltage detection unit having hysteresis characteristics. FIG. 13 shows a detection device 100 according to the sixth embodiment. The voltage detection unit 106f includes a comparator CP having hysteresis characteristics. The resistors R18 and R19 are voltage dividing circuits that divide the DC voltage generated by the rectifying and smoothing circuit 701 and apply the divided voltage to the non-inverting input terminal (+ terminal) of the comparator CP. This is the reference voltage for the comparator CP. The resistor R13 and the resistor R14 described above are voltage dividing circuits that divide the AC voltage of the commercial AC power supply AC and apply it to the inverting input terminal (− terminal) of the comparator CP. The reference voltage input to the non-inverting input terminal (+ terminal) is, for example, a voltage corresponding to the AC voltage 85V (≈60V × √2) of the commercial AC power supply AC. This is to stop the load 320 such as an AC / DC converter when the AC voltage is less than 85V. Therefore, the reference voltage can be set according to the load.

  FIG. 14A shows a voltage waveform in the sixth embodiment. W13 indicates the voltage waveform of the gate voltage of the FET Q7. W14 indicates the output state of the comparator CP. The output of the comparator CP becomes high impedance (Hiz) when the voltage of the commercial AC power supply AC is less than 85V. When the output of the comparator CP is Hiz, a DC voltage is applied to the gate terminal of the FET Q7 by the pull-up resistor R20. As a result, the FET Q7 becomes conductive. When the FET Q7 becomes conductive, the light emitting diode D1 is turned on, and the pulse signal becomes low level. In the sixth embodiment, the falling edge indicates zero cross timing.

  When the voltage of the commercial AC power supply AC is +85 V or higher, the output of the comparator CP is approximately 0 V (L), so that the FET Q7 becomes non-conductive. When the FET Q7 becomes non-conductive, the light emitting diode D1 is turned on, and the pulse signal becomes high level. In the sixth embodiment, the rising edge indicates the voltage level.

  When the output of the comparator CP becomes L, this is equivalent to a state in which the resistor R21 is connected in parallel to the resistor R19. The resistance value of the resistor R21 is set sufficiently lower than the resistance value of the resistor R19. Therefore, the reference voltage input to the non-inverting input terminal (+ terminal) when the output of the comparator CP becomes L is a voltage corresponding to approximately 0 V as the voltage of the commercial AC power supply AC. Once the output of the comparator CP, which has output L, does not invert to Hiz again unless the voltage of the commercial AC power supply AC drops to approximately 0V. That is, the operation of the comparator CP has a hysteresis characteristic such that the output is L when the voltage of the commercial AC power supply AC is 85 V or higher, and Hiz is output when the voltage of the commercial AC power supply AC is approximately 0 V or lower.

  FIG. 14B shows voltage waveforms W1, W3, and W13 when the voltage of the commercial AC power supply AC is changed in four steps in increments of 20V in the range from 80V to 140V. Due to the hysteresis characteristic of the comparator CP, the rising edge changes according to the voltage of the commercial AC power supply AC, and the falling edge does not depend on the voltage of the commercial AC power supply AC. Thus, in the sixth embodiment, the information transmitted by the rising edge and the information transmitted by the falling edge are different from those in the first to fifth embodiments.

  In the first to fifth embodiments, the element that generates the falling edge and the element that generates the rising edge are individually provided. In the sixth embodiment, the falling edge and the rising edge can be generated only by the FET Q7. Therefore, the sixth embodiment can reduce the number of switch elements as compared with the third to fifth embodiments.

<Example 7>
FIG. 15 shows the intermediate transfer type image forming apparatus 1 to which the detection apparatus 100 and the microcomputer 105 can be applied. The image forming apparatus 1 may be an image forming apparatus that forms a single color image, but here is an electrophotographic image forming apparatus that forms a multicolor image by mixing a plurality of colorants. The image forming apparatus 1 uses four color developers such as yellow (Y), magenta (M), cyan (C), and black (BK). In FIG. 15, a character indicating a color is given at the end of the reference number, but this character is omitted when a matter common to the four colors is described.

  The photosensitive drums 6C, 6M, 6Y, and 6BK are image carriers that are arranged at equal intervals and carry an electrostatic latent image and a toner image. The engine controller 1502 includes a microcomputer 105 and controls a power supply device 1500 included in the image forming apparatus 1 and a load 320 such as a motor, an actuator, a solenoid, a sensor, and a heater 15. The power supply device 1500 is connected to a commercial AC power supply AC via a power cable 1501. The power cable 1501 functions as an AC voltage input unit. The power supply device 1500 includes the detection device 100, an AC / DC converter, a DC / DC converter, and the like.

  The primary charger 2 uniformly charges the surface of the photosensitive drum 6 using a charging voltage supplied from the power supply device 1500. The scanning optical device 3 emits a light beam (laser beam) L modulated based on the input image toward the photosensitive drum 6. The light beam (laser beam) L forms an electrostatic latent image on the surface of the photosensitive drum 6. The engine controller 1502 controls the power supply device 1500 to generate a development voltage and supplies it to the developing device 4. The developing device 4 attaches cyan, magenta, yellow, and black developers to the electrostatic latent image through sleeves and blades to which a developing voltage is applied. As a result, the electrostatic latent image is developed, and a developer image (toner image) is formed.

  The paper feed roller 8 is driven by a motor or solenoid controlled by the microcomputer 105. The paper feed roller 8 feeds the sheets P stored in the paper feed tray 7 one by one. The registration roller 9 is driven by a motor controlled by the microcomputer 105. The registration roller 9 sends the sheet P toward the secondary transfer portion in synchronization with the image writing timing.

  The engine controller 1502 controls the power supply device 1500 to generate a primary transfer voltage and supplies it to the primary transfer roller 5. The primary transfer roller 5 primarily transfers the toner image carried on the photosensitive drum 6 to the intermediate transfer belt 10. The primary transfer voltage applied to the primary transfer roller 5 promotes the primary transfer of the toner image. The intermediate transfer belt 10 functions as an intermediate transfer member. The driving roller 11 is a roller that rotates the intermediate transfer belt 10. The secondary transfer unit has a secondary transfer roller 14. The engine controller 1502 controls the power supply device 1500 to generate a secondary transfer voltage and supplies it to the secondary transfer roller 14. In the secondary transfer portion, the intermediate transfer belt 10 and the secondary transfer roller 14 convey the sheet P while sandwiching the sheet P, so that the multicolor toner image carried on the intermediate transfer belt 10 is secondary to the sheet P. Transcribed. The secondary transfer voltage promotes secondary transfer. Thereafter, the sheet P is conveyed to the fixing device 12. The fixing device 12 applies pressure and heat to the toner image carried on the sheet P to fix it. The discharge roller 13 discharges the sheet P on which an image is formed. The fixing device 12 has a heater 15 and the temperature is controlled by a microcomputer 105. The microcomputer 105 controls the power supplied to the heater 15 by the wave number control described above.

<Summary>
As described with reference to the first to sixth embodiments, the detection device 100 generates a superimposed signal in which information indicating the zero-cross timing in the AC voltage and information indicating the voltage level of the AC voltage are superimposed. As a result, it is possible to reduce the number of signal lines for transmitting the zero-cross timing and the voltage level. For example, the detection apparatus 100 generates, as a superimposed signal, a pulse signal that includes a first edge indicating zero-crossing timing in an AC voltage and a second edge whose time interval with respect to the first edge changes according to the voltage level of the AC voltage. There may be provided a pulse generation circuit.

  Such a pulse generation circuit includes a first edge circuit that generates a first edge at the timing of zero crossing, and a second edge circuit that generates a second edge at a timing according to the gradient of the AC voltage. The zero cross detection units 101a and 101c are examples of the first edge circuit. Moreover, the voltage detection parts 106a-106f are examples of a 2nd edge circuit. The first edge circuit generates a first edge when the voltage level of the AC voltage is the first level. As described with reference to FIG. 2A and the like, the first level is the forward voltage VF of the light emitting diode D1. In FIG. 7, the first level is the gate threshold value of the FET Q4. As described above, the forward voltage VF is sufficiently smaller than the effective value of the AC voltage, and can be evaluated as almost 0V. Thereby, the zero cross point is accurately detected.

  As described with reference to FIG. 2B and the like, the second edge circuit detects a second level that is a voltage level of an AC voltage or a voltage correlated with the AC voltage, and generates a second edge according to the second level. . The second level is a gate threshold value such as FET Q2. The slope of the AC voltage changes according to the voltage level of the AC voltage. That is, the timing at which the voltage correlated with the AC voltage exceeds the gate threshold also changes according to the voltage level of the AC voltage. By utilizing such characteristics of the switch element, the voltage level is reflected on the second edge.

  As shown in FIG. 1, the first edge circuit may include a first switch element that conducts when the AC voltage exceeds the threshold and does not conduct unless the AC voltage exceeds the threshold. The light emitting diode D1 is an example of a first switch element. The second edge circuit may include a delay circuit and a second switch element. The delay circuit is a circuit that delays the phase of the AC voltage. The second switch element is a switch element that has a control terminal to which an alternating voltage with a phase delay is applied and switches between a conductive state and a non-conductive state according to the voltage applied to the control terminal. The gate terminal is an example of a control terminal. The level detection unit 107 constituting the low-pass filter is an example of a delay circuit. The FET Q2 is an example of a second switch element. As shown in FIG. 1 and the like, the first switch element and the second switch element are connected in series. As shown in FIG. 2B, the first edge circuit generates the first edge indicating the zero-cross timing because the first switch element is not conductive. As shown in FIG. 2A, in the second edge circuit, when the first switch element is in a conductive state, the second switch element changes from a non-conductive state to a conductive state according to the voltage level of the AC voltage. To generate a second edge indicating the voltage level. Here, the first edge is a rising edge generated when the pulse signal is switched from the low level to the high level. The second edge is a falling edge generated by switching from a high level to a low level. The relationship between these edges may be reversed.

  As described in the second embodiment, the first edge circuit includes the first switch element that is conductive when the AC voltage exceeds the threshold value and that is not conductive unless the AC voltage exceeds the threshold value. The second edge circuit may include a first voltage dividing circuit, a delay circuit, an adder circuit, a second switch element, and the like. As shown in FIG. 5, the voltage detector 106b is an example of a second edge circuit. The level detection unit 501 is an example of a first voltage dividing circuit that divides an AC voltage and generates a voltage correlated with the AC voltage. The timing adjustment unit 502 is an example of a delay circuit that delays the phase of the AC voltage. The resistor R7 is an example of an adding circuit that adds the voltage output from the first voltage dividing circuit and the voltage output from the delay circuit. The FET Q3 is an example of a second switch element that has a control terminal to which a voltage output from the adder circuit is applied and switches between a conductive state and a non-conductive state according to the voltage applied to the control terminal. Also in Example 2, the first switch element and the second switch element are connected in series. As illustrated in FIG. 6B and the like, the first edge circuit generates the first edge indicating the zero-cross timing when the first switch element is not conductive. The second edge circuit changes the voltage level by changing the second switch element from the non-conductive state to the conductive state according to the voltage level of the voltage output from the adder circuit when the first switch element is conductive. The second edge shown is generated.

  As described in the second embodiment, the second edge circuit further includes a rectifying / smoothing circuit that rectifies and smoothes an AC voltage to generate a DC voltage, and applies the DC voltage to the control terminal of the second switch element. May be. The voltage generator 503 is an example of a rectifying / smoothing circuit. By employing such a rectifying / smoothing circuit, the voltage level detection accuracy is further improved. As described in the second embodiment, the voltage generation unit 503 may include a second voltage dividing circuit that divides a DC voltage and applies the divided voltage to the control terminal of the second switch element. As shown in FIG. 5, the resistors R8 and R9 are an example of a second voltage dividing circuit.

  As shown in the third embodiment, the first edge circuit may be realized by the zero cross detection unit 101c. The rectifying / smoothing circuit 701 is an example of a rectifying / smoothing circuit that generates a DC voltage by rectifying and smoothing an AC voltage. The FET Q4 operates by being supplied with a DC voltage, has a control terminal to which a voltage correlated with the AC voltage is applied, and conducts when the voltage correlated with the AC voltage exceeds a threshold, and the voltage correlated with the AC voltage becomes a threshold. It is an example of the 1st switch element which does not conduct unless it exceeds. The second edge circuit may be realized by the voltage detection unit 106c. The HPF 703 is an example of a phase circuit that advances the phase of the AC voltage. The FET Q5 is an example of a second switch element that has a control terminal to which an AC voltage whose phase is advanced by a phase circuit is applied, and switches between a conductive state and a non-conductive state according to the voltage applied to the control terminal. is there. As shown in FIG. 7, the first switch element and the second switch element are connected in parallel. The zero-cross detection unit 101c generates a first edge indicating the zero-cross timing when the first switch element transitions from the conductive state to the non-conductive state. As shown in FIG. 8A and the like, the voltage detection unit 106c causes the second switch element to transition from the conductive state to the non-conductive state according to the voltage level of the AC voltage when the first switch element is in a conductive state. To generate a second edge indicating the voltage level. As shown in FIG. 7, the first switch element may be formed by a series connection of a light emitting diode D1 that is a rectifying element and an FET Q4 that is a semiconductor switch.

  As described in the fourth embodiment, the first edge circuit may be realized by the zero-cross detection unit 101c. The second edge circuit may be realized by the voltage detection unit 106d. As shown in FIG. 9, the level detection unit 501 is an example of a first voltage dividing circuit that divides an AC voltage and generates a voltage correlated with the AC voltage. The timing adjustment unit 502 is an example of a delay circuit that delays the phase of the AC voltage. The resistor R7 is an example of an adding circuit that adds the voltage output from the first voltage dividing circuit and the voltage output from the delay circuit. The FET Q3 is an example of a second switch element that has a control terminal to which a voltage output from the adder circuit is applied and switches between a conductive state and a non-conductive state according to the voltage applied to the control terminal. The FET Q6 is a DC voltage generated from an AC voltage, and has a control terminal to which a DC voltage that is controlled to be applied and not applied by the second switch element is applied, and is connected in parallel with the first switch element. It is an example of a 3rd switch element. In the voltage detection unit 106d, when the first switch element is in a conductive state, the third switch element is in a conductive state by the second switch element transitioning from a non-conductive state to a conductive state according to the voltage level of the AC voltage. The second edge indicating the voltage level is generated by transitioning from to non-conducting state. This is illustrated in FIGS. 10A and 10B.

  As described in the fifth embodiment, the first edge circuit may be the zero cross detection unit 101a. The second edge circuit may be the voltage detection unit 106e. As shown in FIG. 10, the level detection unit 501 is an example of a first voltage dividing circuit that divides an AC voltage and generates a voltage correlated with the AC voltage. The timing adjustment unit 502 is a delay circuit that delays the phase of the AC voltage. The resistor R3 is an example of an adding circuit that adds the voltage output from the first voltage dividing circuit and the voltage output from the delay circuit. The FET Q3 is an example of a second switch element that has a control terminal to which a voltage output from the adder circuit is applied and switches between a conductive state and a non-conductive state according to the voltage applied to the control terminal. The FET Q6 is a DC voltage generated from an AC voltage, and has a control terminal to which a DC voltage that is controlled to be applied and not applied by the second switch element is applied, and is connected in parallel with the first switch element. It is an example of a 3rd switch element. When the first switch element is conductive, the voltage detection unit 106e changes the second switch element from the non-conductive state to the conductive state according to the voltage level of the AC voltage, so that the third switch element is changed from the conductive state. The second edge indicating the voltage level is generated by transitioning to the non-conduction state.

  As described in the sixth embodiment, the pulse generation circuit may include a FET Q7 that is a switch element and a comparator CP. Comparator CP has hysteresis characteristics and switches between a conductive state and a non-conductive state of the switch element in accordance with a voltage correlated with the AC voltage. As shown in FIG. 14A, the comparator CP causes the switch element to transition from the non-conductive state to the conductive state so that the switch element generates the first edge at the timing of zero crossing. As illustrated in FIG. 14B, the comparator CP causes the switch element to transition from the conductive state to the non-conductive state so that the second edge is generated at a timing corresponding to the slope of the voltage correlated with the AC voltage. In Example 6, the rising edge corresponds to the second edge, and the falling edge corresponds to the first edge.

  As shown in FIGS. 3 and 15, the microcomputer 105 and the engine controller 1502 are examples of controllers. The input port 104 is an input unit to which a pulse signal including a first edge indicating the timing of zero crossing in the AC voltage and a second edge whose time interval with respect to the first edge changes according to the voltage level of the AC voltage is input. It is an example. The second counter 304 is an example of a measuring unit that measures a time interval between the first edge and the second edge. Here, the time interval from the second edge to the first edge is measured. The voltage determination unit 305 is an example of a determination unit that determines the voltage level of the AC voltage based on the time interval measured by the measurement unit. The load control unit 301 is an example of a control unit that controls the load using the zero-cross timing and voltage level indicated by the first edge. As described above, the microcomputer 105 can acquire the zero-cross timing and the voltage level by using the single input port 104.

  As described with reference to FIG. 15, the photosensitive drum 6 is an example of an image carrier. The primary charger 2 is an example of a charging unit that uniformly charges the image carrier. The scanning optical device 3 is an example of an exposure unit that exposes an image carrier to form an electrostatic latent image. The developing device 4 is an example of a developing unit that develops an electrostatic latent image to form a toner image. The primary transfer roller 5, the intermediate transfer belt 10, and the secondary transfer roller 14 are an example of a transfer unit that transfers a toner image to a sheet. The toner image may be directly transferred from the photosensitive drum 6 to the sheet P. In this case, the intermediate transfer belt 10 and the secondary transfer roller 14 are not necessary. The fixing device 12 is an example of a fixing unit that includes a heating unit and heats the toner image by the heating unit to fix the toner image on the sheet. The heater 15 is an example of a heating unit. The detection device 100 generates a pulse signal including a first edge indicating a zero-crossing timing in an AC voltage supplied from an AC power supply, and a second edge whose time interval with respect to the first edge changes according to the voltage level of the AC voltage. It is an example of the production | generation means to do. The microcomputer 105 receives the pulse signal, acquires the zero-cross timing of the AC voltage and the voltage level of the AC voltage from the pulse signal, and controls the power supplied to the heating means based on the zero-cross timing and the voltage level. It is an example of a control means. As an example of a control method for a device such as a heating unit, a wave number control method that performs on / off control of the power for each half cycle of the AC voltage according to the timing of zero crossing can be used. As another method, a phase control method in which the ON time is controlled and supplied within a half cycle of the AC voltage can be used. It is also possible to control by combining the wave number control method and the phase control method.

  A cooling fan or the like may be employed as the load.

  AC ... commercial AC power supply, 100 ... detection device, 101 ... zero cross detection unit, 107 ... level detection unit

Claims (18)

  A detection apparatus that generates a superimposed signal in which information indicating a timing of zero crossing in an AC voltage and information indicating a voltage level of the AC voltage are superimposed.   Pulse generation that generates, as the superimposed signal, a pulse signal including a first edge indicating the timing of zero crossing in the AC voltage and a second edge whose time interval with respect to the first edge changes according to the voltage level of the AC voltage The detection apparatus according to claim 1, further comprising a circuit. The pulse generation circuit includes:
A first edge circuit for generating the first edge at the timing of the zero crossing;
The detection apparatus according to claim 2, further comprising: a second edge circuit that generates the second edge at a timing corresponding to a gradient of the AC voltage.   The detection device according to claim 3, wherein the first edge circuit generates the first edge when a voltage level of the AC voltage is a first level.   The second edge circuit detects a second level which is a voltage level of the AC voltage or a voltage correlated with the AC voltage, and generates the second edge according to the second level. 5. The detection device according to 3 or 4. The first edge circuit is
A first switch element that conducts when the alternating voltage exceeds a threshold and does not conduct unless the alternating voltage exceeds the threshold;
The second edge circuit is
A delay circuit for delaying the phase of the AC voltage;
A control terminal to which the phase-delayed AC voltage is applied, and a second switch element that switches between a conductive state and a non-conductive state according to the voltage applied to the control terminal,
The first switch element and the second switch element are connected in series,
The first edge circuit generates the first edge indicating the timing of the zero cross by the first switch element not conducting,
The second edge circuit changes the voltage level by changing the second switch element from a non-conductive state to a conductive state according to the voltage level of the AC voltage when the first switch element is conductive. The detection device according to claim 3, wherein the second edge is generated. The first edge circuit is
A first switch element that conducts when the alternating voltage exceeds a threshold and does not conduct unless the alternating voltage exceeds the threshold;
The second edge circuit is
A first voltage dividing circuit for dividing the alternating voltage to generate a voltage correlated with the alternating voltage;
A delay circuit for delaying the phase of the AC voltage;
An adding circuit for adding the voltage output from the first voltage dividing circuit and the voltage output from the delay circuit;
A control terminal to which a voltage output from the adding circuit is applied, and a second switch element that switches between a conductive state and a non-conductive state according to the voltage applied to the control terminal,
The first switch element and the second switch element are connected in series,
The first edge circuit generates the first edge indicating the timing of the zero cross by the first switch element not conducting,
In the second edge circuit, when the first switch element is conductive, the second switch element changes from a non-conductive state to a conductive state in accordance with a voltage level of a voltage output from the adding circuit. 6. The detection device according to claim 3, wherein the second edge indicating the voltage level is generated. The second edge circuit is
The detection device according to claim 7, further comprising a rectifying and smoothing circuit that rectifies and smoothes the AC voltage to generate a DC voltage, and applies the DC voltage to the control terminal of the second switch element. .   The detection device according to claim 8, wherein the rectifying and smoothing circuit includes a second voltage dividing circuit that divides the DC voltage and applies the divided voltage to the control terminal of the second switch element. The first edge circuit is
A rectifying and smoothing circuit for generating a DC voltage by rectifying and smoothing the AC voltage;
It has a control terminal that is operated by being supplied with the DC voltage and to which a voltage correlated with the AC voltage is applied, and conducts when the voltage correlated with the AC voltage exceeds a threshold, and the voltage correlated with the AC voltage is Having a first switch element that does not conduct unless the threshold is exceeded,
The second edge circuit is
A phase circuit for advancing the phase of the AC voltage;
A control terminal to which an AC voltage whose phase has been advanced by the phase circuit is applied, and a second switch element that switches between a conductive state and a non-conductive state according to the voltage applied to the control terminal. ,
The first switch element and the second switch element are connected in parallel,
The first edge circuit generates the first edge indicating the timing of the zero crossing by transitioning the first switch element from a conductive state to a non-conductive state,
The second edge circuit is configured such that when the first switch element is in a conductive state, the second switch element transitions from a conductive state to a non-conductive state according to the voltage level of the AC voltage. The detection device according to any one of claims 3 to 5, wherein the second edge is generated.   The detection device according to claim 10, wherein the first switch element is formed by series connection of a rectifying element and a semiconductor switch. The first edge circuit is
A rectifying and smoothing circuit for generating a DC voltage by rectifying and smoothing the AC voltage;
It has a control terminal that is operated by being supplied with the DC voltage and to which a voltage correlated with the AC voltage is applied, and conducts when the voltage correlated with the AC voltage exceeds a threshold, and the voltage correlated with the AC voltage is Having a first switch element that does not conduct unless the threshold is exceeded,
The second edge circuit is
A first voltage dividing circuit for dividing the alternating voltage to generate a voltage correlated with the alternating voltage;
A delay circuit for delaying the phase of the AC voltage;
An adding circuit for adding the voltage output from the first voltage dividing circuit and the voltage output from the delay circuit;
A second switching element having a control terminal to which a voltage output from the adding circuit is applied, and switching between a conductive state and a non-conductive state according to the voltage applied to the control terminal;
A control terminal to which a DC voltage generated from the AC voltage and controlled to be applied and not applied by the second switch element is applied and connected in parallel with the first switch element; A third switch element,
The first edge circuit generates the first edge indicating the timing of the zero crossing by transitioning the first switch element from a conductive state to a non-conductive state,
The second edge circuit is configured such that when the first switch element is in a conductive state, the second switch element transitions from a non-conductive state to a conductive state according to a voltage level of the AC voltage. 6. The detection device according to claim 3, wherein the second edge indicating the voltage level is generated by a switching element transitioning from a conductive state to a non-conductive state. 6. The first edge circuit is
A first switch element that conducts when the alternating voltage exceeds a threshold and does not conduct unless the alternating voltage exceeds the threshold;
The second edge circuit is
A first voltage dividing circuit for dividing the alternating voltage to generate a voltage correlated with the alternating voltage;
A delay circuit for delaying the phase of the AC voltage;
An adding circuit for adding the voltage output from the first voltage dividing circuit and the voltage output from the delay circuit;
A second switching element having a control terminal to which a voltage output from the adding circuit is applied, and switching between a conductive state and a non-conductive state according to the voltage applied to the control terminal;
A control terminal to which a DC voltage generated from the AC voltage and controlled to be applied and not applied by the second switch element is applied and connected in parallel with the first switch element; A third switch element,
The first edge circuit generates the first edge indicating the timing of the zero crossing by transitioning the first switch element from a conductive state to a non-conductive state,
The second edge circuit is configured such that when the first switch element is conductive, the second switch element transitions from a non-conductive state to a conductive state in accordance with a voltage level of the AC voltage. 6. The detection device according to claim 3, wherein the second edge indicating the voltage level is generated by transition of an element from a conduction state to a non-conduction state. 6. The pulse generation circuit includes:
A switch element;
Having a hysteresis characteristic, and having a comparator that switches between a conduction state and a non-conduction state of the switch element according to a voltage correlated with the AC voltage,
The comparator causes the switch element to transition from a non-conductive state to a conductive state so that the switch element generates the first edge at the timing of the zero crossing, and at a timing according to a slope of a voltage correlated with the AC voltage. The detection device according to claim 2, wherein the switch element is transitioned from a conductive state to a non-conductive state so that a second edge is generated. An input means to which a pulse signal including a first edge indicating a timing of zero crossing in an AC voltage and a second edge in which a time interval with respect to the first edge changes according to a voltage level of the AC voltage;
Measuring means for measuring a time interval between the first edge and the second edge;
A determining unit that determines a voltage level of the AC voltage based on a time interval measured by the measuring unit;
A controller comprising: control means for controlling a load using a zero-cross timing indicated by the first edge and the voltage level. An image carrier;
Charging means for uniformly charging the image carrier;
Exposure means for exposing the image carrier to form an electrostatic latent image;
Developing means for developing the electrostatic latent image to form a toner image;
Transfer means for transferring the toner image to a sheet;
A fixing unit that includes a heating unit and heats the toner image by the heating unit to fix the toner image on the sheet;
Generation that generates a pulse signal including a first edge indicating a timing of zero crossing in an AC voltage supplied from an AC power supply, and a second edge whose time interval with respect to the first edge changes according to the voltage level of the AC voltage. Means,
The pulse signal is received, the timing of the zero crossing of the AC voltage and the voltage level of the AC voltage are acquired from the pulse signal, and the electric power supplied to the heating means is based on the timing of the zero crossing and the voltage level. And an image forming apparatus comprising: a control unit that controls the image forming apparatus. In the detection device provided in the image forming apparatus,
AC voltage input,
A generating circuit that generates a superimposed signal that superimposes information indicating the timing of zero crossing in the AC voltage input to the input unit and information indicating the voltage level of the AC voltage;
The detection apparatus, wherein the superimposed signal is a signal for controlling a device used for image formation.   The device is a heating unit for fixing the image on a sheet on which an image is formed, and the superimposed signal is a signal for controlling electric power supplied to the heating unit. The detection device according to claim 17.