JP2018136922A - Memory division for computing system having memory pool - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide performance-efficient division of a memory hierarchy in a COTS multi-core processor.SOLUTION: A computing system comprises: at least one processing unit 110; a memory controller 120; and a main memory 130 for communicating, via the memory controller, with the processing unit. A memory hierarchy is divided into a plurality of memory pools. The main memory includes a set of memory modules divided into ranks each having a rank address determined by a set of rank address bits. Each rank has a set of memory devices including one or more banks each having a bank address determined by a set of bank address bits. A plurality of threads are executed on the processing unit, and allocated to the memory pools on the basis of one or more memory division technologies including bank division, rank division or memory controller division.SELECTED DRAWING: Figure 1

Description

  [0001] One of the most important requirements in avionics systems is to ensure time and space partitioning of the execution process. Time division is a technique that ensures that threads in a process get a predetermined portion of processor time. To ensure that a predetermined portion of processor time is sufficient to complete thread execution, a safety margin is typically added above the measured worst case execution time (WCET). Spatial partitioning refers to hardware-enforced restrictions on memory access that prevent processes from losing each other's data. Time division and space division are guaranteed by a real-time operating system (RTOS), which is typically performed on a commercial off-the-shelf (COTS) single core processor.

  [0002] The complexity and computing power of avionic systems is constantly increasing, while COTS single-core processors are obsolete. It is therefore necessary to select a new computer architecture to meet the needs of avionic systems. Available COTS multi-core processors tend to be some of their best candidates because of their high performance capabilities combined with low size, weight and power (SWaP) characteristics. Apart from the advantages, the COTS multi-core processor has the problem of being subject to the time effects of unpredictable contention. Time division can be compromised as a result of unpredictable contention.

  [0003] Unpredictable contention is caused by access to the same shared hardware resource from multiple cores. Examples of shared hardware resources are caches, main memory, and input / output (I / O) interfaces. As a result of unpredictable contention, conservative task timing is associated with processor performance penalty. Therefore, there is a need to have a performance efficient technology that addresses the time effects of the shared hardware resources of the COTS multi-core processor.

  [0004] In a COTS multi-core processor, the cache is a hardware resource, and its availability greatly affects the performance of the application. If the cache is shared between processor cores, tasks mapped to different cores may invalidate each other's cache lines. Cache invalidation across cores can result in processor performance penalties.

  [0005] Various approaches have been developed to reduce cache invalidation across cores, each increasing processor performance. In one approach, cache partitioning is provided through a mechanism called the “memory pool” of Deos RTOS from DDC-I, which provides refined control over which memory pages are included in each memory pool. Is possible.

US Pat. No. 8,069,308 US Publication No. 2015/0205724

Int'l Conf. on Parallel Architecture and Compilation Techniques (PACT), Proceedings of 2012, Liu et al., pp. 367-376, Multi-levels in the A Software memory partitioning approach)

  [0006] Even though the memory pool concept has been successfully applied to partition the cache, there is still a large unpredictable contention of COTS multi-core processors caused by significant interference in main memory, and main memory is dynamically random It can be an access memory (DRAM). Main memory is accessed by the processor with the help of one or more memory controllers.

  [0007] In another approach, DRAM banking and cache coloring are performed using Linux kernel extensions to control the memory management unit (MMU). This approach suggests that cache and main memory partitioning can provide significant performance improvements.

  [0008] Accordingly, there is a need to address the problem of providing a performance efficient partitioning of memory hierarchies in COTS multi-core processors.

  [0009] The computing system includes at least one processing unit, at least one memory controller with or without cache in operative communication with the at least one processing unit, and at least one via the at least one memory controller. Main memory in operation communication with the processing unit. The memory hierarchy of the computing system includes at least one cache, at least one memory controller, and main memory, and the memory hierarchy is divided into a plurality of memory pools. The main memory includes a set of memory modules that are divided into ranks each having a rank address defined by a set of rank address bits, each rank having a set of memory devices, each memory device having a set of memory devices. It includes one or more banks each having a bank address defined by a bank address bit. The plurality of threads are executed on at least one processing unit and use bank address bits to define one or more sizes and patterns of the memory pool, bank division, one or more using rank address bits Assigned to a memory pool based on one or more memory partitioning techniques, including rank partitioning to access the ranks of the memory, or memory controller partitioning using memory controller interleaving.

  [0010] The features of the present invention will become apparent to those skilled in the art from the following description with reference to the drawings. With the understanding that the drawings represent only exemplary embodiments and therefore should not be considered as limiting the scope, the present invention is directed to additional specificities and details by using the accompanying drawings. Have been described.

[0011] FIG. 2 is a block diagram of a multi-core processor architecture, according to one embodiment that may be implemented with memory partitioning. [0012] FIG. 2 is a block diagram of a memory hierarchy implemented in the multi-core processor architecture of FIG. [0013] FIG. 2 is a block diagram of an exemplary arrangement of a plurality of dynamic random access memory (DRAM) devices in a dual in-line memory module, according to one embodiment that may be implemented in the multi-core processor architecture of FIG. [0014] FIG. 2B is a block diagram of an architecture of a DRAM device that can be implemented in the dual in-line memory module of FIG. 2B. [0015] FIG. 2 is a block diagram of the logic structure of a DRAM memory controller that may be implemented in the multi-core processor architecture of FIG. [0016] FIG. 6 is a flowchart of a method for memory partitioning of a computing system, according to one embodiment. [0017] FIG. 4 is a graphical representation of thread mapping and execution timelines for worker and trasher process iterations in a COTS multi-core processor. [0018] FIG. 6 is a graph showing execution times of worker processes for both undivided DRAM and DRAM bank partitioning.

  [0019] In the following detailed description, the embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that other embodiments may be utilized without departing from the scope of the present invention. The following detailed description is, therefore, not to be construed in a limiting sense.

  [0020] A memory partition for a computing system implemented with a memory pool is disclosed herein. In particular, the approach herein provides a performance efficient partitioning of the memory hierarchy of a commercial off-the-shelf (COTS) multi-core processor system. In the approach herein, the memory pool concept is utilized particularly for applications in dynamic random access memory (DRAM) devices.

  [0021] The memory hierarchy to which the approach herein can be applied includes one or more caches, one or more memory controllers, and one or more main memories. As used herein, “memory partitioning” refers to partitioning of one or more caches, one or more memory controllers, or one or more main memories.

  [0022] The approach herein can be used to enhance cache partitioning by memory partitioning, including bank partitioning, rank partitioning, and managing multiple DRAM controller interleaves. The memory pool contains the address bits that select a memory bank, the active memory rank, the number of rank bits and the type of interleaving, the number of active memory controllers, the interleaving granularity and type, and optionally the cache index address bits. Implemented for memory partitioning by taking into account various factors including:

  [0023] One or more memory partitioning techniques, including bank partitioning, rank partitioning and memory controller partitioning, can be used by conventional cache partitioning techniques to significantly reduce execution time cycles per processing core, thereby Processing performance is greatly increased.

  [0024] Since the address bits for selecting the DRAM bank are sufficiently high in the address space, no additional modification is required in existing memory pool implementations. As a result, the approach herein can apply memory hierarchy partitioning simply by using the appropriate configuration (offset and size) of the memory pool.

  [0025] The memory partitioning techniques herein are particularly advantageous and beneficial in avionics applications, such as avionics platforms mounted on aircraft that use an avionic computer system to perform multiple simultaneous processes. In addition, the memory partitioning techniques herein can be applied to both single-core processors and multi-core processors.

[0026] Further details of the approach herein are described below with reference to the drawings.
[0027] FIG. 1 illustrates a multi-core processor architecture 100 that can implement memory partitioning, according to one embodiment. The multi-core processor architecture 100 generally includes a memory hierarchy including a COTS multi-core processor unit 110 and one or more caches 114, 116, 118, one or more memory controllers 120 and a main storage device 130 such as DRAM.

  [0028] The COTS multi-core processor unit 110 includes one or more processor clusters 112, and each processor cluster 112 includes one or more central processing unit (CPU) cores (CPU0, CPU1, ... CPUk). Each core has a dedicated level 1 (L1) cache such as cache 114 and a shared level 2 (L2) cache such as cache 116. The processor cluster 112 is operatively connected to the memory hierarchy via interconnect 117. Interconnect 117 may also provide input / output connections between other input / output interfaces 119 and processor cluster 112.

  [0029] In some implementations, there is at least one level 3 (L3) cache, such as cache 118, which is located between the interconnect 117 and the memory hierarchy. The L3 cache 118, well known as a platform cache, buffers memory accesses by the core. The L3 cache 118 is operatively connected to one or more memory controllers 120, and the memory controller 120 issues an instruction to access the main memory 130.

  [0030] The main memory 130 is operatively connected to one or more processor clusters 112 via one or more memory controllers 120. The main storage device 130 includes at least one memory module 132 such as a dual in-line memory module (DIMM). The main storage device 130 is a physical memory in which data is stored and accessed during execution.

  [0031] In a DRAM memory architecture, each memory cell (single bit) is implemented by a small capacitor. Over time, the capacitor charge will weaken, so the stored data will eventually be lost unless explicitly refreshed. To prevent data loss, additional hardware periodically reads and writes back each memory cell (ie, performs a refresh) and returns the capacitor charge to its original level. DRAM refresh is automatic and is not visible to the user.

  [0032] The DRAM memory architecture provides three levels of parallelism including a memory controller, rank, and bank. Furthermore, the number of ranks determines the number of banks. These levels of DRAM memory architecture are described below.

  [0033] FIG. 2A is a block diagram of a memory hierarchy implemented in the multi-core processor architecture 100 of FIG. The memory hierarchy includes one or more caches 114, 116, 118, one or more memory controllers 120, and a main memory 130 (DRAM), which includes one or more memories, such as one or more DIMMs. A module 132 may be included. The DIMM enables rank interleaving, which will be described later.

  [0034] FIG. 2B illustrates an exemplary arrangement of DIMM 240, according to one embodiment. The DIMM 240 is typically configured with two ranks (for example, rank 0 and rank 1), which are connected to the circuit board 242. The rank is explicitly selected by a chip select signal. Each rank has a rank address defined by a set of rank address bits. A rank consists of a set of DRAM devices 200. All DRAM devices in the rank share an address, data, and command bus.

  [0035] FIG. 2C represents the architecture of a single DRAM device 200 that may be implemented in DIMM 240, according to one embodiment. DRAM device 200 includes a set of memory banks 210 (eg, bank 1 through bank 8), each bank including a row and column DRAM array 212 with associated logic. Each bank 210 has a bank address defined by a set of bank address bits. Each row of bank 210 contains a single memory page, which is the smallest addressable data unit in DRAM device 200, typically equal to 4 kB. Each page can be either open or closed. The row buffer 214 holds the most recently opened page. Each bank 210 also includes a row decoder 216 and a column decoder 218.

  [0036] The DRAM device 200 has three basic interfaces: a command (cmd) interface 220, an address (addr) interface 222, and a data interface 224. Command interface 220 is in operational communication with instruction decoder 226 to indicate the type of memory operation, read, write, or refresh. Address interface 222 is in operative communication with row decoder 216 and column decoder 218. The data interface is in operational communication with the column decoder 218. The refresh counter 228 is operatively connected between the instruction decoder 226 and the row decoder 216.

  [0037] FIG. 3 is a block diagram of the logic structure of the DRAM memory controller 300, which can be implemented in a processor unit. The DRAM memory controller 300 receives a memory request from the CPU core, such as via an L3 cache (block 310). Memory requests are stored in request buffer 320, which includes its own priority queue 322 for each of the memory banks (eg, bank 0, bank 1... Bank 8). Once there are multiple memory requests in the priority queue 322, the memory scheduler 330 is invoked to select one of the memory requests using each bank scheduler 332 that communicates with each priority queue 322. The selected memory request is then sent to the channel scheduler 340. The channel scheduler 340 communicates with the DRAM address and command bus.

  [0038] The DRAM memory controller allows the user to specify DRAM parameters such as refresh rate. While the refresh proceeds, the DRAM device is temporarily unavailable for read / write operations. If many pages of the DRAM device are accessed simultaneously, page eviction may occur in the row buffer, resulting in increased memory access time. The mitigation of row buffer eviction is to assign a single bank to each processing core.

  [0039] If multiple CPU cores are sending memory requests simultaneously, channel scheduler reordering may also occur. The use of multiple memory controllers can mitigate interference delays caused by channel scheduler reordering.

  [0040] The approach herein includes cache index address bits, address bits for selecting a DRAM bank, active memory rank, number of rank bits and type of interleaving, and number of active memory controllers, interleaving Implement a memory pool concept for memory partitioning by taking into account granularity and type. Depending on the application needs, the approach herein can achieve various levels of memory access isolation. For example, a single memory pool can be assigned to one memory controller, or a single memory pool can be separated into a specific bank of a specific rank. In general, fewer memory pools are available as a result of the tighter separation of memory access.

  [0041] FIG. 4 is a flowchart of a method 400 for implementing memory partitioning according to the approach herein. The method 400 includes dividing 410 the main memory of the computing system into a plurality of memory pools. The main memory can include a set of memory devices, such as DRAM devices, that are arranged in one or more ranks each having a rank address defined by a set of rank address bits. Each memory device includes one or more banks each having a bank address defined by a set of bank address bits. Multiple threads executing on one or more CPU cores are assigned to a memory pool based on one or more memory partitioning techniques (block 420), which is divided into banks (block 422), rank Includes partitioning (424) or memory controller partitioning (426). In addition, one or more of these memory partitioning techniques can optionally be used in conjunction with conventional cache partitioning techniques that use cache index address bits to determine the size and number of cache partitions (block 430). ).

  [0042] In some implementations, at least some of the threads can be assigned to the same memory pool, or at least some of the threads can each be assigned to different memory pools. In addition, at least some of the threads can be mapped to the same CPU core, or at least some of the threads can each be mapped to different CPU cores. Furthermore, at least some of the memory pools can be mapped to memory controllers, one or more ranks, or one or more banks, respectively, in a one-to-one (1: 1) correspondence. Alternatively, at least some of the memory pools can be mapped to a plurality of memory controllers, one or more ranks, and one or more banks, respectively, in a one-to-many (1: N) correspondence.

  [0043] Bank partitioning technology uses bank address bits to define the size and pattern of the memory pool of main memory. The memory pool is mapped to main memory with respect to bank address bits and rank address bits. In this technique, DRAM bank partitioning can be used to avoid the delay caused by bank sharing between cores resulting in row buffer eviction and provide an expected performance increase of up to about 30%.

[0044] Rank partitioning techniques use rank address bits to access ranks, so the higher the number of ranks, the greater the number of available banks.
[0045] A typical memory address layout for a DRAM device is shown in Table 1.

As the address layout in Table 1 suggests, there are dedicated address bits for the memory bank.
[0046] If the processor documentation is limited and information about the address layout is lost, a discovery algorithm can be applied to determine the address layout, see, eg, Int'l Conf. on Parallel Architecture and Compilation Techniques (PACT), Proceedings of 2012, Liu et al., pp. 367-376, Multi-levels in the A There is an algorithm proposed by a software memory partitioning approach), the disclosure of which is incorporated as part of this specification.

  [0047] The memory controller partitioning technique can be implemented on a 32-bit system, uses memory controller interleaving, and it takes into account the granularity and type of interleaving. Memory controller interleaving can be used to distribute memory requests across multiple memory controllers fairly or evenly, or can be used to completely separate memory requests across specific memory controllers. In 64-bit systems, memory controller partitioning can be implemented by disabling memory controller interleaving while allowing all memory controllers to be accessed.

  [0048] If a cache partitioning technique is used, the memory pool is mapped to main memory in terms of cache index address bits. Further details relating to the cache partitioning technique can be found in US Pat. No. 8,069,308 entitled CACHE POOLING FOR COMPUTING SYSTEMS, and SYSTEM AND METHOD OF CACHETING PROCESSORS FORS US Patent Publication No. 2015/0205724, entitled LIMITED CACHED MEMORY POOLS (cache partitioning system and method for processors with limited memory pool cache), the contents of both of which are disclosed herein. Incorporated as part of the book.

  [0049] Depending on the memory address layout, a 1: 1 (one-to-one) or 1: N (one-to-many) mapping of memory pools can be made between caches, memory controllers, ranks, and banks. .

  [0050] Experimental studies have been conducted on DRAM bank partitioning to show its advantages. These studies were performed on COTS multi-core processors using the Deos Real-Time Operating System (RTOS) from DDC-I. The COTS multi-core processor has 12 physical CPUs, each physical CPU has 2 hardware threads, resulting in a total of 24 virtual CPUs. Each virtual CPU has its own small 32 KB instruction and data L1 cache. Virtual CPUs are grouped into three clusters, each cluster having eight virtual CPUs. Each cluster has its own 2MB L2 cache. All clusters are connected to on-chip interconnects. The DRAM memory is mapped to three memory controllers, and each memory controller has a dedicated L3 cache capacity of 512 KB.

  [0051] The benefits of DRAM bank partitioning have been demonstrated by memory accesses without a set of caches that are induced in the same and different DRAM banks simultaneously. Since memory access without a cache is used, the assumption is made that the presence or absence of a cache does not affect the measured execution time. Nevertheless, the L3 cache (platform cache) is invalidated in subsequent experiments. The experiments performed are for two processes, a worker process and a trasher process, both processes being called repeatedly.

  [0052] The worker process has two threads, including a writer thread and a reader thread. The writer thread writes a predetermined number of pages to a memory array larger than its own memory pool. When the writer thread finishes, the reader thread reads the page and calculates the checksum of the memory array. Both threads of the worker process share the same memory pool. At the end of a single thread iteration, the cache is invalidated to ensure that all memory requests from worker threads are not registered in the cache.

  [0053] The trasher process has a plurality of trasher threads. The trasher thread continuously writes a large number of pages to the memory array so that the accessed memory is the same size or larger than the allocated memory pool. Therefore, the trasher process can continuously execute writing and stress without using a cache in the memory hierarchy. The trasher process runs in parallel with the worker process, enabling loose use. The trasher thread is mapped to the CPU differently from the CPU on which the worker process thread is running.

  [0054] FIG. 5 is a graphical representation of thread mapping and execution timelines for worker and trasher process iterations. Worker process threads, including writers and leaders, were mapped to CPU0, while trasher threads ran on the remaining seven CPUs (CPU1 to CPUN) of the same cluster. Execution time measurements are shown relative to writer and / or reader timing.

  [0055] FIG. 6 is a graph showing execution times of worker processes for both undivided DRAM and DRAM bank partitioning. The listed performance results are for the highest measured, lowest measured, and average execution time over 100 thread iterations. To outline the advantages of DRAM bank partitioning with a memory pool, non-partitioned DRAM is compared to DRAM bank partitioning. Non-divided DRAM is implemented by placing trasher threads in the same memory pool as the worker and leader threads. DRAM bank partitioning is implemented by placing trasher threads in separate memory pools. Worker and trasher memory pools are defined by considering the address bits used for DRAM banks. As experimental data indicates, DRAM bank partitioning reduced the execution time cycle by about 20% for each processing core compared to non-partitioned DRAM, thereby adding an additional 20% CPU performance.

  [0056] Additional experimental results show that cache partitioning can obtain up to about 60% performance improvement over non-partitioned caches when the operational dataset of the application can be fully cache resident ( And the cache can be protected from eviction / contamination across the core). Cache size is often too small to support 100% cache resident area for most applications, so the combination of cache partitioning and DRAM bank partitioning reduces the worst case memory transactions for each application and The worst case execution is reduced (due to cache partitioning) as well as the minimum possible DRAM access time (due to DRAM bank partitioning) for those memory operations that occur.

  [0057] The computer or processor used in the systems and methods herein can be implemented using software, firmware, hardware, or any suitable combination thereof, as known to those skilled in the art. . For example, without limitation, hardware components include one or more microprocessors, storage elements, digital signal processing (DSP) elements, interface cards, and other standard components known in the art. Can do. These can be supplemented by or incorporated in specially designed application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). The computer or processor may also include functions having software programs, firmware, or other computer readable instructions for performing various process tasks, computation and control functions used in the methods and systems herein.

  [0058] The method may be performed by computer-executable instructions, such as program modules or components, which are executed by at least one processor. Generally, program modules include routines, programs, objects, components, data structures, algorithms, etc. that perform particular tasks or implement particular data types.

  [0059] Instructions for performing various process tasks, calculations and other data generation used in the operation of the methods described herein may be software, firmware, or other computer readable or processor It can be implemented as a readable instruction. These instructions are typically stored in any suitable computer program product including computer readable instructions or computer readable media used for storage of data structures. Such computer-readable media can be any available media that can be accessed by a general purpose or special purpose computer or processor, or any programmable logic device.

[0060] Suitable computer readable media may include storage or memory media such as magnetic or optical media. For example, the storage or memory medium can be a conventional hard disk, compact disk read only memory (CD-ROM), DVD, random access memory (RAM) (but not limited to synchronous dynamic random access memory (SDRAM), double Volatile or non-volatile media such as data rate (DDR) RAM, RAMBUS dynamic RAM (RDRAM), static RAM (SRAM), etc.), read only memory (ROM), electrically erasable programmable ROM ( EEPROM), flash memory, Blu-ray disc, and the like. Combinations of the above are also included within the scope of computer-readable media.
Exemplary embodiment
[0061] Example 1 includes at least one processing unit, at least one memory controller with or without cache in operational communication with the at least one processing unit, and via the at least one memory controller. A computing system including a main memory in operational communication with at least one processing unit is included. The memory hierarchy of the computing system includes at least one cache, the at least one memory controller, and the main memory, and the memory hierarchy is divided into a plurality of memory pools. Each of the main memories includes a set of memory modules that are divided into ranks each having a rank address defined by a set of rank address bits, each rank having a set of memory devices, each of the memory devices being Each includes one or more banks having a bank address defined by a set of bank address bits. A plurality of threads execute on the at least one processing unit and use the bank address bits to define one or more sizes and patterns of the memory pool using the bank address bits, using the rank address bits The memory pool is assigned based on one or more memory partitioning techniques including rank partitioning that accesses the one or more ranks, or memory controller partitioning that uses memory controller interleaving.

[0062] Example 2 includes the computing system of Example 1, wherein the main memory includes dynamic random access memory (DRAM).
[0063] Example 3 includes the computing system of any of Examples 1-2, wherein the thread also uses a cache index address bit to determine the size and number of cache partitions, in a cache partitioning technique. Based on the memory pool.

[0064] Example 4 includes the computing system of any of Examples 1-3, wherein at least some of the threads are assigned to the same memory pool.
[0065] Example 5 includes the computing system of any of Examples 1-3, wherein at least some of the threads are each assigned to a different memory pool.

  [0066] Example 6 includes the computing system of any of Examples 1-5, wherein the at least one processing unit includes one or more central processing unit (CPU) cores.

[0067] Example 7 includes the computing system of Example 6, wherein at least some of the threads are mapped to the same CPU core.
[0068] Example 8 includes the computing system of Example 6, wherein at least some of the threads are each mapped to a different CPU core.

  [0069] Example 9 includes the computing system of any of Examples 1-8, wherein at least some of the memory pools include the at least one memory controller, the one or more ranks, or the Each is mapped to one or a plurality of banks in a one-to-one (1: 1) correspondence.

  [0070] Example 10 includes the computing system of any of Examples 1-8, wherein at least some of the memory pools include the at least one memory controller, the one or more ranks, and the The data are mapped to one or a plurality of banks in a one-to-many (1: N) correspondence.

  [0071] Example 11 is a multi-core processor unit, one or more processor clusters, each including a plurality of central processing unit (CPU) cores, each of the cores being a dedicated level fast cache One or more processor clusters having a first cache and a shared level second cache, an interconnect operatively coupled to the one or more processor clusters, and via the interconnect An avionics computer system is included that includes a multi-core processor unit that includes one or more memory controllers in operative communication with the one or more processor clusters. Main memory is in operative communication with the one or more processor clusters via the one or more memory controllers. The memory hierarchy of the avionic computer system includes at least one of the first or second cache, the one or more memory controllers, and the main memory, and the memory hierarchy is divided into a plurality of memory pools. The main memory includes a set of dual in-line memory modules (DIMMs) that are divided into ranks each having a rank address defined by a set of rank address bits, each rank being a set of dynamic random access memory (DRAM) devices. Each of the DRAM devices includes one or more banks each having a bank address defined by a set of bank address bits. A plurality of threads are executed on the CPU core. The thread uses the bank address bits to define one or more sizes and patterns in the memory pool, and the rank address bits use the rank address bits to access the one or more ranks. One or more comprising a memory controller partition that uses the memory controller interleave to distribute the memory requests fairly to a plurality of memory controllers or to completely separate the memory requests to specific memory controllers The memory pool is allocated based on a memory partitioning technique. The avionic computer system is implemented as a part of an avionics platform installed on an aircraft.

  [0072] Example 12 includes the avionics computer system of Example 11, wherein one or more of the threads is also based on a cache partitioning technique that uses cache index address bits to determine the size and number of cache partitions. And assigned to one or more of the memory pools.

  [0073] Example 13 includes the avionic computer system of any of Examples 11-12, at least some of the threads being assigned to the same memory pool.

  [0074] Example 14 includes the avionic computer system of any of Examples 11-12, wherein at least some of the threads are each assigned to a different memory pool.

  [0075] Example 15 includes the avionic computer system of any of Examples 11-14, wherein at least some of the threads are mapped to the same CPU core.

  [0076] Example 16 includes the avionic computer system of any of Examples 11-14, wherein at least some of the threads are each mapped to a different CPU core.

  [0077] Example 17 includes the avionics computer system of any of Examples 11-16, wherein at least some of the memory pools include the one or more memory controllers, the one or more ranks, Alternatively, the data is mapped to the one or more banks in a one-to-one (1: 1) correspondence.

  [0078] Example 18 includes the avionics computer system of any of Examples 11-16, wherein at least some of the memory pools are a plurality of the one or more memory controllers, the one or more A plurality of ranks and one or more banks are mapped in a one-to-many (1: N) correspondence.

  [0079] Example 19 includes a method of operating a computing system, the method comprising dividing the memory hierarchy of the computing system into a plurality of memory pools, the memory hierarchy comprising at least one memory hierarchy A cache, at least one memory controller, and a main memory, wherein the main memory includes a set of memory modules, each of which is divided into ranks having a rank address defined by a set of rank address bits, each rank having a A set of memory devices, each of the memory devices including one or more banks each having a bank address defined by a set of bank address bits; and at least one of the computing systems Each of a plurality of threads executed on a processing unit of the bank using the bank address bits to define one or more sizes and patterns of the memory pool using the bank address bits, using the rank address bits Use rank splitting to access the one or more ranks, or use memory controller interleaving to evenly distribute the memory requests to multiple memory controllers, or completely separate the memory requests to specific memory controllers Assigning to one or more of the memory pools based on one or more memory partitioning techniques including memory controller partitioning.

  [0080] Example 20 includes the method of Example 19, wherein one or more of the threads is also based on a cache partitioning technique that uses cache index address bits to determine the size and number of cache partitions, Assigned to one or more of the memory pools.

  [0081] The present invention may be embodied in other specific forms without departing from the essential characteristics thereof. The described embodiments are to be considered in all respects as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within the scope of the claims.

110 COTS multi-core processor 114 cache 116 cache 117 interconnect 118 cache 119 input / output interface 120 memory controller 130 main memory 132 DIMM
200 DRAM device 214 row buffer 216 row decoder 218 column decoder 220 command 222 address 224 data 226 command decoder 228 refresh counter 320 request buffer 330 memory scheduler 340 channel scheduler

Claims (3)

A computing system,
At least one processing unit;
At least one memory controller, with or without cache, in operational communication with the at least one processing unit;
A main memory operatively communicating with the at least one processing unit via the at least one memory controller;
The memory hierarchy of the computing system includes at least one cache, the at least one memory controller, and the main memory, and the memory hierarchy is divided into a plurality of memory pools,
The main memory includes a set of memory modules each divided into ranks having a rank address defined by a set of rank address bits, each rank having a set of memory devices, each of the memory devices Includes one or more banks each having a bank address defined by a set of bank address bits;
A plurality of threads are executed in the at least one processing unit;
A bank partition that uses the bank address bits to define one or more sizes and patterns of the memory pool;
Assigned to the memory pool based on one or more memory partitioning techniques, including rank partitioning using the rank address bits to access the one or more ranks, or memory controller partitioning using memory controller interleaving Be
Computing system. An avionics computer system,
A multi-core processor unit,
One or more processor clusters, each including a plurality of central processing unit (CPU) cores, each of the cores having a dedicated level first cache and a shared level second cache A cluster,
An interconnect operatively coupled to the one or more processor clusters;
A multi-core processor unit comprising: one or more memory controllers in operational communication with the one or more processor clusters via the interconnect;
A main memory operatively communicating with the one or more processor clusters via the one or more memory controllers;
The memory hierarchy of the avionic computer system includes at least one of the first or second cache, the one or more memory controllers, and the main memory, and the memory hierarchy is divided into a plurality of memory pools,
The main memory includes a set of dual inline memory modules (DIMMs) that are divided into ranks each having a rank address defined by a set of rank address bits, each rank being a set of dynamic random access memory (DRAM) devices. Each of the DRAM devices includes one or more banks each having a bank address defined by a set of bank address bits;
A plurality of threads are executed on the CPU core, and the threads are
A bank partition that uses the bank address bits to define one or more sizes and patterns of the memory pool;
Rank splits using the rank address bits to access the one or more ranks, or use memory controller interleaving to distribute the memory requests fairly across the memory controllers, or Assigned to the memory pool based on one or more memory partitioning techniques, including memory controller partitioning that is completely separated into specific memory controllers,
The avionic computer system is implemented as part of an avionics platform installed on an aircraft,
Avionics computer system. A method of operating a computing system, comprising:
Dividing the memory hierarchy of the computing system into a plurality of memory pools, the memory hierarchy including at least one cache, at least one memory controller, and main memory;
The main memory includes a set of memory modules that are divided into ranks each having a rank address defined by a set of rank address bits, each rank having a set of memory devices, each of the memory devices comprising: Including one or more banks each having a bank address defined by a set of bank address bits;
Steps,
Each of a plurality of threads executing on at least one processing unit of the computing system;
A bank partition that uses the bank address bits to define one or more sizes and patterns of the memory pool;
Rank splits using the rank address bits to access the one or more ranks, or use memory controller interleaving to distribute the memory requests fairly across the memory controllers, or Assigning to one or more of said memory pools based on one or more memory partitioning techniques, including memory controller partitioning that completely separates into specific memory controllers.

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