CN103678155B

CN103678155B - Memory address mappings processing method and polycaryon processor

Info

Publication number: CN103678155B
Application number: CN201210349302.0A
Authority: CN
Inventors: 崔泽汉; 陈明宇; 陈明扬; 阮元
Original assignee: Huawei Technologies Co Ltd; Institute of Computing Technology of CAS
Current assignee: Institute of Computing Technology of CAS; Huawei Cloud Computing Technologies Co Ltd
Priority date: 2012-09-19
Filing date: 2012-09-19
Publication date: 2016-12-21
Anticipated expiration: 2032-09-19
Also published as: CN103678155A

Abstract

The embodiment of the present invention provides a kind of memory address mappings processing method and polycaryon processor, method includes: each group the first address and the second address in the physical address of polycaryon processor alternate access memory system, obtaining and often organize the first average access latency corresponding to the first address and the second address, the first address value the most corresponding on two identical address bits from the second address be different and two address bits are address bit in addition to row address bit and column address bit in each address bit of physical address；Polycaryon processor, according to each first average access latency, determines the bank-address position of physical address.Memory address mappings processing method and polycaryon processor that the embodiment of the present invention provides can obtain the physical address address mapping relation to the memory bank bank of memory system easily, and then can use the mapping relations of the bank address of acquisition that bank partition is applied to entity computer memory system, to avoid polycaryon processor to share bank interference.

Description

Memory address mappings processing method and polycaryon processor

Technical field

The present embodiments relate to computer technology, particularly relate to a kind of memory address mappings processing method and multinuclear processes Device.

Background technology

Along with developing rapidly of computer technology, polycaryon processor how is avoided to share cache memory (cache) In the case of the interference that causes be widely studied and applied.

In prior art, cache sector (cache can be realized by page dyeing (page coloring) technology Partition), by different processes, thread or the data of core or the page, it is mapped to different cache set (cache set), With the interference avoiding different process, between thread or core, cache sharing causes.If known cache line (cache line) Length, cache size, cache set associative way and operating system page-size, it is possible to dyeed by page on entity device Technology realizes cache sector.

Inventor finds during realizing the embodiment of the present invention, the interference that polycaryon processor shared drive system is brought Problem still exists, such as polycaryon processor shared drive bandwidth or the interference of shared drive memory bank (bank).Although in the recent period Occur in that passage subregion (channel partition) or the memory bank utilizing page staining technique to realize internal memory in an operating system Subregion (bank partition) is to avoid sharing bandwidth interference or the research of shared bank interference.But page dyeing skill will be utilized Art realizes channel partition or bank partition and is applied to entity computer memory system, needs known entities In calculator memory system, physical address is to the address mapping relation of memory system, arrives passage (channel) including physical address Or the mapping relations of bank.Owing to the mapping relations of the physical address on entity device to channel or bank are by Memory control Device realizes, and Memory Controller Hub manufacturer tends not to disclose the mapping method used in its last word, therefore, how to obtain Take physical address and become technical problem urgently to be resolved hurrily to the address mapping relation of memory system.

Summary of the invention

The embodiment of the present invention provides a kind of memory address mappings processing method and polycaryon processor.

The memory address mappings processing method that the embodiment of the present invention provides includes: polycaryon processor alternate access memory system Physical address in each group the first address and the second address, obtain and often organize corresponding first average in the first address and the second address Access delay, the value the most corresponding on two identical address bits in described first address and described second address is different and described Two address bits are the address bit in each address bit of described physical address in addition to row address bit and column address bit；Polycaryon processor According to each first average access latency, determine the bank-address position of described physical address.

Further, described polycaryon processor, according to each first average access latency, determines the storage of described physical address Body address bit, including: polycaryon processor according to access delay time length, is carried out described each first average access latency point Group；If described each first average access latency is divided into multiple groups, then by one group of corresponding two the longest the access delay time Address bit XOR is processed as the first set, determines that the described bank-address position of described physical address includes in described first set And except described row address bit, described column address bit and described time delay the longest one group in the described each address bit of physical address The corresponding all address bits outside said two address bit；If described each first average access latency is divided into a group, then Determine that the described bank-address position of described physical address includes all said two address bits.

Further, each group the first address and second in the physical address of described polycaryon processor alternate access memory system Before address, also include: each group the 3rd address and the 4th address in polycaryon processor alternate access physical address, obtain and often group The second average access latency that 3rd address is corresponding with the 4th address, described 3rd address and described 4th address are only identical Value corresponding on one row address bit and a non-row address bit is different；Polycaryon processor prolongs according to each second average access Late, the column address bit of described physical address is determined.

Further, described polycaryon processor, according to each second average access latency, determines the row ground of described physical address Position, location, including: described each second average access latency, according to access delay time length, is grouped, really by polycaryon processor The described column address bit of fixed described physical address include the described access delay time the longest one group of corresponding non-row address bit.

Further, each group the 3rd address and the 4th in the physical address of described polycaryon processor alternate access memory system Before address, also include: each group the 5th address and the 6th address in polycaryon processor alternate access physical address, obtain and often group The 3rd average access latency that 5th address is corresponding with the 6th address, described 5th address and the 6th address are only at identical one The value of address bit is different；Polycaryon processor, according to each 3rd average access latency, determines the row address bit of described physical address.

Further, described polycaryon processor, according to each 3rd average access latency, determines the row ground of described physical address Position, location, including: described each 3rd average access latency, according to access delay time length, is grouped, really by polycaryon processor Described row address bit in fixed described physical address includes the longest one group of corresponding address bit of described access delay time.

Further, described polycaryon processor, according to each first average access latency, determines the storage of described physical address After body address bit, also include: the multiple core of polycaryon processor concurrently accesses the first address sequence in the physical address of memory system Row, obtain the memory bandwidth that the first address sequence is corresponding, and the address in described first address sequence includes a bank-address Position, multiple row address bit and multiple column address bit, the described bank-address of address adjacent in described first address sequence Value on position is different；Polycaryon processor, according to each memory bandwidth, determines the channel address position of described physical address.

Further, described polycaryon processor, according to each memory bandwidth, determines the channel address position of described physical address, bag Include: described each memory bandwidth, according to the size of described memory bandwidth, is grouped by polycaryon processor；If described each memory bandwidth It is divided into multiple groups, it is determined that the described channel address position of described physical address includes one group of correspondence that described memory bandwidth is maximum Described bank-address position.

Further, described polycaryon processor according to each memory bandwidth, determine described physical address channel address position it After, also include: the single core of polycaryon processor accesses the physics of described memory system in the way of skipping cache memory The second address sequence in address, remaining multiple core of described polycaryon processor are by concurrent in the way of cache memory Access the 3rd address sequence in described physical address, obtain the 4th average access latency that described second address sequence is corresponding； Address in described second address sequence is different with the value on same channel address position of the address in the 3rd address sequence, and The value of other address bit of the address in described second address sequence is constant, other of the address in described 3rd address sequence The value of address bit is continually changing；Polycaryon processor, according to each 4th average access latency, determines the internal memory of described physical address Controller address position.

Further, described polycaryon processor, according to each 4th average access latency, determines the internal memory of described physical address Controller address position, including: described each 4th average access latency, according to access delay time length, is carried out by polycaryon processor Packet；If described each 4th average access latency is divided into multiple groups, it is determined that the described Memory Controller Hub of described physical address Address bit includes the longest one group of corresponding described channel address position of described access delay time.

The polycaryon processor that the embodiment of the present invention provides includes: memory access module, for the physics of alternate access memory system Each group the first address and the second address in address；Measurement module is corresponding with often organizing the first address and the second address for obtaining First average access latency, the value the most corresponding on two identical address bits in described first address and described second address is not Same and said two address bit is the address bit in each address bit of described physical address in addition to row address bit and column address bit；Point Analyse module, be used for according to each first average access latency, determine the bank-address position of described physical address.

Further, described analysis module is additionally operable to: according to access delay time length, to described each first average access Postpone to be grouped；If described each first average access latency is divided into multiple groups, then by the longest for the access delay time one group Two corresponding address bit XORs are processed as the first set, determine that the described bank-address position of described physical address includes described Described row address bit, described column address bit and described time delay is removed in first set and in each address bit of described physical address The longest all address bits outside one group of corresponding said two address bit；If described each first average access latency is divided into One group, it is determined that the described bank-address position of described physical address includes all said two address bits.

Further, described memory access module be additionally operable in the physical address of alternate access memory system respectively to organize the 3rd address and 4th address；The most described measurement module is additionally operable to obtain second corresponding with often group the 3rd address and the 4th address and averagely visits Asking delay, described 3rd address is only corresponding on an identical row address bit and a non-row address bit with described 4th address Value different；The most described analysis module is additionally operable to, according to each second average access latency, determine described physical address Column address bit.

Further, described analysis module is additionally operable to according to access delay time length, by described each second average access Postpone be grouped, determine the described column address bit of described physical address include the described access delay time the longest one group pair The non-row address bit answered.

Further, described memory access module be additionally operable in the physical address of alternate access memory system respectively to organize the 5th address and 6th address；The most described measurement module is additionally operable to obtain threeth corresponding with often group the 5th address and the 6th address and averagely visits Ask that delay, described 5th address and the 6th address are only different in the value of an identical address bit；The most described analysis mould Block is additionally operable to, according to each 3rd average access latency, determine the row address bit of described physical address.

Further, described analysis module is additionally operable to according to access delay time length, by described each 3rd average access Postpone to be grouped, determine that the described row address bit in described physical address includes the longest one group pair of described access delay time The address bit answered.

Further, during described memory access module is additionally operable to concurrently to access the physical address of memory system with many kernel form One address sequence；The most described measurement module is additionally operable to obtain the memory bandwidth that the first address sequence is corresponding, described first ground Address in the sequence of location includes a bank-address position, multiple row address bit and multiple column address bit, described first address Value on the described bank-address position of address adjacent in sequence is different；The most described analysis module is additionally operable to according to each Memory bandwidth, determines the channel address position of described physical address.

Further, described analysis module is additionally operable to the size according to described memory bandwidth, enters described each memory bandwidth Row packet；If described each memory bandwidth is divided into multiple groups, it is determined that the described channel address position of described physical address includes institute State one group of corresponding described bank-address position that memory bandwidth is maximum.

Further, described memory access module is additionally operable in the way of monokaryon form skips cache memory to access described The second address sequence in the physical address of memory system, concurrently accesses in the way of cache memory by many kernel form The 3rd address sequence in described physical address；Accordingly: it is corresponding that described measurement module is used for obtaining described second address sequence The 4th average access latency, the address in described second address sequence and the address in the 3rd address sequence are on same passage ground Value on position, location is different, and the value of other address bit of the address in described second address sequence is constant, described 3rd ground The value of other address bit of the address in the sequence of location is continually changing；Accordingly: described analysis module is for according to each Siping City All access delay, determines the Memory Controller Hub address bit of described physical address.

Further, described analysis module is additionally operable to according to access delay time length, to described each 4th average access Postpone to be grouped；If described each 4th average access latency is divided into multiple groups, it is determined that described physical address described in Memory controller address bit includes the longest one group of corresponding described channel address position of described access delay time.

Memory address mappings processing method and polycaryon processor that the embodiment of the present invention provides can obtain physics easily Address is to the address mapping relation of memory system, including the address mapping relation of memory bank bank, and then can use acquisition Bank partition is applied to entity computer memory system by the mapping relations of bank address, to avoid polycaryon processor altogether Enjoy bank interference.

Accompanying drawing explanation

In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is this Some bright embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to Other accompanying drawing is obtained according to these accompanying drawings.

Fig. 1 is the flow chart of memory address mappings processing method embodiment one of the present invention；

Fig. 2 is the flow chart of memory address mappings processing method embodiment two of the present invention；

Fig. 3 is the flow chart of memory address mappings processing method embodiment three of the present invention；

Fig. 4 is the flow chart of memory address mappings processing method embodiment four of the present invention；

Fig. 5 is the flow chart of memory address mappings processing method embodiment five of the present invention；

Fig. 6 is the flow chart of memory address mappings processing method embodiment six of the present invention；

Fig. 7 is the flow chart of memory address mappings processing method embodiment seven of the present invention；

Fig. 8 is the flow chart of memory address mappings processing method embodiment eight of the present invention；

Fig. 9 is the flow chart of memory address mappings processing method embodiment nine of the present invention；

Figure 10 is the flow chart of memory address mappings processing method embodiment ten of the present invention；

Figure 11 is this structural representation for polycaryon processor embodiment one of the present invention.

Detailed description of the invention

For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the embodiment of the present invention In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is The a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art The every other embodiment obtained under not making creative work premise, broadly falls into the scope of protection of the invention.

In prior art, the physical address of memory system includes multiple address bit, some the address bit conduct in physical address The index address position of Memory Controller Hub, some address bit is as the index address position of channel, and some address bit is as bank's Index address position, some address bit is as the index address position of row, and some address bit is as the index address position of row.Such as, interior The index address position of memory controller is that this address of 0 expression is positioned at Memory Controller Hub 0, is that this address of 1 expression is positioned at Memory Controller Hub 1；The index address position of channel is that this address of 0 expression is positioned at channel0, is that 1 expression is positioned at channel1；The index of bank Address bit is that to be positioned at the index address position of bank0, bank be that this address of 001 expression is positioned at bank1, with this to this address of 000 expression Analogizing, the index address position of bank is 111 and represents that this address is positioned at bank7.

The memory address mappings processing method and processing device that the embodiment of the present invention provides is many for determining that physical address includes Individual address bit is right with bank address bit, row address bit, column address bit, channel address bit and storage control address bit Should be related to.

Fig. 1 is the flow chart of memory address mappings processing method embodiment one of the present invention, as it is shown in figure 1, the present embodiment carries The memory address mappings processing method of confession may include that

Step S 102, polycaryon processor alternate access memory system physical address in each group the first address and the second ground Location, obtains and often organizes the first average access latency corresponding to the first address and the second address, and the first address exists with the second address Value corresponding on two identical address bits is different and two address bits be in each address bit of physical address except row address bit and Address bit outside column address bit.

Specifically, if it is known that the row address bit in each address bit of the physical address of memory system and column address bit, that Taking two address bits in addition to row address bit and column address bit in each address bit of physical address, the two address bit is for example, Xth position and y bit address position.Constructing one group of first address and the second address, the xth position of the first address and the value of y position are divided The most different from the value of two address xth position and y position, the xth of the such as first address, y position take 0,0 respectively, the second address Xth, y position take 1,1 respectively.This group first address and the second address correspondence of other address bits in addition to xth position and y position takes It is worth the most identical.

Polycaryon processor in the way of skipping cache memory, alternate access this group the first address and second address, Obtain first average access latency corresponding with this group first address and the second address.In the embodiment of the present invention, alternate access is secondary Number can be 1,000,000 times or other values with value, and to be obtained in that accurate first average access latency is as the criterion, the present invention is real Execute example without limitation.

Owning in addition to row address bit and column address bit in above-mentioned xth position and the y position traversal each address bit of physical address Address bit, when xth position is different with present position, y position, constitute difference group the first address and the second address, polycaryon processor with Skipping the mode of cache memory, alternate access respectively organizes the first address and the second address, obtain with each group of the first address and Each first average access latency that second address is corresponding.

Step S104, polycaryon processor, according to each first average access latency, determine the memory bank bank ground of physical address Position, location.

After polycaryon processor obtains each first average access latency corresponding with each group of the first address and the second address, permissible The bank address bit of physical address is determined according to each first average access latency.

The memory address mappings processing method that the present embodiment provides can obtain physical address easily to memory system The mapping relations of bank address, and then the mapping relations of the bank address of acquisition can be used to be applied to by bank partition Entity computer memory system, to avoid polycaryon processor to share bank interference.

Fig. 2 is the flow chart of memory address mappings processing method embodiment two of the present invention, as in figure 2 it is shown, the present embodiment carries The method of confession is on the basis of above-described embodiment, and polycaryon processor, according to each first average access latency, determines physical address Memory bank bank address bit, may include that

Each first average access latency, according to access delay time length, is grouped by polycaryon processor；If each first Average access latency is divided into multiple groups, then be processed as by one group of corresponding two address bit XOR the longest the access delay time First set, determines that the memory bank bank address bit of physical address includes in the first set and removes in each address bit of physical address All address bits outside one group of two corresponding address bit that row address bit, column address bit are the longest with time delay；Ruo Ge One average access latency is divided into a group, it is determined that the memory bank bank address bit of physical address includes all two addresses Position.

Specifically, the memory address mappings processing method that the present embodiment provides may include that

Step S202, by the address bit combination of two structure of all physical address in addition to known row address bit and column address Become set B.Such as by the address bit of physical address, the xth position in the address bit in addition to row address bit and column address bit and Y position is as a combination, and this combination of all of xth position and y bit address position collectively forms set B.

Step S204, take set B in an xth, the address bit of y position, construct one group of first address and the second address, the first ground The xth position of location is different from the value of two address xth position and y position respectively with the value of y position, the of the such as first address X, y position takes 0,0 respectively, and two address xth, y position take 1,1 respectively.This group first address and the second address are except xth position and y Outside Wei, the value of the correspondence of other address bits is the most identical.

Step S206, polycaryon processor be this group first address of alternate access and in the way of skipping cache memory Double-address, obtains first average access latency corresponding with this group first address and the second address.

Step S208, judge that whether gather B is empty, i.e. judge xth, the address bit of y position has traveled through the institute in set B the most There is combination of address bits.If set B is not sky, repeats step S204, if set B is sky, perform step S210.

Step S210, polycaryon processor obtain each first average access corresponding with each group of the first address and the second address and prolong Late, according to access delay time length, each first average access latency is grouped.

Step S212, judge whether each first average access latency is divided into a group, if each first average access latency It is divided into multiple groups and then performs step S214, if each first average access latency is divided into a group, perform step S216.

Step S214, by two ground in the combination of address bits in one group of corresponding set B the longest the access delay time Position, location, such as xth position and y bit address position XOR is processed as the first set, determines that the bank address bit of physical address includes Address bit in one set.

Step S216, determine that the memory bank bank address bit of physical address includes the institute of set B in addition to the first set There is address bit.

Fig. 3 is the flow chart of memory address mappings processing method embodiment three of the present invention, as it is shown on figure 3, the present embodiment carries The memory address mappings processing method of confession is on the basis of above-described embodiment, each in polycaryon processor alternate access physical address Before organizing the first address and the second address, also include:

Step S302, polycaryon processor alternate access memory system physical address in each group the 3rd address and the 4th ground Location, obtains second average access latency corresponding with often group the 3rd address and the 4th address, and the 3rd address only exists with the 4th address Value corresponding on an identical row address bit and a non-row address bit is different.

Specifically, if in the memory address mappings processing method embodiment of Fig. 1 or Fig. 2 offer, physical address various places Row address bit in position, location is known, and column address bit is unknown, then can take in each address bit of physical address except row A non-row address bit outside address bit, such as this non-row address bit is c bit address position, and takes a row address bit such as It it is r bit address position.Construct one group of the 3rd address and the 4th address, the c position of the 3rd address and the value of r position respectively with Four address c position is different with the value of r position, and c, r position of the such as the 3rd address takes 0,0 respectively, four address c, r Position takes 1,1 respectively.This group the 3rd address and the 4th address corresponding value of other address bits in addition to c position and r position are homogeneous With.

Polycaryon processor in the way of skipping cache memory, alternate access this group the 3rd address and the 4th address, Obtain second average access latency corresponding with this group the 3rd address and the 4th address.In the embodiment of the present invention, alternate access is secondary Number can be 1,000,000 times or other values with value, and to be obtained in that the second average access latency is as the criterion accurately, the present invention implements Example is without limitation.

Above-mentioned c position travels through all address bits in each address bit of physical address in addition to row address bit, position residing for c position When putting difference, constitute difference group the 3rd address and the 4th address, polycaryon processor in the way of skipping cache memory, Alternate access respectively organizes the 3rd address and the 4th address, obtains each second corresponding with each group of the 3rd address and the 4th address and averagely visits Ask delay.

Step S304, polycaryon processor, according to each second average access latency, determine the column address bit of physical address.

After polycaryon processor obtains each second average access latency corresponding with each group of the 3rd address and the 4th address, permissible The column address bit of physical address is determined according to each second average access latency.

Step S 102 step corresponding to Fig. 1 with step S 104 is similar, and here is omitted.

First the memory address mappings processing method that the present embodiment provides, by obtaining the physical address row to memory system The mapping relations of address, then obtain the physical address mapping relations to the bank address of memory system, and then acquisition can be used The mapping relations of bank address bank partition is applied to entity computer memory system, to avoid polycaryon processor Share bank interference.

Fig. 4 is the flow chart of memory address mappings processing method embodiment four of the present invention, and as shown in Figure 4, the present embodiment carries The method of confession is on the basis of embodiment illustrated in fig. 3, and polycaryon processor, according to each second average access latency, determines physical address Column address bit, including:

Each second average access latency, according to access delay time length, is grouped, determines physics by polycaryon processor The column address bit of address include the access delay time the longest one group of corresponding non-row address bit.

Specifically, the memory address mappings processing method that the present embodiment provides is implementing what Fig. 1 or Fig. 2 embodiment provided Can also include before method:

Step S402, the address bit of all physical address in addition to known row address bit is constituted set C.

Step S404, the r address bit taken in row address bit, take a c address bit in set C and construct one group of the 3rd address With the 4th address: the 3rd address with the 4th address only on c address bit and r address bit value different, the such as the 3rd ground The c address bit of location and r address bit values are all 0, and two address c address bit and r address bit values are all 1, other ground The corresponding value of position, location is the most identical.

Step S406, polycaryon processor be this group of alternate access the 3rd address and in the way of skipping cache memory Four addresses, obtain second average access latency corresponding with this group the 3rd address and the 4th address.

Step S408, judge that whether gather C is empty, i.e. judges that c address bit has traveled through all addresses in set C the most Position.If set C is not sky, repeats step S404, if set C is sky, perform step S410.

Step S410, polycaryon processor obtain each second average access corresponding with each group of the 3rd address and the 4th address and prolong Late, according to access delay time length, each second average access latency is grouped.

Step S412, determine that the column address bit of physical address includes access delay time the longest one group of second average access Postpone the address bit in corresponding set C.

Fig. 5 is the flow chart of memory address mappings processing method embodiment five of the present invention, as it is shown in figure 5, the present embodiment carries The memory address mappings processing method of confession is on the basis of the embodiment that Fig. 3 or Fig. 4 provides, at polycaryon processor alternate access thing Before the 3rd address and the 4th address are respectively organized in reason address, also include:

Step S502, polycaryon processor alternate access memory system physical address in each group the 5th address and the 6th ground Location, obtains threeth average access latency corresponding with often group the 5th address and the 6th address, the 5th address and the 6th address and only exists The value of an identical address bit is different.

Specifically, if in the memory address mappings processing method embodiment of Fig. 3 or Fig. 4 offer, physical address various places Row address bit in position, location is unknown, then can construct one group of the 5th address and the 6th address, and the 5th address only has r position Value different from the value of the r position of the 6th address, the r position of the such as the 5th address takes 0, and the r position of the 6th address takes 1, 5th address is the most identical with the 6th address corresponding value of other address bits in addition to r position.

Polycaryon processor in the way of skipping cache memory, alternate access this group the 5th address and the 6th address, Obtain threeth average access latency corresponding with this group the 5th address and the 6th address.In the embodiment of the present invention, alternate access is secondary Number can be 1,000,000 times or other values with value, and to be obtained in that the 3rd average access latency is as the criterion accurately, the present invention implements Example is without limitation.

All address bits in the traversal physical address of above-mentioned r position, during the present position difference of r position, constitute difference group 5th address and the 6th address, polycaryon processor is in the way of skipping cache memory, and alternate access respectively organizes the 5th address With the 6th address, obtain each threeth average access latency corresponding with each group of the 5th address and the 6th address.

Step S504, polycaryon processor, according to each 3rd average access latency, determine the row address bit of physical address.

After polycaryon processor obtains each 3rd average access latency corresponding with each group of the 5th address and the 6th address, permissible The row address bit of physical address is determined according to each 3rd average access latency.

Step S302, step S304, step S102 and step S104 step corresponding with Fig. 3 is similar, the most superfluous State.

First the memory address mappings processing method that the present embodiment provides, by obtaining the physical address row to memory system Address and the mapping relations of column address, then obtain the physical address mapping relations to the bank address of memory system, so that permissible Bank partition is applied to entity computer memory system by the mapping relations using the bank address obtained, many to avoid Core processor shares bank interference.

Fig. 6 is the flow chart of memory address mappings processing method embodiment six of the present invention, and as shown in Figure 6, the present embodiment carries The method of confession is on the basis of embodiment illustrated in fig. 5, and polycaryon processor, according to each 3rd average access latency, determines described physics The row address bit of address, including:

Each 3rd average access latency, according to access delay time length, is grouped, determines physics by polycaryon processor Row address bit in address includes access delay time the longest one group of corresponding address bit.

Specifically, the memory address mappings processing method that the present embodiment provides is implementing what Fig. 3 or Fig. 4 embodiment provided Can also include before method:

Step S602, the address bit of unknown all physical address is constituted set R.

Step S604, take a r address bit in set R and construct one group of the 5th address and the 6th address: the 5th address is only Different in the r address bit value of r address bit and the 6th address, the r address bit of the such as the 5th address is 0, the 6th address R address bit be 1, the corresponding value of other address bits is the most identical.

Step S606, polycaryon processor be this group of alternate access the 5th address and in the way of skipping cache memory Six addresses, obtain threeth average access latency corresponding with this group the 5th address and the 6th address.

Step S608, judge that whether gather R is empty, i.e. judges that r address bit has traveled through all addresses in set R the most Position.If set R is not sky, repeats step S604, if set R is sky, perform step S610.

Step S610, polycaryon processor obtain each threeth average access corresponding with each group of the 5th address and the 6th address and prolong Late, according to access delay time length, each 3rd average access latency is grouped.

Step S612, determine that the row address bit of physical address includes access delay time the longest one group of the 3rd average access Postpone the address bit in corresponding set R.

Fig. 7 is the flow chart of memory address mappings processing method embodiment seven of the present invention, as it is shown in fig. 7, the present embodiment carries The memory address mappings processing method of confession is on the basis of above-described embodiment, and polycaryon processor prolongs according to each first average access Late, after determining the memory bank bank address bit of physical address, it is also possible to including:

The multiple core of step S702, polycaryon processor concurrently accesses the first address sequence in the physical address of memory system, Obtaining memory bandwidth, the address in the first address sequence includes a bank-address position, multiple row address bit and multiple row Address bit, the value on the bank-address position of address adjacent in the first address sequence is different.

Specifically, in the case of the bank address bit of physical address is determined, first address can be constructed Sequence, each address in the first address sequence includes the bank-address position b address bit that position is identical, m row Address bit and n column address bit.Wherein the value of m+n should be greater than a threshold value, and such as m+n ＞ 20, to ensure constructed address The size of the sequence size more than cache memory Cache.The b address bit of address adjacent in the first address sequence Value is different, such as in the first address sequence, the b address bit of odd positions address takes 0, the b address of the address of even number position Position takes 1；M row address bit and n the column address bit of each address in the first address sequence are sequentially incremented by, until traversal is all Combining form, m row address bit in the first first address sequence all takes 0, and n column address bit is incremented to one by one from entirely taking 0 Entirely taking 1, then the value of m row address increases by 1, and n column address bit is incremented to entirely take 1, by that analogy, directly one by one from entirely taking 0 It is all 1 to m row address bit and n column address bit value.

Multiple cores of polycaryon processor, by the way of cache memory, concurrently access the first address sequence, can To access the different fragments of the first address sequence with different IPs, obtain and access the execution time and then obtain memory bandwidth.

B address bit in above-mentioned first address sequence travels through all bank address bits, and b address bit present position is different Time, multiple cores of polycaryon processor, by the way of cache memory, concurrently access the first address sequence, obtain with each Each memory bandwidth that the b address bit of diverse location is corresponding.

Step S704, polycaryon processor, according to each memory bandwidth, determine the passage channel address bit of physical address.

After polycaryon processor obtains each memory bandwidth, the channel of physical address can be determined according to each memory bandwidth Address bit.

Step S102 step corresponding to Fig. 1 with step S104 is similar, and here is omitted.

The memory address mappings processing method that the present embodiment provides can obtain physical address easily to memory system The mapping relations of bank address, thus obtain the physical address mapping relations to the channel address of memory system, so that permissible The mapping relations of the bank address that use obtains and the mapping relations of channel address are by bank partition and channel Partition is applied to entity computer memory system, and what to avoid polycaryon processor to share, bank and channel caused is dry Disturb.

Fig. 8 is the flow chart of memory address mappings processing method embodiment eight of the present invention, and as shown in Figure 8, the present embodiment carries The method of confession is on the basis of embodiment illustrated in fig. 7, and polycaryon processor, according to each memory bandwidth, determines the passage ground of physical address Position, location, including:

Each memory bandwidth, according to the size of memory bandwidth, is grouped by polycaryon processor；

If each memory bandwidth is divided into multiple groups, it is determined that the passage channel address bit of physical address includes memory access band One group of corresponding memory bank bank address bit of wide maximum.

Specifically, the memory address mappings processing method that the present embodiment provides is implementing what Fig. 1 or Fig. 2 embodiment provided Can also include after method:

Step S802, the bank address bit of all physical address is constituted set T.

Step S804, take m row address bit, n column address bit and set T in a b address bit, construct the first address Sequence.

Each address in first address sequence includes the bank-address position b address bit that position is identical, m Row address bit and n column address bit.Wherein the value of m+n should be greater than a threshold value, and such as m+n ＞ 20, to ensure constructed ground The size of the location sequence size more than cache memory Cache.The b address bit of address adjacent in the first address sequence Value different, such as in the first address sequence, the b address bit of odd positions address takes 0, the b ground of the address of even number position Position, location takes 1；M row address bit and n the column address bit of each address in the first address sequence are sequentially incremented by, until traversal institute Having combining form, m row address bit in the first first address sequence all takes 0, and n column address bit is incremented by one by one from entirely taking 0 To entirely taking 1, then the value of m row address increases by 1, and n column address bit is incremented to entirely take 1 one by one from entirely taking 0, by that analogy, Until m row address bit and n column address bit value are all 1.

Step S806, polycaryon processor multiple cores concurrently to access the first address in the way of cache memory Sequence, obtains the memory bandwidth corresponding with b address bit.

Step S808, judge that whether gather T is empty, i.e. judges that b address bit has traveled through all addresses in set T the most Position.If set T is not sky, repeats step S804, if set T is sky, perform step S810.

Step S810, polycaryon processor obtain each memory bandwidth corresponding with each b address bit, big according to memory bandwidth Little, each memory bandwidth is grouped.

Step S812, judge whether each memory bandwidth is divided into a group, if each memory bandwidth is divided into multiple groups, hold Row step S814, if each memory bandwidth is divided into a group, performs step S816.

Step S814, determine that the channel address bit of physical address includes one group of memory bandwidth pair that memory bandwidth is maximum Address bit in the set T answered.

Step S816, determine physical address does not include channel address bit.If each memory bandwidth is divided into a group Time, memory system only has unique channel, so without channel address.

Fig. 9 is the flow chart of memory address mappings processing method embodiment nine of the present invention, as it is shown in figure 9, the present embodiment carries The memory address mappings processing method of confession is on the basis of Fig. 7 or Fig. 8 provides embodiment, and polycaryon processor is according to each memory access band Width, after determining the passage channel address bit of physical address, it is also possible to including:

Step S902, the single core of polycaryon processor access the thing of memory system in the way of skipping cache memory The second address sequence in reason address, the multiple core of remaining of polycaryon processor is concurrently to visit in the way of cache memory Ask the 3rd address sequence in physical address, obtain the 4th average access latency that the second address sequence is corresponding；Second address sequence Address in row is different with the value on same channel address position of the address in the 3rd address sequence, and in the second address sequence The value of other address bit of address constant, the value of other address bit of the address in the 3rd address sequence is continually changing.

Specifically, in the case of the channel address bit of physical address is determined, the second address sequence can be constructed Row and the 3rd address sequence, the second address sequence and the 3rd address sequence all include a same channel address bit, and the second ground The value of this channel address bit in the sequence of location and this channel address bit in the 3rd address sequence is different.Such as second The channel address bit of all addresses in address sequence, it is assumed that be a address bit, value is all 0；Institute in 3rd address sequence The a address bit value having address is all 1.

The single core of polycaryon processor accesses the second address in physical address in the way of skipping cache memory Sequence, in access process, other address bit in addition to a address bit of the address in the second address sequence keeps constant；Multinuclear processes The multiple core of remaining of device, concurrently to access the 3rd address sequence in physical address in the way of cache memory, accesses During address in the 3rd address sequence other address bit in addition to a address bit persistently change, can also with consecutive variations Change at random.Multiple cores concurrently access the 3rd address sequence mainly in order to disturb the single core access to the second address sequence.Many Core processor obtains single core and the access of the second address sequence performs the time, and then obtains corresponding with the second address sequence the Four average access latency.

A address bit in above-mentioned second address sequence and the 3rd address sequence travels through all channel address bits, a During the difference of address bit present position, each 4th average access latency that a address bit of variant position is corresponding can be obtained.

Step S904, polycaryon processor, according to each 4th average access latency, determine the Memory Controller Hub ground of physical address Position, location.

After polycaryon processor obtains each 4th average access latency, thing can be determined according to each 4th average access latency The Memory Controller Hub address bit of reason address.

Step S102, step S104, step S702 and step S704 step corresponding with Fig. 7 is similar, the most superfluous State.

The memory address mappings processing method that the present embodiment provides can obtain physical address easily to memory system The mapping relations of bank address and the mapping relations of channel address, thus obtain the Memory Controller Hub address of memory system Mapping relations, and then the mapping relations of bank address of acquisition, the mapping relations of channel address and internal memory control can be used The mapping relations of device address processed, are applied to bank partition, channel partition and Memory Controller Hub subregion Entity computer memory system, with the interference avoiding polycaryon processor shared drive system to cause.

Figure 10 is the flow chart of memory address mappings processing method embodiment ten of the present invention, as shown in Figure 10, the present embodiment The method provided is on the basis of embodiment illustrated in fig. 9, and polycaryon processor, according to each 4th average access latency, determines physically The Memory Controller Hub address bit of location, including:

Each 4th average access latency, according to access delay time length, is grouped by polycaryon processor；Ruo Ge tetra- Average access latency is divided into multiple groups, it is determined that the Memory Controller Hub address bit of physical address includes that the access delay time is the longest One group of corresponding channel address position.

Specifically, the memory address mappings processing method that the present embodiment provides is implementing what Fig. 7 or Fig. 8 embodiment provided Can also include after method:

Step S1002, the channel address bit of all physical address is constituted set U.

Step S 1004, take set U in an a address bit, construct the second address sequence and the 3rd address sequence.

Second address sequence and the 3rd address sequence all include a address in an a address bit, and the second address sequence Position is different from the value of a address bit in the 3rd address sequence.Such as in the second address sequence a address bit of all addresses Value is all 0；In 3rd address sequence, a address bit value of all addresses is all 1.

Step S1006, the single core of polycaryon processor access in physical address in the way of skipping cache memory The second address sequence, the multiple core of remaining of polycaryon processor is concurrently to access physically in the way of cache memory The 3rd address sequence in location, obtains the 4th average access latency.

Step S1008, judge that whether gather U is empty, i.e. judge a address bit the most traveled through in set U allly Position, location.If set U is not sky, repeats step S1004, if set U is sky, perform step S1010.

Step S1010, obtain each fourth average access latency corresponding with each a address bit, according to the access delay time Length, is grouped each 4th average access latency.

Whether step S1012, each 4th average access latency are divided into a group, if each 4th average access latency is divided Then perform step S1014 for multiple groups, if each 4th average access latency is divided into a group, perform step S1016.

Step S1014, determine that the Memory Controller Hub address bit of physical address includes access delay time the longest one group Address bit in the set U that four average access latency are corresponding.

Step S1016, determine physical address does not include Memory Controller Hub address bit.Ruo Ge tetra-average access latency quilt When being divided into one to organize, memory system only has unique Memory Controller Hub, so without Memory Controller Hub address.

Figure 11 is the structural representation of polycaryon processor embodiment one of the present invention, and as shown in figure 11, the present embodiment provides Polycaryon processor 1100 includes:

Memory access module 1110, each group the first address and the second address in the physical address of alternate access memory system；

Measurement module 1120, the first average access latency being used for acquisition with often organizing the first address and the second address is corresponding, The value the most corresponding on two identical address bits in described first address and described second address is different and said two address Position is the address bit in each address bit of described physical address in addition to row address bit and column address bit；

Analyze module 1130, be used for according to each first average access latency, determine the bank-address of described physical address Position.

The polycaryon processor 1100 of the present embodiment, may be used for performing memory address mappings processing method shown in Fig. 1 and implements The technical scheme of example, it is similar with technique effect that it realizes principle, and here is omitted.

Above-mentioned analysis module 1130 can be also used for, according to access delay time length, prolonging described each first average access It is grouped late；If described each first average access latency is divided into multiple groups, then by the longest for the access delay time one group pair Two the address bit XORs answered are processed as the first set, determine that the described bank-address position of physical address includes described first collection Close and in each address bit of described physical address except row address bit, described column address bit and the longest one group pair described time delay All address bits outside the said two address bit answered；If described each first average access latency is divided into a group, the most really The described bank-address position of fixed described physical address includes all said two address bits.

Use the polycaryon processor 1100 of present embodiment, may be used for performing memory address mappings process side shown in Fig. 2 The technical scheme of method embodiment, it is similar with technique effect that it realizes principle, and here is omitted.

Memory access module 1110 described above be additionally operable in the physical address of alternate access memory system respectively to organize the 3rd address and 4th address；It is flat that the most described measurement module 1120 is additionally operable to obtain second corresponding with often group the 3rd address and the 4th address All access delay, described 3rd address and described 4th address are on an identical row address bit and a non-row address bit Corresponding value is different；The most described analysis module 1130 is additionally operable to, according to each second average access latency, determine described thing The column address bit of reason address.

Use the polycaryon processor 1100 of present embodiment, may be used for performing memory address mappings process side shown in Fig. 3 The technical scheme of method embodiment, it is similar with technique effect that it realizes principle, and here is omitted.

Analysis module 1130 in a upper embodiment can be also used for according to access delay time length, by described each second Average access latency is grouped, and determines that the described column address bit of described physical address includes that the described access delay time is the longest One group of corresponding non-row address bit.

Use the polycaryon processor 1100 of present embodiment, may be used for performing memory address mappings process side shown in Fig. 4 The technical scheme of method embodiment, it is similar with technique effect that it realizes principle, and here is omitted.

Memory access module 1110 is additionally operable in the physical address of alternate access memory system respectively organize the 5th address and the 6th address； The most described measurement module 1120 is additionally operable to obtain threeth average access corresponding with often group the 5th address and the 6th address and prolongs Late, described 5th address is only different in the value of an identical address bit with the 6th address；The most described analysis module 1130 are additionally operable to, according to each 3rd average access latency, determine the row address bit of described physical address.

Use the polycaryon processor 1100 of present embodiment, may be used for performing memory address mappings process side shown in Fig. 5 The technical scheme of method embodiment, it is similar with technique effect that it realizes principle, and here is omitted.

Analysis module 1130 in a upper embodiment can be also used for according to access delay time length, by the described each 3rd Average access latency is grouped, and determines that the described row address bit in described physical address includes that the described access delay time is the longest One group of corresponding address bit.

Use the polycaryon processor 1100 of present embodiment, may be used for performing memory address mappings process side shown in Fig. 6 The technical scheme of method embodiment, it is similar with technique effect that it realizes principle, and here is omitted.

Memory access module 1110 is additionally operable to the first address sequence concurrently accessing in the physical address of memory system with many kernel form Row；The most described measurement module 1120 is additionally operable to obtain the memory bandwidth that the first address sequence is corresponding, described first address sequence Address in row includes a bank-address position, multiple row address bit and multiple column address bit, described first address sequence In adjacent address described bank-address position on value different；The most described analysis module 1130 is additionally operable to according to each Memory bandwidth, determines the channel address position of described physical address.

Use the polycaryon processor 1100 of present embodiment, may be used for performing memory address mappings process side shown in Fig. 7 The technical scheme of method embodiment, it is similar with technique effect that it realizes principle, and here is omitted.

Analysis module 1130 in a upper embodiment can be also used for the size according to described memory bandwidth, to described each visit Deposit bandwidth to be grouped；If described each memory bandwidth is divided into multiple groups, it is determined that the described channel address of described physical address Position includes one group of corresponding described bank-address position that described memory bandwidth is maximum.

Use the polycaryon processor 1100 of present embodiment, may be used for performing memory address mappings process side shown in Fig. 8 The technical scheme of method embodiment, it is similar with technique effect that it realizes principle, and here is omitted.

Memory access module 1110 is additionally operable in the way of monokaryon form skips cache memory access described memory system Physical address in the second address sequence, in the way of cache memory, concurrently access described physics by many kernel form The 3rd address sequence in address；The most described measurement module 1120 is used for obtaining the 4th that described second address sequence is corresponding Average access latency, the address in described second address sequence and the address in the 3rd address sequence are on same channel address position Value different, and the value of other address bit of the address in described second address sequence is constant, described 3rd address sequence In the value of other address bit of address be continually changing；The most described analysis module 1130 is for averagely visiting according to each 4th Ask delay, determine the Memory Controller Hub address bit of described physical address.

Use the polycaryon processor 1100 of present embodiment, may be used for performing memory address mappings process side shown in Fig. 9 The technical scheme of method embodiment, it is similar with technique effect that it realizes principle, and here is omitted.

Analysis module 1130 in a upper embodiment can be also used for according to access delay time length, to the described each 4th Average access latency is grouped；If described each 4th average access latency is divided into multiple groups, it is determined that described physical address Described Memory Controller Hub address bit include the longest one group of corresponding described channel address position of described access delay time.

Use the polycaryon processor 1100 of present embodiment, may be used for performing memory address mappings process side shown in Figure 10 The technical scheme of method embodiment, it is similar with technique effect that it realizes principle, and here is omitted.

One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each method embodiment can be led to The hardware crossing programmed instruction relevant completes.Aforesaid program can be stored in a computer read/write memory medium.This journey Sequence upon execution, performs to include the step of above-mentioned each method embodiment；And aforesaid storage medium includes: ROM, RAM, magnetic disc or The various media that can store program code such as person's CD.

Last it is noted that various embodiments above is only in order to illustrate technical scheme, it is not intended to limit；To the greatest extent The present invention has been described in detail by pipe with reference to foregoing embodiments, it will be understood by those within the art that: it depends on So the technical scheme described in foregoing embodiments can be modified, or the most some or all of technical characteristic is entered Row equivalent；And these amendments or replacement, do not make the essence of appropriate technical solution depart from various embodiments of the present invention technology The scope of scheme.

Claims

1. a memory address mappings processing method, it is characterised in that including:

Each group the first address and the second address in the physical address of polycaryon processor alternate access memory system, obtain and often organize the The first average access latency that one address is corresponding with the second address, described first address and described second address are only identical two Value corresponding on individual address bit is different and said two address bit be in each address bit of described physical address except row address bit and Address bit outside column address bit；

Polycaryon processor, according to each first average access latency, determines the bank-address position of described physical address, specifically includes:

Described first average access latency, according to access delay time length, is grouped by polycaryon processor；

If described first average access latency is divided into multiple groups, then by the longest for the access delay time one group corresponding described two Individual address bit XOR is processed as the first set, determines that the described bank-address position of described physical address includes described first set And except described row address bit, described column address bit and described time delay the longest one group in the described each address bit of physical address The corresponding all address bits outside said two address bit；

If described first average access latency is divided into a group, it is determined that the described bank-address position bag of described physical address Include all said two address bits.

Method the most according to claim 1, it is characterised in that in described polycaryon processor alternate access physical address each group Before first address and the second address, also include:

Each group the 3rd address and the 4th address in the physical address of polycaryon processor alternate access memory system, obtain and often organize the The second average access latency that three addresses are corresponding with the 4th address, described 3rd address and described 4th address are only identical one Value corresponding on individual row address bit and a non-row address bit is different；

Polycaryon processor, according to each second average access latency, determines the column address bit of described physical address, specifically includes:

Described second average access latency, according to access delay time length, is grouped, determines described thing by polycaryon processor Reason address described column address bit include the described access delay time the longest one group of corresponding non-row address bit.

Method the most according to claim 2, it is characterised in that in described polycaryon processor alternate access physical address each group Before 3rd address and the 4th address, also include:

Each group the 5th address and the 6th address in the physical address of polycaryon processor alternate access memory system, obtain and often organize the The 3rd average access latency that five addresses are corresponding with the 6th address, described 5th address and the 6th address are only on an identical ground The value of position, location is different；

Polycaryon processor, according to each 3rd average access latency, determines the row address bit of described physical address, specifically includes:

Described 3rd average access latency, according to access delay time length, is grouped, determines described thing by polycaryon processor Described row address bit in reason address includes the longest one group of corresponding address bit of described access delay time.

4. according to the arbitrary described method of claim 1-3, it is characterised in that described polycaryon processor is averagely visited according to each first Ask delay, after determining the bank-address position of described physical address, also include:

The multiple core of polycaryon processor concurrently accesses the first address sequence in the physical address of memory system, obtains the first address sequence The memory bandwidth that row are corresponding, the address in described first address sequence include a bank-address position, multiple row address bit with And multiple column address bit, the value on the described bank-address position of address adjacent in described first address sequence is different；

Polycaryon processor, according to each memory bandwidth, determines the channel address position of described physical address, specifically includes:

Described memory bandwidth, according to the size of described memory bandwidth, is grouped by polycaryon processor；

If described memory bandwidth is divided into multiple groups, it is determined that the described channel address position of described physical address includes described memory access One group of corresponding described bank-address position that bandwidth is maximum.

Method the most according to claim 4, it is characterised in that described polycaryon processor, according to each memory bandwidth, determines institute After stating the channel address position of physical address, also include:

The single core of polycaryon processor accesses in the physical address of described memory system in the way of skipping cache memory The second address sequence, remaining multiple core of described polycaryon processor are concurrently to access institute in the way of cache memory State the 3rd address sequence in physical address, obtain the 4th average access latency that described second address sequence is corresponding；

Address in described second address sequence and the address in the 3rd address sequence value on same channel address position is not With, and the value of other address bit of the address in described second address sequence is constant, the address in described 3rd address sequence The value of other address bit be continually changing；

Polycaryon processor, according to each 4th average access latency, determines the Memory Controller Hub address bit of described physical address, specifically Including:

Described 4th average access latency, according to access delay time length, is grouped by polycaryon processor；

If described 4th average access latency is divided into multiple groups, it is determined that the described Memory Controller Hub address of described physical address Position includes the longest one group of corresponding described channel address position of described access delay time.

6. a polycaryon processor, it is characterised in that including:

Memory access module, each group the first address and the second address in the physical address of alternate access memory system；

Measurement module, the first average access latency being used for acquisition with often organizing the first address and the second address is corresponding, described first The value the most corresponding on two identical address bits in address and described second address is different and said two address bit is described Address bit in addition to row address bit and column address bit in each address bit of physical address；

Analysis module is used for:

According to access delay time length, described first average access latency is grouped；

If described first average access latency is divided into multiple groups, then by the longest for the access delay time one group corresponding described two Individual address bit XOR is processed as the first set, determine the bank-address position of described physical address include described first set and In each address bit of described physical address except described row address bit, described column address bit is the longest with described time delay one group corresponding Said two address bit outside all address bits；

Polycaryon processor the most according to claim 6, it is characterised in that

Described memory access module is additionally operable in the physical address of alternate access memory system respectively organize the 3rd address and the 4th address；Corresponding Ground:

Described measurement module is additionally operable to obtain second average access latency corresponding with often group the 3rd address and the 4th address, described The value the most corresponding on an identical row address bit and a non-row address bit in 3rd address and described 4th address is different； Accordingly:

Described analysis module is additionally operable to, according to access delay time length, be grouped, really by described second average access latency The described column address bit of fixed described physical address include the described access delay time the longest one group of corresponding non-row address bit.

Polycaryon processor the most according to claim 7, it is characterised in that

Described memory access module is additionally operable in the physical address of alternate access memory system respectively organize the 5th address and the 6th address；Corresponding Ground:

Described measurement module is additionally operable to obtain threeth average access latency corresponding with often group the 5th address and the 6th address, described 5th address is only different in the value of an identical address bit with the 6th address；Accordingly:

Described analysis module is additionally operable to, according to access delay time length, be grouped, really by described 3rd average access latency Described row address bit in fixed described physical address includes the longest one group of corresponding address bit of described access delay time.

9. according to the arbitrary described polycaryon processor of claim 6-8, it is characterised in that

Described memory access module is additionally operable to the first address sequence concurrently accessing in the physical address of memory system with many kernel form；Right Ying Di:

Described measurement module is additionally operable to obtain the memory bandwidth that the first address sequence is corresponding, the address in described first address sequence Including a bank-address position, multiple row address bit and multiple column address bit, ground adjacent in described first address sequence Value on the described bank-address position of location is different；Accordingly:

Described analysis module is additionally operable to the size according to described memory bandwidth, is grouped described memory bandwidth；

If described memory bandwidth is divided into multiple groups, it is determined that the channel address position of described physical address includes described memory bandwidth One group of maximum corresponding described bank-address position.

Polycaryon processor the most according to claim 9, it is characterised in that

Described memory access module is additionally operable to access the thing of described memory system in the way of monokaryon form skips cache memory The second address sequence in reason address, concurrently accesses described physical address by many kernel form in the way of cache memory In the 3rd address sequence；Accordingly:

Described measurement module is for obtaining the 4th average access latency that described second address sequence is corresponding, described second address sequence Address in row is different with the value on same channel address position of the address in the 3rd address sequence, and described second address sequence The value of other address bit of the address in row is constant, and the value of other address bit of the address in described 3rd address sequence is not Disconnected change；Accordingly:

Described analysis module is additionally operable to, according to access delay time length, be grouped described 4th average access latency；

If described 4th average access latency is divided into multiple groups, it is determined that the Memory Controller Hub address bit bag of described physical address Include the longest one group of corresponding described channel address position of described access delay time.