JP2018132914A - Information processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress adding parts for recording trace information of a control apparatus.SOLUTION: An information processing apparatus executes a predetermined control program for realizing control to a control target in a first mode, and executes a pseudo program for simulating operation of the control program in a second mode. The information processing apparatus comprises a read only memory for storing the control program, a random access memory for holding the pseudo program in the second mode, a processor for executing the control program of the read only memory in the first mode and executing the pseudo program of the random access memory in the second mode, and a debugging function unit for acquiring trace information indicating the operation of the processor and recording the same in the random access memory in the first mode and acquiring the trace information and outputting the same to an external debugging apparatus in the second mode.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a technique for accumulating the operation of an information processing device in a control device as trace information.

  In recent years, the control of automobiles has become complicated. Therefore, an ECU (Electric Control Unit) that realizes complicated control by a microcomputer is installed in many automobiles. In the ECU, various controls of the automobile are programmed as software, and the processor executes the software program. Various information is input to the ECU from the automobile, and based on the information, complicated control is performed on the automobile according to the situation.

  When entering the market, automobiles are used in various situations, so the information input to the ECU also changes in various ways. For this reason, it is not easy to identify the cause when an ECU microcomputer mounted on an automobile on the market has some sort of malfunction. Even if it tries to analyze the operation of the microcomputer at the time of malfunction, the malfunction cannot be reproduced and the analysis may not be possible. Identification of the cause of the malfunction of the ECU is a work that requires a lot of labor and time.

  To eliminate malfunctions, narrow down the conditions under which malfunctions occur in the market, identify the causes of malfunctions, and implement permanent measures against the causes of malfunctions so that malfunctions do not occur under those conditions. However, in the market, unexpected conditions often accumulate and cause malfunctions, and a great deal of time is spent investigating the conditions that cause malfunctions.

  It is difficult to identify what conditions have accumulated and led to a malfunction only from the situation when the malfunction occurred. For this reason, Patent Document 1 discloses a technique in which a memory is built in the ECU and the operation of the microcomputer is continuously stored in the memory as trace information.

  If the technique of Patent Document 1 is used, trace information indicating the operation of the microcomputer over time is accumulated in the memory, so that when a malfunction occurs, it can be used to identify the cause of the malfunction.

Japanese Patent Laid-Open No. 8-95945

  However, in the technique of Patent Document 1, it is necessary to newly install a memory for storing the trace result in the ECU. For this reason, there is a problem in that the addition of the memory increases the size of the ECU and increases the cost.

  The present invention is to provide a technique for suppressing the addition of components for recording trace information of a control device.

  An information processing apparatus according to an aspect of the present invention executes an information processing apparatus that executes a predetermined control program that realizes control of a control target in a first mode, and executes a pseudo program that simulates the operation of the control program in a second mode. A read-only memory for storing the control program; a random access memory for holding the pseudo program in the second mode; and the control program for the read-only memory in the first mode. In the second mode, the processor that executes the pseudo program in the random access memory, and the trace information representing the operation of the processor in the first mode is acquired and recorded in the random access memory, and the trace information in the second mode Is obtained and output to an external debugging device. Tsu has a grayed function unit.

  A random access memory that holds a pseudo program executed by the processor in the development mode (second mode) is used to record trace information in the mass production mode (first mode). Addition of parts can be suppressed.

It is a figure which shows the debugging environment in the software development of a control apparatus. It is a figure which shows the debugging environment in the software development of the control apparatus in this embodiment. It is a block diagram which shows the control apparatus of the mass-produced product in this embodiment. It is a flowchart which shows the operation | movement at the time of debugging in this embodiment.

  A control apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings. The control device of the present embodiment is a device that acquires various types of information and transmits a control signal to a control target based on the information, and performs complicated processing. For this reason, the control device is equipped with a microcomputer, and the processor executes a software program on the microcomputer (hereinafter also referred to as “microcomputer”) to execute complicated processing. Debugging is essential for software that implements complex processing. Therefore, a debugging environment is prepared for the microcomputer mounted on the control device.

  First, a debugging environment for developing control unit software will be described.

  FIG. 1 is a diagram showing a debugging environment in software development of a control device. Referring to FIG. 1, as a debugging environment, a debugger 109 is connected to the control apparatus 101 to be developed, and a personal computer (PC) 110 is connected to the debugger 109.

  A microcomputer 102 is mounted on the control device 101. The microcomputer 102 includes an emulation RAM (ERAM) 103, a flash memory (Flash) 104, a global RAM (Global RAM) 105, a processor (CPU) 106, an EEPROM 107, a debug function unit 108, a system interconnect 111, a flash interface 112, and a peripheral bus 113. And a peripheral function unit 114. The ERAM 103, the EEPROM 107, and the debug function unit 108 are provided for debugging. The above-described debugger 109 is connected to the debug function unit 108.

  The processor 106 is connected to the system interconnect 111. A global RAM 105, EEPROM 107, flash interface 112, peripheral bus 113, and debug function unit 108 are connected to the system interconnect 111.

  The processor 106 can access the global RAM 105 and the EEPROM 107 via the system interconnect 111.

  An ERAM 103 and a flash memory 104 are connected to the flash interface 112. The processor 106 can access the ERAM 103 and the flash memory 104 via the system interconnect 111 and the flash interface 112.

  A control program executed by the processor 106 in the mass production mode in which the control device 101 controls a control target (not shown) is installed in the flash memory 104. The mass production product of the control device 101 is in the mass production mode. In the mass production mode, the processor 106 executes a control program stored in the flash memory 104. The processor 106 executes the control program while using the global RAM 105.

  A plurality of peripheral function units 114 are connected to the peripheral bus 113. The peripheral function unit 114 is various function units used for control of the control device 101. For example, the peripheral function unit 114 is a sensor interface that acquires sensor inputs from a control target or a sensor installed in the vicinity thereof. The sensor input is an input signal indicating information observed by the sensor. Alternatively, the peripheral function unit 114 is a control interface that transmits a control output to the control target. The control output is an output signal indicating control instructed to the control target. The processor 106 transmits and receives signals to and from the peripheral function unit 114 as appropriate according to the processing of the control program.

  A pseudo program that is appropriately executed by the processor 106 in the development mode used at the time of debugging in software development of the control device 101 is mounted on the ERAM 103 that can be easily rewritten. The product (prototype) at the time of development is in development mode. In the development mode, the processor 106 executes a pseudo program stored in the ERAM 103. The pseudo program is a software program that simulates a control program.

  The developer debugs the control program while monitoring and controlling the debug function unit 108 with the personal computer 110 via the debugger 109 which is an external device. In debugging, the developer repeatedly executes the pseudo program while rewriting it. Debug functions that can be executed from the personal computer 110 via the debug function unit 108 include a trace function, a calibration function, and an emulation function.

  The trace function is a function for accumulating information on the operation and state of the processor 106 in order to confirm the operation of the software executed by the processor 106 for each step. In the trace function, the debug function unit 108 observes a signal flowing on the system interconnect 111 that is a processor bus, and acquires trace information indicating the operation of the processor 106. The trace information is, for example, information obtained by compressing a series of instructions executed by the processor 106 so that the debug function unit 108 can easily use the instructions for debugging. The debug function unit 108 outputs the acquired trace information to the debugger 109. The developer can trace the operation of the processor 106 that has executed the pseudo program based on the trace information input to the personal computer 110 via the debugger 109. This trace function is valid for a product (prototype) at the time of development, but is generally invalidated so that various types of program information cannot be read for mass-produced products.

  The calibration function is a function for tuning a set value of a control parameter used for control of a control target. The control parameter is also called ROM data, and is stored in the flash memory 104 in mass-produced products, but is held on the ERAM 103 in debugging. The control parameter is a parameter used for controlling each part of the automobile, for example. Tuning is to determine the optimum control parameter by observing the result while changing the value of the control parameter and examining the optimum value. The developer operates the debug function unit 108 from the personal computer 110 via the debugger 109 to tune the ROM data on the ERAM 103.

  The emulation function is a function for downloading pseudo software to the ERAM 103 and causing the processor 106 to execute the pseudo software. In the emulation function, the flash memory 104 can be emulated by the ERAM 103 which is an emulation memory while the processor 106 is operating. That is, instead of causing the processor 106 to execute the control program using the control parameter on the flash memory 104, the pseudo program can be executed using the control parameter on the ERAM 103. Again, this emulation function is valid for products at the time of development (prototype), but for mass-produced products, it is generally invalidated so that various program information is not read and the control program is not modified. It is.

  Debugging is performed by combining these trace function, calibration function, and emulation function. Application software (hereinafter referred to as “debugger application”) for using the debugger 109 is installed in the personal computer 110. Further, the personal computer 110 holds various types of information related to a control software program (hereinafter also referred to as “control program”) to be developed. The developer executes a debugger application on the personal computer 110, and performs debugging using an emulation function, a calibration function, and a trace function while referring to various information of the control program.

  FIG. 2 is a diagram showing a debug environment in software development of the control device in the present embodiment. Referring to FIG. 2, as a debugging environment, a debugger 209 is connected to the control apparatus 201 to be developed, and a personal computer (PC) 210 is connected to the debugger 209.

  A microcomputer 202 is mounted on the control device 201. The microcomputer 202 includes an emulation RAM (ERAM) 203, a flash memory (Flash) 204, a global RAM (Global RAM) 205, a processor (CPU) 206, an EEPROM 207, a debug function unit 208, corresponding to each unit shown in FIG. In addition to the system interconnect 211, the flash interface 212, the peripheral bus 213, and the peripheral function unit 214, the system further includes a bus switch 221, a bus switch 222, a debug bus 223, and a communication function unit 224. The ERAM 203, the EEPROM 207, and the debug function unit 208 are provided for debugging. The debugger 209 described above is connected to the debug function unit 208.

  The debug bus 223 is a bus provided for debugging. The bus switches 221 and 222 are switches for switching the bus connection between the development mode and the mass production mode, and can be switched by the processor 206. Therefore, the bus switches 221 and 222 may be set to the mass production mode in the control program used for the mass production product. Further, the bus switches 221 and 222 may be set to the development mode in the pseudo program used for the prototype product.

  The bus switch 221 is turned on (closed) in the development mode, and turned off (opened) in the mass production mode. The bus switch 222 is turned off (opened) in the development mode, and turned on (closed) in the mass production mode. In the product (prototype) at the time of development of the control device 201, the microcomputer 202 is used in the development mode, and in the mass production product of the control device 201, the microcomputer 202 is used in the mass production mode. The bus switches 221 and 222 shown in FIG. 2 are in a development mode, that is, the control device 201 in FIG. 2 is a prototype.

  The communication function unit 224 is an interface unit that connects the diagnostic tool 225. The communication function unit 224 can access the EEPROM 207 via the peripheral bus 213 and the system interconnect 221 in response to a request from the diagnostic tool 225. The diagnostic tool 225 can read data from the EEPROM 207 by communicating with the communication function unit 224. As will be described later, in this embodiment, trace information acquired in the mass production mode is saved in the EEPROM 207. Trace information stored in the EEPROM 207 can be extracted by the diagnostic tool 225 via the communication function unit 224.

  The processor 206 is connected to the system interconnect 211. A global RAM 205, EEPROM 207, flash interface 212, peripheral bus 213, and debug function unit 208 are connected to the system interconnect 211.

  The processor 206 can access the global RAM 205 and the EEPROM 207 via the system interconnect 211.

  A flash memory 204 is connected to the flash interface 212, and an ERAM 203 is further connected via a bus switch 222. As described above, the bus switch 222 is turned off in the mass production mode and turned on in the development mode. The bus switch 221 is turned on in the mass production mode and turned off in the development mode. Therefore, the processor 206 can access the ERAM 203 and the flash memory 204 via the system interconnect 211 and the flash interface 212 in the development mode. Further, in the mass production mode, the processor 206 can access the flash memory 204 via the system interconnect 211 and the flash interface 212, but cannot access the ERAM 203.

  A control program executed by the processor 206 in the mass production mode is installed in the flash memory 204. In the mass production mode, the processor 206 executes a control program stored in the flash memory 204. The processor 206 executes a control program while using the global RAM 205.

  A plurality of peripheral function units 214 and communication function units 224 are connected to the peripheral bus 213. The peripheral function unit 214 is various function units used for control of the control device 201. For example, the peripheral function unit 214 is a sensor interface that acquires sensor inputs from a control target or a sensor installed in the vicinity thereof. The sensor input is an input signal indicating information observed by the sensor. Alternatively, the peripheral function unit 214 is a control interface that transmits a control output to the control target. The control output is an output signal indicating control instructed to the control target. The processor 206 transmits and receives signals to and from the peripheral function unit 214 as appropriate according to the processing of the control program.

  The pseudo program that is appropriately executed by the processor 206 in the development mode is mounted on the ERAM 203 that can be easily rewritten. In the development mode, the processor 206 executes a pseudo program stored in the ERAM 203. The pseudo program is a software program that simulates a control program.

  The developer debugs the control program while monitoring or controlling the debug function unit 208 with the personal computer 210 via the debugger 209 which is an external device. In debugging, the developer repeatedly executes the pseudo program while rewriting it. Debug functions that can be executed from the personal computer 210 via the debug function unit 208 include a trace function, a calibration function, and an emulation function.

  The trace function is a function for accumulating information on the operation and state of the processor 206 in order to confirm the operation of the software executed by the processor 206 for each step. In the trace function, the debug function unit 208 observes a signal flowing on the system interconnect 211 that is a processor bus, and acquires trace information indicating the operation of the processor 206. The trace information is, for example, information obtained by compressing a series of instructions executed by the processor 206 so that the debug function unit 208 can easily use the instructions for debugging. The debug function unit 208 outputs the acquired trace information to the debugger 209. The developer can trace the operation of the processor 206 that has executed the pseudo program based on the trace information input to the personal computer 210 via the debugger 209. This trace function is valid for a product (prototype) at the time of development, but is invalidated so that various types of program information cannot be read for mass-produced products.

  The calibration function is a function for tuning a set value of a control parameter used for control of a control target. The control parameter is also called ROM data, and is stored in the flash memory 204 in mass-produced products, but is held on the ERAM 203 in debugging. The control parameter is a parameter used for controlling each part of the automobile, for example. The developer operates the debug function unit 208 from the personal computer 210 via the debugger 209 to tune ROM data on the ERAM 203.

  The emulation function is a function for downloading pseudo software to the ERAM 203 and causing the processor 206 to execute the pseudo software. In the emulation function, the flash memory 204 can be emulated by the ERAM 203 which is an emulation memory while the processor 206 is operating. That is, instead of causing the processor 206 to execute the control program using the control parameter on the flash memory 204, the pseudo program can be executed using the control parameter on the ERAM 203. The emulation function is valid for a product at the time of development (prototype), but is invalidated for mass-produced products so that various information of the program is not read and the control program is not modified.

  Debugging is performed by combining these trace function, calibration function, and emulation function. Application software (hereinafter referred to as “debugger application”) for using the debugger 209 is installed in the personal computer 210. Further, the personal computer 210 holds various types of information related to a control software program (hereinafter also referred to as “control program”) to be developed. The developer executes a debugger application on the personal computer 210 and performs debugging using an emulation function, a calibration function, and a trace function while referring to various information of the control program.

  FIG. 3 is a block diagram illustrating a mass production product control apparatus according to the present embodiment. The mass-produced product control device 201 includes the same microcomputer 202 as the development environment control device 201 shown in FIG. The mass production product control device 201 shown in FIG. 3 differs from the prototype product shown in FIG. 2 in the settings of the bus switches 221 and 222. Further, unlike the prototype product of FIG. 2, the mass-produced control device 201 does not have an interface for connecting to the debugger 209.

  As described above, in the mass production mode or mass production product, the bus switch 222 is turned off and the bus switch 221 is turned on. Therefore, the processor 206 can access the flash memory 204 via the system interconnect 211 and the flash interface 212 in the mass production mode, but cannot access the ERAM 203. Instead, the ERAM 203 is accessible from the debug function unit 208.

  In the mass-produced product control apparatus 201, the debug function unit 208 records the trace information acquired by observing signals flowing on the system interconnect 211 in the ERAM 203. While the processor 206 continues to operate normally, the debug function unit 208 acquires trace information and continues to record it in the ring buffer configured on the ERAM 203.

  Further, when a predetermined abnormality occurs, the debug function unit 208 stops the acquisition of the trace information, and saves the trace information existing in the ERAM 203 in the EEPROM 207 at that time. That is, the debug function unit 208 reads the trace information recorded in the ERAM 203 and writes it in the EEPROM 207. The trace information saved in the EEPROM 207 can be taken out by the diagnostic tool 225 via the communication function unit 224 and the peripheral bus 213.

  As described above, in this embodiment, the trace information is accumulated in the mass production mode by using the ERAM 203 in which the pseudo program and the control parameters are stored in the development mode. Therefore, the components of the recording apparatus for recording the trace information are provided. There is no need to add it separately.

  Further, the mass production product control device 201 and the prototype control device 201 differ only in the presence or absence of an interface to the debugger 209 as hardware. This difference can be realized by whether or not an interface is attached, so that the prototype and the mass-produced product can be designed in common.

  As described above, the microcomputer 202 according to the present embodiment executes a predetermined control program that realizes control of a control target in the mass production mode (first mode), and operates the control program in the development mode (second mode). This is an information processing apparatus that executes a pseudo program that simulates. The microcomputer 202 includes a read only memory (flash memory 204), a random access memory (ERAM 205), a processor 206, and a debug function unit 208. The flash memory 204 stores a control program. The ERAM 205 holds a pseudo program in the development mode. The processor 206 executes a control program of the flash memory 204 in the mass production mode, and executes a pseudo program of the ERAM 205 in the development mode. The debug function unit 208 acquires trace information representing the operation of the processor 206 in the mass production mode, records it in the ERAM 203, acquires the trace information in the development mode, and outputs it to an external debugging device (debugger 209). A random access memory that holds a pseudo program executed by the processor in the development mode (second mode) is used to record trace information in the mass production mode (first mode). Addition of parts can be suppressed.

  The ERAM 203 further includes bus switches 221 and 222 that are accessible from the debug function unit 208 in the mass production mode and accessible from the processor 206 in the development mode. For this reason, bus switches 221 and 222 for switching whether the ERAM 203 is connected to the processor 206 or the debug function unit 208 are provided, so that both the development using the pseudo program and the mass production for tracing the operation of the processor 206 at all times are provided. The same microcomputer 202 can be shared by switching.

  The bus switches 221 and 222 switch whether the ERAM 203 can be accessed from the debug function unit 208 or the processor 206 depending on a value set in a register that can be set by the processor 206. Since the bus switches 221 and 222 can be switched by software, it is possible to adopt common hardware for a prototype that uses the development mode (second mode) and a mass-produced product that uses the mass production mode (first mode). It can contribute to reduction of development cost and development period.

  The control program sets registers so that the ERAM 203 can be accessed from the debug function unit 208, and the pseudo program sets registers so that the ERAM 203 can be accessed from the processor 206. By changing the value set in the register between the control software and the pseudo program, it is possible to realize a prototype that uses the development mode (second mode) and a mass-produced product that uses the mass production mode (first mode).

  Further, in the first mode, the debug function unit 208 configures a ring buffer in the ERAM 203 and records trace information in the ring buffer. Since the ring buffer is configured to record the trace information, the trace information can be continuously recorded, and the state in which a new part of the continuously generated trace information exists in the random access memory is maintained. be able to. 20

  The microcomputer 202 further includes a save memory (EEPROM) 207 that can be accessed from the debug function unit 208. The debug function unit 208 displays the trace information recorded in the ERAM 203 when a predetermined condition is satisfied. Retreat to EEPROM 207. When a predetermined condition occurs, it is saved from the ring buffer to the EEPROM 207 so that the previous trace information is not overwritten, so that desired trace information can be left.

  The predetermined condition is the occurrence of a predetermined failure. As a result, the trace information at the time of occurrence of the failure and immediately before the failure can be saved so as not to be erased.

  The debug function unit 208 manages a save destination address that is an address of the EEPROM 207 that records race information. When the trace information is recorded in the EEPROM 207, the save address is updated so that the trace information is not overwritten. . Each time the trace information is saved, the area in which the trace information is written is updated so that the trace information is not overwritten, so that the trace information of a plurality of events can be acquired.

  Further, the EEPROM 207 can extract data to the outside without going through the processing of the processor 206. As described above, since data can be extracted without going through the processing of the processor 206, data can be easily extracted even in an abnormal state and used for cause analysis of the abnormality.

  Further, the control target of the control device 201 according to the present embodiment is an automobile. It is possible to realize a processing apparatus suitable for mounting in an automobile, which is desired to be small, light, and low in cost.

  Hereinafter, processing of the control device 201 according to the present embodiment will be described.

  FIG. 4 is a flowchart showing an operation at the time of debugging in the present embodiment.

  First, when the power of the control device 201 on which the microcomputer 202 is mounted is turned on (step 301), the debug function unit 208 sets the bus switches 221 and 222 by the control program or the pseudo program (step 302).

  The debug function unit 208 determines whether or not the setting of the microcomputer 202 is the mass production mode (step 303). If the development mode is not the mass production mode, the debug function unit 208 performs the development mode operation of acquiring trace information and outputting it to the debugger 209 (step 304).

  On the other hand, if the setting of the microcomputer 202 is the mass production mode, the debug function unit 208 acquires trace information and records it in the ERAM 203 (step 305). The debug function unit 208 determines whether an abnormality has been detected (step 306). While no abnormality is detected, the debug function unit 208 repeats the operation of acquiring trace information and recording it in the ERAM 203. At this time, the debug function unit 208 configures a ring buffer of a predetermined size in the ERAM 203 and writes the storage information therein.

  On the other hand, when an abnormality is detected, the debug function unit 208 transfers the trace information currently existing in the ERAM 203 to the EEPROM 207 for recording. Then, the recording destination address is changed so that the trace information saved when the abnormality is repeatedly detected is not overwritten, and the normal operation described in step 305 is resumed (step 308).

  Note that the trace information recorded in the EEPROM 207 can be extracted outside using the diagnostic tool 215 which is an external device via the communication function unit 224 of the microcomputer 202.

DESCRIPTION OF SYMBOLS 101 ... Control apparatus, 102 ... Microcomputer, 103 ... ERAM, 104 ... Flash memory, 105 ... Global RAM, 106 ... Processor, 107 ... EEPROM, 108 ... Debug function part, 109 ... Debugger, 110 ... Personal computer, 111 ... System interconnect , 112 ... Flash interface, 113 ... Peripheral bus, 114 ... Peripheral function unit, 201 ... Control device, 202 ... Microcomputer, 203 ... ERAM, 204 ... Flash memory, 205 ... Global RAM, 206 ... Processor, 207 ... EEPROM, 208 ... Debug function unit 209 Debugger 210 210 Personal computer 211 System interconnect 212 Flash interface 213 Peripheral bus 214 Peripheral function unit 215 Diagnostic tools, 221 ... bus switch, 222 ... bus switch, 223 ... debugging bus, 224 ... communication function unit, 225 ... diagnostic tool

Claims (10)

An information processing apparatus that executes a predetermined control program that realizes control of a control target in the first mode, and that executes a pseudo program that simulates the operation of the control program in the second mode,
A read only memory for storing the control program;
A random access memory for holding the pseudo program in the second mode;
A processor that executes the control program of the read-only memory in a first mode, and executes the pseudo program of the random access memory in the second mode;
A debug function unit for acquiring trace information representing the operation of the processor in the first mode and recording the trace information in the random access memory; acquiring the trace information in the second mode; and outputting the trace information to an external debugging device;
An information processing apparatus.   The information processing apparatus according to claim 1, further comprising a switch that makes the random access memory accessible from the debug function unit in the first mode and accessible from the processor in the second mode.   3. The switch according to claim 2, wherein the switch switches whether the random access memory is accessible from the debug function unit or is accessible from the processor according to a value set in a register settable from the processor. Information processing device. The control program sets the register so that the random access memory can be accessed from the debug function unit,
The pseudo program sets the register so that the random access memory is accessible from the processor.
The information processing apparatus according to claim 3.   The information processing apparatus according to claim 1, wherein the debug function unit configures a ring buffer in the random access memory and records the trace information in the ring buffer in the first mode. The information processing apparatus further includes a save memory accessible from the debug function unit,
The debug function unit saves the trace information recorded in the random access memory to the save memory when a predetermined condition is satisfied,
The information processing apparatus according to claim 5.   The information processing apparatus according to claim 6, wherein the predetermined condition is occurrence of a predetermined failure.   The debug function unit manages a save destination address that is an address of the save memory for recording the trace information. When the trace information is recorded in the save memory, the debug information is not overwritten. The information processing apparatus according to claim 6, wherein the save destination address is updated.   The information processing apparatus according to claim 6, wherein the evacuation memory is capable of taking out data outside the processing of the processor.   The information processing apparatus according to claim 1, wherein the control target is an automobile.

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