JP2018121097A - Solid-state relay and electric power triac chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state relay which can increase an electrostatic discharge (ESD) resistance.SOLUTION: In an output side, there are provided a firing triac chip 2 which turns on and off according to an input signal, and an electric power triac chip 3 which turns on and off according to an on current of the firing triac chip 2. To reduce disequilibrium between repeated peak-off electric voltages in both directions in the electric power triac chip 3, a difference between a repeated peak-off electric voltage of a mode I in which one output side terminal T2 has more positive potential than the other output side terminal T1 and a repeated peak-off electric voltage of a mode III in which the one output side terminal T2 has more negative potential than the other output side terminal T1 is in a predetermined allowable range.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a solid-state relay, and more particularly, a solid-state relay in which terminals on an output side are turned on and off according to an input signal, and includes an ignition triac chip and an ignition triac chip on an output side. The present invention relates to a solid state relay including a power triac chip that is turned on and off.

  The present invention also relates to a power triac chip used to configure such a solid state relay.

  Conventionally, as this type of solid state relay, as disclosed in, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2003-274636) and Patent Document 2 (Japanese Patent Laid-Open No. 2001-7690), an input is provided on the output side. Bidirectional photothyristor chip for firing that is turned on and off according to an optical signal (hereinafter referred to as “triac chip for firing”) and power that is turned on and off according to the on-current of the firing triac chip The thing provided with the triac chip for is known.

  Although the triac chip for ignition has a small current capacity, it is turned on and off with high sensitivity according to the input optical signal. On the other hand, although the power triac chip is not turned on (triggered) at the level of the input optical signal, it is turned on / off according to the on-current of the firing triac chip, and a large current can flow.

  As a starting triac chip, for example, a lateral type (horizontal) structure in which an on-current mainly flows in the surface direction of the chip as disclosed in Patent Document 3 (Japanese Patent Laid-Open No. 2015-005704) is widely used. It is used. On the other hand, as a power triac chip, for example, one having a vertical structure in which on-current mainly flows in the thickness direction of the chip as disclosed in Patent Document 4 (Japanese Patent Laid-Open No. 2009-206193) is widely used. It has been.

JP 2003-274636 A JP 2001-7690 A JP2015-005704A JP 2009-206193 A

  Such a solid-state relay is used, for example, in a power supply circuit section of a white goods home appliance or an OA (office automation) device. In recent years, with the improvement of the market quality level of these devices, it has been demanded that solid state relays also increase ESD (Electrostatic Discharge) resistance, that is, resistance to electrostatic surges.

  Accordingly, an object of the present invention is to provide a solid state relay capable of increasing ESD tolerance.

  Another object of the present invention is to provide a power triac chip used to configure such a solid state relay.

When the present inventors analyzed by performing an electrostatic discharge test (human body model (HBM)) on a conventional solid state relay, among the starting triac chip and the power triac chip, the starting triac having a small current capacity is used. It was found that the chip was destroyed by the surge current. As a main cause, in the conventional solid state relay, as shown in Table 1 below, in the power triac chip, there is a repetitive peak-off voltage imbalance in both directions (mode I and mode III) on the output side. Can be mentioned. That is, in the power triac chip, the PN junction that determines the repetitive peak-off voltage is asymmetric with respect to the bidirectional output (mode I and mode III), and the repetitive peak-off in mode III is higher than the repetitive peak-off voltage in mode I. The voltage is high. As a result, when the direction of voltage application to the solid state relay is, for example, channel 2 for the starting triac chip and mode III for the power triac chip, the power is higher than the repetitive peak-off voltage of the starting triac chip. The repetitive peak-off voltage of the triac chip for use is high. For this reason, when an electrostatic discharge is received in the direction of the voltage application, as illustrated in FIG. 15, first, the voltage between the output side terminals of the solid state relay is changed to the repetitive peak off voltage (typical value 800 V) of the firing triac chip. ) Is reached at time t1 before the firing triac chip breaks down and current flows through the power triac chip (typically before time t2 when the output terminal voltage exceeds 1200V), It is considered that the firing triac chip is destroyed by a surge current due to electrostatic discharge (this is shown as “surge current flowing into the LT chip” in FIG. 15). As a result, the surge current flowing into the power triac chip (shown as “surge current flowing into the TC chip” in FIG. 15) is relatively small. In the electrostatic discharge test for the solid state relay, as illustrated in FIG. 14, the output terminal voltage is the repetitive peak off voltage of the solid state relay (conventionally corresponds to the repetitive peak off voltage of the starting triac chip. At the time t1 when the voltage reaches 800V, the discharge current from the capacitor of the tester flows into the solid state relay as a surge current having a steep rise (this is shown as “surge current flowing into the SSR” in FIG. 14). .) The area S in FIG. 14 corresponds to the amount of charge (this is represented by the symbol Q) charged in the capacitor of the tester. The solid state relay must receive this amount of charge Q as a surge current and consume it as heat.
(Table 1) When the rated peak off voltage rating in the product specifications is 600V

Therefore, in order to solve the above problems, the solid state relay of the present invention is
A solid-state relay that turns on and off between terminals on the output side according to the input signal.
On the output side, a triac chip for firing that is turned on and off according to an input signal, and a triac chip for power that is turned on and off according to the on-current of the firing triac chip,
In the power triac chip, in order to reduce an imbalance between the two-way repetitive peak-off voltages, one output-side terminal has a repetitive peak-off voltage in mode I in which one of the output-side terminals is more positive than the other output-side terminal; The difference between the output side terminal and the repetitive peak-off voltage of mode III in which the output side terminal is more negative than the other output side terminal is within a predetermined allowable range.

  In this specification, the “repetitive peak-off voltage” refers to the maximum value of a repetitive voltage that can be continuously applied between output terminals. This “repeated peak off voltage” is not a “rated value” defined in the product specification of the solid state relay unless otherwise specified, but refers to a value at which each solid state relay actually causes breakdown (breakdown).

  “Mode I” and “Mode III” are general names indicating the operation mode of the triac. In “Mode I” and “Mode III”, the direction of voltage application between the terminals on the output side is opposite to each other in the power triac chip.

  In the solid state relay of the present invention, in the power triac chip, in order to reduce the imbalance between the two-way repetitive peak-off voltages, one output side terminal is in a positive potential than the other output side terminal. The repetitive peak off voltage of mode III in which the one output side terminal is more negative than the other output side terminal with respect to the repetitive peak off voltage is within a predetermined allowable range. Therefore, when the repetitive peak off voltage of the starting triac chip is maintained at the conventional level or higher, the product of the solid state relay is different from the repetitive peak off voltage of the starting triac chip in both directions on the output side. The repeated peak-off voltage of the power triac chip can be lowered.

  As such, if the repetitive peak-off voltage of the power triac chip is lower than the repetitive peak-off voltage of the firing triac chip, the electrostatic discharge (ESD) is applied in any direction of voltage application. Even if it is received, as illustrated in FIG. 13, first, the power triac chip breaks down at the time t1 ′ when the voltage between the output side terminals of the solid state relay reaches the repeated peak-off voltage of the power triac chip. The power triac chip absorbs most of the surge current due to electrostatic discharge (this is shown as “surge current flowing into the TC chip” in FIG. 13). Therefore, a surge current due to electrostatic discharge (shown as “surge current flowing into the LT chip” in FIG. 13) is reduced with respect to the firing triac chip, and the firing triac chip is destroyed. It becomes difficult. As a result, ESD tolerance as a solid state relay can be increased.

In one embodiment of the solid state relay,
The power triac chip is an element that repeatedly determines the peak-off voltage,
A semiconductor substrate having one of P-type and N-type conductivity types;
A first diffusion region having the other conductivity type of P-type and N-type, which is formed by penetrating the semiconductor substrate in the thickness direction in a frame-like pattern that defines a chip size;
A second diffusion region having the other conductivity type formed in an inner region separated and surrounded by the first diffusion region on the surface side of the semiconductor substrate;
A third diffusion region having the other conductivity type, which is formed so as to partially overlap the first diffusion region over substantially the entire back surface side of the semiconductor substrate;
On the surface side of the semiconductor substrate, a channel stopper region formed between the first diffusion region and the second diffusion region and spaced apart from the first diffusion region and the second diffusion region, respectively. And
A second dimension along the surface of the semiconductor substrate between the second diffusion region and the channel stopper region defines the repetitive peak off voltage of the mode I, and the first diffusion region, the channel stopper region, A first dimension along a surface of the semiconductor substrate between the first diffusion layer and a third dimension along the thickness direction of the semiconductor substrate between the second diffusion region and the third diffusion region. III repetitive peak-off voltage is determined,
The third dimension is larger than the first dimension and the second dimension;
The first dimension is set within a range of 1.0 to 1.5 times the second dimension.

  In the solid state relay of this embodiment, the second dimension defines the mode I repetitive peak off voltage. Further, since the third dimension is larger than the first dimension and the second dimension, the first dimension determines the repetitive peak-off voltage of the mode III. Here, the first dimension is set within a range of 1.0 to 1.5 times the second dimension. As a result, the repetitive peak off voltage in mode III approaches the repetitive peak off voltage in mode I. The reason for this will be described later.

In one embodiment of the solid state relay,
The power triac chip is an element that repeatedly determines the peak-off voltage,
A semiconductor substrate having one of P-type and N-type conductivity types;
A first diffusion region having the other conductivity type of P-type and N-type, which is formed by penetrating the semiconductor substrate in the thickness direction in a frame-like pattern that defines a chip size;
A second diffusion region having the other conductivity type formed in an inner region separated and surrounded by the first diffusion region on the surface side of the semiconductor substrate;
A third diffusion region having the other conductivity type, which is formed so as to partially overlap the first diffusion region over substantially the entire back surface side of the semiconductor substrate;
On the surface side of the semiconductor substrate, a channel stopper region formed between the first diffusion region and the second diffusion region and spaced apart from the first diffusion region and the second diffusion region, respectively. And
A second dimension along the surface of the semiconductor substrate between the second diffusion region and the channel stopper region defines the repetitive peak off voltage of the mode I, and the first diffusion region, the channel stopper region, A first dimension along a surface of the semiconductor substrate between the first diffusion layer and a third dimension along the thickness direction of the semiconductor substrate between the second diffusion region and the third diffusion region. III repetitive peak-off voltage is determined,
The third dimension is smaller than the first dimension and the second dimension,
The third dimension is set in a range of 0.8 times or more and less than 1.0 times the second dimension.

  In the solid state relay of this embodiment, the second dimension defines the mode I repetitive peak off voltage. Further, since the third dimension is smaller than the first dimension and the second dimension, the third dimension determines the repetitive peak off voltage of the mode III. Here, the third dimension is set in a range of 0.8 times or more and less than 1.0 times the second dimension. As a result, the repetitive peak off voltage in mode III approaches the repetitive peak off voltage in mode I. The reason for this will be described later.

In another aspect, the power triac chip of the present invention is a power triac chip constituting the solid state relay,
In order to reduce the imbalance between the two-way repetitive peak-off voltage, the repetitive peak-off voltage of mode I in which one output side terminal is more positive than the other output-side terminal, and the one output-side terminal is the other The difference from the repetitive peak-off voltage of mode III that is a negative potential from the output side terminal is within a predetermined allowable range.

  In the power triac chip of the present invention, with respect to the repetitive peak off voltage of mode I in which one output side terminal is more positive than the other output side terminal so as to reduce the imbalance between the bidirectional repetitive peak off voltages. The mode III repetitive peak-off voltage in which the one output side terminal is at a negative potential more than the other output side terminal is within a predetermined allowable range. Therefore, when the repetitive peak off voltage of the starting triac chip is maintained at the conventional level or higher, the product of the solid state relay is different from the repetitive peak off voltage of the starting triac chip in both directions on the output side. The repeated peak-off voltage of the power triac chip can be lowered.

  If the repetitive peak-off voltage of the power triac chip is lower than the repetitive peak-off voltage of the starting triac chip, the power triac chip having the lower repetitive peak-off voltage first when receiving electrostatic discharge (ESD). Breaks down, and the power triac chip absorbs most of the surge current due to electrostatic discharge. Therefore, a surge current due to electrostatic discharge is reduced with respect to the starting triac chip, and the starting triac chip is hardly broken. As a result, ESD tolerance as a solid state relay can be increased.

  As is clear from the above, according to the solid state relay of the present invention, the ESD tolerance can be increased.

  Moreover, according to the power triac chip of the present invention, the ESD tolerance of the solid state relay in which the power triac chip is incorporated can be increased.

It is a figure which shows schematic structure of the solid state relay of one Embodiment of this invention. It is a figure which compares and shows the ESD tolerance which the solid-state relay of the conventional product and the solid-state relay of the invention showed. It is a figure which shows the schematic pattern layout of the triac chip | tip for ignition (LT chip) which comprises the said solid state relay. It is a figure which shows typically the cross section of the said LT chip. It is a figure which shows the schematic pattern layout of the electric power triac chip (TC chip) which comprises the said solid state relay. It is a figure which shows the cross section of the said TC chip | tip typically. FIGS. 7A to 7C are diagrams illustrating the repetitive peak off voltage in mode I in the TC chip. FIGS. 8A to 8C are diagrams for explaining the mode III repetitive peak-off voltage in the TC chip. It is a figure explaining the method of an electrostatic discharge (ESD) test. It is a figure which shows the relationship between the repetition peak-off voltage of the said LT chip, the repetition peak-off voltage of the said TC chip | tip, and the repetition peak-off voltage about the product of the said solid state relay. It is a figure explaining the repetitive peak off voltage of the mode III in the said TC chip | tip in case the dimension of the said TC chip | tip differs from the example of FIG. It is a figure which shows the pattern layout of the modification of the said LT chip. It is a figure which illustrates typically the surge current which flows into TC chip and LT chip in the solid state relay of the above-mentioned embodiment. It is a figure which illustrates typically the surge current which flows into a solid state relay by an electrostatic discharge test. It is a figure which illustrates typically the surge current which flows into TC chip and LT chip in the conventional solid state relay.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
(Schematic configuration of solid state relay)
FIG. 1 shows a schematic configuration of a solid state relay (generally indicated by reference numeral 10) of one embodiment.

  The solid state relay 10 includes a GaAs light emitting diode chip (hereinafter referred to as “GL chip”) 1, a lateral-type firing triac chip (hereinafter referred to as “LT chip”) 2, and a power triac chip ( (Hereinafter referred to as “TC chip”) 3. The GL chip 1 receives an electrical input signal between the anode terminal A and the cathode terminal K and emits infrared light. The LT chip 2 is connected between one terminal T2 of the TC chip 3 and the gate terminal G. The LT chip 2 is electrically separated from the GL chip 1 and is turned on / off according to an input optical signal from the GL chip 1. The TC chip 3 is turned on / off according to the on-current of the LT chip 2. As a result, the output side terminals (that is, the terminals of the TC chip 3) T1 and T2 of the solid state relay 10 are turned on (conductive) and turned off (non-conductive).

(LT chip configuration and repeated peak-off voltage)
3 shows a schematic pattern layout of the LT chip 2, and FIG. 4 shows a cross section taken along line IV-IV in FIG.

  As shown in FIGS. 3 and 4, the LT chip 2 has two P-type anode diffusion regions 12a and 12b on the surface side of the N-type silicon substrate 11, and the outside of these P-type anode diffusion regions 12a and 12b. Are provided with two P gate diffusion regions 13a and 13b extending in a symmetrical manner in the figure. N-type cathode diffusion regions 14a and 14b are provided in the two P gate diffusion regions 13a and 13b, respectively. A P-type gate resistance diffusion region 15a is provided between the left P-type anode diffusion region 12a and the P-gate diffusion region 13a in FIG. Similarly, a P-type gate resistance diffusion region 15b is provided across the P-type anode diffusion region 12b and the P-gate diffusion region 13b on the right side in FIG. Further, on the left side in FIG. 3, the P-type anode diffusion region 12a, the P-gate diffusion region 13a, the N-type cathode diffusion region 14a, and the P-type gate resistance diffusion region 15a are part of the N-type cathode diffusion region 14a (windows). In general, except for 16aw), it is covered with an Al electrode 16a. Similarly, on the right side of FIG. 3, the P-type anode diffusion region 12b, the P-gate diffusion region 13b, the N-type cathode diffusion region 14b, and the P-type gate resistance diffusion region 15b are part of the N-type cathode diffusion region 14b. Except for (window 16bw), it is generally covered with an Al electrode 16b. As can be seen from FIG. 4, the Al electrode 16a electrically connects the P-type anode diffusion region 12a and the N-type cathode diffusion region 14a. Similarly, the Al electrode 16b electrically connects the P-type anode diffusion region 12b and the N-type cathode diffusion region 14b.

  The Al electrode 16a is connected to the gate terminal G shown in FIG. 1 via the Au wire 17a as one terminal T1 ′ of the LT chip 2. The Al electrode 16b is connected to the terminal T2 shown in FIG. 1 via the Au wire 17b as the other terminal T2 ′ of the LT chip 2.

  As shown in FIGS. 3 and 4, an N-type channel stopper region 18 and an Al guard ring 19 are provided around the surface of the N-type silicon substrate 11.

  In the LT chip 2, the P-type anode diffusion region 12b, the N-type silicon substrate 11, the P-gate diffusion region 13a, and the N-type cathode diffusion region 14a constitute a photothyristor portion (PNPN structure) of the channel 1. Further, the P-type anode diffusion region 12a, the N-type silicon substrate 11, the P-gate diffusion region 13b, and the N-type cathode diffusion region 14b constitute a channel 2 photothyristor portion (PNPN structure). When an input optical signal is received in a state where a voltage is applied in the direction of channel 1 (terminal T2 'is a positive potential and terminal T1' is a negative potential), an arrow labeled "CH1" in FIGS. On-state current flows in the direction of. On the other hand, when an input optical signal is received in a state where a voltage is applied in the direction of channel 2 (terminal T1 ′ is positive potential and terminal T2 ′ is negative potential), reference numeral “CH2” is attached in FIGS. On-state current flows in the direction of the arrow.

The LT chip 2 relates to a repetitive peak off voltage (repeated peak off voltage of CH1 is represented by a symbol “V _DRM LTCH1”, and repetitive peak off voltage of CH2 is represented by a symbol “V _DRM LTCH2”). The design is substantially the same as a known ignition phototriac chip as disclosed in Japanese Patent No. 187280. Thereby, the distribution range of the repetitive peak-off voltage of the LT chip 2 is within the range of 750 to 950 V for both CH1 and CH2. The inspection regarding the repetitive peak-off voltages V _DRM LTCH1 and V _DRM LTCH2 of the LT chip 2 alone is performed on the basis of allowing 830 V or more, respectively, as shown in FIG.

(TC chip configuration and repeated peak-off voltage)
FIG. 5 shows a schematic pattern layout of the TC chip 3, and FIG. 6 schematically shows a cross section of the TC chip 3.

  As shown in FIGS. 5 and 6, the TC chip 3 is formed by penetrating the silicon substrate 30 in the thickness direction using an N-type silicon substrate 30 as a semiconductor substrate and a frame-like pattern that determines the chip size. And a P-type isolation diffusion region 31 as a first diffusion region. As can be seen from FIG. 6, the isolation diffusion region 31 includes a portion 31 a diffused from the front surface side of the silicon substrate 30 and a portion 31 b diffused from the back surface side of the silicon substrate 30. Further, as shown in FIGS. 5 and 6, the TC chip 3 includes a P-type front gate diffusion region 32 as a second diffusion region and a back gate diffusion region 33 as a third diffusion region. Yes. The P-type surface gate diffusion region 32 is formed on the surface side of the silicon substrate 30 in an inner region surrounded and separated by the isolation diffusion region 31 (particularly, the portion 31a). The back gate diffusion region 33 is formed so as to partially overlap the isolation diffusion region 31 (particularly, the portion 31 b) over substantially the entire back surface side of the silicon substrate 30. On the surface side of the silicon substrate 30, an N-type surface high concentration diffusion region 36 is provided in a substantially half region in the surface gate diffusion region 32. An N-type surface high-concentration diffusion region 35 that is separated from the N-type surface high-concentration diffusion region 36 is also provided in a partial region in the surface gate diffusion region 32. Further, an N-type back surface high concentration diffusion region 37 is provided in a substantially half of the back surface gate diffusion region 33 (a region not facing the front surface high concentration diffusion region 36) on the back surface side of the silicon substrate 30. . An annular channel formed on the surface side of the silicon substrate 30 between the isolation diffusion region 31 and the surface gate diffusion region 32 so as to be separated from the isolation diffusion region 31 and the surface gate diffusion region 32. A stopper region 38 is provided.

  A patterned Al electrode layer 41 is provided on the surface side of the silicon substrate 30. The Al electrode layer 41 includes a main electrode portion 41d disposed across the P-type surface gate diffusion region 32 and the N-type surface high concentration diffusion region 36, and a P-type surface gate diffusion region spaced apart from the main electrode portion 41d. 32 and the N-type surface high concentration diffusion region 36, the gate electrode portion 41c disposed over the channel stopper region 38, the channel stopper electrode portion 41b disposed on the channel stopper region 38, and the isolation diffusion region 31 (particularly, the portion 31a). And a guard ring portion 41a disposed thereon. On the other hand, a back electrode layer 42 made of Al, Ti, Ni, Ag alloy or Al, Mo, Pt, Ag alloy is provided on the entire back surface side of the silicon substrate 30.

  The back electrode layer 42 is connected to one terminal T2 on the output side of the solid state relay 10 by die bonding. Of the Al electrode layer 41 on the front surface side, the main electrode portion 41d is connected to the other terminal T1 on the output side of the solid state relay 10 via the Au wire 39b. The gate electrode portion 41c is connected to the gate terminal G of the solid state relay 10 via the Au wire 39a.

  With the voltage applied in the direction of mode I (terminal T2 is positive potential and terminal T1 is negative potential), the on-current from the LT chip 2 is changed from the gate terminal G to the P-type surface gate diffusion region 32, the N-type surface height. When flowing to the terminal T1 through the concentration diffusion region 36, an on-current flows from the terminal T2 toward the terminal T1 in the direction of the arrow indicated by the symbol “Mode I” in FIG. In a state where a voltage is applied in the direction of mode III (terminal T1 is positive potential and terminal T2 is negative potential), from terminal T1 to gate terminal G through P-type surface gate diffusion region 32 and N-type surface high concentration diffusion region 35. When the current is extracted as the on-current of the LT chip 2, the on-current flows from the terminal T1 toward the negative potential toward the negative potential in the direction of the arrow with the sign “Mode III” in FIG.

In the TC chip 3, the bidirectional repetitive peak off voltage (mode I repetitive peak off voltage is represented by “V _DRM TCI” and mode III repetitive peak off voltage is represented by “V _DRM TCIII”). to reduce the imbalance, the difference between the repetitive peak off-state voltage _V DRM TCIII of repetitive peak off-state voltage _V DRM TCI and mode III mode _{I | V DRM TCI-V DRM} TCIII | is, the allowable range [Delta] V (this predetermined In the example, ΔV = 60V). Next, the setting of the bidirectional repetitive peak off voltage of the TC chip 3 will be described in detail.

In this TC chip 3, the repetitive peak off voltage V _DRM TCI of mode I is the first along the surface of the silicon substrate 30 between the surface gate diffusion region 32 and the channel stopper region 38 as shown in FIG. It is determined by the two dimensions L2. The reason for this is as follows. In mode I, an applied voltage is mainly applied to the PN junction formed by the surface gate diffusion region 32 and the silicon substrate 30 (referred to as “PN junction of the surface gate diffusion region 32”). In the PN junction of the surface gate diffusion region 32, on the surface side of the silicon substrate 30, as indicated by an arrow D 1 in FIG. 7B, from the internal surface gate diffusion region 32 toward the surrounding channel stopper region 38. The depletion layer 32d tends to extend. The direction D1 in which the depletion layer 32d tends to extend is the direction in which the equipotential lines 32e1, 32e2, 32e3,... In the depletion layer 32d spread as seen in a plan view, as shown in FIG. Therefore, the depletion layer 32d is relatively easy to spread, and the electric field concentration is alleviated to some extent. However, when the applied voltage between the terminals T1 and T2 increases, a constant electric field value is reached in the depletion layer 32d, and voltage breakdown occurs. As a result, the repetitive peak off voltage V _DRM TCI of mode I is determined according to the second dimension L2.

On the other hand, in this example, the repetitive peak off voltage V _DRM TCIII of mode III is along the surface of the silicon substrate 30 between the isolation diffusion region 31 and the channel stopper region 38 as shown in FIG. It is determined by the first dimension L1.

When the third dimension L3 along the thickness direction of the silicon substrate 30 between the front surface gate diffusion region 32 and the back surface gate diffusion region 33 is smaller than the first dimension L1 and the second dimension L2 described above, Rather than the first dimension L1, the third dimension L3 defines the repetitive peak off voltage V _DRM TCIII of mode III. However, in this example, the third dimension L3 is larger than the first dimension L1 and the second dimension L2.

The reason why the repetitive peak off voltage V _DRM TCIII of mode III is determined by the first dimension L1 is as follows. In mode III, an applied voltage is mainly applied to the PN junction formed by the isolation diffusion region 31 and the silicon substrate 30 (referred to as “PN junction of the isolation diffusion region 31”) (note that the backside gate diffusion region 33). The applied voltage is also applied to the PN junction formed by the silicon substrate 30, but if the third dimension L3 is larger than the first dimension L1, the PN junction is less involved.) When the applied voltage between the terminals T1 and T2 increases, a constant electric field value is reached in the depletion layer 31d, and voltage breakdown occurs. Here, in the PN junction of the isolation diffusion region 31, on the surface side of the silicon substrate 30, as indicated by an arrow D 3 in FIG. The depletion layer 31d tends to extend toward the bottom. The direction D3 in which the depletion layer 31d tends to extend is a direction in which the equipotential lines 31e1, 31e2, 31e3,... In the depletion layer 31d gather as seen in a plan view, as shown in FIG. Therefore, the depletion layer 31d is difficult to spread and the electric field tends to concentrate. As a result, the repetitive peak off voltage V _DRM TCIII of mode III tends to be lower for the first dimension L1.

Based on this tendency, in the TC chip 3, the first dimension L1 is set within a range of 1.0 to 1.5 times the second dimension L2 (that is, 1.0 ≦ (L1 /L2)≦1.5.) Therefore, the tendency that the repetitive peak off voltage V _DRM TCIII of mode III becomes lower than the first dimension L1 is offset. As a result, the repetitive peak off voltage V _DRM TCIII of mode III approaches the repetitive peak off voltage V _DRM TCI of mode I.

Specifically, in this example, the first dimension L1 = 50 μm, the second dimension L2 = 40 μm, and the third dimension L3 = 170 μm are set. That is, the dimension ratio (L1 / L2) is set to 1.25. As a result, as shown in the following Table 2, it was possible to repeat peak off voltage _V DRM TCIII = 750V ± 30V of repetitive peak off-state voltage _V DRM TCI = 750V ± 30V, Mode III Mode I. _{V DRM TCI-V DRM TCIII |} | difference between repetitive peak off-state voltage _V DRM TCIII of repetitive peak off-state voltage _V DRM TCI and Mode III Mode I, the predetermined allowable range [Delta] V (in this example, [Delta] V = 60V) in In.
(Table 2) When the rated peak off voltage in the product specifications is 600V

As a result, when the repetitive peak-off voltages V _DRM LTCH1 and V _DRM LTCH2 of the LT chip 2 are maintained at the conventional level or higher (in this example, 830 V or higher), as a product of the solid-state relay 10, both on the output side With respect to the direction, the repetitive peak off voltages V _DRM TCI and V _DRM TCIII of the TC chip 3 can be made lower than the repetitive peak off voltages V _DRM LTCH1 and V _DRM LTCH2 of the LT chip 2, respectively. In particular, in this example, as shown in FIG. 10, the repetitive peak off voltage V _DRM TCI, V of the TC chip 3 is higher than the repetitive peak off voltage V _DRM LTCH1, V _DRM LTCH2 of the LT chip 2 with respect to the output side bidirectional. _DRM TCIII could be lowered by 50V or more.

  Therefore, regardless of the direction in which the voltage is applied in both directions on the output side, the voltage between the output side terminals of the solid state relay 10 is first set to the TC chip 3 as illustrated in FIG. TC chip 3 breaks down at the time t1 'when the peak off voltage (typical value of 750 V) is reached, and most of the surge current due to electrostatic discharge (this is shown in FIG. 13 as “surge current flowing into TC chip”). TC chip 3 absorbs. For example, as shown in FIG. 1, most of the surge current Is1 flows through the TC chip 3, and only a portion Is2 of the surge current Is flows through the LT chip 2 (FIG. 1 shows electrostatic discharge in the direction of mode III. Shows the case of discharge.) Therefore, a surge current due to electrostatic discharge with respect to the LT chip 2 (this is shown as “surge current flowing into the LT chip” in FIG. 13. The output-side terminal voltage is the repetitive peak-off voltage of the LT chip 2 (in this example, 850V), it flows at time t2 '.) Is reduced, and the LT chip 2 is not easily destroyed. As a result, the ESD tolerance as the solid state relay 10 can be increased.

(Result of electrostatic discharge test)
FIG. 2 shows a conventional solid-state relay having a repetitive peak-off voltage shown in Table 1 (represented as “conventional product”) and a solid-state relay having a repetitive peak-off voltage shown in Table 2 (represented as “invention product”). )), An electrostatic discharge test (human body model (HBM)) was conducted, and the ESD tolerance was compared. In this electrostatic discharge test, as shown in FIG. 9, a high voltage power source 900 charges a capacitor C (= 100 pF) with a DC high voltage, switches the switch 901, and passes through a resistor R (= 1.5 kΩ). The specimen X (conventional product or invention) was discharged.

The vertical axis of FIG. 2 shows a comparison of the ESD tolerance (unit: kV) shown by the conventional solid state relay and the inventive solid state relay. The horizontal axis in FIG. 2 represents the difference obtained by subtracting the repetitive peak off voltages V _DRM LTCH1 and V _DRM LTCH2 of the LT chip 2 from the repetitive peak off voltages V _DRM TCI and V _DRM TCIII of the TC chip 3 with respect to the output side bidirectional. ing. That is, the direction of mode I represents (V _DRM TCI-V _DRM LTCH1), and the direction of mode III represents (V _DRM TCIII-V _DRM LTCH2). 2 represents data when the discharge is performed in the direction of the mode I, and the ◯ mark in FIG. 2 represents the data when the discharge is performed in the direction of the mode III. As can be seen from FIG. 2, the ESD tolerance tends to increase as (V _DRM TCI-V _DRM LTCH 1) or (V _DRM TCIII-V _DRM LTCH 2) decreases in both the conventional product and the invention (FIG. 2). The relationship approximated by the straight line α in the figure). Here, the solid state relay of the _inventions, since _{(V DRM TCI-V DRM LTCH1} ) or _{(V DRM TCIII-V DRM LTCH2} ) is negative, repeating the LT chip 2 other words peak off voltage _V DRM LTCH1, _{V Since} the repetitive peak-off voltages V _DRM TCI and V _DRM TCIII of the TC chip 3 are lower than those of the _DRM LTCH 2, the ESD tolerance is high. Thus, according to the solid state relay of this invention, it has confirmed that ESD tolerance could be improved.

(Solid state relay test method)
In, for example, a pre-shipment test for a product of the solid state relay 10 (a test for inspecting whether each product satisfies the product specifications before the product is shipped), it is desirable to implement the following test method. That is, the repetitive peak off voltage of the solid state relay 10 is inspected, and the reference range from the rated value of the repetitive peak off voltage to 1.3 times the rated value (600 V or more, 780 V in this example) for each of the bidirectional outputs. Products out of the following range) are excluded, and products that are within the reference range as shown by the reference numeral “SSR” in FIG. 10 are allowed.

Here, as described above, the repetitive peak off voltages V _DRM TCI and V _DRM TCIII of the TC chip 3 are lower than the repetitive peak off voltages V _DRM LTCH1 and V _DRM LTCH2 of the LT chip 2 in both directions on the output side. The repetitive peak off voltage for the product of the solid state relay 10 substantially corresponds to the repetitive peak off voltages V _DRM TCI and V _DRM TCIII of the TC chip 3. Therefore, the product in which the repetitive peak off voltages V _DRM TCI and V _DRM TCIII of the TC chip 3 substantially exceed the upper limit (more than 1.3 times the rated value) of the reference range is excluded by the inspection. As a result, the products of the solid state relay 10 that are shipped are only those having a high ESD tolerance.

  Thereby, it can be assured that the product of the solid state relay 10 to be shipped has a high ESD tolerance.

  In addition, when the rated value of the repetitive peak off voltage in the product specification is 400 V, in a pre-shipment test for the product, a reference range from the rated value to 1.3 times the rated value (that is, 400 V or more, 520 V It is desirable to exclude products that fall outside the following range and to allow products that are within the reference range. In addition, when the rated value of the repetitive peak-off voltage in the product specification is 800V, in the pre-shipment test for the product, a reference range from the rated value to 1.3 times the rated value (that is, 800V or higher, 1040V). It is desirable to exclude products that fall outside the following range and to allow products that are within the reference range.

Second Embodiment
(Modification of TC chip)
In the above example, as shown in FIGS. 7A and 8A, in the TC chip 3, along the surface of the silicon substrate 30 between the isolation diffusion region 31 and the channel stopper region 38. More than the first dimension L1 and the second dimension L2 along the surface of the silicon substrate 30 between the front surface gate diffusion region 32 and the channel stopper region 38, between the front surface gate diffusion region 32 and the back surface gate diffusion region 33. The third dimension L3 along the thickness direction of the silicon substrate 30 is assumed to be large. Then, the range of the dimension ratio (L1 / L2) was set so as to reduce the imbalance between the bidirectional repetitive peak-off voltages V _DRM TCI and V _DRM TCIII. On the other hand, as shown in FIG. 11, when the third dimension L3 is smaller than the first dimension L1 and the second dimension L2, the repetitive peak off voltage V _DRM TCI of the mode I is the same as the second case. Although determined by the dimension L2, the repetitive peak off voltage V _DRM TCIII of mode III is determined by the third dimension L3 rather than the first dimension L1.

Therefore, when the third dimension L3 is smaller than the first dimension L1 and the second dimension L2, the third dimension L3 is set within a range of 0.8 times or more and less than 1.0 times the second dimension L2. (In other words, 0.8 ≦ (L3 / L2) <1.0 is set). As a result, the repetitive peak off voltage V _DRM TCIII of mode III approaches the repetitive peak off voltage V _DRM TCI of mode I.

The reason for this is as follows. In mode III, an applied voltage is mainly applied to the PN junction formed by the backside gate diffusion region 33 and the silicon substrate 30 (referred to as “PN junction of the backside gate diffusion region 33”). In the PN junction of the back surface gate diffusion region 33, as indicated by an arrow D3 ′ in FIG. 11, the depletion layer 33d extends as a flat surface from the back surface side of the silicon substrate 30 toward the front surface gate diffusion region 32. (The equipotential surfaces 33e1, 33e2, 33e3,... Are flat), the depletion layer 33d is more easily spread, and the electric field concentration is further relaxed. As a result, the repetitive peak off voltage V _DRM TCIII of mode III tends to be higher for the third dimension L3. Based on this tendency, in the TC chip 3, the third dimension L3 is set within a range of 0.8 times or more and less than 1.0 times the second dimension L2 (that is, 0.8 ≦ (L3 / L2) Set to <1.0). Therefore, the tendency that the repetitive peak-off voltage V _DRM TCIII of mode III becomes higher than the third dimension L3 is offset. As a result, the repetitive peak off voltage V _DRM TCIII of mode III approaches the repetitive peak off voltage V _DRM TCI of mode I.

Specifically, for example, when the first dimension L1 = 120 μm and the second dimension L2 = 120 μm, the third dimension L3 = 100 μm is set. That is, the dimension ratio (L3 / L2) = 0.83 is set. As a result, in the same manner as shown in Table 2 described above, it was possible to repeat peak off voltage _V DRM TCIII = 750V ± 30V of repetitive peak off-state voltage _V DRM TCI = 750V ± 30V, Mode III Mode I. _{V DRM TCI-V DRM TCIII |} | difference between repetitive peak off-state voltage _V DRM TCIII of repetitive peak off-state voltage _V DRM TCI and Mode III Mode I, the predetermined allowable range [Delta] V (in this example, [Delta] V = 60V) in In.

Therefore, even when the third dimension L3 is smaller than the first dimension L1 and the second dimension L2, as a product of the solid state relay 10, the repetitive peak-off voltage V of the LT chip 2 with respect to both directions on the output side. _{DRM LTCH1,} V repetitive peak OFF-state voltage _V DRM _TCI of TC chip 3 than DRM _LTCH2, it is possible to lower the _V DRM TCIII. As a result, the ESD tolerance as the solid state relay 10 can be increased.

<Third Embodiment>
(Modification of LT chip)
In the above example, as shown in FIGS. 3 and 4, the LT chip 2 has the channel 1 on-current (indicated by the arrow CH1 in the figure) and the channel 2 on-current (indicated by the arrow CH2 in the figure). )), And the same region flows alternately and intersects. However, the present invention is not limited to this. For example, as in the LT chip (indicated by reference numeral 102) shown in FIG. 12, the on-current of channel 1 (indicated by arrow CH1 in the figure) and the on-current of channel 2 ( May be of a type that flows in different regions (in this example, an upper half region and a lower half region).

  Specifically, the LT chip 102 includes a P-type anode diffusion region 112b constituting a photothyristor portion of the channel 1 and a P-gate diffusion region 113a in the upper half region of the surface of the N-type silicon substrate 111 in FIG. And an N-type cathode diffusion region 114a. Further, in the lower half region of the surface of the N-type silicon substrate 111 in FIG. 12, a P-type anode diffusion region 112a, a P-gate diffusion region 113b, and an N-type cathode diffusion region 114b constituting the photothyristor portion of the channel 2 It has. A P-type gate resistance diffusion region 115a is provided across the P-type anode diffusion region 112a and the P-gate diffusion region 113a on the left side in FIG. Similarly, a P-type gate resistance diffusion region 115b is provided between the right P-type anode diffusion region 112b and the P-gate diffusion region 113b in FIG. Further, on the left side in FIG. 12, the P-type anode diffusion region 112a, the P-gate diffusion region 113a, the N-type cathode diffusion region 114a, and the P-type gate resistance diffusion region 115a are covered with an Al electrode 116a. Similarly, on the right side in FIG. 12, the P-type anode diffusion region 112b, the P-gate diffusion region 113b, the N-type cathode diffusion region 114b, and the P-type gate resistance diffusion region 115b are covered with the Al electrode 116b. The Al electrode 116a electrically connects the P-type anode diffusion region 112a and the N-type cathode diffusion region 114a. Similarly, the Al electrode 116b electrically connects the P-type anode diffusion region 112b and the N-type cathode diffusion region 114b. 110 is an Al wiring.

The LT chip 102 has the same design as the LT chip 2 described above with respect to repeated peak-off voltage. Thereby, the distribution range of the repetitive peak-off voltage of the LT chip 102 is in the range of 750 to 950 V for both CH1 and CH2. The inspection regarding the repetitive peak-off voltages V _DRM LTCH1 and V _DRM LTCH2 of the LT chip 102 alone is performed on the basis of allowing 830 V or more in the same manner as in the LT chip 2.

  Even when the LT chip 102 is used, the ESD tolerance as the solid state relay 10 can be increased as in the case where the LT chip 2 is used.

Incidentally, Repetitive peak OFF-state voltage _V DRM TCI and mode III difference between repetitive peak off-state voltage _V DRM TCIII of mode _{I | V DRM TCI-V DRM} TCIII | tolerance ΔV for is not limited to the above-mentioned 60V As long as the yield permits, it can be set as narrow as, for example, 50V, 40V, 30V, or 20V. On the contrary, if the repetitive peak off voltage V _DRM TCI, V _DRM TCIII of the TC chip 3 can be made lower than the repetitive peak off voltage V _DRM LTCH1, V _DRM LTCH2 of the LT chip 2, the allowable range ΔV is 70V, 80V, It can be set widely such as 90V or 100V.

  In FIG. 1, the gate terminal G of the TC chip 3 is pulled out to the outside, but is not limited thereto. As the solid state relay 10, the gate terminal G may be sealed inside and may have the appearance of four terminals (two terminals on the input side and two terminals on the output side).

  The above-described embodiments are merely examples, and various modifications can be made without departing from the scope of the present invention.

1 GL chip 2,102 LT chip 3 TC chip 10 Solid state relay

Claims (4)

A solid-state relay that turns on and off between terminals on the output side according to the input signal.
On the output side, a triac chip for firing that is turned on and off according to an input signal, and a triac chip for power that is turned on and off according to the on-current of the firing triac chip,
In the power triac chip, in order to reduce an imbalance between the two-way repetitive peak-off voltages, one output-side terminal has a repetitive peak-off voltage in mode I in which one of the output-side terminals is more positive than the other output-side terminal; A solid state relay characterized in that the difference between the output side terminal and the repetitive peak-off voltage of mode III in which the output side terminal is more negative than the other output side terminal is within a predetermined allowable range. The solid state relay according to claim 1,
The power triac chip is an element that repeatedly determines the peak-off voltage,
A semiconductor substrate having one of P-type and N-type conductivity types;
A first diffusion region having the other conductivity type of P-type and N-type, which is formed by penetrating the semiconductor substrate in the thickness direction in a frame-like pattern that defines a chip size;
A second diffusion region having the other conductivity type formed in an inner region separated and surrounded by the first diffusion region on the surface side of the semiconductor substrate;
A third diffusion region having the other conductivity type, which is formed so as to partially overlap the first diffusion region over substantially the entire back surface side of the semiconductor substrate;
On the surface side of the semiconductor substrate, a channel stopper region formed between the first diffusion region and the second diffusion region and spaced apart from the first diffusion region and the second diffusion region, respectively. And
A second dimension along the surface of the semiconductor substrate between the second diffusion region and the channel stopper region defines the repetitive peak off voltage of the mode I, and the first diffusion region, the channel stopper region, A first dimension along a surface of the semiconductor substrate between the first diffusion layer and a third dimension along the thickness direction of the semiconductor substrate between the second diffusion region and the third diffusion region. III repetitive peak-off voltage is determined,
The third dimension is larger than the first dimension and the second dimension;
The solid state relay, wherein the first dimension is set within a range of 1.0 times or more and 1.5 times or less of the second dimension. The solid state relay according to claim 1,
The power triac chip is an element that repeatedly determines the peak-off voltage,
A semiconductor substrate having one of P-type and N-type conductivity types;
A first diffusion region having the other conductivity type of P-type and N-type, which is formed by penetrating the semiconductor substrate in the thickness direction in a frame-like pattern that defines a chip size;
A second diffusion region having the other conductivity type formed in an inner region separated and surrounded by the first diffusion region on the surface side of the semiconductor substrate;
A third diffusion region having the other conductivity type, which is formed so as to partially overlap the first diffusion region over substantially the entire back surface side of the semiconductor substrate;
On the surface side of the semiconductor substrate, a channel stopper region formed between the first diffusion region and the second diffusion region and spaced apart from the first diffusion region and the second diffusion region, respectively. And
A second dimension along the surface of the semiconductor substrate between the second diffusion region and the channel stopper region defines the repetitive peak off voltage of the mode I, and the first diffusion region, the channel stopper region, A first dimension along a surface of the semiconductor substrate between the first diffusion layer and a third dimension along the thickness direction of the semiconductor substrate between the second diffusion region and the third diffusion region. III repetitive peak-off voltage is determined,
The third dimension is smaller than the first dimension and the second dimension,
The solid state relay, wherein the third dimension is set in a range of 0.8 times or more and less than 1.0 times the second dimension. A power triac chip constituting the solid state relay according to any one of claims 1 to 3,
In order to reduce the imbalance between the two-way repetitive peak-off voltage, the repetitive peak-off voltage of mode I in which one output side terminal is more positive than the other output-side terminal, and the one output-side terminal is the other A power triac chip characterized in that a difference from a repetitive peak-off voltage of mode III, which has a negative potential from the output side terminal, is within a predetermined allowable range.

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