JP2018120902A - Power electronics package and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new planar packaging technology that maintains reliability at elevated operating temperatures, frequencies and voltages of SiC and other high temperature power devices.SOLUTION: An electronics package is disclosed herein that includes a glass substrate with an exterior portion surrounding an interior portion, where the interior portion has a first thickness and the exterior portion has a second thickness larger than the first thickness. An adhesive layer is formed on a lower surface of the interior portion of the glass substrate. A semiconductor device having an upper surface is coupled to the adhesive layer, the semiconductor device having at least one contact pad disposed on the upper surface thereof. A first metallization layer is coupled to an upper surface of the glass substrate and extends through a first via formed through the first thickness of the glass substrate to couple with the at least one contact pad of the semiconductor device.SELECTED DRAWING: None

Description

  Embodiments of the present invention generally relate to semiconductor device packages or electronic circuit packages, and more particularly to power electronic circuit packages that include interconnect structures formed of glass dielectric.

  The power semiconductor element is a semiconductor element used as a switch or a rectifier in a power electronic circuit such as a switching power supply. Many power semiconductor devices are used in high voltage power applications and are designed to carry large amounts of current and withstand large voltages.

  In use, a power semiconductor device is typically mounted on an external circuit through a package structure, which provides electrical connection to the external circuit, removes heat generated by the device, and removes the device from the external environment. It can also be protected. Power semiconductor elements are provided with a number of input / output (I / O) interconnections to electrically connect both sides of each semiconductor element to an external circuit. I / O connections can be provided in the form of solder balls, plated bumps, wire bond connections. In the case of a wire bond package, a wire bond is provided that connects an adhesive pad or contact pad provided on the power semiconductor element to a corresponding pad or conductive element on the next level of packaging, which can be a circuit board or lead frame. It is done. Most existing power device package structures use a combination of wire bonds and a substrate (eg, a bonded copper substrate (DBC) substrate) to provide I / O interconnects on both sides of each semiconductor device. .

  As semiconductor device packages have become increasingly smaller and provide good operating performance, packaging technology has correspondingly evolved from lead packages to planar integrated packages incorporating embedded or embedded semiconductor devices. The overall structure of a prior art planar package structure 10 incorporating an embedded power device is shown in FIG. A standard manufacturing process for the POL structure 10 typically involves placing one or more power semiconductor elements 12 on the dielectric layer 14 via an adhesive 16 that is applied to the dielectric layer using spin coating techniques. Begin to place. The POL structure 10 may also include one or more additional die packages, packaged controllers, or other electrical components such as inductors or passive components 18. The dielectric layer 14 is polyimide or other organic material such as Kapton and has a coefficient of thermal expansion of about 20 ppm / ° C. The dielectric layer 14 is provided as a prefabricated planar film or stack, or is formed as a planar layer on a frame structure (not shown).

  A metal interconnect 20 (eg, a copper interconnect) is then electroplated on the dielectric layer 14 to form a direct metal connection to the power semiconductor element 12. The metal interconnect 20 may be in the form of a thin (eg, less than 200 μm) planar interconnect structure that forms an input / output (I / O) system 22 for the power semiconductor device 12.

  The POL structure 10 also includes a copper circuit (DBC) substrate 24, which is typically formed from an inorganic ceramic substrate 26 such as alumina, for example, with upper and lower copper sheets 28, 30 being copper circuits. It is bonded to both sides via a soldering interface or brazing material layer 32. The copper sheet 28 on the upper side of the DBC substrate 24 is patterned to form a number of conductive contact regions before the DBC substrate 24 is attached to the semiconductor element 12. A conductive shim 34 is provided to electrically couple a portion of the metal interconnect 20 to the DBC substrate 24.

  During the manufacturing process of the POL structure 10, solder 36 is applied to the surfaces of the semiconductor element 12 and the shim 34. The DBC substrate 24 is then lowered onto the solder 36 so that the patterned portion of the lower copper sheet 30 is aligned with the solder 36. After the DBC substrate 24 is bonded to the semiconductor element 12 and the shim 34, an underfill technique is used to apply the polymer dielectric material 38 to the space between the adhesive layer 16 and the DBC substrate 24. Although the polymeric dielectric material 38 provides some environmental resistance to the semiconductor device 12, the semiconductor device is not hermetically sealed due to the inherent properties of the polymeric dielectric material 38 that diffuses moisture and other gases.

  Advances in semiconductor chip packaging technology are driven by the ever-increasing demand to achieve better performance, further miniaturization, and higher reliability. Such advances have led to the development of new semiconductor technologies such as silicon carbide (SiC) power devices. These new power devices can be operated to switch at high frequencies and voltages. However, these devices operate at higher temperatures compared to prior art devices, ie, temperatures in excess of 150 ° C., typically in the range of 150-250 ° C., but sometimes temperatures in excess of 300 ° C.

  As described with respect to FIG. 1, existing planar packaging techniques use polyimide and other organic materials for the various dielectric and encapsulation layers within the package structure. While these materials can provide a planar package structure, polyimides and other organic materials have a maximum temperature in the range of 150-175 ° C, which limits the temperature and limits reliability at high temperatures. Ceramic materials such as alumina can also be incorporated into the planar package structure. However, the high cost and fragile nature of these materials severely limits their properties.

  In order to fully exploit the characteristics of these new semiconductor technologies, it is desirable to provide a new planar packaging technology that maintains the high operating temperature, frequency, and voltage reliability of SiC and other high temperature power devices. . It is further desirable that such packaging techniques hermetically seal power devices and simplify current manufacturing processes.

Japanese Patent Laying-Open No. 2015-126002

  According to one aspect of the invention, an electronic circuit package includes a glass substrate having an outer portion surrounding an inner portion, the inner portion having a first thickness and the outer portion being greater than the first thickness. Having a second thickness; The electronic circuit package includes an adhesive layer formed on the lower surface of the inner portion of the glass substrate, and a semiconductor element having an upper surface bonded to the adhesive layer, the semiconductor element being at least one contact pad disposed on the upper surface. Have A first metallization layer is bonded to the top surface of the glass substrate and extends through a first via formed through a first thickness of the glass substrate to bond with at least one contact pad of the semiconductor device. doing.

  According to another aspect of the invention, a method of manufacturing an electronic circuit package includes providing a glass substrate having an inner portion surrounded by an outer portion, the outer portion having a thickness greater than the thickness of the inner portion. Including. The method also includes forming an adhesive layer on the lower surface of the inner portion of the glass substrate and bonding the upper surface of the semiconductor element to the glass substrate via the adhesive layer, the upper surface comprising at least one contact pad. And forming a first metallization layer on the glass substrate, the first metallization layer extending through at least one via formed through the thickness of the inner portion of the glass substrate. And connecting to at least one contact pad of the semiconductor element.

  According to yet another aspect of the invention, a power electronic circuit package is coupled to a substrate having a plurality of thicknesses having at least one via formed through the first thickness and a substrate having the plurality of thicknesses. A power device having a configured active surface, the active surface comprising at least one contact pad aligned with at least one via in a substrate having a plurality of thicknesses. A first metallization layer is formed on the top surface of the substrate having a plurality of thicknesses and extends through the at least one via to contact the at least one contact pad. The difference between the coefficient of thermal expansion of the multilayer substrate and the coefficient of thermal expansion of the power element is less than about 7 ppm / ° C.

  These and other advantages and features will be more readily understood from the following detailed description of preferred embodiments of the invention, presented with reference to the accompanying drawings.

  The drawings illustrate presently contemplated embodiments for carrying out the invention.

1 is a schematic cross-sectional side view of a prior art electronic circuit package incorporating a power element. FIG. 2 is a schematic cross-sectional side view of an electronic circuit package at various stages of a manufacturing / integration process, according to an embodiment of the invention. FIG. 2 is a schematic cross-sectional side view of an electronic circuit package at various stages of a manufacturing / integration process, according to an embodiment of the invention. FIG. 2 is a schematic cross-sectional side view of an electronic circuit package at various stages of a manufacturing / integration process, according to an embodiment of the invention. FIG. 2 is a schematic cross-sectional side view of an electronic circuit package at various stages of a manufacturing / integration process, according to an embodiment of the invention. FIG. 2 is a schematic cross-sectional side view of an electronic circuit package at various stages of a manufacturing / integration process, according to an embodiment of the invention. FIG. 2 is a schematic cross-sectional side view of an electronic circuit package at various stages of a manufacturing / integration process, according to an embodiment of the invention. FIG. 1 is a schematic cross-sectional side view of an electronic circuit package at various stages of a manufacturing / integration process, according to an embodiment of the invention. 2 is a schematic cross-sectional side view of an electronic circuit package at various stages of a manufacturing / integration process, according to an embodiment of the invention. FIG. FIG. 10 is a schematic top view of an electronic circuit package manufactured by the processes illustrated in FIGS. 2 to 9. 6 is a schematic cross-sectional side view of an electronic circuit package according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional side view of an electronic circuit package according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional side view of an electronic circuit package according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional side view of an electronic circuit package according to another embodiment of the present invention. FIG. FIG. 6 is a schematic cross-sectional side view of an electronic circuit package according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional side view of an electronic circuit package according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional side view of an electronic circuit package according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional side view of an electronic circuit package according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional side view of an electronic circuit package according to still another embodiment of the present invention. FIG. 6 is a schematic cross-sectional side view of an electronic circuit package according to still another embodiment of the present invention.

  An embodiment of the present invention is a method of forming an electronic circuit package including a glass substrate, wherein the thermal expansion coefficient of the glass substrate can be controlled by its composition, and the semiconductor element or the electronic circuit component compared with a conventional polymer substrate A method is provided that more closely matches the coefficient of thermal expansion. By using the disclosed glass substrate, the element or component can be made airtight or substantially airtight. The embodiments described herein also provide the ability to fully exploit the characteristics of new semiconductor technologies, such as SiC, and to switch at high frequencies at high voltages and temperatures.

  Embodiments of the present invention are directed to electronic circuit packages in which one or more semiconductor elements, dies, or chips are embedded. The semiconductor element embedded in the electronic circuit package is specifically referred to as a power element in the following embodiments of FIGS. 2 to 20, but may be replaced with other components in the electronic circuit package. It will be appreciated that embodiments of the present invention are not limited to embedding power elements in electronic circuit packages. That is, the use of power elements in the electronic circuit package embodiments described below can be provided in the electronic circuit package alone or in combination with one or more power elements, resistors, capacitors, inductors, filters It should also be understood to include other electrical components such as, or other similar elements. In addition, although the embodiments of FIGS. 2-20 are described as including two power elements and one passive element, the concepts described herein may be used alone or in combination to form a single semiconductor. It is contemplated that it can be extended to electronic circuit packages that include elements or passive elements, or electronic circuit packages that include any other number of semiconductor or passive elements.

  2-9, techniques for manufacturing an electronic circuit package 40 in accordance with an embodiment of the present invention are described. Although a cross-section of an integration process of a single electronic circuit package 40 is shown in each of FIGS. 2-9 to facilitate visualization of the integration process, those skilled in the art will recognize that multiple electronic circuit packages are It will be appreciated that it can be manufactured in a similar manner at the panel level and then individualized into individual electronic circuit package components as needed. Each of the electronic circuit packages can also include a single die, multiple dies, or a combination of one or more dies, chips, and passive components.

  The manufacture of the electronic circuit package 40 begins with the provision of a dielectric layer 42 in the form of a rigid or flexible glass substrate, the stiffness / flexibility of the substrate being based on the thickness, composition of the substrate and the method of its manufacture. Can be controlled. According to various embodiments, the dielectric layer 42 has a coefficient of thermal expansion in the range of about 3-9 ppm / ° C. As shown, the dielectric layer 42 has a non-planar geometry and a plurality of thicknesses, and the outer portion 44 of the dielectric layer 42 has a thickness greater than the thickness 48 of the inner portion 50 of the dielectric layer 42. 46. In one non-limiting embodiment, the thickness 48 is about 50 microns, although a thickness of 25 to 150 microns is recognized to be appropriate. As shown, a recess 51 is formed between the outer portion 44 and the inner portion 50 of the dielectric layer 42 as a result of the difference in thickness between the two portions 44, 50. It is contemplated that the dielectric layer 42 may be provided to have a constant thickness, according to alternative embodiments. In yet another embodiment, the dielectric layer 42 is formed by bonding two glass layers by glass frit bonding or other bonding method, with the upper layer having a thickness 48 and the lower glass layer being thick. 52.

  As shown in FIG. 3, a number of vias 54, 56, 58, 60 are formed through the inner portion 50 of the dielectric layer 42 through the thickness 48. One or more vias 62 may also be formed through the outer portion 44 of the dielectric layer 42. The vias 54, 62 can be formed, for example, by UV laser drilling or etching. Alternatively, vias 54, 62 may be formed by plasma etching, dry and wet etching techniques, other laser techniques such as CO2 and excimers, or other methods including mechanical drilling processes. In one embodiment, the vias 54, 62 are formed with sloped sides as shown in FIG. 3 to facilitate later filling and metal deposition.

  In the next step of the manufacturing process, an adhesive layer 64 is applied to the bottom surface 66 of the inner portion 50 of the dielectric layer 42 as shown in FIG. According to the illustrated embodiment, the adhesive layer 64 is applied to cover the entire bottom surface 66. In an alternative embodiment, the adhesive layer 64 can be applied to cover only selected portions of the bottom surface 66. The adhesive layer 64 may be applied using a coating technique such as spin coating or slot die coating, and may be applied by a programmable dispensing tool in the form of an ink jet printing device technique as a non-limiting example. Adhesive layer 64 is a high temperature adhesive, such as, for example, high temperature polyimide, epoxy, cyanate material, or mixtures thereof, suitable for use at temperatures having a lower limit of 150 ° C. and an upper limit of 250 ° C. It will be appreciated that other adhesives suitable for use at temperatures higher than 250 ° C., such as 300 ° C. or 400 ° C., may be implemented depending on the application.

  Referring to FIG. 5, one or more semiconductor elements 68, 70 or electronic components are bonded to the adhesive layer 64. The semiconductor elements 68, 70 may be the same thickness as shown in FIG. 5, or may be different thicknesses in alternative embodiments. In one non-limiting embodiment, the semiconductor elements 68, 70 have a thickness in the range of about 50-500 microns. The semiconductor elements 68, 70 may be generally described as “power elements” or “non-power elements”. Thus, the semiconductor elements 68, 70 can be in the form of, for example, a die, diode, MOSFET, transistor, application specific integrated circuit (ASIC), or processor. In the illustrated embodiment, the semiconductor device 68 is depicted as a diode having contact pads 72 disposed on the active surface 74. The semiconductor device 70 is depicted as a MOSFET having a source pad 76 and a gate pad 78 disposed on the active surface 80. However, the semiconductor elements 68, 70 may be provided as alternative forms of power or non-power elements, and fewer or more semiconductor elements or electronic components are included in the electronic circuit package 40. It will be appreciated that this may be done. In one embodiment, the semiconductor elements 68, 70 are formed of silicon or silicon carbide (SiC) and have a coefficient of thermal expansion in the range of about 2-3 ppm / ° C. Optionally, one or more passive elements 82 such as, for example, resistors, capacitors, or inductors may be disposed on the adhesive layer 64. After the semiconductor elements 68, 70 and the passive element (s) 82 have been placed, the adhesive layer 64 can be fully cured either thermally or by a combination of heat and radiation. Suitable radiation may include UV light and / or microwaves. In one embodiment, if a volatile material is present, a partial vacuum and / or pressure above atmospheric pressure can be used to facilitate removal of the volatile material from the adhesive during curing. When cured, any portion of the adhesive layer 64 below the via 54 does not significantly affect the structural integrity of the dielectric layer 42, such as reactive ion etching (RIE) or laser processing. Is removed.

  As shown in FIG. 6, in the next step of the manufacturing process, a lower metallization layer 84 is formed on the lower surface 86 of the outer portion 44 of the dielectric layer 42. Following the application process, a portion of the metallization layer 84 can be extended into the via 62 as shown. As shown in FIG. 7, an upper metallization layer 88 is formed on the upper surface 90 of the dielectric layer 42. Upper metallization layer 88 extends through via 54 to electrically couple with contact pads 72, 76, 78 of semiconductor elements 68, 70. Upper metallization layer 88 also extends through via 62 to electrically couple with lower metallization layer 84. Thus, the upper metallization layer 88 and the lower metallization layer 84 together form an electrical connection between the lower surface 86 and the upper surface 90 of the dielectric layer 42. In one embodiment, an optional titanium copper seed layer (not shown) is applied to the upper surface 90 and / or lower surface 86 of the dielectric layer 42 prior to depositing the upper and lower metallization layers 84, 88. Sputtered plating.

  The metallized layers 84, 88 can be formed using sputtering and plating techniques followed by a lithographic process. In one embodiment, the lower and upper metallization layers 84, 88 are formed of copper. However, it is believed that the manufacturing technique of the metallized layers 84, 88 can be extended to the use of other conductive materials or combinations of copper and fillers. In embodiments that do not include the passive element 82, the gate pad 78 of the semiconductor element 70 is an extension of the upper metallization layer 88 (not shown in FIG. 7) that is coupled to the lower metallization layer 84 through the via 62. ) Through the lower metallization layer 84.

  Referring now to FIG. 8, the first bonding layer 92 is aligned with the respective bottom surfaces 94, 96 of the semiconductor elements 68, 70 and with the via (s) 62 of the lower metallization layer 84. It is applied to the part. The first bonding layer 92 is formed of solder or other high temperature bonding material, such as intermetallic compounds formed using sintered silver or other alloy / transient liquid phase bonding techniques, with suitable materials. Examples are solders such as 92.5Pb / 5Sn / 2.5Ag or Au-Si. A second bonding layer 98 or other substantially hermetic (i.e. having a helium leakage rate of 1E-4 to 1E-6 atm cc / sec) high temperature bonding material surrounds the inner portion 50 of the dielectric layer 42. It is applied to the lower metallization layer 84 to form a path. According to various embodiments, the second bonding layer 98 may be, for example, sintered silver, a transient liquid phase bonding material, or low temperature glass, or a polymer system having low hygroscopicity and diffusion rate (eg, a liquid crystal polymer). Can be a conductive material or an electrically insulating material. When solder is used for the second bonding layer 98, the bottom surface of the outer portion of the dielectric layer 42 is metallized.

  In some embodiments, an optional finish layer (not shown) is provided on the lower metallization layer 84 prior to applying the second bonding layer 98. As a non-limiting example, a Ni—Au finish can be used when the second bonding layer 98 is solder, and a Ni—Ag finish can be used when the second bonding layer 98 is sintered silver. . In embodiments where the bottom surfaces of the semiconductor elements 68, 70 are metallized, the first and second bonding layers 92, 98 can be formed of the same material.

  Next, the conductive substrate 100 is bonded to the first and second bonding layers 92, 98 using a suitable welding or bonding process to form an electronic circuit package 40, as shown in FIG. . In the illustrated embodiment, the conductive substrate 100 includes a layer of a ceramic substrate 102, such as alumina, sandwiched between upper and lower sheets 104, 106 formed from a conductive material, such as copper. This is a multilayer substrate 100. As shown in FIG. 9, the upper sheet 104 is partially removed to create a patterned upper surface of the multilayer substrate 100. In an alternative embodiment, one or both of the first and second bonding layers 92, 98 may be initially applied to the multilayer substrate 100 rather than the lower metallization layer 84 and the semiconductor elements 68, 70. In yet another alternative embodiment, after the semiconductor elements 68, 70 are bonded to the multilayer substrate 100, the second bonding layer 98 is applied to bond the multilayer substrate 100 directly to the dielectric layer 42; Thereby, an edge seal can be created around the internal cavity 108 surrounding the semiconductor elements 68, 70 and the passive element (s) 82. In such an embodiment, the portion of the lower metallization layer 84 that is shown disposed between the dielectric layer 42 and the second bonding layer 98 is omitted as described in more detail with respect to FIG. May be. According to one embodiment, the multilayer substrate 100 is a copper circuit attached (DBC) substrate. In an alternative embodiment, the substrate 100 is a metal lead frame, such as copper, which can be molded or encapsulated.

  Although not shown in FIG. 9, an electrical connection is made between an electrical component in the electronic circuit package 40 and an external component (not shown), such as a bus bar or a printed circuit board (PCB). It is contemplated that any number of input / output (I / O) connections may be formed on the upper metallization layer 88 and / or the multilayer substrate 100 as may be obtained. Such I / O connections may be provided as non-limiting examples in the form of plated bumps, columnar bumps, copper straps, direct bonded or solder bonded Cu terminals, or wire bond connections / pads. A solder mask may be applied to partially support the I / O connection method described above.

  How the second bonding layer 98 is arranged to surround the inner portion 50 of the dielectric layer 14 and the semiconductor elements 68 and 70 and passive element (s) 82 coupled thereto. To more clearly illustrate, a top view of the electronic circuit package 40 is presented in FIG. In one embodiment, the second bonding layer 98 hermetically seals the cavity 108 that surrounds the semiconductor elements 68, 70 and the passive element (s) 82. The cavity 108 may then be filled with dry air or an inert gas such as argon or nitrogen as a non-limiting example. In an alternative embodiment, the second bonding layer 98 is applied to surround and seal a small portion of the inner portion 50 of the dielectric layer 14. For example, the passive element 82 may be disposed outside the hermetic seal of the cavity 108 or may be omitted completely.

  In embodiments where the second bonding layer 98 does not hermetically seal the cavity 108, the semiconductor elements 68, 70 and the passive element (s) 82 fill the cavity 108, for example in the form of a non-conductive material such as a polymer. Can be overcoated with an encapsulant (not shown). The encapsulant can be used, for example, in high voltage applications to prevent arcing between the semiconductor element and the metal component, or to provide rigidity and ease of handling. In another alternative embodiment, passive element (s) 82 may be disposed on top surface 110 of upper metallization layer 88.

  FIG. 10 illustrates an exemplary arrangement of upper metallization layer 88 and vias 54, 56, 58, 62 with respect to semiconductor devices 68, 70 and passive device (s) 82. As shown, the first portion 112 of the upper metallization layer 88 is disposed over the via 54 and via 56 and is therefore electrically coupled to the contact pad 72 of the semiconductor element 68 and the source pad 76 of the semiconductor element 70. The The second portion 114 of the upper metallization layer 88 is aligned with the via 56 that is electrically coupled to the gate pad 78 of the semiconductor device 70 and the via 58 of the passive device 82. Similarly, the third portion 116 of the upper metallization layer 88 forms an electrical connection between the passive element 82 and the lower metallization layer 84 through the via 60 and via 62.

  An electronic circuit subpackage that includes the dielectric layer 42, the adhesive layer 64, and one or both of the lower metallization layer 84 and the upper metallization layer 88 involves the semiconductor elements 68, 70 and the passive element (s) 82. It is contemplated that it can be manufactured as a pre-manufactured module with or without. In embodiments in which the electronic circuit subpackage is manufactured without semiconductor elements 68, 70 and passive element (s) 82, adhesive layer 64 is semi-cured that is sufficiently stable for further handling or transportation. Can be provided in a state (eg, as a B-stage material). This allows the semiconductor elements 68, 70 and passive element (s) 82 to be subsequently attached to the electronic circuit subpackage in a later processing step.

  The order and sequence of processing or method steps associated with the above-described manufacturing or integration techniques of electronic circuit package 40 may vary depending on alternative embodiments. As a non-limiting example, the adhesive layer 64 can be applied prior to forming the vias 54-62. In addition, the lower metallization layer 84 may be formed on the lower surface 86 of the dielectric layer 42 before placing the semiconductor elements 68, 70 and the passive elements 82, or before applying the adhesive layer 64.

  Optionally, an additional integrated layer 118 may be coupled to the upper metallization layer 88, as shown in FIG. In one embodiment, the integrated layer 118 is formed by applying a layer of adhesive 120 to the top surface 90 and upper metallization layer 88 of the dielectric layer 42 and then placing the upper dielectric layer 122 on the adhesive 120. However, it will be appreciated that the integrated layer 118 can be a single layer that functions as an adhesive and a film to be metallized, or two layers, an adhesive and an immobile film. The integration layer can be a polymer or glass. In the illustrated embodiment, the upper dielectric layer 122 has a thickness 123 that is uniform or substantially uniform throughout. Similar to the dielectric layer 42, the upper dielectric layer 122 is a glass substrate having a number of vias 124 formed through its thickness. In an alternative embodiment, the upper dielectric layer 122 may be a polyimide material such as Kapton. In such alternative embodiments, the upper dielectric layer 122 may be applied as a film or stack and later etched to form the vias 124.

  A metallization layer 126 is formed on the top surface 128 of the upper dielectric layer 122 and extends through the via 124 to make electrical connection with the upper metallization layer 88. Similar to the upper metallization layer 88, the metallization layer 126 may comprise a conductive material, such as copper, and may be formed using sputtering and plating techniques followed by a lithographic process. Additional redistribution layers may be formed on the redistribution layer 118 based on design specifications.

  FIG. 12 illustrates an alternative embodiment of an electronic circuit package 159 having a stacked configuration and includes an electronic circuit package sub that includes one or more semiconductor elements 132, 133, a passive element 134, and an upper dielectric substrate 136. Module 130 is coupled to electronic circuit package 40. In one embodiment, the semiconductor element 133 is a power semiconductor element having a backside connection that is electrically coupled to an upper metallization layer 88 of an optional conductive shim 135 (shown in dashed lines). The upper dielectric substrate 136 is a glass substrate configured in the same manner as described above for the dielectric layer 42 and is bonded to the elements 132, 133, 134 via the adhesive layer 138. The upper dielectric substrate 136 is provided to have one or more vias 140 extending through the inner portion 142 of the substrate 136 and one or more vias 144 extending through its outer portion 146. Similar to upper metallization layer 88 and lower metallization layer 84, upper metallization layer 148 and lower metallization layer 150 are formed on top surface 152 and bottom surface 154 of upper dielectric substrate 136, respectively.

  A bonding layer 156 electrically connects the lower metallization layer 150 of the electronic circuit package submodule 130 to the upper metallization layer 88. Similar to the first bonding layer 92, the bonding layer 156 is solder or other conductive high temperature bonding material such as, for example, sintered silver. Another bonding layer 158 extends around the outer portion 146 of the upper dielectric substrate 136 between the lower metallization layer 150 and the upper metallization layer 88 of the electronic circuit package submodule 130. According to alternative embodiments, depending on the application, one of bonding layer 158 or bonding layer 98 is hermetic. In one embodiment, the bonding layer 158 creates a hermetic or substantially hermetic seal within the cavity 160 surrounding the elements 132, 134.

  An electronic circuit package 161 according to an alternative embodiment of the present invention is illustrated in FIG. Similar to the electronic circuit package 159 of FIG. 12, the electronic circuit package 161 includes two electronic circuit package submodules 40 and 130 arranged in a stacked configuration. Other common parts between the electronic circuit package 161 and the electronic circuit package 159 are suitably illustrated with respect to the same reference numbers. In the embodiment of FIG. 13, the upper dielectric substrate 136 includes a central post 137 that extends downward into the cavity 160. A portion of the lower metallization layer 150 is formed on the bottom surface 139 of the central post 137. A via 141 extends through the thickness of the central post 137 and is metalized in a manner similar to the via 144 to electrically connect the upper metallization layer 148 to the lower metallization layer 150.

  FIG. 14 illustrates an electronic circuit package 163 according to another embodiment of the present invention that includes two electronic circuit package sub-modules 41, 131 arranged in a stacked configuration. As in the embodiment described above, components common to the electronic circuit package 163 and the electronic circuit package 159 (FIG. 12) are appropriately referred to by common reference numerals. As shown in FIG. 14, the electronic circuit package submodule 131 is inverted on the electronic circuit package submodule 41, and their upper metallization layers 88 facing each other are electrically connected to each other through a bonding layer 156. Each electronic circuit package sub-module 41, 131 has a thermally conductive and conductive substrate 43, 143 coupled to the semiconductor elements 68, 70 and the upper metallization layer 88 via bonding layers 92, 98 as shown. Including. According to various embodiments, one of both conductive substrates 43, 143 can be an encapsulated metal lead frame or a multilayer substrate, such as a DBC substrate or a printed circuit board (PCB). In one non-limiting embodiment, the conductive substrate 43 is a DBC substrate and the conductive substrate 143 is a PCB. One or both of the conductive substrates 43, 143 may further include a heat sink (not shown) to facilitate cooling of the semiconductor elements 68, 70. Such an arrangement is particularly advantageous in embodiments where the semiconductor elements 68, 70 are power elements, as it allows for double-sided cooling of the electronic circuit package 163. Optionally, the electronic circuit package 163 is electrically connected to the semiconductor elements 68, 70 through the upper metallization layer 88, input / output (I / O) connections 167 (shown in phantom lines) and / or Or a downward I / O connection 169 (shown in phantom). The I / O connections 167, 169 can be configured as metal (eg, copper) leadframe connections, or other known forms of I / O connections according to alternative embodiments.

  According to various embodiments, both electronic circuit package sub-modules 41, 131 may include one or more semiconductor elements 68, 70 and one or more other circuits such as passive elements 82, as illustrated in FIG. And can be configured in a manner similar to a power module having components. In alternative embodiments, the electronic circuit package sub-modules 41, 131 can be provided with various configurations. As a non-limiting example, the electronic circuit package submodule 41 can be configured as a power module in a manner similar to that illustrated in FIG. 14, while the electronic circuit package submodule 131 can be configured as a control circuit.

  Referring now to FIG. 15, an electronic circuit package 162 according to an alternative embodiment is shown. Electronic circuit package 162 and electronic circuit package 40 (FIG. 9) share a number of common components that are discussed and illustrated as appropriate with respect to the same reference numbers. Similar to electronic circuit package 40, electronic circuit package 162 includes a dielectric layer 42 in the form of a glass substrate having an adhesive layer 64 formed on its bottom surface 66. Upper metallization layer 88 extends through vias 54, 58 to electrically connect to semiconductor elements 68, 70 that are bonded to adhesive layer 64. A portion of the upper metallization layer 88 extends through the via 62 and is electrically coupled to the lower metallization layer 84. The lower metallization layer 84 extends to the periphery of the dielectric layer 42 and is coupled to the multilayer substrate 100 via a second bonding layer 98 that can hermetically seal the cavities 108 according to various embodiments. A first bonding layer 92 couples the semiconductor elements 68, 70 and the lower metallization layer 84 to the multilayer substrate 100.

  In addition to the components common to electronic circuit package 40 (FIG. 9), electronic circuit package 162 includes a metallization layer 164 formed on bottom surface 66 of inner portion 50 of dielectric layer 42. Similar to metallization layers 84, 88, metallization layer 164 is a conductive material, such as copper, and can be formed using sputtering and plating techniques, followed by lithographic processing. A bonding material 168 mechanically and electrically couples the passive element 82 to the metallization layer 164. According to various embodiments, the bonding material 168 can be a conductive adhesive such as a polymer filled with a conductive filler such as solder, sintered silver, silver, or another conductive material that can withstand high temperatures. . In one embodiment, bonding material 168 is used to bond passive element 82 to metallization layer 164 using liquid phase bonding bonding techniques.

  FIG. 16 illustrates an electronic circuit package 170 according to another alternative embodiment. Electronic circuit package 170 is similar to FIG. 15 except that portions of via 62 and upper metallization layer 88 extending through via 62 of electronic circuit package 162 are replaced by conductive shims 172 in electronic circuit package 170. The same components as those of the electronic circuit package 162 are included. According to various embodiments, the conductive shim 172 can be copper or other conductive metal material. As shown in FIG. 16, a portion of the upper metallization layer 88 extends through the via 174 formed through the dielectric layer 42 and the thickness 48 of the adhesive layer 64 and is coupled to the conductive shim 172. A portion of the first bonding layer 92 electrically and mechanically couples the conductive shim 172 to the multilayer substrate 100.

  17 and 18 illustrate an electronic circuit package 170 according to alternative embodiments in which the height or thickness of the semiconductor elements 68, 70 are different. In the embodiment illustrated in FIG. 17, a conductive shim 171 is provided to compensate for the height difference between the semiconductor elements 68, 70 and is formed on the semiconductor element 70 with a layer of solder 93 or other conductive bonding material. Combined. In the embodiment illustrated in FIG. 18, the dielectric layer 42 is provided to have a central post 173 that extends downward into the cavity 108. The semiconductor element 70 is coupled to the bottom surface 175 of the central support column 173 with an adhesive layer 177 as in the adhesive layer 64.

  Referring now to FIG. 19, an electronic circuit package 176 is shown according to another embodiment of the present invention. Again, the electronic circuit package 176 includes a number of components similar to those described with respect to the electronic circuit package 40 (FIG. 9), and corresponding part numbers are referred to herein as appropriate. Although the passive element 82 is shown as being directly bonded to the adhesive layer 64 of FIG. 19, in an alternative embodiment, the metallization layer 164 (FIG. 15) and the bonding material 168 (FIG. 15) are coupled to the passive element. It is contemplated that 82 may be used to couple to dielectric layer 42.

  In addition to the components common to electronic circuit package 40 (FIG. 9), electronic circuit package 176 shown in FIG. 19 is a bond that directly bonds lower surface 86 of dielectric layer 42 to upper surface 180 of upper copper sheet 104 of multilayer substrate 100. Layer 178 is included. The bonding layer 178 is a high-temperature bonding material such as glass frit or a liquid crystal polymer that provides low diffusion characteristics. In one embodiment, the bonding layer 178 is applied after the semiconductor elements 68, 70 are bonded to the multilayer substrate 100 by a dispense and cure method. The bonding layer 178 can be applied to have an outer surface with a fillet, as shown in FIG.

  FIG. 20 illustrates an electronic circuit package 182 including a bonding layer 178 according to an alternative embodiment of the present invention. Parts common to the electronic circuit package 182, the electronic circuit package 170, and the electronic circuit package 40 (FIG. 9) are discussed appropriately with reference to the same part numbers. In the embodiment of FIG. 20, the lower metallization layer 84 of FIG. 9 is omitted completely. The semiconductor elements 68, 70 and the conductive shim 172 are directly bonded to the upper copper sheet 104 of the multilayer substrate 100. An airtight or substantially airtight seal is formed so as to surround the periphery of the cavity 108 by applying a bonding layer 178 between the lower surface 86 of the dielectric layer 42 and the upper copper sheet 104. As shown, the bonding layer 178 can be formed to have an outer surface with a fillet. In this embodiment, the need for a metallization layer similar to the lower metallization layer 84 (FIG. 9) on the lower surface 86 of the dielectric layer 42 by using the conductive shim 172 and the first bonding layer 92 together. Is reduced.

  Accordingly, embodiments of the present invention provide a dielectric provided in the form of a glass substrate having a coefficient of thermal expansion that substantially matches the coefficient of thermal expansion of SiC or other high temperature semiconductor element (s) contained within the electronic circuit package. An electronic circuit package having a body layer is included. The nearly identical thermal expansion coefficient minimizes thermal stresses in the electronic circuit package, and the reliability of the package, as well as SiC and other semiconductor elements operating at high frequencies, voltages, and temperatures in the electronic circuit package. Properties that are particularly desirable when incorporated are improved. The use of a glass substrate facilitates the manufacture of electronic circuit packages with high power density.

  In addition, in embodiments where the glass substrate is provided as a substrate having a plurality of thicknesses, one or more semiconductor elements and other electronic components are hermetically sealed within a cavity formed between the glass substrate and the multilayer substrate. Can be done. Such an airtight environment extends the high temperature reliability of SiC or other high temperature semiconductor devices and the adhesive used to attach the devices to the glass substrate. The ability to provide a hermetic seal reduces the need to provide an encapsulant or other underfill material surrounding the semiconductor element, thereby reducing material and processing costs. Embodiments incorporating glass substrates having multiple thicknesses also provide through interconnects in the form of metallized vias through the thicker portions of the glass substrate, thereby replacing the conductive shims and reducing manufacturing steps. .

  Thus, according to one embodiment of the present invention, an electronic circuit package includes a glass substrate having an outer portion surrounding an inner portion, the inner portion having a first thickness and the outer portion having a first thickness. A second thickness greater than the second thickness. The electronic circuit package includes an adhesive layer formed on the lower surface of the inner portion of the glass substrate, and a semiconductor element having an upper surface bonded to the adhesive layer, the semiconductor element being at least one contact pad disposed on the upper surface. Have A first metallization layer is bonded to the top surface of the glass substrate and extends through a first via formed through a first thickness of the glass substrate to bond with at least one contact pad of the semiconductor device. doing.

  According to another embodiment of the present invention, a method of manufacturing an electronic circuit package includes providing a glass substrate having an inner portion surrounded by an outer portion, the outer portion having a thickness greater than the thickness of the inner portion. Including. The method also includes forming an adhesive layer on the lower surface of the inner portion of the glass substrate and bonding the upper surface of the semiconductor element to the glass substrate via the adhesive layer, the upper surface comprising at least one contact pad. And forming a first metallization layer on the glass substrate, the first metallization layer extending through at least one via formed through the thickness of the inner portion of the glass substrate. And connecting to at least one contact pad of the semiconductor element.

  According to yet another embodiment of the present invention, a power electronic circuit package includes: a substrate having a plurality of thicknesses having at least one via formed through a first thickness; and a substrate having a plurality of thicknesses. A power device having a coupled active surface, the active surface comprising at least one contact pad aligned with at least one via in a substrate having a plurality of thicknesses. . A first metallization layer is formed on the top surface of the substrate having a plurality of thicknesses and extends through the at least one via to contact the at least one contact pad. The difference between the coefficient of thermal expansion of the multilayer substrate and the coefficient of thermal expansion of the power element is less than about 7 ppm / ° C.

  Although the invention has been described in detail with respect to only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not described herein but which are commensurate with the spirit and scope of the invention. In addition, while various embodiments of the invention have been described, it is to be understood that aspects of the present disclosure may include only some of the described embodiments. Accordingly, the invention is not considered limited by the foregoing description, but is only limited by the scope of the appended claims.

DESCRIPTION OF SYMBOLS 10 Planar package structure 12,68,70,132,133 Power semiconductor element, Semiconductor element 14,42 Dielectric layer 16 Adhesive, adhesive layer 18 Passive component 20 Metal interconnection 22 Input / output (I / O) system 24 Copper Circuit board (DBC) substrate 26, 102 Inorganic ceramic substrate 28, 104 Upper copper sheet 30, 106 Lower copper sheet 32 Brazing material layer 34, 135, 171, 172 Conductive shim 36, 93 Solder 38 Polymer dielectric material 40 41, 159, 161, 162, 163, 170, 176, 182 Electronic circuit package 43, 100, 143 Conductive substrate 44, 146 Outer portion 46, 48, 52, 123 Thickness 50, 142 Inner portion 51 Recess 54, 56, 58, 60, 62, 124, 140, 141, 144, 174 Via 64, 138, 177 Adhesive layer 6, 86, 94, 96, 139, 154, 175 Bottom, bottom surface 72 Contact pad 74, 80 Active surface 76 Source pad 78 Gate pad 82, 134 Passive element 84, 150 Lower metallization layer 88, 148 Upper metallization layer 90, 110, 128, 152, 180 Upper surface 92 First bonding layer 98 Second bonding layer 108, 160 Internal cavity 112 First portion 114 Second portion 116 Third portion 118 Integration layer, redistribution layer 16 , 120 Adhesive 122 Upper dielectric layer 126, 164 Metallized layer 130, 131 Electronic circuit package sub-module 136 Upper dielectric substrate 137, 173 Center post 156, 158, 178 Bonding layer 167, 169 Input / output (I / O ) Connection 168 Joining material

Claims (20)

An electronic circuit package (40),
A glass substrate (42) having an outer portion (44) surrounding an inner portion (50), said inner portion (50) having a first thickness (48), said outer portion (44) being A glass substrate (42) having a second thickness (46) greater than the first thickness (48);
An adhesive layer (64) formed on the lower surface (66) of the inner portion (50) of the glass substrate (42);
A semiconductor element (68) having an upper surface coupled to the adhesive layer (64), the semiconductor element (68) having at least one contact pad (72) disposed on the upper surface;
A first metallization layer (88) bonded to an upper surface (90) of the glass substrate (42), the first metallization layer (88) formed through the first thickness (48) of the glass substrate (42). A first metallization layer (88) extending through the via (54) of the semiconductor element and coupled to the at least one contact pad (72) of the semiconductor device (68);
An electronic circuit package (40) comprising:   The electronic circuit package (40) according to claim 1, wherein a difference between a coefficient of thermal expansion of the glass substrate (42) and a coefficient of thermal expansion of the semiconductor element (68) is 7 ppm / ° C or less.   The electronic circuit package (40) of claim 1, wherein the semiconductor element (68) comprises a power element. A second metallization layer (84) bonded to the lower surface (86) of the outer portion (44) of the glass substrate (42);
The first metallization layer (88) and the second metallization layer (84) are formed in a second via (62) formed through the second thickness (46) of the glass substrate (42). The electronic circuit package (40) of claim 1, wherein the electronic circuit package (40) is electrically connected within. A passive element (82) coupled to the adhesive layer (64);
The electronic circuit package (40) of claim 4, wherein the passive element (82) is electrically connected to the first metallization layer (88).   The conductive shim (135) of claim 1, further comprising a conductive shim (135) disposed adjacent to a bottom surface (66) of the glass substrate (42) and electrically coupled to the first metallization layer (88). Electronic circuit package (40). A conductive substrate (100) coupled to the bottom surface (94) of the semiconductor element (68);
A second bonding layer (98) disposed between the conductive substrate (100) and the outer portion (44) of the glass substrate (42), the inner portion of the glass substrate (42); A second bonding layer (98) surrounding at least a small portion of (50);
The electronic circuit package (40) of claim 1, further comprising:   The electronic circuit package of claim 7, wherein the second bonding layer (98) comprises a material that hermetically seals the semiconductor element (68) within an internal cavity (108) of the electronic circuit package (40). (40).   The electronic circuit package (40) of claim 7, wherein the second bonding layer (98) is directly coupled to the lower surface (86) of the outer portion (44) of the glass substrate (42).   The electronic circuit package of claim 7, further comprising an encapsulant that fills a cavity (108) disposed between the glass substrate (42) and the conductive substrate (100) and surrounds the semiconductor element (68). (40). A method of manufacturing an electronic circuit package (40) comprising:
Providing a glass substrate (42) having an inner portion (50) surrounded by an outer portion (44), wherein the outer portion (44) is less than a thickness (48) of the inner portion (50); Having a greater thickness (46),
Forming an adhesive layer (64) on the lower surface (66) of the inner portion (50) of the glass substrate (42);
Bonding the upper surface of a semiconductor element (68) to the glass substrate (42) via the adhesive layer (64), the upper surface comprising at least one contact pad (72);
Forming a first metallization layer (88) on the glass substrate (42), the first metallization layer (88) being the inner portion (50) of the glass substrate (42); Extending through at least one via (54) formed through the thickness (48) of the semiconductor element (68) and connecting to the at least one contact pad (72) of the semiconductor element (68);
A method of manufacturing an electronic circuit package (40), comprising: Bonding the bottom surface (94) of the semiconductor element (68) to the conductive substrate (100) using the first bonding layer (92), wherein the conductive substrate (100) is the conductive substrate. Comprising a ceramic layer (102) having a metal structure applied to (100);
Bonding the outer portion (44) of the glass substrate (42) to the conductive substrate (100) using a second bonding layer (98);
The method of claim 11, further comprising:   13. The method of claim 12, further comprising directly bonding a lower surface (86) of the outer portion (44) of the glass substrate (42) to the conductive substrate (100) using glass frit or liquid crystal polymer adhesion. the method of.   The method of claim 11, further comprising forming a second metallization layer (84) on a lower surface (86) of the outer portion (44) of the glass substrate (42).   The first metallization layer (88) passes through the via (62) extending through the thickness (46) of the outer portion (44) of the glass substrate (42) to the second metallization layer (84). 15. The method of claim 14, further comprising electrically coupling to. Bonding a passive element (82) to the glass substrate (42) via the adhesive layer (64);
Electrically coupling the passive element (82) to the first metallization layer (88) and the second metallization layer (84);
16. The method of claim 15, further comprising: A power electronic circuit package (40) comprising:
A substrate (42) having a plurality of thicknesses having at least one via (54) formed through the first thickness (48);
A power element (68) having an active surface coupled to a substrate (42) having a plurality of thicknesses, the active surface being the at least one in the substrate (42) having the plurality of thicknesses. A power element (68) comprising at least one contact pad (72) aligned with one via (54);
A first surface formed on an upper surface (90) of the substrate (42) having the plurality of thicknesses, extends through the at least one via (54), and contacts the at least one contact pad (72). A metallization layer (88) of
The power electronic circuit package (40), wherein a difference between the thermal expansion coefficient of the multilayer substrate (42) and the thermal expansion coefficient of the power element (68) is less than about 7 ppm / ° C.   An adhesive layer (64) disposed between the substrate (42) having the plurality of thicknesses and the power element (68), wherein the adhesive layer (64) of the substrates (42) having the plurality of thicknesses. The power electronic circuit package (40) of claim 17, further comprising an adhesive layer (64) coupled to the portion having the first thickness (48). A conductive substrate (100) coupled to a portion of the plurality of substrates (42) having a second thickness (46) greater than the first thickness (48). The working element (68) is hermetically sealed in a cavity (108) formed between the substrate (42) having the plurality of thicknesses and the conductive substrate (100). A power electronic circuit package (40) as described. An electrical component (82) coupled to the plurality of thicknessed substrates (42) and the first metallization layer (88);
A second metallization layer (84) formed on the lower surface (86) of the portion having the second thickness (46) of the substrate (42) having the plurality of thicknesses;
The electrical component (82) is connected to the second metallized layer (62) through a metallized via (62) formed through the second thickness (46) of the substrate (42) having the plurality of thicknesses. A power electronic circuit package (40) according to claim 19, electrically coupled to 84).