JP2018117235A - Power-on reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power-on reset circuit capable of stably outputting a reset signal at low electric without depending upon rise characteristics of a power supply voltage.SOLUTION: A power-on reset circuit 1 includes a reference voltage source 10 and a comparator 20. The reference voltage source 10, when a power supply voltage VDD is lower than a reference voltage Vref, outputs the power supply voltage VDD, and when the power supply voltage VDD is not less than the reference voltage Vref, outputs the reference voltage Vref. The comparator 20 is configured so that a voltage output by the reference voltage source 10 is applied to an inverted input terminal, the power supply voltage VDD is applied to a non-inverted input terminal and to transit a reset signal output from an output terminal when the power supply voltage VDD is larger than the reference voltage Vref by a predetermined value.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power-on reset circuit.

  The introduction of devices that operate with a power source used in energy harvesting technologies such as solar cells is advancing. For example, a solar cell is mounted as a power source in a hand-held position detector. In this position detector, when the light applied to the solar cell is low illuminance, the output voltage of the solar cell becomes low, and the built-in detection circuit and other semiconductor devices cannot operate stably. There is a voltage domain. In addition, in this unstable voltage range, any part of the system may operate abnormally, so if the current consumption increases, the system will not start normally even if the illuminance increases. Can occur.

  Therefore, such a device is designed such that the system is in a reset state when the power supply voltage is lower than the predetermined voltage, and the reset is released when the power supply voltage reaches the predetermined voltage. As a configuration for realizing such a function, a power-on reset circuit is known. As a power-on reset circuit, a circuit based on time delay and a circuit based on voltage are generally known.

  A circuit based on a time delay (for example, Patent Document 1) supplies a pulse signal for releasing reset when the voltage rises quickly after power-on. On the other hand, circuits based on voltage (for example, Patent Documents 2 and 3) have a voltage detection circuit, and the voltage detection circuit compares the power supply voltage with a predetermined reference voltage, and the power supply voltage has reached a desired voltage. Is detected and a signal for releasing the reset is output.

JP 2008-54091 A Japanese Patent Laid-Open No. 3-48519 JP 2005-109659 A

  However, the above-described circuit based on the time delay can be used for a power supply whose voltage rises quickly after power-on, but normally supplies a pulse signal with a power supply with a slow voltage rise such as a solar cell. I can't.

  Also, in the circuit based on the voltage described above, the reference voltage to be compared with the power supply voltage reaches an accurate value after the power supply voltage has increased to some extent, and is correct when the power supply voltage is excessively low. It will not be. Therefore, such a reference voltage generation circuit can be considered to generate a reference voltage by dividing the power supply voltage by resistance. In order to operate the system with as low illuminance as possible, it is necessary to suppress the current consumption of the voltage detection circuit, so the value of the voltage dividing resistor must be increased. In this case, the area occupied by the resistance element increases, and the cost of the chip on which the system is mounted increases.

  On the other hand, a method for suppressing the average current consumption of the voltage detection circuit is also conceivable. In this case, the current consumption can be suppressed by reducing the area of the resistance element by reducing the value of the voltage dividing resistor and intermittently operating the voltage detection circuit. This requires a system clock for controlling intermittent operation of the voltage detection circuit, but an accurate system clock can only be generated after reset release. Therefore, it is difficult to realize such a voltage detection circuit.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a power-on reset circuit that can stably output a reset signal with low power regardless of the rising characteristics of the power supply voltage. That is.

  The power-on reset circuit according to the first aspect of the present invention outputs the power supply voltage when the power supply voltage is lower than the reference voltage, and outputs the reference voltage when the power supply voltage is equal to or higher than the reference voltage. The reference voltage source to be applied and the voltage output from the reference voltage source to one input are applied, the power supply voltage is applied to the other input, and the power supply voltage becomes a value larger than the reference voltage by a predetermined value. And a comparator that transitions a reset signal output from the output terminal.

  A power-on reset circuit according to a second aspect of the present invention is the power-on reset circuit described above, wherein the reference voltage source includes a depletion type MOS transistor connected in series between the power supply voltage and the ground, and An enhancement-type first MOS transistor is provided, and a first node between the depletion-type MOS transistor and the first MOS transistor is connected to one input of the comparator, and the depletion-type MOS transistor The power supply voltage is applied to one end of the first MOS transistor, the other end is connected to one end of the first MOS transistor, and the other end of the first MOS transistor is preferably connected to the ground.

  A power-on reset circuit according to a third aspect of the present invention is the power-on reset circuit described above, wherein the reference voltage source includes a current source or a resistor to which a power supply voltage is applied at one end, and the current source at one end. Or a second MOS transistor connected to the other end of the resistor and the other end connected to the ground, the gates of the first and second MOS transistors, and the gate of the depletion type MOS transistor Is preferably connected to a second node between the current source or the resistor and the second MOS transistor.

  A power-on reset circuit according to a fourth aspect of the present invention is the power-on reset circuit described above, wherein the comparator includes a first input transistor to which the voltage output from the reference voltage source is applied to a gate. A second input transistor to which the power supply voltage is applied to the gate, and the same voltage is applied to the gate of the first input transistor and the gate of the second input transistor. A differential input stage in which a first current flows in the first input transistor and a second current smaller than the first current flows in the second input transistor, the power supply voltage, and the output terminal And a third MOS transistor for passing a current replicating the second current, connected between the ground and the output terminal, and having a gate connected to the second node. And a fourth MOS transistor, and when the voltage source is connected between the output terminal and the ground, and when the power supply voltage is equal to the reference voltage, the fourth MOS transistor It is desirable that the differential input stage, the third MOS transistor, and the fourth MOS transistor are designed so that the current flowing through the third MOS transistor is larger than the current flowing through the third MOS transistor.

  A power-on reset circuit according to a fifth aspect of the present invention is the power-on reset circuit described above, wherein a value obtained by dividing the current flowing through the fourth MOS transistor by the current flowing through the third MOS transistor is: It is desirable that it is 1.5 or more.

  A power-on reset circuit according to a sixth aspect of the present invention is the power-on reset circuit described above, wherein the differential input stage includes fifth and sixth MOS transistors connected at one end to the power supply voltage. A seventh MOS transistor having one end connected to the ground and a gate connected to the second node, wherein one end of the first input transistor is the other end of the fifth MOS transistor and a gate , The other end is connected to the other end of the seventh MOS transistor, the gate is connected to the first node, and one end of the second input transistor is connected to the other end of the sixth MOS transistor and The gate is connected to the gate of the third MOS transistor, the other end is connected to the other end of the seventh MOS transistor, and the power supply voltage is applied to the gate. Rukoto is desirable.

  According to the present invention, it is possible to provide a power-on reset circuit capable of stably outputting a reset signal with low power regardless of the rising characteristics of the power supply voltage.

  The above and other objects, features and advantages of the present invention will be more fully understood from the following detailed description and the accompanying drawings. The accompanying drawings are presented for purposes of illustration only and are not intended to limit the present invention.

1 is a block diagram schematically showing a configuration of a power-on reset circuit according to a first embodiment; 1 is a circuit diagram schematically showing a configuration of a power-on reset circuit according to a first embodiment; FIG. 3 is a diagram for explaining an input offset of a comparator of the power-on reset circuit according to the first embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary.

Embodiment 1
A power-on reset circuit according to the first embodiment will be described. FIG. 1 is a block diagram schematically showing the configuration of the power-on reset circuit according to the first embodiment. As illustrated in FIG. 1, the power-on reset circuit 1 according to the first embodiment includes a reference voltage source 10 and a comparator 20.

  The reference voltage source 10 is supplied with power by being connected between the power supply 2 and the ground GND. When the power supply voltage VDD is smaller than the constant reference voltage Vref to be output from the reference voltage source 10, the reference voltage source 10 outputs the power supply voltage VDD instead of the reference voltage Vref. When the power supply voltage VDD is equal to or higher than the reference voltage Vref, the reference voltage source 10 outputs a constant reference voltage Vref.

  The comparator 20 is configured as a comparator with an offset that is supplied with power by being connected between the power supply 2 and the ground GND. The voltage output from the reference voltage source 10 is input to the inverting input terminal (first input) of the comparator 20, and the power supply voltage VDD is input to the non-inverting input terminal (second input). The comparator 20 compares the value obtained by adding a predetermined input offset ΔV to the reference voltage Vref (Vref + ΔV) with the value of the power supply voltage VDD in a state where the reference voltage source 10 outputs the reference voltage Vref, and compares The voltage level of the output signal OUT, which is a reset signal, is transitioned according to the result. In this example, the comparator 20 outputs a reset signal by changing the level of the output voltage OUT from LOW to HIGH. Needless to say, the comparator 20 may output the reset release signal by changing the level of the output voltage OUT from HIGH to LOW.

  In the present embodiment, the power source 2 is, for example, a solar cell, and a power source that changes the power source voltage VDD output according to the illuminance of the irradiated light is used. However, the power source 2 is not limited to the solar cell, and various power sources such as another power source having a large voltage fluctuation or a stable power source having a small voltage fluctuation may be used.

  Hereinafter, the configuration of the power-on reset circuit 1 will be described in more detail. FIG. 2 is a circuit diagram schematically showing a configuration of the power-on reset circuit according to the first embodiment.

  The reference voltage source 10 includes a current source 11, a depletion type NMOS (N-Channel Metal-Oxide Semiconductor) transistor DN, an enhancement type NMOS transistor MN11 (also referred to as a second MOS transistor) and an MN12 (also referred to as a first MOS transistor). Called).

  The power source voltage VDD is applied to one end of the current source 11, and the other end is connected to the drain of the NMOS transistor MN11. The source of the NMOS transistor MN11 is connected to the ground GND. The power supply voltage VDD is applied to the drain of the NMOS transistor DN, and the source is connected to the drain of the NMOS transistor MN12. The source of the NMOS transistor MN12 is connected to the ground GND. The gates of the NMOS transistor DN and the NMOS transistors MN11 and MN12 are connected to a node N1 (also referred to as a second node) between the current source 11 and the NMOS transistor MN11. A node N2 (also referred to as a first node) between the source of the NMOS transistor DN and the drain of the NMOS transistor MN12 is an output node of the reference voltage source 10, that is, an output terminal, and an inverting input terminal (described later) of the comparator 20. And the gate of the NMOS transistor MN21.

  The comparator 20 includes enhancement type PMOS (P-Channel Metal-Oxide Semiconductor) transistors MP21 to MP23 and enhancement type NMOS transistors MN21 to MN24. In the comparator 20, PMOS transistors MP 21 and MP 22 and NMOS transistors MN 21 to MN 23 constitute a differential input stage 21. Further, the PMOS transistor MP23 and the NMOS transistor MN24 constitute an output stage 22 that transitions the voltage level of the output voltage OUT according to the output of the differential input stage 21.

  Hereinafter, the PMOS transistor MP23 is the third MOS transistor, the NMOS transistor MN24 is the fourth MOS transistor, the PMOS transistor MP21 is the fifth MOS transistor, the PMOS transistor MP22 is the sixth MOS transistor, and the NMOS transistor MN21 is the second MOS transistor. 1, the NMOS transistor MN22 is also referred to as a second input transistor, and the NMOS transistor MN23 is also referred to as a seventh MOS transistor.

  The differential input stage 21 will be described. A power supply voltage VDD is applied to the source of the PMOS transistor MP21. The drain of the PMOS transistor MP21 is connected to the gate of the PMOS transistor MP21 and the drain of the NMOS transistor MN21. The power supply voltage VDD is applied to the source of the PMOS transistor MP22. The drain of the PMOS transistor MP22 is connected to the gate of the PMOS transistor MP22, the drain of the NMOS transistor MN22, and the gate of the PMOS transistor MP23 in the output stage 22. The sources of the NMOS transistors MN21 and MN22 are connected to the drain of the NMOS transistor MN23. The gate of the NMOS transistor MN21 is connected to the output terminal of the reference voltage source 10, that is, the node N2. The power supply voltage VDD is applied to the gate of the NMOS transistor MN22 (that is, the non-inverting input terminal of the comparator 20). The source of the NMOS transistor MN23 is connected to the ground GND. The gate of the NMOS transistor MN23 is connected to the node N1 of the current source 11.

  The output stage 22 will be described. A power supply voltage VDD is applied to the source of the PMOS transistor MP23. The drain of the PMOS transistor MP23 is connected to the drain of the NMOS transistor MN24. The source of the NMOS transistor MN24 is connected to the ground GND. The gate of the NMOS transistor MN24 is connected to the node N1 of the current source 11.

  Here, an example in which a reference voltage source is configured using a current source has been described, but the configuration of the reference voltage source is not limited to this. For example, the reference voltage source may be configured by replacing the current source with a resistor.

  Next, the operation of the power-on reset circuit 1 according to the value of the power supply voltage VDD will be described. Here, first, the operation of the reference voltage source 10 will be described. In this configuration, when the gate voltage of the depletion type NMOS transistor DN and the NMOS transistor MN12 is small and no current flows through the NMOS transistor MN12, even if the gate voltage of the depletion type NMOS transistor DN is 0 [V], The depletion type NMOS transistor DN is turned on. As a result, the power supply voltage VDD is output to the comparator 20 from the node N2 between the depletion type NMOS transistor DN and the NMOS transistor MN12.

  Thereafter, when the power supply voltage VDD rises, the NMOS transistors MN11, MN12, MN23, and MN24 are turned on and a current flows. When the power supply voltage reaches a sufficiently large value, a constant voltage obtained by subtracting the threshold voltage of the depletion type NMOS transistor DN from the threshold voltage of the NMOS transistor MN12 is output from the node N2 as the reference voltage Vref. It becomes. That is, when the power supply voltage VDD is sufficiently high, it is possible to obtain the reference voltage Vref that is not easily affected by temperature changes.

  Next, the input offset and its operation in the comparator 20 will be described. The comparator 20 is configured as a comparator having a predetermined input offset ΔV. FIG. 3 is a diagram illustrating a current when the power supply voltage VDD is equal to the reference voltage Vref in the power-on reset circuit 1 according to the first embodiment. 3, in order to facilitate understanding of the input offset in the comparator 20, a voltage source (for example, a voltage source that outputs a voltage of VDD / 2) is output to an output terminal (that is, a terminal that outputs the output voltage OUT). Description will be made by paying attention to the current flowing through the PMOS transistor MP23 and the NMOS transistor MN24.

In FIG. 3, the gate width _{W MP22} gate width _W MP21, PMOS transistor MP22 of the PMOS transistors MP21 and "10" the gate width _{W MP23} of the PMOS transistor MP23, "25 the gate width _{W MN21} of the NMOS transistor MN21 The gate width W _MN22 of the NMOS transistor _MN22 is “5”, the gate width W _MN23 of the NMOS transistor _MN23 is “6”, and the gate width W _MN24 of the NMOS transistor _MN24 is “4”. In addition, the gate width _{W MN11} of the NMOS transistor MN11 is set to "5". Here, it is assumed that the gate lengths of the MOS transistor and the NMOS transistor MN11 in the comparator 20 are the same.

As shown in FIG. 3, the PMOS transistor MP22 and the PMOS transistor MP23 constitute a current mirror. When the current flowing through the current flowing through the PMOS transistor MP22 to _i MP22, PMOS transistors MP23 and _{i MP23,} relationship is established as shown in formula (1).

The NMOS transistor MN23 and the NMOS transistor MN24 also constitute a current mirror. When the current flowing through the current flowing through the NMOS transistor MN23 to _i MN23, NMOS transistors MN24 and _{i MN24,} relationship is established as shown in formula (2).

The NMOS transistor MN21 and the NMOS transistor MN22, which are input transistors of the comparator 20, are connected to the NMOS transistor MN23 via a source couple. Therefore, if the current flowing through the NMOS transistor MN21 is i _MN21 (also referred to as a first current) and the current flowing through the NMOS transistor MN22 is _defined as i _MN22 (also referred to as a second current), the relationship _expressed by the following formula (3) is established. To establish.

When the power supply voltage VDD is equal to the reference voltage Vref (VDD = Vref), the gate voltage of the NMOS transistor MN21 and the gate voltage of the NMOS transistor MN22 are the same, so that the current flowing through both depends on the gate width. Equation (4) is established.

In addition, since the PMOS transistor MP22 and the NMOS transistor MN22 are connected in series, the currents flowing through them are equal, and the following equation (5) is established.

ここで、ゲート幅のそれぞれに上記で説明した値を代入すると、ＰＭＯＳトランジスタＭＰ２３の電流ｉ_ＭＰ２３とＮＭＯＳトランジスタＭＮ２４の電流ｉ_ＭＮ２４との比は以下の式（７）で求められる。

式（７）で示されるように、この例では、ＮＭＯＳトランジスタＭＮ２４の電流ｉ_ＭＮ２４は、ＰＭＯＳトランジスタＭＰ２３の電流ｉ_ＭＰ２３の４倍の値をとることとなる。この場合、この電流比により生じるコンパレータ２０の入力オフセットΔＶは、約８０ｍＶとなる。換言すれば、電源電圧ＶＤＤが基準電圧Ｖｒｅｆよりも約８０ｍＶ大きくなったときに、コンパレータ２０の出力電圧ＯＵＴがＬＯＷからＨＩＧＨに遷移することとなる。結果として、コンパレータ２０は、電源電圧ＶＤＤが基準電圧Ｖｒｅｆよりも所定の入力オフセットΔＶ（この例では約８０ｍＶ）だけ大きくなったときに、リセット信号である出力電圧ＯＵＴを遷移させる。これにより、電源電圧ＶＤＤが緩やかに立ち上がるときでも、電源電圧ＶＤＤが上昇し、回路が不安定な領域を脱したときにリセット解除信号を出力することができる。 Thus, the ratio of the current _{i MN24} of the current _{i MP23} and NMOS transistors MN24 of the PMOS transistor MP23 is represented by the following equation (6).

Here, when substituting the values described above, each of the gate width, the ratio between the current _{i MN24} of the current _{i MP23} and NMOS transistors MN24 of the PMOS transistor MP23 is obtained by the following expression (7).

As shown in Expression (7), in this example, the current i _MN24 of the NMOS transistor MN24 takes a value four times the current i _MP23 of the PMOS transistor MP23. In this case, the input offset ΔV of the comparator 20 generated by this current ratio is about 80 mV. In other words, when the power supply voltage VDD becomes approximately 80 mV greater than the reference voltage Vref, the output voltage OUT of the comparator 20 transitions from LOW to HIGH. As a result, the comparator 20 transitions the output voltage OUT that is a reset signal when the power supply voltage VDD becomes larger than the reference voltage Vref by a predetermined input offset ΔV (about 80 mV in this example). Thus, even when the power supply voltage VDD rises gently, the reset release signal can be output when the power supply voltage VDD rises and the circuit leaves the unstable region.

As described above, according to the present embodiment, by appropriately designing the ratio of the current flowing through the transistors in the comparator, an input offset of the comparator is generated, and the transition condition of the output voltage OUT is set to an appropriate condition. be able to. In general, when considering the characteristic variation of the MOS transistor, it is preferable that the input offset is 20 mV or more, and the current ratio (i _MN24 / i _MP23 ) corresponding to this is preferably 1.5 or more.

  According to this configuration, for example, when the power-on reset circuit 1 and an integrated circuit are mounted in an apparatus or system, by setting the reference voltage so as to correspond to a voltage at which the integrated circuit can operate stably, After the power supply voltage reaches a sufficiently high level, the reset of the integrated circuit or the like can be released by a reset release signal given from the power-on reset circuit 1 to the integrated circuit or the like. This makes it possible to start up and operate the integrated circuit and the like in a stable state.

  Further, according to this configuration, since the resistance voltage division is not required for generating the reference voltage, the power consumption can be reduced as compared with the case where the resistance voltage division is used. In addition, as described above, since it is not necessary to intermittently operate the voltage detection circuit using the voltage dividing resistor, power consumption can be reduced without performing the intermittent operation.

  As described above, according to this configuration, it is possible to provide a power-on reset circuit that can stably output a reset signal with low power regardless of the rising characteristics of the power supply voltage.

Other Embodiments The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit of the present invention. For example, the conductivity types of the depletion-type MOS transistor and the enhancement-type MOS transistor described above can be switched as appropriate. That is, the NMOS transistor can be replaced with a PMOS transistor, and the PMOS transistor can be replaced with an NMOS transistor.

DESCRIPTION OF SYMBOLS 1 Power-on reset circuit 2 Power supply 10 Reference voltage source 11 Current source 20 Comparator 21 Differential input stage 22 Output stage DN NMOS transistor MN11, MN12, MN21-MN24 NMOS transistor MP21-MP23 PMOS transistor GND Ground N1, N2 Node OUT Output voltage VDD power supply voltage Vref reference voltage

Claims (6)

When the power supply voltage is lower than the reference voltage, the power supply voltage is output, and when the power supply voltage is equal to or higher than the reference voltage, the reference voltage source that outputs the reference voltage;
When the voltage output from the reference voltage source is applied to one input, the power supply voltage is applied to the other input, and the power supply voltage becomes a value larger than the reference voltage by a predetermined value, the output terminal A comparator that transitions a reset signal to be output,
Power-on reset circuit. The reference voltage source is
A depletion type MOS transistor and an enhancement type first MOS transistor connected in series between the power supply voltage and the ground;
A first node between the depletion type MOS transistor and the first MOS transistor is connected to one input of the comparator;
The power supply voltage is applied to one end of the depletion type MOS transistor, the other end is connected to one end of the first MOS transistor,
The other end of the first MOS transistor is connected to the ground.
The power-on reset circuit according to claim 1. The reference voltage source is
A current source or resistor to which a power supply voltage is applied at one end;
A second MOS transistor having one end connected to the other end of the current source or the resistor and the other end connected to the ground;
The gates of the first and second MOS transistors and the gate of the depletion type MOS transistor are connected to a second node between the current source or the resistor and the second MOS transistor,
The power-on reset circuit according to claim 2. The comparator is
A first input transistor to which the voltage output from the reference voltage source is applied to a gate; and a second input transistor to which the power supply voltage is applied to a gate. When the same voltage is applied to the gate and the gate of the second input transistor, a first current flows through the first input transistor, and the second input transistor has a higher current than the first current. A differential input stage through which a small second current flows;
A third MOS transistor connected between the power supply voltage and the output terminal and configured to flow a current that is a duplicate of the second current;
A fourth MOS transistor connected between the ground and the output terminal and having a gate connected to the second node;
When a voltage source is connected between the output terminal and the ground, and when the power supply voltage is equal to the reference voltage, a current flowing through the fourth MOS transistor flows through the third MOS transistor. The differential input stage, the third MOS transistor, and the fourth MOS transistor are designed to be larger than
The power-on reset circuit according to claim 3. The value obtained by dividing the current flowing through the fourth MOS transistor by the current flowing through the third MOS transistor is 1.5 or more.
The power-on reset circuit according to claim 4. The differential input stage is:
Fifth and sixth MOS transistors having one ends connected to the power supply voltage;
A seventh MOS transistor having one end connected to the ground and a gate connected to the second node;
One end of the first input transistor is connected to the other end and gate of the fifth MOS transistor, the other end is connected to the other end of the seventh MOS transistor, and a gate is connected to the first node. ,
One end of the second input transistor is connected to the other end and gate of the sixth MOS transistor and the gate of the third MOS transistor, and the other end is connected to the other end of the seventh MOS transistor. And the power supply voltage is applied to the gate,
The power-on reset circuit according to claim 4 or 5.

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