JP2018113419A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device that has a high withstanding voltage without increasing its size.SOLUTION: In a semiconductor device, a pair of main electrodes are provided on a front face of a semiconductor layer. The semiconductor layer comprises: a first well region of a first conductivity type exposed to the front face of the semiconductor layer; a cathode region of a second conductivity type surrounded by the first well region; a second well region of the second conductivity type exposed to the front face of the semiconductor layer and that is adjacent to the first well region; and an anode region of the first conductivity type surrounded by the second well region. In this semiconductor device, an overlapping part where the first well region and the second well region are overlapped with each other is provided in a direction connecting between the front face and a rear face of the semiconductor layer. In addition, in the overlapping part, the first well region and the second well region configure a super junction structure.SELECTED DRAWING: Figure 1

Description

  The present specification relates to a semiconductor device. In particular, the present specification relates to a lateral semiconductor device having a thyristor structure.

Patent Document 1 discloses a lateral semiconductor device having a thyristor structure. In the semiconductor device of Patent Document 1, the semiconductor layer includes a p-type well region exposed on the surface of the n ⁻ -type semiconductor layer, an n ⁺ -type cathode region surrounded by the p-type well region, and an n ⁻ -type semiconductor layer. And an n-type well region adjacent to the p-type well region and a p ⁺ -type anode region surrounded by the n-type well region. In the semiconductor device of Patent Document 1, the n-type well region and the p-type well region are in contact at an intermediate portion between the anode region and the cathode region. That is, the anode region side end surface of the n-type well region and the cathode region side end surface of the p-type well region are in surface contact.

JP 2014-165245 A

  In the semiconductor device of Patent Document 1, a region (n-type well region and p-type well region) existing between the anode region and the cathode region functions as a drift region of the thyristor. Therefore, in order to achieve a high breakdown voltage in the semiconductor device disclosed in Patent Document 1, it is necessary to increase the size of the drift region (distance between the anode region and the cathode region) and increase the size of the semiconductor device. The present specification discloses a technique for realizing a high breakdown voltage in a lateral semiconductor device having a thyristor structure without increasing the device size.

  The semiconductor device disclosed in this specification is a horizontal type, and a pair of main electrodes is provided on a surface of a semiconductor layer. The semiconductor layer has a first conductivity type first well region exposed on the surface of the semiconductor layer, and a second conductivity type cathode region surrounded by the first well region and connected to one of the pair of main electrodes. A second well region of the second conductivity type exposed on the surface of the semiconductor layer and adjacent to the first well region, and surrounded by the second well region and connected to the other of the pair of main electrodes An anode region of the first conductivity type may be provided. In this semiconductor device, an overlapping portion in which the first well region and the second well region overlap may be provided in a direction connecting the front surface and the back surface of the semiconductor layer. In the overlapping portion, the first well region and the second well region may constitute a super junction structure.

  In the semiconductor device described above, an overlapping portion in which the first well region and the second well region overlap in the depth direction (the direction connecting the front and back surfaces of the semiconductor layer) is provided in the drift region (the region between the anode region and the cathode region). It has been. In the overlapping portion, the first well region and the second well region form a super junction structure, and many carriers are also generated in the deep portion of the semiconductor layer by the avalanche phenomenon under the reverse bias condition. Therefore, when the semiconductor device is turned on, current flows not only on the surface of the semiconductor layer but also on the deep portion of the semiconductor layer. That is, it is possible to suppress the current from concentrating on the surface layer of the semiconductor layer. When the current is concentrated locally (surface layer) of the semiconductor layer, the semiconductor device is likely to be in a state where the voltage does not increase (negative characteristics) as the current increases. When the semiconductor device has a negative characteristic, a withstand voltage against a surge or the like decreases. In the semiconductor device, since current is suppressed from being concentrated on the surface layer of the semiconductor layer, the breakdown voltage can be improved without increasing the size of the drift region (the size of the semiconductor device).

  The impurity concentration of the first well region in the overlapping portion may be higher than the impurity concentration of other portions of the first well region. Further, the impurity concentration of the second well region in the overlapping portion may be higher than the impurity concentration of other portions of the second well region. Under the reverse bias condition, more carriers can be generated in the overlapping portion. The current concentration on the surface layer of the drift region can be further relaxed.

  In the overlapping portion, the first well region may be provided on the surface of the semiconductor layer. That is, in the overlapping portion, the second well region is not exposed to the surface layer of the semiconductor layer, and may be provided below (on the back surface side) the one well region. The distance from the cathode region provided on the surface of the semiconductor layer to the second well region can be increased, and current concentration between the cathode region and the second well region can be reduced.

  When the first well region is provided on the surface of the semiconductor layer in the overlapping portion, the first well region may appear a plurality of times in the direction connecting the front surface and the back surface of the semiconductor layer. In this case, the first well region located on the surface of the semiconductor layer among the plurality of first well regions may extend to the anode region side most. In the surface layer of the semiconductor layer through which current flows most easily, the distance between the cathode region and the second well region can be increased.

Sectional drawing of the semiconductor device of 1st Example is shown. Sectional drawing of the semiconductor device of 2nd Example is shown. The current-voltage characteristic in the semiconductor device of an Example is shown. The current-voltage characteristic in the conventional semiconductor device is shown.

(First embodiment)
The semiconductor device 100 will be described with reference to FIG. In the semiconductor device 100, a thyristor structure is formed using the semiconductor active layer 6 of the SOI substrate 8. The SOI substrate 8 includes a p-type semiconductor support layer 2, a buried insulating layer 4, and an n ⁻ -type semiconductor active layer 6. The semiconductor active layer 6 is an example of a semiconductor layer. The material of the semiconductor support layer 2 is single crystal silicon and contains boron (B) as an impurity. The semiconductor support layer 2 is grounded. The material of the buried insulating layer 4 is silicon oxide. The material of the semiconductor active layer 6 is single crystal silicon and contains phosphorus (P) as an impurity. The impurity concentration of the semiconductor active layer 6 is adjusted to approximately 1 × 10 ¹⁵ cm ⁻³ .

The semiconductor active layer 6 includes a p-type well region 14 and an n-type well region 40. The p-type well region 14 is an example of a first well region, and the n-type well region 40 is an example of a second well region. The p-type well region 14 is provided in the surface layer portion of the semiconductor active layer 6 and is exposed on the surface of the semiconductor active layer 6. The p-type well region 14 is a region formed by ion-implanting boron into the surface of the semiconductor active layer 6. A part of the semiconductor active layer 6 remains between the p-type well region 14 and the buried insulating layer 4. The impurity concentration of the p-type well region 14 is adjusted to approximately 1 × 10 ¹⁷ cm ⁻³ .

The cathode region 20 is provided at a position surrounded by the p-type well region 14. The cathode region 20 is separated from the n-type well region 40 by the p-type well region 14. The cathode region 20 is a region formed by ion implantation of phosphorus into the surface of the semiconductor active layer 6. The cathode region 20 is formed in the surface layer portion of the semiconductor active layer 6 and is exposed on the surface of the semiconductor active layer 6. A cathode electrode 18 is connected to the cathode region 20. The cathode electrode 18 is provided on the insulating film 12 and connected to the cathode region 20 through a through hole provided in the insulating film 12. The cathode electrode 18 is ohmically connected to the cathode region 20. The impurity concentration of the cathode region 20 is adjusted to 1 × 10 ¹⁹ cm ⁻³ or more.

A p-type contact region 16 is provided at a position surrounded by the p-type well region 14. A gap is provided between the p-type contact region 16 and the cathode region 20. The p-type contact region 16 is a region formed by ion-implanting boron into the surface of the semiconductor active layer 6. The p-type contact region 16 is formed in the surface layer portion of the semiconductor active layer 6 and is exposed on the surface of the semiconductor active layer 6. A cathode electrode 18 is connected to the p-type contact region 16. The cathode electrode 18 is connected to the p-type contact region 16 through a through hole provided in the insulating film 12. The cathode electrode 18 is in ohmic contact with the p-type contact region 16. That is, the cathode electrode 18 is in ohmic contact with both the cathode region 20 and the p-type contact region 16. The impurity concentration of the p-type contact region 16 is adjusted to approximately 1 × 10 ¹⁸ cm ⁻³ . The order in which the cathode region 20, the p-type contact region 16 and the p-type well region 14 are formed is arbitrary.

The n-type well region 40 is formed in the surface layer portion of the semiconductor active layer 6 and is exposed on the surface of the semiconductor active layer 6. The n-type well region 40 is a region formed by ion implantation of phosphorus into the surface of the semiconductor active layer 6. The n-type well region 40 is adjacent to the p-type well region 14. A part of the semiconductor active layer 6 remains between the n-type well region 40 and the buried insulating layer 4. The impurity concentration of the n-type well region 40 is adjusted to approximately 1.5 × 10 ¹⁷ cm ⁻³ . An overlapping portion 30 is provided at the boundary between the p-type well region 14 and the n-type well region 40. The overlapping part 30 will be described later.

An anode region 42 is provided at a position surrounded by the n-type well region 40. The anode region 42 is separated from the p-type well region 14 by the n-type well region 40. The anode region 42 is a region formed by ion-implanting boron into the surface of the semiconductor active layer 6. The anode region 42 is formed in the surface layer portion of the semiconductor active layer 6 and is exposed on the surface of the semiconductor active layer 6. An anode electrode 44 is connected to the anode region 42. The anode electrode 44 is provided on the insulating film 12 and is connected to the anode region 42 through a through-hole provided in the insulating film 12. The anode electrode 44 is ohmically connected to the anode region 42. The impurity concentration of the anode region 42 is adjusted to 5 × 10 ¹⁸ cm ⁻³ or more.

An n-type contact region 46 is provided at a position surrounded by the n-type well region 40. A gap is provided between the n-type contact region 46 and the anode region 42. The n-type contact region 46 is a region formed by ion implantation of phosphorus into the surface of the semiconductor active layer 6. The n-type contact region 46 is formed in the surface layer portion of the semiconductor active layer 6 and is exposed on the surface of the semiconductor active layer 6. An anode electrode 44 is connected to the n-type contact region 46. The anode electrode 44 is connected to the p-type contact region 16 through a through hole provided in the insulating film 12. The anode electrode 44 is in ohmic contact with the n-type contact region 46. That is, the anode electrode 44 is in ohmic contact with both the anode region 42 and the n-type contact region 46. The impurity concentration of the n-type contact region 46 is adjusted to 1 × 10 ¹⁹ cm ⁻³ or more. The order in which the anode region 42, the n-type contact region 46, and the n-type well region 40 are formed is arbitrary.

  As described above, the overlapping portion 30 is provided at the boundary portion between the p-type well region 14 and the n-type well region 40. The overlapping portion 30 includes a plurality of p-type protruding portions 14 a in which a part of the p-type well region 14 protrudes toward the n-type well region 40, and a portion of the n-type well region 40 toward the p-type well region 14. A plurality of protruding n-type protrusions 40a are formed. In the overlapping portion 30, p-type protruding portions 14 a and n-type protruding portions 40 a appear alternately in the thickness direction of the semiconductor active layer 6 (the direction connecting the front surface and the back surface of the semiconductor active layer 6). Therefore, in the overlapping portion 30, the p-type well region 14 and the n-type well region 40 overlap in the thickness direction. In the overlapping portion 30, the p-type well region 14 and the n-type well region 40 form a super junction structure.

In the overlapping portion 30, a p-type protruding portion 14 a (p-type well region 14) is provided on the surface of the semiconductor active layer 6. In other words, the p-type well region 14 protrudes toward the n-type well region 40 on the surface of the semiconductor active layer 6. The impurity concentration of the p-type protrusion 14a is adjusted to 5 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less. The impurity concentration of the p-type protrusion 14a is higher than the impurity concentration of the p-type well region 14 other than the p-type protrusion 14a. Further, in the depth direction (thickness direction) of the n-type well region 40, the impurity concentration in the depth range (range 41) where the n-type protrusion 40a is provided is the other depth range of the n-type well region 40. It is deeper than the impurity concentration. In the n-type well region 40, the impurity concentration in the depth range 41 is adjusted to 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. The n-type well region 40 is composed of a plurality of n-type impurity layers having different n-type impurity concentrations, and the n-type impurity layer having a high n-type impurity concentration of the plurality of n-type impurity layers forms the protruding portion 40a. It can also be understood as comprising.

  In the semiconductor device 100, the cathode region 20, the p-type well region 14, and the n-type well region 40 constitute an npn transistor. The anode region 42, the n-type well region 40, and the p-type well region 14 constitute a pnp transistor. A thyristor is configured by the npn transistor and the npn transistor.

  In the semiconductor device 100, when a high voltage such as a surge is applied to the wiring of the anode electrode 44, the high electric field region of the pn junction surface between the p-type well region 14 and the n-type well region 40 is broken down by the avalanche. Carriers are generated in the region, and a current flows through the p-type well region 14 and the n-type well region 40. As a result, the base potential of the npn transistor and the base potential of the pnp transistor rise, and the thyristor is turned on.

  In the semiconductor device 100, the super junction structure is configured by the p-type well region 14 (p-type protruding portion 14 a) and the n-type well region 40 (n-type protruding portion 40 a) in the overlapping portion 30. Therefore, many carriers are generated also in the deep part of the semiconductor active layer 6. For this reason, when the thyristor is turned on, the current easily flows not only in the surface layer of the semiconductor active layer 6 but also in the deep part of the semiconductor active layer 6. Suppressing current concentration in the surface layer of the semiconductor active layer 6 makes it difficult for the thyristor to have negative characteristics (that is, realizes positive characteristics) and increases the distance between the drift region (between the anode region 42 and the cathode region 20). Therefore, a high breakdown voltage (high surge breakdown voltage) can be realized.

  In the semiconductor device 100, since the super junction structure is formed in the overlapping portion 30, the impurity concentration of the p-type protruding portion 14a can be made higher than that of the p-type well region 14 other than the overlapping portion 30, and the n-type protruding portion can be formed. By making the impurity concentration of the portion 40 a higher than that of the n-type well region 40 other than the overlapping portion 30, many carriers can be generated in the drift region.

  Further, in the semiconductor device 100, since the super junction structure is formed in the overlapping portion 30, a depletion layer is formed from the junction interface between the p-type protruding portion 14a and the n-type protruding portion 40a when the semiconductor device 100 is turned off. Elongation and the overlapping part 30 can be completely depleted. A wide range of the drift region can be depleted, and the device breakdown voltage is improved.

  The advantages of the semiconductor device 100 will be further described with reference to FIGS. 3 shows current-voltage characteristics of the semiconductor device 100, and FIG. 4 shows current-voltage characteristics of the conventional semiconductor device. In the conventional semiconductor device, when the distance of the drift region is shortened, a negative characteristic phenomenon occurs in which the voltage decreases (region surrounded by the broken line 60) as the current increases, as indicated by a curve 60 in FIG. When the negative characteristic phenomenon occurs, the semiconductor device may not operate normally. Therefore, the conventional semiconductor device needs to be designed with a long distance in the drift region so that a negative characteristic phenomenon does not occur. Since the semiconductor device 100 suppresses current concentration on the surface layer of the semiconductor active layer 6, even if the length of the drift region is the same as the length at which the negative characteristic phenomenon occurs in the conventional semiconductor device, FIG. As shown in the curve 50, a positive characteristic phenomenon is obtained in which the voltage monotonously increases as the current increases. Therefore, the semiconductor device 100 can be made smaller in element size than before.

(Second embodiment)
The semiconductor device 200 will be described with reference to FIG. The semiconductor device 200 is a modification of the semiconductor device 100, and the structure of the p-type well region 214 is different from that of the p-type well region 14 of the semiconductor device 100. About the semiconductor device 200, about the same characteristic as the semiconductor device 100, description may be abbreviate | omitted by attaching the same reference number.

  In the semiconductor device 200, the p-type protrusion 214 a exposed on the surface of the semiconductor active layer 6 protrudes toward the anode region 42 with respect to the p-type protrusion 214 b provided inside the semiconductor active layer 6. That is, among the plurality of p-type protrusions (p-type protrusions 214a and 214b), the p-type protrusion 214a located on the surface of the semiconductor active layer 6 extends to the anode region 42 side most. Compared with the semiconductor device 100, the semiconductor device 200 can increase the distance between the n-type well region 40 and the cathode region 20 on the surface of the semiconductor active layer 6. As a result, the breakdown voltage of the semiconductor device 200 is higher than that of the semiconductor device 100.

In the semiconductor device 200, the impurity concentration of the p-type protrusion 214a is adjusted to approximately 8 × 10 ¹⁶ cm ⁻³ , and the impurity concentration of the p-type protrusion 214b is approximately 1.1 × 10 ¹⁷ cm ⁻³ . The impurity concentration of the p-type well region 214 other than the p-type protrusions 214a and 214b is adjusted to about 1 × 10 ¹⁷ cm ⁻³ . That is, the impurity concentration of the p-type protrusion 214b located deep in the semiconductor active layer 6 is higher than that of the p-type protrusion 214a located on the surface of the semiconductor active layer 6. More carriers are generated in the deep part of the semiconductor active layer 6, and more current flows in the deep part of the semiconductor active layer 6. A semiconductor device is realized in which the current flowing through the surface layer of the semiconductor active layer 6 is relatively reduced and the negative characteristics hardly occur.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

6: Semiconductor active layer (semiconductor layer)
8: SOI substrate 14: p-type well region (first well region)
20: Cathode region 30: Overlapping portion 40: n-type well region (second well region)
42: Anode region 100: Semiconductor device

Claims (5)

A pair of main electrodes is a semiconductor device provided on the surface of the semiconductor layer,
The semiconductor layer is
A first well region of a first conductivity type exposed on a surface of the semiconductor layer;
A cathode region of a second conductivity type surrounded by the first well region and connected to one of the pair of main electrodes;
A second well region of a second conductivity type exposed on the surface of the semiconductor layer and adjacent to the first well region;
An anode region of a first conductivity type surrounded by the second well region and connected to the other of the pair of main electrodes;
With
In the direction connecting the front surface and the back surface of the semiconductor layer, there is provided an overlapping portion where the first well region and the second well region overlap,
The semiconductor device in which the first well region and the second well region form a super junction structure in the overlapping portion.   2. The semiconductor device according to claim 1, wherein an impurity concentration of the first well region in the overlapping portion is higher than an impurity concentration of other portions of the first well region.   3. The semiconductor device according to claim 1, wherein an impurity concentration of the second well region in the overlapping portion is higher than an impurity concentration of other portions of the second well region.   4. The semiconductor device according to claim 1, wherein the first well region is provided on a surface of the semiconductor layer in the overlapping portion. 5. In the direction connecting the front surface and the back surface of the semiconductor layer, the first well region appears multiple times,
5. The semiconductor device according to claim 4, wherein among the plurality of first well regions, the first well region located on the surface of the semiconductor layer extends to the anode region side most.

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