JP2014103193A - Lateral bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To disclose a lateral bipolar transistor which can inhibit decrease in a current gain while improving a withstand voltage.SOLUTION: A lateral bipolar transistor 10 comprises: an n-type semiconductor layer 16; a p-type emitter region 40 provided on a part of a surface of the semiconductor layer 16; a p-type collector region 20 which is provided at a part of the surface of the semiconductor layer 16 and arranged at a distance from the emitter region 40; and an n-type base region 30 which is provided at a part of the surface of the semiconductor layer 16 and arranged between the emitter region 40 and the collector region 20. The emitter region 40, the collector region 20 and the base region 30 are isolated from each other by the semiconductor layer 16. The lateral bipolar transistor further comprises a p-type first buried region 50 in the semiconductor layer 16 and under the base region 30 in a depth direction from the surface of the semiconductor layer 16, in which a charge amount of the first buried region 50 is equal to a charge amount of the base region 30.

Description

  The technology disclosed in this specification relates to a lateral bipolar transistor.

For example, Patent Document 1 discloses a lateral type having a p-type collector region, a p-type emitter region, and an n ⁺ -type base region on the surface side of an n-type semiconductor layer formed on the surface of a semiconductor substrate. A pnp transistor is disclosed. In this pnp transistor, a p ⁺ -type collector second region is formed inside the semiconductor layer and below the collector region in the depth direction from the surface of the semiconductor layer. That is, in this pnp transistor, the collector region is formed up to a deep position of the semiconductor layer. Thereby, the movement distance of a carrier (hole) is shortened and suppression of the fall of a current gain is aimed at.

JP 2010-67901 A

  Incidentally, a lateral bipolar transistor having a structure in which a base region is disposed between a collector region and an emitter region is also known. In the lateral bipolar transistor having this structure, a long distance is secured between the collector region and the emitter region, so that there is an advantage that the breakdown voltage can be improved. However, since the distance between the collector region and the emitter region is long, the moving distance of carriers (holes) is also long, and the current amplification factor may be reduced.

  The present specification discloses a lateral bipolar transistor that can suppress a decrease in current gain while improving a withstand voltage.

  The lateral bipolar transistor disclosed in this specification is provided in a first conductivity type semiconductor layer, a second conductivity type emitter region provided in a part of the surface of the semiconductor layer, and in a part of the surface of the semiconductor layer. A collector region of the second conductivity type disposed at a distance from the emitter region, and a base of the first conductivity type provided on a part of the surface of the semiconductor layer and disposed between the emitter region and the collector region. And have a region. The emitter region, the collector region, and the base region are separated from each other by a semiconductor layer. A second conductivity type first buried region is further provided in the semiconductor layer and below the base region in the depth direction from the surface of the semiconductor layer. The charge amount of the first buried region is equal to the charge amount of the base region.

  In the above lateral bipolar transistor, since the base region is disposed between the collector region and the emitter region, a long distance can be secured between the collector region and the emitter region, and the breakdown voltage can be improved. In addition, a second conductivity type first buried region is provided below the first conductivity type base region in the semiconductor layer. When carriers move between the emitter and the collector, no charge and carrier coupling occurs in the first buried region, and no loss occurs. Therefore, the carrier can shorten the moving distance by the amount corresponding to the first buried region. As a result, a decrease in current gain can be suppressed. Therefore, according to the above lateral bipolar transistor, it is possible to suppress a decrease in current gain while improving a withstand voltage.

Sectional drawing of the lateral bipolar transistor of 1st Example. The figure which shows typically equipotential line distribution when the horizontal bipolar transistor of 1st Example is OFF. Sectional drawing of the lateral bipolar transistor of 2nd Example. Sectional drawing which shows the semiconductor device which formed the lateral bipolar transistor and LDMOS of 1st Example on the same semiconductor substrate.

  The main features of the embodiments described below are listed. The technical elements described below are independent technical elements and exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Absent.

(Characteristic 1) In the semiconductor layer, a second conductivity type second buried region disposed at a distance from the first buried region below the first buried region in the depth direction from the surface of the semiconductor layer. The specific region of the first conductivity type disposed between the first embedded region and the second embedded region may be further provided. The charge amount in the specific region may be equal to the charge amount in the second buried region. According to this configuration, when carriers move between the emitter and the collector, the movement distance of more carriers can be shortened by the amount corresponding to the first and second buried regions, thereby further suppressing a decrease in current gain. can do.

(First embodiment)
As shown in FIG. 1, a lateral bipolar transistor 10 of this embodiment includes a semiconductor substrate 12 mainly made of Si, a buried insulating film 14 formed on the surface side of the semiconductor substrate 12 (upper side in FIG. 1), The semiconductor layer 16 is formed on the surface side of the buried insulating film, electrodes 26, 36, and 46 provided on the surface of the semiconductor layer 16, and metal wiring. The lateral bipolar transistor 10 of the present embodiment is a pnp transistor.

  The semiconductor layer 16 is a layer mainly made of Si. The semiconductor layer 16 is n-type and has a low impurity concentration. An emitter region 40, a collector region 20, and a base region 30 are formed on part of the surface of the semiconductor layer 16. The emitter region 40, the collector region 20, and the base region 30 are separated from each other by the semiconductor layer 16. In this embodiment, the base region 30 is disposed between the emitter region 40 and the collector region 20. A first buried region 50 is formed in the semiconductor layer 16 and below the base region 30 in the depth direction from the surface of the semiconductor layer 16.

  The emitter region 40 is p-type. The emitter region 40 includes a high concentration region 42 having a high impurity concentration and a low concentration region 44 having a lower impurity concentration than the high concentration region 42. The emitter region 40 is formed in an island shape in a range exposed on the surface of the semiconductor layer 16. An emitter electrode 46 is connected to the surface of the emitter region 40.

  The collector region 20 is p-type. The collector region 20 includes a high concentration region 22 having a high impurity concentration and a low concentration region 24 having a lower impurity concentration than the high concentration region 22. The collector region 20 is also formed in an island shape in a range exposed on the surface of the semiconductor layer 16. The collector region 20 is formed at a distance from the emitter region 40. In this embodiment, since the base region 30 is disposed between the collector region 20 and the emitter region 40, a long distance is ensured between the collector region 20 and the emitter region 40. A collector electrode 26 is connected to the surface of the collector region 20.

  Base region 30 is n-type. The base region 30 includes a high concentration region 32 having a high impurity concentration and a low concentration region 34 having a lower impurity concentration than the high concentration region 32. The base region 30 is also formed in an island shape in a range exposed on the surface of the semiconductor layer 16. As described above, the base region 30 is disposed between the collector region 20 and the emitter region 40. A base electrode 36 is connected to the surface of the base region 30.

  The first embedded region 50 is n-type. The impurity concentration of the first buried region 50 is higher than the impurity concentration of the semiconductor layer 16. The charge amount of the first buried region 50 is equal to the charge amount of the base region 30 provided immediately above. That is, impurities are implanted into the first buried region 50 so that the charge amount is equal to that of the base region 30. Specifically, when the first buried region 50 is formed, the concentration and depth of the implanted impurity are adjusted so that the amount of charge is equal to that of the base region 30. As described above, the first buried region 50 is formed below the base region 30 in the depth direction from the surface of the semiconductor layer 16.

  An isolation trench 60 for isolating the lateral bipolar transistor 10 from other regions (not shown) is formed at an end portion (left end in FIG. 1) in the semiconductor layer 16. The isolation trench 60 extends downward from the surface of the semiconductor layer 16 and is formed to a depth that reaches the surface of the buried insulating film 14. In the isolation trench 60, an isolation insulating layer 62 that covers the inner wall of the isolation trench 60 is formed. A buried electrode 64 is formed inside the isolation insulating layer 62. Although not shown in FIG. 1, in this embodiment, the embedded electrode 64 is connected to the collector electrode 26. For this reason, the buried electrode 64 has the same potential as the collector electrode 26.

  Next, the operation of the lateral bipolar transistor 10 of this embodiment will be described. When a voltage (that is, a forward voltage with respect to the lateral bipolar transistor 10) that makes the emitter electrode 46 positive is applied between the emitter electrode 46 and the collector electrode 26 and a predetermined on-potential is applied to the base electrode 36, the lateral bipolar transistor 10 Turns on. That is, electrons move in the semiconductor layer 16 from the collector region 20 toward the emitter region 40, and carriers (holes) move from the emitter region 40 toward the collector region 20. As a result, a current flows from the emitter electrode 46 to the collector electrode 26. Some holes pass through the first buried region 50 when moving from the emitter region 40 toward the collector region 20. In the first buried region 50, the combination of electrons and holes does not occur and no loss occurs. For this reason, the holes move from the emitter region 40 to the collector region 20, but the substantial moving distance of some holes is shortened by the amount of the first buried region 50. As a result, it is possible to suppress a decrease in current amplification factor of the lateral bipolar transistor 10.

  When the potential applied to the base electrode 36 is switched from the on potential to the off potential, the lateral bipolar transistor 10 is turned off. In that case, a depletion layer 70 is formed between the emitter region 40 and the collector region 20 as shown in FIG. FIG. 2 shows equipotential lines 80, 82, 84, 86, 88, 90, 92, 94, 96 formed in the depletion layer 70 of the lateral bipolar transistor 10 in the off state. In the present embodiment, the charge amount of the first buried region 50 and the charge amount of the base region 30 are equal. Therefore, as shown by equipotential lines 80 to 96, the potential distribution in the depletion layer 70 formed between the emitter region 40 and the collector region 20 is in the vicinity of the base region 30 while the lateral bipolar transistor 10 is turned off. It is suppressed that it fluctuates greatly. Accordingly, the concentration of the electric field in the vicinity of the base region 30 is also suppressed.

  The structure and operation of the lateral bipolar transistor 10 of this embodiment have been described above. As described above, the lateral bipolar transistor 10 of this embodiment has the p-type first buried region 50 below the n-type base region 30 in the semiconductor layer 16. When holes move from the emitter region 40 to the collector region 20, no electron-hole coupling occurs in the first buried region 50, and no loss occurs. Therefore, the substantial moving distance of the hole can be shortened by the amount corresponding to the first buried region 50. As a result, a decrease in current gain can be suppressed. Furthermore, in the lateral bipolar transistor 10 of the present embodiment, since the base region 30 is disposed between the collector region 20 and the emitter region 40, a long distance between the collector region 20 and the emitter region 40 can be secured, The breakdown voltage can also be improved. Therefore, according to the lateral bipolar transistor 10 described above, it is possible to suppress a decrease in the current gain while improving the breakdown voltage.

(Second embodiment)
Next, with reference to FIG. 3, the lateral bipolar transistor 100 of the second embodiment will be described focusing on differences from the first embodiment. The basic configuration of the lateral bipolar transistor 100 of this embodiment is the same as that of the first embodiment. However, in this embodiment, as shown in FIG. 3, a p-type second embedded region 152 is formed below the first embedded region 150 at a distance from the first embedded region 150. An n-type specific region 160 is formed between the second embedded region 152 and the second embedded region 152.

  In the present embodiment, the second buried region 152 is formed at a position where the lower end portion reaches the surface of the buried insulating film 14. In addition, the charge amount of the specific region 160 is equal to the charge amount of the second buried region 152 immediately below. Furthermore, in this embodiment, the charge amount of the specific region 160 is equal to the charge amount of the first buried region 150.

  The lateral bipolar transistor 100 of the present embodiment can also exhibit the same operational effects as the lateral bipolar transistor 10 of the first embodiment. Furthermore, in this embodiment, as described above, the second embedded region 152 and the specific region 160 are formed below the first embedded region 150. Therefore, when the lateral bipolar transistor 100 is turned on and carriers (holes) move from the emitter region 40 toward the collector region 20, more holes move in the first and second buried regions 150 and 152. It becomes. That is, more holes can reduce the substantial moving distance by the first and second buried regions 150 and 152. Accordingly, it is possible to further suppress a decrease in current gain.

(Third embodiment)
FIG. 6 shows a semiconductor device 200 according to the third embodiment. A semiconductor device 200 shown in FIG. 6 is a semiconductor device in which a lateral bipolar transistor 10 (see FIG. 1) and an LDMOS (Laterally Diffused MOS) 210 are formed on the same substrate. The lateral bipolar transistor 10 is separated by the LDMOS 210 and the isolation trench 60. The structure of the lateral bipolar transistor 10 is the same as that of the first embodiment. Therefore, the lateral bipolar transistor 10 can exhibit the same operational effects as the first embodiment.

The LDMOS 210 has an n ⁺ type source region 220, a p type body region 230, a p ⁺ type diffusion body region 232, an n type drift region 240, and an n type drain region 250 in the semiconductor layer 16. Yes. A source electrode 222 is connected to the source region 220. A drain electrode 252 is connected to the drain region 250. A gate electrode 260 is provided opposite to the surface of the body region 230 that separates the source region 220 and the drift region 240. In this embodiment, a p-type drift region 242 is formed below the n-type drift region 240. The charge amount of the n-type drift region 240 is equal to the charge amount of the p-type drift region 242. By having the p-type drift region 242 below the n-type drift region 240, the concentration of the electric field in the vicinity of the n-type drift region 240 is suppressed when the LDMOS 210 is turned off.

  As mentioned above, although the specific example of the technique disclosed by this specification was demonstrated in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. For example, the following modifications may be adopted.

(Modification 1) In each of the above embodiments, the case where the lateral bipolar transistor 10 (100) is a pnp transistor has been described. The lateral bipolar transistor is not limited to a pnp transistor, and may be an npn transistor. Even when the lateral bipolar transistor is an npn transistor, the techniques of the above-described embodiments can be applied.

(Modification 2) In the second embodiment, the p-type first and second buried regions 150 and 152 are provided below the n-type base region 30, and the first and second buried regions 150 and 152 are provided. An n-type specific region is provided between them. However, the present invention is not limited to this, and p-type buried regions may be formed at three or more locations below the n-type base region 30. In that case, an n-type specific region may be provided between the embedded regions. The charge amount of each specific region may be equal to the charge amount of the buried region provided immediately below the specific region.

(Modification 3) In the second embodiment, the charge amount of the specific region 160 is equal to both the charge amount of the second embedded region 152 and the charge amount of the first embedded region 150. However, the charge amount of the specific region 160 may be different from the charge amount of the first embedded region 150 as long as it is equal to the charge amount of the second embedded region 152 provided immediately below the specific region 160. Also in this case, it is possible to suppress the potential distribution in the depletion layer 70 formed between the emitter region 40 and the collector region 20 from fluctuating greatly in the vicinity of the base region 30.

The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: lateral bipolar transistor 12: semiconductor substrate 14: buried insulating film 16: semiconductor layer 20: collector region 22: high concentration region 24: low concentration region 26: collector electrode 30: base region 32: high concentration region 34: low concentration region 36: base electrode 40: emitter region 42: high concentration region 44: low concentration region 46: emitter electrode 50: first buried region 60: isolation trench 62: isolation insulating layer 64: buried electrode 70: depletion layers 80, 82, 84 86, 88, 90, 92, 94, 96: equipotential line 100: lateral bipolar transistor 150: first buried region 152: second buried region 160: specific region 200: semiconductor device 210: LDMOS
220: source region 222: source electrode 230: body region 232: diffusion body region 240: n-type drift region 242: p-type drift region 250: drain region 252: drain electrode 260: gate electrode

Claims (2)

A first conductivity type semiconductor layer;
An emitter region of a second conductivity type provided on a part of the surface of the semiconductor layer;
A collector region of a second conductivity type provided on a part of the surface of the semiconductor layer and spaced from the emitter region;
A base region of a first conductivity type provided on a part of the surface of the semiconductor layer and disposed between the emitter region and the collector region;
The emitter region, the collector region, and the base region are separated from each other by a semiconductor layer,
A second conductivity type first buried region is further provided in the semiconductor layer and below the base region in the depth direction from the surface of the semiconductor layer,
The charge amount of the first buried region is equal to the charge amount of the base region,
A lateral bipolar transistor characterized by that. In the semiconductor layer,
A second buried region of a second conductivity type disposed below the first buried region in the depth direction from the surface of the semiconductor layer and spaced from the first buried region;
A specific region of the first conductivity type disposed between the first embedded region and the second embedded region is further provided,
The charge amount of the specific region is equal to the charge amount of the second embedded region,
The lateral bipolar transistor according to claim 1, wherein:

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