JP2018101882A - Output driver circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To deal with an event, such as short circuit, without increasing the number of components, in an output driver circuit.SOLUTION: A transistor Q1 has a source S connected with a first power supply terminal 13, and a drain D connected with a second power supply terminal 20 via a load RL. A series resistor R1 is inserted in series between the source S of the transistor Q1 and the first power supply terminal 13. A voltage-dividing circuit 15 applies a predetermined voltage to a gate G of the transistor Q1. The voltage applied to the gate G is set to such a voltage that Vgs is equal to or more than a threshold voltage at a normal time, and that Vgs is less than the threshold voltage at an abnormal time.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an output driver circuit, and more particularly to an output driver circuit having a transistor for controlling power supply to a load.

  One drive circuit (output driver circuit) that includes a field effect transistor (FET) and controls application of a DC power supply to a load is disclosed in Patent Document 1. In the drive circuit described in Patent Document 1, the source and drain of the FET are inserted between the DC power source and the load, and the supply and stop of the power to the load are controlled according to the voltage applied to the gate of the FET. Is done. In general, in a drive circuit, there is a demand for reducing the ON resistance of an FET in order to increase energy efficiency. For this demand, the voltage applied to the gate is set sufficiently higher than the threshold voltage Vth.

  Regarding the drive circuit, Patent Document 2 discloses a drive circuit for the purpose of eliminating a burden on an output transistor (power FET) when an excessive current occurs. The drive circuit described in Patent Document 2 has a current detection resistor (current detection resistor) between the source of the power FET and the DC power supply. In addition, this drive circuit has two bipolar transistors between the gate and source of the power FET.

  In the drive circuit described in Patent Document 2, when the drain resistance of the power FET increases due to a short circuit of the load resistance, the voltage drop of the current detection resistor increases. When the voltage drop across the current detection resistor increases, the two bipolar transistors quickly lower the gate voltage of the power FET and turn off the power FET. By doing in this way, it can suppress that an excessive drain current flows at the time of a short circuit, and the burden of power FET at the time of an excessive current can be eliminated. A drive circuit having a function for protecting a current drive element such as a power FET from an overcurrent is also described in Patent Document 3, for example.

Japanese Utility Model Publication No. 63-106226 JP-A-6-236812 JP 2003-9375 A

  In the drive circuit described in Patent Document 1, the source of the FET is directly connected to a DC power source. By connecting the source of the FET directly to the DC power supply, a voltage drop until the power is supplied to the load can be minimized. The method in which the source of the FET is directly connected to the DC power source is a general method that is considered to supply power to the load without waste as a method of using energy.

  However, in the drive circuit described in Patent Document 1, it is not considered that an excessive current flows through the FET when a short circuit occurs. For example, consider a case where the drive circuit of Patent Document 1 is applied to an in-vehicle application, and the drive circuit and the load are connected using a wire harness. When the FET is turned on in the drive circuit, the wire harness breaks, and when the wire harness is short-circuited to another wiring member or the vehicle body different from the output potential, a large current flows through the FET or the wire harness. In general, a battery of a vehicle can supply a large current, and when the short circuit occurs, a current exceeding the absolute maximum standard current flows through the FET. In that case, a wire harness and FET may be damaged when a large current flows.

  In the drive circuit described in Patent Document 2, even when a short circuit occurs and an excessive current flows, it is possible to eliminate the burden on the power FET. However, in Patent Document 2, two bipolar transistors are used to change the potential difference Vgs between the gate and source of the power FET when an excessive current occurs. In Patent Document 2, two bipolar transistors are required to switch between the ON region and the OFF region of the power FET, and there is a problem that the number of parts is large.

  Moreover, in the load drive device described in Patent Document 3, when an overcurrent is detected, the current drive element can be stopped. However, in Patent Document 3, a CPU (Central Processing Unit) is used for control, and protection against excessive current is implemented using software. When a short circuit or the like occurs, it is desired to stop the current driving element quickly. On the other hand, in the load driving device described in Patent Document 3, the time required for software processing is relatively long, and the short circuit or the like. It is difficult to deal with this event.

  In view of the above circumstances, an object of the present invention is to provide an output driver circuit that can cope with an event such as a short circuit while suppressing an increase in the number of components.

To achieve the above object, the present invention provides a field effect transistor having a source connected to one terminal of a power source and a drain connected to the other terminal of the power source via a load, the source and the power source. And a gate voltage generation circuit for applying a predetermined voltage to the gate of the field effect transistor, wherein the predetermined voltage is V _G , a voltage of one terminal and is V, a rated current of the load and I _r, the excessive current when a short circuit occurs greater than the constant rated current I _r and I _o, the resistance value of the series resistor and R, the electric field When the first threshold voltage at which the effect transistor is turned on is V _th1 ,
| V _th1 | + I _r × R ≦ | V−V _G | <| V _th1 | + I _o × R
An output driver circuit that satisfies the above requirements is provided.

  The output driver circuit of the present invention can cope with an event such as a short circuit while suppressing an increase in the number of components.

1 is a circuit diagram showing an output driver circuit according to a first embodiment of the present invention. The figure which shows the circuit model used for the transient analysis of the operation | movement of a transistor. The wave form diagram which shows a transient waveform. The figure which shows the circuit model used for the transient analysis at the time of normal operation of an output driver circuit. The wave form diagram which shows the transient waveform at the time of normal operation | movement of an output driver circuit. The figure which shows the circuit model used for the transient analysis at the time of the short circuit failure of an output driver circuit. The wave form diagram which shows the transient waveform at the time of the short circuit failure of an output driver circuit. The circuit diagram which shows the output driver circuit which concerns on 2nd Embodiment of this invention. The figure which shows the circuit model used for the transient analysis at the time of normal operation of an output driver circuit. The wave form diagram which shows the transient waveform at the time of normal operation | movement of an output driver circuit. The figure which shows the circuit model used for the transient analysis at the time of the short circuit failure of an output driver circuit. The wave form diagram which shows the transient waveform at the time of the short circuit failure of an output driver circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an output driver circuit according to a first embodiment of the present invention. The output driver circuit 10 includes a transistor Q1, a series resistor R1, a voltage dividing circuit 15, and a switch circuit 22. The output driver circuit 10 is used as, for example, an in-vehicle output driver circuit. The output driver circuit 10 is connected to a DC power source such as a battery, for example, and supplies power (load current) to the load RL via the wire harness 17.

  In the present embodiment, a p-channel field effect transistor is used as the transistor Q1. The source S of the transistor Q1 is connected via a series resistor R1 to a first power supply terminal 13 to which, for example, a DC power supply of 12V DC is connected. The drain D of the transistor Q1 is connected to the load RL via the wire harness 17, and is further connected to the second power supply terminal 20 to which a ground potential is applied via the load RL. When the transistor Q1 is ON, the DC power supplied from the first power supply terminal 13 is supplied to the load RL through the wire harness 17. When the transistor Q1 is OFF, no DC power is supplied to the load RL.

  The voltage dividing circuit 15 includes a voltage dividing resistor R3 and a voltage dividing resistor R5. The voltage dividing circuit 15 generates a predetermined voltage applied to the gate G of the transistor Q1. The voltage dividing circuit 15 is connected to the second power supply terminal 20 via the switch circuit 22. The switch circuit 22 includes, for example, a resistor R4 and a transistor Q2. The transistor Q2 is a bipolar transistor, and its base is connected to a control signal terminal 14 to which a control signal Sin is input via a resistor R4. The voltage dividing circuit 15 and the switch circuit 22 constitute a gate voltage generation circuit.

  The transistor Q <b> 2 is turned on when a sufficiently high voltage, for example, 12 V is applied to the control signal terminal 14, and connects between the voltage dividing circuit 15 and the second power supply terminal 20. When the transistor Q2 is in the ON state, a current flows from the first power supply terminal 13 side to the second power supply terminal 20 side through the voltage dividing resistor R3 and the voltage dividing resistor R5 in the voltage dividing circuit 15. The transistor Q <b> 2 is in an OFF state when a low voltage, for example, 0 V is applied to the control signal terminal 14, and does not connect the voltage dividing circuit 15 and the second power supply terminal 20. When the transistor Q2 is in the OFF state, no current flows from the first power supply terminal 13 side to the second power supply terminal 20 side in the voltage dividing circuit 15.

When the transistor Q2 in the switch circuit 22 is in the ON state, the voltage dividing circuit 15 converts the power supply voltage input from the first power supply terminal 13 to the ratio between the resistance value of the voltage dividing resistor R3 and the resistance value of the voltage dividing resistor R5. The pressure is divided at a predetermined pressure dividing ratio determined by. A connection node between the voltage dividing resistor R3 and the resistor R5 is connected to the gate G of the transistor Q1, and a predetermined voltage (V _G ) divided by the voltage dividing circuit 15 is applied to the gate G.

The voltage dividing ratio in the voltage dividing circuit 15 is the potential difference Vgs between the gate G and the source S of the transistor Q1 during normal use, ie, when the wire harness 17 or the like is not short-circuited. (Absolute value) is set to be slightly higher than the threshold voltage (first threshold voltage V _th1 ) when the transistor Q1 is ON. Since the potential difference Vgs is larger than the threshold voltage _Vth1 , the transistor Q1 operates in a saturation region where the transistor Q1 is turned on. In this case, a current (drain current) _Ids flowing between the source S and the drain D of the transistor Q1 is supplied as a load current to the load RL via the wire harness 17.

  On the other hand, when the transistor Q2 is in the OFF state in the switch circuit 22, one end side of the voltage dividing circuit 15 is released. In this case, the voltage dividing circuit 15 does not divide the power supply voltage input from the first power supply terminal 13 at a predetermined voltage dividing ratio. When the transistor Q2 is in the OFF state, a voltage equal to the power supply voltage is applied to the gate G of the transistor Q1, and the potential difference Vgs between the gate G and the source S of the transistor Q1 becomes almost zero. When the potential difference Vgs becomes approximately 0 V, the transistor Q1 is turned off. This state is a state in which the resistance value of the resistor Rds between the source S and the drain D in the transistor Q1 is increased. In this case, the drain current of the transistor Q1 is 0 or almost 0, and no load current is supplied to the load RL.

In the present embodiment, a series resistor R1 is connected in series to the source S of the transistor Q1, and when a load current flows through the load RL while the transistor Q1 is ON, a voltage drop occurs in the series resistor R1. The voltage drop _{V R1} in the series resistor R1 is the load current (drain current) expressed as _V R1 = R1 × I as I. The potential difference Vgs between the gate G and the source S of the transistor Q1 is expressed by Vgs = V _G − (Vcc−R1 × I) when the power supply voltage is Vcc.

In the present embodiment, the resistance value of the series resistor R1, the resistance value of the voltage dividing resistor R3 in the voltage dividing circuit 15, and the resistance value of the voltage dividing resistor R5 are load currents in a normal state where no short circuit occurs, for example, the rated current _{I r} of the load RL, the potential difference Vgs is set so that the threshold voltage _{V th1} or more ON the transistor Q1. Specifically, the gate voltage V _G is set to a voltage that satisfies | Vcc−V _G | ≧ | V _th1 | + I _r × R1. The drain current of the transistor Q1 changes exponentially with respect to the potential difference Vgs between the gate G and the source S. As described above, since the potential difference Vgs is set to be a voltage slightly higher than the threshold voltage _Vth1 , heat generation during normal time can be reduced.

Here, generally, the threshold voltage V _th1 of the transistor Q1 is defined as a potential difference Vgs between the gate G and the source S when the drain current starts to flow. For example, the threshold voltage V _th1 is defined as the potential difference Vgs when the drain current becomes equal to a predetermined reference current when the drain current is increased by increasing the potential difference Vgs (its absolute value). In the transistor Q1, when the potential difference Vgs is equal to or higher than the threshold voltage _Vth1 , the drain current is constant without depending on the potential difference Vds between the source and the drain. For the threshold voltage V _th1 , the relationship between the drain voltage and the drain current is obtained for a plurality of potential differences Vgs, and in the saturation region, the drain voltage is fixed and the relationship between the drain power ½ power and Vgs is obtained. It can also be defined as a voltage obtained by obtaining the voltage of the intercept of the X axis in the relationship (Vgs at which the drain current half power is 0).

When damage or the like occurs in the wire harness 17 and the wiring of the supply-side wire harness 17 directly contacts a location connected to the second power supply terminal 20, the current supplied from the first power supply terminal 13 is in series. The current flows into the second power supply terminal 20 through the resistor R1 and the transistor Q1 without passing through the load RL. In this case, the drain current of the transistor Q1 is larger than normal, the voltage drop V _R1 in series resistance R1 is increased by the amount of the drain current is larger than that of normal.

Gate voltage V _G of the voltage divider circuit 15 generates does not change even if the drain current is increased. That is, the voltage applied to the gate G of the transistor Q1 does not change. The voltage drop V _R1 in series resistance R1 with increasing drain current increases, the potential difference Vgs (the absolute value) between the gate G and the source S of the transistor Q1 is reduced by the voltage drop V _R1 increased To do. When the potential difference Vgs becomes smaller than the ON threshold voltage _{Vth1 of} the transistor Q1, the transistor Q1 operates in the non-saturated region, and the drain current decreases.

In the present embodiment, the gate voltage V _G of the voltage divider circuit 15 is generated when the short circuit and the overcurrent occurs caused, for that excessive current, the potential difference Vgs is the ON transistor Q1 threshold It is set to be lower than the voltage V _th1 . Specifically, when an excessive current was _{I o,} the gate voltage _{V G is, | Vcc-V G | <} | V th1 | + I o × R1 is set to a voltage which is filled. In this embodiment, | V−V _G |> | V _th2 | + I _o × R1 is satisfied when the threshold voltage (second threshold voltage) when the transistor Q1 is turned off is V _th2. It is preferable. The OFF threshold voltage V _th2 is, for example, when the drain current becomes 0 when the potential difference Vgs (the absolute value) between the gate G and the source S is reduced to reduce the drain current. Is defined as a potential difference Vgs. In this case, when an excessive current occurs, the transistor Q1 can be operated in a range that is not completely turned off.

In the output driver circuit 10, when the potential difference Vgs between the gate G and the source S of the transistor Q1 falls below the threshold voltage _Vth1, and the drain current of the transistor Q1 decreases, accordingly, the voltage drop V _{R1 at the} series resistor R1. Will decline. The potential difference Vgs and the drain current converge depending on a constant defined by the resistance value of the series resistor R1, and the drain current does not exceed a preset current value. As a result, even if the wire harness 17 is damaged and the current increases, current limitation is applied. At this time, the potential difference Vgs takes a value between the ON threshold value V _th1 and the OFF threshold value V _th2 of the transistor Q1. In other words, the transistor Q1 operates between an ON region and an OFF region.

In the present embodiment, the output driver circuit 10 includes a series resistor R1 between the first power supply terminal 13 and the source S of the transistor Q1. In addition, when the transistor Q1 is turned on, the voltage difference Vgs between the gate G and the source S in the normal state is slightly higher than the threshold voltage _Vth1 by using the voltage dividing circuit 15 at the gate G of the transistor Q1. A voltage set so as to become is applied. In the output driver circuit 10, when a short circuit or the like occurs and the drain current of the transistor Q1 increases, the voltage drop of the series resistor R1 increases accordingly, and the potential of the source S approaches the potential of the gate G. When the potential difference Vgs falls below the threshold voltage _Vth1 , the transistor Q1 cannot maintain the ON state, and the drain current decreases. If the transistor Q1, the series resistor R1, and the voltage dividing resistors R3 and R5 of the voltage dividing circuit 15 are selected and mounted in advance so that the transistor Q1 cannot be turned on within the component rating, the circuit components will be damaged. Can be prevented. For this reason, reliability can be improved and maintainability can be improved. In the present embodiment, for example, even if the wire harness 17 is short-circuited, the circuit components can be prevented from being damaged. Therefore, an accident leading to smoke or fire can be prevented in advance, and the spread of a vehicle or the like in which the output driver circuit 10 is mounted is prevented. it can.

  In the present embodiment, the transistor Q1 is used in the saturation region when normally ON. The transistor Q1 operates in a non-saturated region when the wire harness 17 or the like in an emergency is shorted. In the present embodiment, the normal operation and the emergency operation can be realized by using one transistor Q1, so that the number of components is small and the output driver circuit 10 can be manufactured at low cost. Furthermore, in this embodiment, since the transistor Q1 can be protected when the wire harness 17 is damaged, it is not necessary to perform special protection of the wire harness itself. For example, it is not necessary to use a double insulated wire harness for the wire harness 17 or to use electric piping. In this embodiment, the cost can be reduced also in this respect.

Hereinafter, description will be made using numerical examples. First, the threshold voltages V _th1 and V _th2 of the transistor Q1 will be described. FIG. 2 shows a circuit model used for transient analysis of transistor operation. The present inventor conducted a transient analysis of the operation of the transistor Q1 using Spice using the circuit model shown in FIG. In the transient analysis, IRF9510, which is a p-channel FET, was used as the transistor Q1. In the circuit model shown in FIG. 2, a variable voltage power supply is connected to the gate of the transistor Q1 via a resistor R4. In the transient analysis, the voltage output from the variable voltage power supply was gradually changed in the range from 0V to 12V.

In the following numerical examples, it is assumed that the load current of the load RL is 1 A or more as a design target. The threshold voltage _Vth and the resistance Rds between the source and the drain vary depending on the drain current of the transistor Q1. The inventors set the drain current to a current of about 1.2 A as a design target, and confirmed the threshold voltage _Vth using simulation. The resistance value of the resistor R4 was 10 kΩ, and the resistance value of the load RL was 8.2Ω. As shown in FIG. 2, the series resistor R1 is omitted in the circuit model used for analyzing the operation of the transistor Q1.

  FIG. 3 shows a transient waveform during the operation of the transistor Q1. In FIG. 3, the vertical axis represents voltage or current, and the horizontal axis represents time. In the transient analysis, while gradually changing the gate voltage from 12V to 0V, the voltage at point A (VA), voltage at point B (VB), current flowing through point C (IC), and voltage at point D in FIG. (VD) was determined. The voltage VA at the point A corresponds to the gate voltage of the transistor Q1, and the voltage at the point B corresponds to the source voltage. The difference between the voltage VA and the voltage VB corresponds to the potential difference Vgs between the gate and the source in the transistor Q1. The current IC flowing through the point C corresponds to the drain current (load current) of the transistor Q1, and the voltage VD at the point D corresponds to the voltage supplied to the load.

When the voltage VA is 12V, the potential difference Vgs between the gate and the source is 0V, and the current IC is 0. When the voltage VA was gradually decreased from 12V, the current IC began to flow at time t11. The voltage VA at this time was 8.866V. When the difference between the voltage VA and the voltage VB (power supply voltage) at time t11 is defined as the threshold voltage V _th2 of the transistor Q1 being OFF, the threshold voltage V _th2 is VA−VB = 8.866-12≈ -3.1V.

  As the voltage VA was further lowered, the current IC as the drain current increased as the potential difference Vgs between the gate and the source increased. When the potential difference Vgs becomes sufficiently large, the transistor Q1 is turned on, and the magnitude of the current IC becomes almost constant even when the voltage VA is changed.

Referring to FIG. 3, it can be seen that the current IC is substantially constant after time t12. The voltage VA at time t12 when the current IC starts to be constant was 4.817V. When the difference between the voltage VA and the voltage VB at time t12 is defined as the threshold voltage V _th1 of the transistor Q1 being ON, the threshold voltage V _th1 is VA−VB = 4.817−12≈−7.2V. It becomes. After time t12 when the potential difference Vgs between the gate and the source is equal to or higher than the threshold voltage _Vth1 , a sufficiently large voltage is supplied to the load RL as indicated by the voltage VD.

  Next, the operation of the output driver circuit 10 during normal operation will be described. FIG. 4 shows a circuit model used for transient analysis during normal operation of the output driver circuit. The inventor performed transient analysis of the operation of the output driver circuit during normal operation using the circuit using the circuit model shown in FIG.

  In the transient analysis, the IRF9510, which is a p-channel FET, was used as the transistor Q1 as in the circuit model of FIG. The resistance value of the load RL was set to 8.2Ω. The series resistor R1 is a 2W resistor, and the resistance value of the series resistor R1 is 0.74Ω from the E24 series in anticipation of a voltage drop of less than 1V during normal operation. The resistance values of the voltage dividing resistors R3 and R5 of the voltage dividing circuit 15 (see FIG. 1) are 82 kΩ and 39 kΩ, respectively, from the E24 series so that the potential difference Vgs between the gate and the source is about 8 V as a design target. did. An npn bipolar transistor 2N2484 is used as the transistor Q2 constituting the switch circuit 22 (see FIG. 1), and the resistance value of the resistor R4 is 3 kΩ.

  FIG. 5 shows a transient waveform during normal operation of the output driver circuit. In FIG. 5, the vertical axis represents voltage or current, and the horizontal axis represents time. In the transient analysis, the control signal Sin input to the control signal terminal 14 is switched between a high voltage and a low voltage, and flows through the voltage at point A (VA), voltage at point B (VB), and point C in FIG. The current (IC) and the voltage at point D (VD) were determined. The voltage VA at the point A corresponds to the gate voltage of the transistor Q1, the voltage at the point B corresponds to the source voltage, the current IC flowing through the point C corresponds to the drain current (load current) of the transistor Q1, and the voltage at the point D VD corresponds to the voltage supplied to the load. The difference between the power supply voltage and the voltage VB corresponds to a voltage drop in the series resistor R1.

When the transistor Q2 is turned on at time t21, the voltage at the connection node between the voltage dividing resistor R3 and the voltage dividing resistor R5 becomes 3.84V, and the voltage VA that is the gate voltage of the transistor Q1 becomes about 3.84V. At this time, the potential difference Vgs between the gate and the source of the transistor Q1 is larger than the threshold voltage _Vth1 , and when the transistor Q1 is turned on, a current IC that is also a load current starts to flow.

After the transistor Q1 was turned on at time 21, the current IC was 1.19A. As the current IC flows, the voltage VB, which is the source voltage of the transistor Q1, is about 11.12V. In other words, the voltage drop of the series resistor R1 accompanying the current IC was about 0.88V. The voltage VA is set such that the potential difference Vgs between the gate and the source becomes lower than the threshold voltage V _th1 when the current IC becomes the load current at the time of abnormality with respect to the load current at the time of abnormality, for example. It shall be. The voltage VA is set so that the potential difference Vgs between the gate and the source does not become the threshold voltage _Vth1 or less even when a voltage drop occurs in the series resistor R1 during normal operation, and the transistor Q1 can be kept ON.

  When the transistor Q1 is ON, the voltage VD that is a voltage supplied to the load is about 9.75 V, and it was confirmed that a sufficiently large voltage was supplied to the load RL. When the transistor Q2 of the switch circuit 22 is turned off at time t22 and the voltage VA becomes the power supply voltage 12V, the transistor Q1 is turned off. At this time, the current IC was 0, the voltage VB was 12V, and the voltage VD was 0V.

  Next, the operation of the output driver circuit 10 when a short circuit occurs will be described. FIG. 6 shows a circuit model used for transient analysis when the output driver circuit is short-circuited. In the circuit model shown in FIG. 6, the wire harness 17 is damaged between the drain of the transistor Q1 and the load RL, and the drain of the transistor Q1 is connected to the second power supply terminal 20 via the short-circuit resistor R6 having a low resistance. 4 is different from the circuit model shown in FIG. The resistance value of the short-circuit resistor R6 was 0.001Ω. The present inventor conducted transient analysis of the operation when a short circuit (ground fault) failure occurred in the output driver circuit using the circuit model shown in FIG.

  FIG. 7 shows a transient waveform when a short circuit fault occurs in the output driver circuit. In FIG. 7, the vertical axis represents voltage or current, and the horizontal axis represents time. In the transient analysis, the control signal Sin input to the control signal terminal 14 is switched between a high voltage and a low voltage as in the case of the normal operation, and the voltage at point A (VA) and the point B in FIG. The voltage (VB), the current flowing through point C (IC), and the voltage at point D (VD) were determined. The voltage VA at the point A corresponds to the gate voltage of the transistor Q1, the voltage at the point B corresponds to the source voltage, the current IC flowing through the point C corresponds to the drain current (load current) of the transistor Q1, and the voltage at the point D VD corresponds to the voltage supplied to the load.

When the transistor Q2 is turned on at time t31, the voltage at the connection node between the voltage dividing resistor R3 and the voltage dividing resistor R5 becomes 3.84V, and the voltage VA that is the gate voltage of the transistor Q1 becomes about 3.84V. This is the same as that shown in FIG. When the potential difference Vgs between the gate and the source of the transistor Q1 becomes larger than the threshold voltage _Vth1 , the transistor Q1 is turned on and a current IC that is also a load current starts to flow. At this time, the drain of the transistor Q1 is grounded through the short-circuit resistor R6, and a larger current than usual starts to flow as the current IC.

When a current larger than the normal time starts to flow as the current IC, the voltage drop of the series resistor R1 increases as the current increases, and the voltage VB that is the source voltage of the transistor Q1 decreases accordingly. When the voltage VB decreases, the difference between the voltage VA and the voltage VB decreases. When the potential difference Vgs between the gate and the source becomes smaller than the threshold voltage _Vth1 , the transistor Q1 cannot be kept ON. Since the transistor Q1 cannot be kept ON, the current IC decreases, the voltage VB increases, and the potential difference Vgs increases. As a result of such an operation, the current IC was 1.6 A, and the voltage VB was 10.8 V. Potential difference Vgs is the 3.84V-10.8V = -6.96V, this potential difference (absolute value thereof), the absolute value of the threshold voltage _{V th1} described above is lower than (7.2V).

Since the drain of the transistor Q1 is grounded through the low-resistance short-circuit resistor R6, the voltage VD remains almost zero. Transistor Q1, the potential difference Vgs continues to operate in lower than the threshold voltage _{V th1,} the output driver circuit 10, to be able to limit the current IC to 1.6A was confirmed. At time t32, when the transistor Q2 of the switch circuit 22 is turned off and the voltage VA becomes the power supply voltage 12V, the transistor Q1 is turned off, the current IC becomes 0, and the voltage VB becomes 12V.

  As can be understood from the above specific numerical examples, the output driver circuit 10 according to the present embodiment is different from Patent Document 2 in that the output current is limited without providing a bipolar transistor between the gate and the source. Is possible. Therefore, the output driver circuit 10 according to the present embodiment can cope with an event such as a short circuit while suppressing an increase in the number of components.

  Next, a second embodiment of the present invention will be described. FIG. 8 shows an output driver circuit according to the second embodiment of the present invention. The output driver circuit 10a includes a transistor Q1, a series resistor R1, and a logic gate 16. The logic gate (logic circuit) 16 is composed of, for example, a TTL (Transistor-transistor logic) circuit or a CMOS (Complementary Metal Oxide Semiconductor) circuit.

  In the present embodiment, an n-channel field effect transistor is used as the transistor Q1. The drain D of the transistor Q1 is connected to the load RL via the wire harness 17, and is further connected to the first power supply terminal 13 to which, for example, a + 12V DC power supply is connected via the load RL. The source S of the transistor Q1 is connected to a second power supply terminal 20 to which a ground potential is applied via a series resistor R1. When the transistor Q1 is ON, the wire harness 17 is connected to the second power supply terminal 20, and current is supplied to the load RL. When the transistor Q1 is OFF, no current is supplied to the load RL.

  In this embodiment, a logic gate 16 is used instead of the voltage dividing circuit 15 and the switch circuit 22 (see FIG. 1). The logic gate 16 constitutes a gate voltage generation circuit and outputs a predetermined voltage to the gate of the transistor Q1. The logic gate 16 is connected to the control signal terminal 14, and in response to the control signal Sin input from the control signal terminal 14, the voltage (gate voltage) output to the gate G of the transistor Q1 is set to a predetermined voltage and 0V. Switch between.

  The control signal Sin has logic levels of 0V and 5V, for example. The logic gate 16 sets the gate voltage to 0 V when the control signal Sin is 0 V (Low level), and sets the gate voltage to a predetermined voltage when the control signal Sin is 5 V (High level). Generally, the output voltage of the logic gate 16 is 5V or less. In the present embodiment, when an n-channel FET is used for the transistor Q1, the ground potential is a reference potential, so that the logic gate 16 can be directly connected to the gate G of the transistor Q1.

The predetermined voltage output from the logic gate 16 is a potential difference Vgs between the gate and the source of the transistor Q1 during normal use, that is, when the wire harness 17 or the like is not short-circuited. It is set to be slightly higher than the threshold voltage _Vth1 when the transistor Q1 is ON. Since the potential difference Vgs is larger than the threshold voltage _Vth1 , the transistor Q1 operates in a saturation region where the transistor Q1 is turned on. In this case, a current (drain current) flows between the source S and the drain D of the transistor Q1, and a load current flows through the load RL.

Also in this embodiment, the series resistor R1 is connected in series to the source S of the transistor Q1, and when a load current flows through the load RL while the transistor Q1 is ON, a voltage drop occurs in the series resistor R1. . Potential difference Vgs between the gate G and the source S of the transistor Q1, when a predetermined voltage logic gate 16 outputs a (gate voltage) was _{V G,} is represented by Vgs ₌ V G -R1 × I. That is, the potential difference Vgs is the gate voltage _{V G,} is lower by the voltage drop of the series resistance R1.

In the present embodiment, the gate voltage V _G of the resistance value and the logic gate 16 of the series resistor R1 to the output, the load current in the normal state where the short-circuit and the like does not occur, the rated current I _r for example the load RL, potential difference Vgs is set so that the threshold voltage _{V th1} or more ON the transistor Q1. Specifically, the gate voltage V _G is set to a voltage that satisfies V _G ≧ V _th1 + I _r × R1.

When damage or the like occurs in the wire harness 17 and the wiring of the wire harness 17 directly contacts a portion connected to the first power supply terminal 13, current flows toward the transistor Q1 through the contact portion without passing through the load RL. As a result, the current flows from the transistor Q1 to the second power supply terminal 20 through the series resistor R1. In this case, the drain current of the transistor Q1 is larger than normal, the voltage drop V _R1 in series resistance R1 is increased by the amount of the drain current is larger than that of normal.

Gate voltage V _G of logic gate 16 is output does not change even if the drain current is increased. That is, the voltage applied to the gate G of the transistor Q1 does not change. The voltage drop V _R1 in series resistance R1 with increasing drain current increases, the potential difference Vgs between the gate G and the source S of the transistor Q1 is reduced by the voltage drop V _R1 increases. When the potential difference Vgs becomes smaller than the ON threshold voltage _{Vth1 of} the transistor Q1, the transistor Q1 operates in the non-saturated region, and the drain current decreases.

In the present embodiment, the gate voltage V _G output from the logic gate 16 is such that when an overcurrent occurs due to a short circuit or the like, the potential difference Vgs is an ON threshold voltage of the transistor Q1 with respect to the overcurrent. It is set to be lower than _Vth1 . Specifically, when the excessive current is I _o , the voltage V _G is set to a voltage that satisfies V _G <V _th1 + I _o × R1. In the present embodiment, it is preferable that V _G > V _th2 + I _o × R1 is satisfied when the threshold voltage when the transistor Q1 is turned off is V _th2 . In this case, when an excessive current occurs, the transistor Q1 can be operated in a range that is not completely turned off.

  Hereinafter, description will be made using numerical examples. First, the operation during normal operation of the output driver circuit 10a will be described. FIG. 9 shows a circuit model used for transient analysis during normal operation of the output driver circuit. The present inventor performed transient analysis of the operation of the output driver circuit during normal operation using Spice, using the circuit model shown in FIG. In the transient analysis, IRF1010G, which is an n-channel FET, was used as the transistor Q1. The resistance value of the series resistor R1 was 0.47Ω, and the resistance value of the load RL was 8Ω.

  FIG. 10 shows a transient waveform during normal operation of the output driver circuit 10a. In FIG. 10, the vertical axis represents voltage or current, and the horizontal axis represents time. In the transient analysis, the control signal Sin input to the control signal terminal 14 is switched between a high voltage and a low voltage, and the voltage at point A (VA), voltage at point B (VB), and voltage at point C in FIG. (VC) and the current (ID) flowing through point D were determined. The voltage VA at the point A corresponds to the source voltage of the transistor Q1, the voltage at the point B corresponds to the voltage on the opposite side of the power supply terminal 13 of the load RL, the voltage at the point C corresponds to the gate voltage of the transistor Q1, The current ID flowing through the point D corresponds to the drain current (load current) of the transistor Q1. The difference between the voltage VC and the voltage VA corresponds to the potential difference Vgs between the gate and the source in the transistor Q1, and the difference between the power supply voltage and the voltage VB corresponds to a voltage drop (applied voltage) of the load RL.

If a logic gate 16 outputs a gate voltage _{V G} at time t21, the voltage VC became 4.96V. At this time, the potential difference Vgs between the gate and the source of the transistor Q1 is larger than the threshold voltage _Vth1 , and when the transistor Q1 is turned on, a current ID that is a load current starts to flow. The current ID was 1.4A. Since the current ID flows and a voltage drop occurs in the series resistor R1, the voltage VA that is the source voltage of the transistor Q1 is 0.66V. The voltage VC is set so that the potential difference Vgs between the gate and the source does not become the threshold voltage _Vth1 or less even when a voltage drop occurs in the series resistor R1 during normal operation, and the transistor Q1 can be kept ON.

When the transistor Q1 was ON, the voltage VB on the other end side of the load RL was 0.79V, and the voltage applied to the load RL was 11.21V. When the voltage output from the logic gate 16 becomes 0V at time t42, the voltage VC, which is the gate voltage, becomes 0V, and the transistor Q1 is turned off. At this time, the current ID was 0, the voltage VA was 0 V, and the voltage VB was 12 V. When logic gates 16 at time t43 to output a voltage _{V G} transistor Q1 is turned ON, the transistor Q1 when the logic gate 16 outputs a 0V at time t44 is with OFF, the same operation is repeated.

  Next, the operation of the output driver circuit 10a when a short circuit occurs will be described. FIG. 11 shows a circuit model used for transient analysis when the output driver circuit 10a is short-circuited. In the circuit model shown in FIG. 11, the wire harness 17 is damaged between the drain of the transistor Q1 and the load RL, and the drain of the transistor Q1 is connected to the first power supply terminal 13 via the short-circuit resistor R7. Is different from the circuit model shown in FIG. The resistance value of the short-circuit resistor R7 was 0.001Ω. The present inventor conducted a transient analysis on the operation at the time of occurrence of a short circuit (power fault) failure of the output driver circuit using the circuit model shown in FIG.

  FIG. 12 shows a transient waveform when a short circuit fault occurs in the output driver circuit. In FIG. 12, the vertical axis represents voltage or current, and the horizontal axis represents time. In the transient analysis, the control signal Sin input to the control signal terminal 14 is switched between a high voltage and a low voltage, and the voltage at point A (VA), voltage at point B (VB), and voltage at point C in FIG. (VC) and the current (ID) flowing through point D were determined. The voltage VA at point A corresponds to the source voltage of the transistor Q1, the voltage at point B corresponds to the voltage at one end of the wire harness 17, the voltage at point C corresponds to the gate voltage of the transistor Q1, and the current ID is the transistor This corresponds to the drain current (load current) of Q1.

At time t51, the logic gate 16 outputs a gate voltage _{V G,} the voltage VC is the gate voltage of the transistor Q1 becomes 4.96V, the transistor Q1 is turn ON. This is the same as that shown in FIG. When the transistor Q1 is turned on, a current ID that is also the drain current of the transistor Q1 starts to flow. At this time, the drain of the transistor Q1 is grounded to the power supply terminal of + 12V through the short-circuit resistor R7, and a larger current than usual starts to flow as the current ID.

When a current larger than the normal current starts to flow as the current ID, the voltage drop of the series resistor R1 increases as the current increases, and the voltage VA that is the source voltage of the transistor Q1 increases correspondingly. When the voltage VA increases, the difference between the voltage VC and the voltage VA decreases. When the potential difference Vgs between the gate and the source becomes smaller than the threshold voltage _Vth1 , the transistor Q1 cannot be kept ON. Since the transistor Q1 cannot be kept ON, the current ID decreases, the voltage VA decreases, and the potential difference Vgs increases. As a result of such an operation, the current ID was 2.8 A, and the voltage VA was 1.31 V.

Since the drain of the transistor Q1 is connected to the power supply on the + 12V side through the low-resistance short-circuit resistor R6, the voltage VB remains almost 12V. Transistor Q1, the potential difference Vgs continues to operate in lower than the threshold voltage _{V th1,} the output driver circuit 10a, to be able to limit the current ID to 2.8A was confirmed.

When the voltage output from the logic gate 16 becomes 0V at time t52, the voltage VC becomes 0V and the transistor Q1 is turned off. At this time, the current ID became 0 and the voltage VA became 0V. When logic gates 16 at time t53 to output a voltage _{V G} transistor Q1 is turned ON, the transistor Q1 when the logic gate 16 outputs a 0V at time t54 is with OFF, the same operation is repeated.

  As can be understood from the above specific numerical examples, in the output driver circuit 10a according to the present embodiment, as in the first embodiment, the output current can be reduced without providing a bipolar transistor between the gate and the source. Restrictions are possible. Therefore, the output driver circuit 10a according to the present embodiment can cope with an event such as a short circuit while suppressing an increase in the number of components. Other effects are the same as those of the first embodiment.

  In the first embodiment, a p-channel FET is used for the transistor Q1, and an n-channel FET is used for the transistor Q1 in the second embodiment. However, in these embodiments, the FET type is particularly limited. Not. In the first embodiment in which the voltage dividing circuit 15 and the switch circuit 22 (see FIG. 1) are used, an n-channel FET may be used for the transistor Q1. In the second embodiment in which the logic gate 16 is used, a p-channel FET may be used for the transistor Q1. When a p-channel FET is used, it is sufficient that the FET is disposed on the high potential side of the load RL, as in the case described in the first embodiment. When an n-channel FET is used, the second Similar to that described in the embodiment, an FET may be disposed on the low potential side of the load RL.

  In the first embodiment, the gate voltage generation circuit includes the voltage dividing circuit 15, and in the second embodiment, the gate voltage generation circuit includes the logic gate 16. However, the present invention is not limited thereto. The gate voltage generation circuit can be configured by any circuit that can apply a desired voltage to the gate of the transistor Q1, and the type and configuration of the circuit are not particularly limited. Further, in each of the above embodiments, the example in which the transistor Q1 and the load RL are connected using the wire harness 17 has been described, but the present invention is not limited to this. An arbitrary wiring material can be used for connection between the transistor Q1 and the load RL.

  As mentioned above, although embodiment of this invention was described in detail, this invention is not limited to above-described embodiment, A change and correction are added with respect to the said embodiment in the range which does not deviate from the meaning of this invention. Also included in the present invention.

10: output driver circuit 13, 20: power supply terminal 14: control signal terminal 15: voltage dividing circuit 16: logic gate 17: wire harness 22: switch circuit Q1, Q2: transistor R1: series resistor R3, R5: voltage dividing resistor R4 : Resistance R6, R7: Short-circuit resistance

Claims (10)

A field effect transistor having a source connected to one terminal of the power supply and a drain connected to the other terminal of the power supply via a load;
A series resistor inserted in series between the source and one terminal of the power source;
A gate voltage generation circuit for applying a predetermined voltage to the gate of the field effect transistor,
Wherein a predetermined voltage is V _G, the voltage of one terminal of the power source and is V, a rated current of the load and I _r, the excessive current during short-circuit occurs greater than the constant rated current I _r and I _o, When the resistance value of the series resistor is R and the first threshold voltage at which the field effect transistor is turned on is V _th1 ,
| V _th1 | + I _r × R ≦ | V−V _G | <| V _th1 | + I _o × R
Output driver circuit that satisfies When the second threshold voltage at which the drain current of the field effect transistor is 0 is V _th2 ,
| V−V _G |> | V _th2 | + I _o × R
The output driver circuit according to claim 1, further satisfying:   3. The output driver circuit according to claim 1, wherein the gate voltage generation circuit includes a voltage dividing circuit that divides a power supply voltage at a predetermined voltage dividing ratio and generates the predetermined voltage.   The gate voltage generation circuit further includes a control transistor inserted between the voltage divider circuit and the other terminal of the power supply, the control transistor is turned on in response to a control signal, and the voltage divider circuit is The output driver circuit according to claim 3, wherein the power supply voltage is divided when the control transistor is turned on.   The output driver circuit according to claim 1, wherein the gate voltage generation circuit includes a logic gate that outputs the predetermined voltage.   The output driver circuit according to claim 5, wherein the logic gate outputs the predetermined voltage in accordance with a control signal.   The output driver circuit according to claim 1, wherein the load is connected to the field effect transistor via a wire harness.   The output driver circuit according to claim 1, wherein the power source is a battery mounted on a vehicle.   9. The output according to claim 1, wherein the field effect transistor is a p-channel transistor, and the series resistor is connected between a power supply terminal on a high potential side of the power supply and the source. Driver circuit.   9. The output according to claim 1, wherein the field effect transistor is an n-channel transistor, and the series resistor is connected between a power supply terminal on a low potential side of the power supply and the source. Driver circuit.

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