JP2018098717A - Voltage monitoring circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage monitoring circuit capable of shortening the time required for self-diagnosis, and a semiconductor device.SOLUTION: A selection circuit SEL1 selects any one voltage from among a normal determination threshold voltage VJD_N, a self-diagnosis determination threshold voltage VJD_T of which the polarity is reverse to that of the determination threshold voltage VJD_N with a monitoring target voltage VMI defined as a reference, and a boost determination threshold voltage VJD_B having the same polarity as the determination threshold voltage VJD_N and a larger potential difference. A comparator circuit CMP1 compares a selection voltage VJDS that is selected by the selection circuit SEL1 with the monitoring target voltage VMI, thereby detecting the presence/absence of specification violation of the monitoring target voltage VMI. In the case of self-diagnosis, the selection circuit SEL1 brings the determination threshold voltage VJD_N into an initial state and successively selects VJD_T, VJD_B and VJD_N, thereby forcibly generating a detection result representing the presence of specification violation.SELECTED DRAWING: Figure 1A

Description

  The present invention relates to a voltage monitoring circuit and a semiconductor device, for example, a voltage monitoring circuit and a semiconductor device equipped with a self-diagnosis function.

  For example, in Patent Document 1, when canceling power down based on LVDS (Low Voltage Differential Signaling), a transition from 0 to plus of a potential difference of two inputs is detected with a small operating current (low current consumption), and thereafter A comparator circuit for detecting a transition from positive to negative at high speed with a large operating current is shown.

JP 2007-315933 A

  In recent years, the voltage of semiconductor devices has been reduced. Accordingly, in the semiconductor device, an operation margin with respect to fluctuations in the power supply voltage and the like is reduced, and it is required to manage fluctuations in the power supply voltage and the like in a narrow range. Therefore, the semiconductor device may be equipped with a voltage monitoring circuit that monitors fluctuations in the power supply voltage, an error processing circuit that performs predetermined error processing when an abnormality is detected by the voltage monitoring circuit, and the like. .

  On the other hand, for example, in a semiconductor device that is required to be reliable, represented by a vehicle application, as one of functional safety, for diagnosing whether the above-described voltage monitoring circuit, error processing circuit, etc. operate normally. A self-diagnosis function may be provided. As one of the methods for realizing the self-diagnosis function, there is a method in which a potential difference for which an abnormality is detected is forcibly applied to a comparison circuit included in the voltage monitoring circuit, and then the potential difference is returned to the original potential difference. Conceivable.

  However, the present inventors have found that such a method may increase the time required for self-diagnosis. Specifically, it takes a long time to return the voltage monitoring circuit to the normal operating state by returning the potential difference to the normal potential difference (that is, when returning from the state where the abnormality is detected to the state where the abnormality is detected). May be required. As described above, this time becomes longer as the normal potential difference becomes smaller as the management range of the power supply voltage and the like becomes narrower.

  Embodiments to be described later have been made in view of the above, and other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  A voltage monitoring circuit according to an embodiment includes a selection circuit and a comparison circuit, detects whether there is a specification violation of the monitoring target voltage by comparing the monitoring target voltage with a first determination threshold voltage, and In the diagnosis, the detection result with the spec violation can be forcibly output. The selection circuit includes a first determination threshold voltage, a second determination threshold voltage having a polarity opposite to that of the first determination threshold voltage, based on the monitored voltage, and a first One of the third determination threshold voltages having the same polarity as the determination threshold voltage and having a larger potential difference is selected. The comparison circuit detects the presence or absence of a specification violation by comparing the selection voltage selected by the selection circuit with the monitoring target voltage. Here, at the time of self-diagnosis, the selection circuit selects the second, third, and first determination threshold voltages in order with the first determination threshold voltage as an initial state.

  According to the one embodiment, the time required for self-diagnosis can be shortened.

It is the schematic which shows the structural example of the voltage monitoring circuit by Embodiment 1 of this invention. It is the schematic which shows the operation example at the time of the self-diagnosis in the voltage monitoring circuit of FIG. 1A. It is the schematic which shows the operation example different from FIG. 1B. It is the schematic which shows the structural example which expanded the voltage monitoring circuit of FIG. 1A. 1B is a circuit diagram showing a detailed configuration example around the voltage monitoring circuit of FIG. 1A. FIG. It is the schematic which shows the structural example of the semiconductor device by Embodiment 1 of this invention. FIG. 5 is a schematic diagram illustrating an example of a problem that may occur when the voltage monitoring circuit of FIG. 4 is used. It is a circuit diagram which shows the detailed structural example around the voltage monitoring circuit by Embodiment 2 of this invention. It is a schematic diagram which shows an example of the size relationship of the main transistors in the voltage monitoring circuit of FIG. It is the schematic which shows the structural example of the voltage monitoring circuit by Embodiment 3 of this invention. It is the schematic which shows the operation example at the time of the self-diagnosis in the voltage monitoring circuit of FIG. 9A. FIG. 9B is a circuit diagram showing a detailed configuration example of the voltage monitoring circuit of FIG. 9A. It is the schematic which shows the structural example of the voltage monitoring circuit examined as a comparative example of this invention. It is the schematic which shows the operation example at the time of the self-diagnosis in the voltage monitoring circuit of FIG. 11A. FIG. 11B is a circuit diagram illustrating a configuration example of a comparison circuit in the voltage monitoring circuit of FIG. 11A.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . In the embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (abbreviated as a MOS transistor) is used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), but a non-oxide film is not excluded as a gate insulating film. In the drawing, a p-channel MOS transistor (referred to as a PMOS transistor) is distinguished from an n-channel MOS transistor (referred to as an NMOS transistor) by adding a circle symbol to the gate. Although the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor can operate normally.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<< Outline and problems of voltage monitoring circuit (comparative example) >>
First, prior to the description of the voltage monitoring circuit of the first embodiment, a voltage monitoring circuit as a comparative example will be described. FIG. 11A is a schematic diagram illustrating a configuration example of a voltage monitoring circuit studied as a comparative example of the present invention. In addition to the monitoring target voltage VMI, a normal determination threshold voltage VJD_N and a self-diagnosis determination threshold voltage VJD_T are input to the voltage monitoring circuit VMNC ′ illustrated in FIG. 11A. The normal determination threshold voltage VJD_N is a voltage for detecting whether or not there is a specification violation such as an upper limit specification violation or a lower limit specification violation of the monitoring target voltage VMI at a normal time. On the other hand, the determination threshold voltage VJD_T for self-diagnosis is a voltage for forcibly outputting the detection result with the specification violation to the voltage monitoring circuit VMNC ′ at the time of self-diagnosis.

  The voltage monitoring circuit VMNC ′ includes a selection circuit SEL4 and a comparison circuit CMP1. The selection circuit SEL4 selects one of the determination threshold voltage VJD_T for self-diagnosis and the determination threshold voltage VJD_N for normal use based on the selection signal SS4. The comparison circuit CMP1 compares the selection voltage VJDS selected by the selection circuit SEL4 with the monitoring target voltage VMI to detect whether there is a spec violation of the monitoring target voltage VMI, and outputs an output signal CMO representing the detection result. To do.

  FIG. 11B is a schematic diagram illustrating an operation example during self-diagnosis in the voltage monitoring circuit of FIG. 11A. As shown in FIG. 11B, in the self-diagnosis, the voltage monitoring circuit VMNC ′ controls the selection signal SS4 by a self-diagnosis control circuit (not shown), so that the self-diagnosis mode MD2 is sequentially set with the normal mode MD1 as an initial state. Transition to the normal mode MD3. In response to this, the selection circuit SEL4 selects the determination threshold voltage VJD_T for normal diagnosis and the determination threshold voltage VJD_N for normal use in order with the normal determination threshold voltage VJD_N as an initial state.

  The determination threshold voltage VJD_T for self-diagnosis is a voltage having a polarity opposite to that of the normal determination threshold voltage VJD_N with reference to the monitoring target voltage VMI. In the example of FIG. 11B, the voltage monitoring circuit VMNC ′ detects whether or not the monitoring target voltage VMI is lower than the normal determination threshold voltage VJD_N during normal time (in normal mode). In this case, with reference to the monitoring target voltage VMI, the normal determination threshold voltage VJD_N is set on the negative side, and the self-diagnosis determination threshold voltage VJD_T is set on the positive side.

  The determination threshold voltage VJD_T for self-diagnosis is set to a value that causes a sufficient potential difference with reference to the monitoring target voltage VMI. As a result, when the transition to the self-diagnosis mode MD2 is performed, the comparison circuit CMP1 changes the output signal CMO from the ‘L’ level to the ‘H’ level at high speed. The 'H' level of the output signal CMO represents a detection result with a specification violation (lower limit specification violation), and the 'L' level represents a detection result with no specification violation.

  Thereafter, when the voltage monitoring circuit VMNC 'transitions from the self-diagnosis mode MD2 to the normal mode MD3, the comparison circuit CMP1 causes the output signal CMO to transition from the ‘H’ level to the ‘L’ level. However, as shown in FIG. 11B, when the potential difference Vd between the monitored voltage VMI and the normal determination threshold voltage VJD_N is small, as described in FIG. There is a possibility that the “level transition time Tt1” becomes long. When the transition time Tt1 'becomes longer, the effective return time Tr1' to the normal mode MD3 becomes longer due to this limitation.

  FIG. 12 is a circuit diagram showing a configuration example of a comparison circuit in the voltage monitoring circuit of FIG. 11A. The comparison circuit CMP1 shown in FIG. 12 includes a differential amplifier circuit DAMP1, a common source amplifier circuit AMP1 that is cascade-coupled to the subsequent stage, and an inverter circuit INV that outputs an output signal CMO by inverting its output. The differential amplifier circuit DAMP1 includes NMOS transistors MN1 and MN2 that are differential pair transistors, a pair of PMOS transistors MP1 and MP2 that are load current sources for differential amplification, and an NMOS transistor MN3 that is a tail current source. . The PMOS transistors MP1 and MP2 are coupled between the power supply voltage VCC1 and the NMOS transistors MN1 and MN2, respectively. The NMOS transistor MN3 is coupled between the common source node of the NMOS transistors MN1 and MN2 and the ground power supply voltage GND. The

  The source grounded amplifier circuit AMP1 has a source coupled to the power supply voltage VCC1 and a PMOS transistor MP4 driven by the output of the differential amplifier circuit DAMP1, and a source coupled to the ground power supply voltage GND to serve as a load current source for amplification. And an NMOS transistor MN4. In the differential amplifier circuit DAMP1, the NMOS transistor MN1 is driven by the selection voltage VJDS, and the NMOS transistor MN2 is driven by the monitoring target voltage VMI.

  If the mutual conductance of the NMOS transistors MN1 and MN2 is “gm” and the differential input voltage to the NMOS transistors MN1 and MN2 is the potential difference Vd shown in FIG. 11B, the output current “I” of the differential amplifier circuit DAMP1. Becomes “gm × Vd”. The gate of the PMOS transistor MP4 of the common source amplifier circuit AMP1 is charged / discharged by this output current “I”, and the input voltage amplitude of the gate of the PMOS transistor MP4 has a predetermined magnitude in the common source amplifier circuit AMP1 due to this charge / discharge. Can reach the logic of the inverter circuit INV.

  At this time, the gate capacitance of the PMOS transistor MP4 is “Cg”, the input voltage amplitude of the gate of the PMOS transistor MP4 necessary to invert the logic of the inverter circuit INV is “ΔVg”, and the gate capacitance of the PMOS transistor MP4 is charged / discharged. When time is “T”, the relationship of Expression (1) is established. Further, the relationship of equation (2) is established by modifying equation (1). As can be seen from Equation (2), the charge / discharge time (that is, the transition period Tt1 'in FIG. 11B) necessary to invert the logic of the inverter circuit INV becomes longer as the potential difference Vd is smaller.

I × T = Cg × ΔVg (1)
T = (Cg × ΔVg) / I = (Cg × ΔVg) / (gm × Vd) (2)
Under such circumstances, as described above, the potential difference Vd required as a specification is getting smaller and smaller due to the trend of lowering the voltage of the semiconductor device. The normal determination threshold voltage VJD_N is generated by, for example, a reference voltage generation circuit (see FIG. 4) including a band gap reference circuit and the like, and becomes a voltage with low dependency on temperature and power supply voltage. However, the normal determination threshold voltage VJD_N may vary for each semiconductor device (semiconductor chip) depending on process variations. Considering such variations, the actual potential difference Vd may be further reduced.

  As the potential difference Vd becomes smaller, the effective return time Tr1 ′ to the normal mode MD3 shown in FIG. 11B becomes longer, and the self-diagnosis cannot be completed until the effective mode MD3 is effectively returned. The time required also becomes long. For example, when the potential difference Vd is 50 mV or the like, the recovery time Tr1 'is required to be several tens of μs or less, but in some cases, may be on the order of ms. In the case where the self-diagnosis is performed at the time of starting the semiconductor device, the longer self-diagnosis causes an increase in the start-up time of the semiconductor device.

<< Outline of Voltage Monitoring Circuit (Embodiment 1) >>
FIG. 1A is a schematic diagram showing a configuration example of a voltage monitoring circuit according to Embodiment 1 of the present invention. As a method of shortening the transition time Tt1 ′ of FIG. 11B, for example, (A) a method of increasing the operating current of the comparison circuit CMP1, (B) a method of reducing the transistor size of the PMOS transistor MP4 of FIG. . However, the method (A) increases the current consumption, leading to an increase in power consumption of the entire semiconductor chip. The method (B) causes an increase in relative characteristic variation between semiconductor chips in the PMOS transistor MP4, which may lead to variation in determination threshold voltage between semiconductor chips.

  Therefore, it is beneficial to use the method of FIG. 1A as a method that does not cause the problems (A) and (B). The voltage monitoring circuit VMNC1 shown in FIG. 1A is different from the configuration example of FIG. 11A in that a boost determination threshold voltage VJD_B is further input. The determination threshold voltage VJD_B for boosting is a voltage for temporarily expanding the input potential difference to the comparison circuit CMP1 at the time of transition from the self-diagnosis mode to the normal mode.

  The voltage monitoring circuit VMNC1 includes a selection circuit SEL1 and a comparison circuit CMP1. The selection circuit SEL1 selects one of the determination threshold voltage VJD_T for self diagnosis, the determination threshold voltage VJD_N for normal use, and the determination threshold voltage VJD_B for boosting based on the selection signal SS1. The comparison circuit CMP1 is composed of, for example, the circuit shown in FIG. 12, and detects whether there is a specification violation of the monitoring target voltage VMI by comparing the selection voltage VJDS selected by the selection circuit SEL1 with the monitoring target voltage VMI. Then, an output signal CMO representing the detection result is output.

  FIG. 1B is a schematic diagram illustrating an operation example during self-diagnosis in the voltage monitoring circuit of FIG. 1A. As shown in FIG. 1B, in the self-diagnosis, the voltage monitoring circuit VMNC1 controls the selection signal SS1 by a self-diagnosis control circuit (not shown), so that the self-diagnosis mode MD2a, Transition to boost mode MD2b and normal mode MD3. In response to this, the selection circuit SEL1 sets the normal determination threshold voltage VJD_N as an initial state, and sequentially determines the self-diagnosis determination threshold voltage VJD_T, the boost determination threshold voltage VJD_B, and the normal determination threshold voltage VJD_B. The determination threshold voltage VJD_N is selected.

  The determination threshold voltage VJD_T for self diagnosis is a voltage having a polarity opposite to that of the normal determination threshold voltage VJD_N with respect to the monitoring target voltage VMI, as in the case of FIG. 11B. On the other hand, the boost determination threshold voltage VJD_B is a voltage having the same polarity as the normal determination threshold voltage VJD_N with respect to the monitoring target voltage VMI, and is larger than the normal determination threshold voltage VJD_N. A voltage having a potential difference.

  In the example of FIG. 1B, the voltage monitoring circuit VMNC1 determines whether or not the monitoring target voltage VMI is lower than the normal determination threshold voltage VJD_N during normal time (in normal mode) (that is, whether or not a lower limit specification is violated). Is detected. In this case, with reference to the monitoring target voltage VMI, the normal determination threshold voltage VJD_N and the boost determination threshold voltage VJD_B are set to the negative side, and the self-diagnosis determination threshold voltage VJD_T is the positive side. Set to Further, with reference to the monitoring target voltage VMI, the potential difference Vb of the boost determination threshold voltage VJD_B is larger than the potential difference Vd of the normal determination threshold voltage VJD_N.

  The determination threshold voltage VJD_T for self-diagnosis is set to a value that causes a sufficient potential difference with reference to the monitoring target voltage VMI, as in the case of FIG. 11B. As a result, when the transition to the self-diagnosis mode MD2a is performed, the comparison circuit CMP1 changes the output signal CMO from the ‘L’ level to the ‘H’ level at high speed. Thereafter, the voltage monitoring circuit VMNC1 makes a transition from the self-diagnosis mode MD2a to the boost mode MD2b. In the boost mode MD2b, a sufficient potential difference Vb is input to the comparison circuit CMP1, so that the comparison circuit CMP1 increases the output signal CMO from the “H” level to the “L” level at a high speed in response to the transition to the boost mode MD2b. Transition. Thereafter, when the transition from the boost mode MD2b to the normal mode MD3 is performed, the selection voltage VJDS input to the comparison circuit CMP1 returns from the boost determination threshold voltage VJD_B to the normal determination threshold voltage VJD_N. .

  When such a configuration and operation are used, as shown in FIG. 1B, the return time Tr1 to the normal mode is not restricted by the transition time Tt1 of the output signal CMO unlike the case of FIG. 11B. As a result, the voltage monitoring circuit VMNC1 can effectively return to the normal mode MD3 at the time of transition from the boost mode MD2b to the normal mode MD3 according to the selection signal SS1. As a result, the time required for self-diagnosis can be shortened, and as a result, the startup time of the semiconductor device can be shortened.

  Note that the transition time Tt1 can be shortened as the potential difference Vb in FIG. 1B increases. Accordingly, the effective return time Tr1 to the normal mode MD3 can be shortened by shortening the time in the boost mode MD2b. Can also be shortened. However, if the potential difference Vb is too large, an overshoot or the like may occur when the selection voltage VJDS returns from the boost determination threshold voltage VJD_B to the normal determination threshold voltage VJD_N. Defined by these trade-offs.

  FIG. 2 is a schematic diagram illustrating an operation example different from FIG. 1B. In FIG. 2, the determination threshold voltage VJD_T for self-diagnosis is a voltage having a polarity opposite to that of the normal determination threshold voltage VJD_N with respect to the monitoring target voltage VMI, as in the case of FIG. 1B. Similarly to the case of FIG. 1B, the boost determination threshold voltage VJD_B is a voltage having the same polarity as the normal determination threshold voltage VJD_N with respect to the monitoring target voltage VMI, and the normal determination. This is a voltage having a potential difference larger than the threshold voltage VJD_N.

  However, in the example of FIG. 2, unlike the case of FIG. 1B, the voltage monitoring circuit VMNC1 determines whether or not the monitoring target voltage VMI is higher than the normal determination threshold voltage VJD_N during normal time (in normal mode). (That is, whether there is a violation of the upper limit specification). In this case, with reference to the monitoring target voltage VMI, the normal determination threshold voltage VJD_N and the boost determination threshold voltage VJD_B are set to the positive side, and the self-diagnosis determination threshold voltage VJD_T is the negative side. Set to

  FIG. 3 is a schematic diagram illustrating a configuration example in which the voltage monitoring circuit of FIG. 1A is expanded. The voltage monitoring circuit VMNC2 shown in FIG. 3 includes two voltage monitoring circuits shown in FIG. 1A. One voltage monitoring circuit includes a selection circuit SEL1u and a comparison circuit CMP1u, and the other voltage monitoring circuit includes a selection circuit SEL1l and a comparison circuit CMP1l. The selection circuits SEL1u and SEL1l perform selection operations based on the selection signals SS1u and SS1l, respectively, and output selection voltages VJDSu and VJDSl.

  The normal determination threshold voltage VJD_Nl input to the selection circuit SEL1l is lower than the monitoring target voltage VMI, and the normal determination threshold voltage VJD_Nu input to the selection circuit SEL1u is the monitoring target voltage. The potential is higher than VMI. Thereby, the selection circuit SEL1l and the comparison circuit CMP1l perform the operation as shown in FIG. 1B based on the normal determination threshold voltage VJD_Nl, and output an output signal CMOL representing the detection result of the lower limit specification violation. On the other hand, the selection circuit SEL1u and the comparison circuit CMP1u perform the operation as shown in FIG. 2 based on the normal determination threshold voltage VJD_Nu, and output an output signal CMou indicating the detection result of the upper limit specification violation.

<< Details around Voltage Monitoring Circuit (Embodiment 1) >>
FIG. 4 is a circuit diagram showing a detailed configuration example around the voltage monitoring circuit of FIG. 1A. Here, a voltage monitoring circuit that performs the operation of FIG. 1B is taken as an example. In FIG. 4, the reference voltage generation circuit VRG includes a band gap reference circuit BGR, a differential amplifier circuit DAMP2, a PMOS transistor MP5, a resistance element Rd1, and a selection circuit SEL2, and is used for self-diagnosis, normal use, and boost. Each determination threshold voltage (VJD_T, VJD_N, VJD_B) is generated.

  As is widely known, the band gap reference circuit BGR generates a band gap voltage Vbg (for example, about 1.2 V) that does not depend on the temperature or the power supply voltage by using the characteristics of the pn junction. The differential amplifier circuit DAMP2 drives the PMOS transistor MP5 so that the band gap voltage Vbg matches the feedback voltage Vf from the selection circuit SEL2. The PMOS transistor MP5 has a source coupled to the power supply voltage VCC2 and is driven by the differential amplifier circuit DAMP2, thereby generating a reference voltage Vref at the drain. The resistance element Rd1 appropriately divides the reference voltage Vref by resistance.

  The selection circuit SEL2 appropriately selects the resistance voltage dividing node (tap) of the resistance element Rd1 based on the trimming signal TRM, and outputs the voltage of the selected tap as the feedback voltage Vf. The value of the trimming signal TRM is determined for each semiconductor chip in the manufacturing stage of the semiconductor device (semiconductor chip), and the reference voltage Vref is the same voltage value even when process variation occurs between the semiconductor chips. Determined by value. The resistance element Rd1 appropriately divides the reference voltage Vref by resistance, thereby generating determination threshold voltages (VJD_T, VJD_N, VJD_B) for self diagnosis, normal use, and boost.

  The voltage monitoring circuit VMNC1a includes a selection circuit SEL1a, a capacitor Cv, and a comparison circuit CMP1 as shown in FIG. The capacitor Cv holds a selection voltage VJDS that is the gate voltage of the NMOS transistor MN1 of the comparison circuit CMP1. Here, the selection circuit SEL1a includes CMOS switches CSWt, CSWn, and CSWb. The CMOS switches CSWt, CSWn, and CSWb determine whether or not to transmit determination threshold voltages (VJD_T, VJD_N, and VJD_B) for self diagnosis, normal use, and boost to the capacitor Cv, respectively.

  Although not shown, the gates of the NMOS transistors and the PMOS transistors constituting the CMOS switches CSWt, CSWn, and CSWb are controlled by the selection signal SS1 shown in FIG. 1A. For example, when the normal determination threshold voltage VJD_N is transmitted to the capacitor Cv (in other words, the selection voltage VJDS), the selection signal SS1 controls the CMOS switch CSWn to turn on and the CMOS switches CSWt and CSWb to turn off. Be controlled.

<Outline of semiconductor device>
FIG. 5 is a schematic diagram showing a configuration example of the semiconductor device according to the first embodiment of the present invention. The semiconductor device DEV shown in FIG. 5 is composed of a single semiconductor chip, and is an in-vehicle microcontroller chip or the like, although not particularly limited thereto. The semiconductor chip DEV includes a plurality of external terminals including external terminals PN1 to PN6. The external terminals PN1, PN2, PN3, and PN4 are supplied with power supply voltages VDD, VCC, VCC_PLL, and VCC_SYS, respectively. The reset signal RST is input to the external terminal PN5, and the system mode signal SMD is input to the external terminal PN6.

  The semiconductor device DEV includes a power management unit PMU, a power generation unit PGU, a PLL (Phase Locked Loop) circuit PLLC, a flash memory FMEM, a logic circuit LGC, a nonvolatile memory RAM, and an IO circuit IOC. The power management unit PMU operates with the power supply voltage VCC_SYS and manages various power supplies used in the semiconductor device DEV. For example, the power management unit PMU controls power-on reset according to the reset signal RST and power saving control of the semiconductor device DEV according to the system mode signal SMD (for example, activation / inactivation control of various circuit blocks). Etc.

  As shown in FIG. 4, the power generation unit PGU includes a reference voltage generation circuit VRG and a plurality of voltage monitoring circuits VMNC1 [1] to VMNC1 to which various determination threshold voltages from the reference voltage generation circuit VRG are input. [3], and in addition, power generation circuits (regulator circuits) VGN1 to VGN3. The reference voltage generation circuit VRG operates with the power supply voltage VCC_SYS. The power supply generation circuits VGN1 to VGN3 receive the predetermined reference voltage from the reference voltage generation circuit VRG and the power supply voltage from the external terminal, and generate various internal power supply voltages. Here, the power supply generation circuit VGN1 receives the power supply voltage VDD and generates the internal power supply voltage VDDI_RAM for the nonvolatile memory RAM. The power supply generation circuit VGN2 receives the power supply voltage VCC and generates an internal power supply voltage VCCI_FM for the flash memory FMEM. The power supply generation circuit VGN3 receives the power supply voltage VCC_PLL and generates an internal power supply voltage VCCI_PLL for the PLL circuit PLLC.

  The voltage monitoring circuit VMNC1 [1] monitors the power supply voltage VDD, the voltage monitoring circuit VMNC1 [2] monitors the power supply voltage VCC, and the voltage monitoring circuit VMNC1 [3] monitors the power supply voltage VCC_PLL. The PLL circuit PLLC generates various clock signals required in the semiconductor device DEV. The logic circuit LGC operates with the power supply voltage VDD. The logic circuit LGC includes an MPU (Micro Processing Unit) that performs predetermined program processing using data in the flash memory FMEM and the nonvolatile memory RAM, a system control circuit SYSC that manages the state of the entire system, and the like. The nonvolatile memory RAM is an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), or the like. The IO circuit IOC serves as an input / output interface with the outside of the semiconductor device DEV.

  In such a configuration, for example, the power management unit PMU includes a self-diagnosis control circuit. The power management unit PMU (self-diagnosis control circuit) controls each selection circuit (for example, SEL1a in FIG. 4) in the voltage monitoring circuits VMNC1 [1] to VMNC1 [3] at the time of self-diagnosis. With the normal determination threshold voltage VJD_N as an initial state, the determination threshold voltages are selected in the order shown in FIG. 1B. Then, the power management unit PMU receives the detection results (the output signal CMO in FIG. 4) of the voltage monitoring circuits VMNC1 [1] to VMNC1 [3].

  Although not particularly limited, specifically, the power management unit PMU first controls the selection signal SS1 of the voltage monitoring circuit VMNC1 [1] as shown in FIG. 1B after power-on reset according to the reset signal RST. As a result, the voltage monitoring circuit VMNC1 [1] is detected to detect that there is a specification violation. The power management unit PMU receives the detection result with the specification violation and notifies the system control circuit SYSC in the logic circuit LGC to that effect. The system control circuit SYSC receives the notification and executes predetermined error processing that is determined in advance, and then notifies the power management unit PMU of completion. Upon receiving the completion notification, the power management unit PMU performs the same self-diagnosis, for example, for the next voltage monitoring circuit VMNC1 [2].

  Here, for example, the power supply voltage VDD is 1.25V, the power supply voltage VCC_SYS is about 3.0V, and the power supply voltages VCC and VCC_PLL are about 3.0V to 5.0V. In such a case, in particular, since it is required to manage the power supply voltage VDD in a narrow range, it is desirable to apply the method of FIG. 1A to at least the voltage monitoring circuit VMNC1 [1].

  For example, the power supply voltage VDD is managed in the range of 1.25V ± 0.05V, and the normal determination threshold voltage VJD_N when detecting the lower limit specification violation is 1.2V−ΔV (ΔV varies) Margin)). In this case, the determination threshold voltage VJD_T for self-diagnosis is set to 1.5 V, for example, and the determination threshold voltage VJD_B for boost is set to 1.0 V, for example. For the other voltage monitoring circuits VMNC1 [2] and VMNC1 [3], the method of FIG. 11A can be applied instead of the method of FIG. 1A depending on the value of the potential difference Vd of FIG. 1B.

<< Main effects of the first embodiment >>
As described above, by using the voltage monitoring circuit and the semiconductor device according to the first embodiment, it is possible to typically shorten the time required for self-diagnosis, and thus to shorten the startup time of the semiconductor device DEV. Further, as described with reference to FIG. 1A, such an effect can be obtained without increasing the power consumption and in a state where the monitoring accuracy is sufficiently maintained.

(Embodiment 2)
<< Problems of voltage monitoring circuit (premise) >>
FIG. 6 is a schematic diagram illustrating an example of a problem that may occur when the voltage monitoring circuit of FIG. 4 is used. FIG. 6 schematically shows a situation when transitioning from the boost mode MD2b to the normal mode MD3 in FIG. 1B. As shown in FIG. 6, when the selection voltage VJDS is switched from the determination threshold voltage VJD_B for boosting to the determination threshold voltage VJD_N for normal use, the selection voltage VJDS exceeds the selection voltage VJDS due to the movement of the charge of the capacitor Cv. Noises such as shoots and undershoots can occur. As a result, as shown in FIG. 6, there is a possibility that erroneous detection occurs in the comparison circuit CMP1.

  This noise is suppressed as the potential difference Vb between the monitoring target voltage VMI and the boost determination threshold voltage VJD_B is reduced. Then, as described in FIG. 1B, the transition time Tt1 (return time Tr1 ) Becomes longer. The noise is also superimposed on the reference voltage Vref through the selection circuit SEL1a and the resistance element Rd1 in FIG. In this case, as shown in FIG. 5, the noise wraps around the plurality of power generation circuits VGN1 to VGN3 and the plurality of voltage monitoring circuits VMNC1 [1] to VMNC1 [3] sharing the reference voltage generation circuit VRG. These circuits can be adversely affected. Specifically, for example, when a plurality of voltage monitoring circuits VMNC1 [1] to VMNC1 [3] perform self-diagnosis in parallel, there is a possibility that erroneous detection occurs in them, and the power generation circuit There is a possibility that malfunction occurs in the activated circuit to which power is supplied by VGN1 to VGN3.

<< Details around Voltage Monitoring Circuit (Embodiment 2) >>
FIG. 7 is a circuit diagram showing a detailed configuration example around the voltage monitoring circuit according to the second embodiment of the present invention. The voltage monitoring circuit VMNC1b shown in FIG. 7 differs from the voltage monitoring circuit VMNC1a shown in FIG. 4 in the following two points. As a first difference, the comparison circuit CMP2 of FIG. 7 includes three NMOS transistors MN1t, MN1n, and MN1b instead of the NMOS transistor MN1 in the comparison circuit CMP1 of FIG. The NMOS transistors MN1t, MN1n, and MN1b have a common drain node. The NMOS transistor MN1t is driven by a self-diagnosis determination threshold voltage VJD_T, the NMOS transistor MN1n is driven by a normal determination threshold voltage VJD_N, and the NMOS transistor MN1b is driven by a boost determination threshold voltage. Driven by VJD_B.

  As a second difference, the comparison circuit CMP2 of FIG. 7 includes a selection circuit SEL1b in the comparison circuit CMP2 instead of the selection circuit SEL1a of FIG. The selection circuit SEL1b includes three switches (both NMOS transistors here) SWt, SWn, and SWb. The three switches SWt, SWn, SWb have one end coupled in common and the other end coupled to three NMOS transistors MN1t, MN1n, MN1b. That is, the three switches SWt, SWn, and SWb are inserted into the current paths of the three NMOS transistors MN1t, MN1n, and MN1b, respectively. For example, when selecting the normal determination threshold voltage VJD_N, the selection circuit SEL1b controls the switch SWn to be on and controls the remaining switches SWt and SWb to be off.

  When the voltage monitoring circuit VMNC1b as shown in FIG. 7 is used, the charge movement as described in FIG. 6 does not occur, so that noise can be reduced and erroneous detection of the voltage monitoring circuit can be prevented. In addition, since noise does not wrap around the reference voltage Vref, it is possible to prevent erroneous detection of each voltage monitoring circuit and malfunction of each circuit. As a result, the potential difference Vb between the monitoring target voltage VMI and the boost determination threshold voltage VJD_B may be increased, and accordingly, the time required for self-diagnosis may be further shortened.

  FIG. 8 is a schematic diagram showing an example of the size relationship of main transistors in the voltage monitoring circuit of FIG. In the comparison circuit CMP2 of FIG. 7, the NMOS transistor MN1 of FIG. 4 is divided into three, so there is a concern about an increase in circuit area compared to the case of FIG. Therefore, it is useful to determine the size of each transistor as shown in FIG. FIG. 8 shows a simple layout configuration of each MOS transistor. In this example, the transistor size of each MOS transistor is not necessarily limited, but is set by the gate width with the same gate length.

  In FIG. 8, the NMOS transistor MN1n driven by the normal determination threshold voltage VJD_N and the NMOS transistor MN2 constituting the differential pair transistor are both set to the same size (gate width W1), resulting in process variations. In order to suppress the influence (ie, the deterioration of the monitoring voltage accuracy), the size is set to be somewhat large. On the other hand, the NMOS transistor MN1t driven with the determination threshold voltage VJD_T for self-diagnosis and the NMOS transistor MN1b driven with the determination threshold voltage VJD_B for boost are affected by process variations (that is, monitoring voltage accuracy). Since there is no particular problem, both or at least one of them is set to a size smaller than that of the NMOS transistor MN1n.

  In this example, the NMOS transistors MN1t and MN1b are both set to a size smaller than that of the NMOS transistor MN1n. Referring to FIGS. 7 and 8, NMOS transistor MN1t only needs to have a driving capability capable of discharging the drain node voltage to the 'L' level by self-diagnosis determination threshold voltage VJD_T. Is set to the smallest possible size (gate width W2).

  Further, the NMOS transistor MN1t plays a role of discharging the drain voltage of the “H” level to the “L” level by a strong ON state, whereas the NMOS transistor MN1b has a “ON” state due to the weak ON state. It plays the role of charging the drain voltage at the L level to the H level. With such a role, the NMOS transistor MN1b does not require a driving capability as compared with the NMOS transistor MN1t. Accordingly, the size (gate width W3) of the NMOS transistor MN1b may be smaller than the size (gate width W2) of the NMOS transistor MN1t.

  By setting the transistor size as described above, for example, the circuit area can be reduced as compared with the case where the NMOS transistors MN1t, MN1n, and MN1b are all configured with the same size (gate width W1). However, the circuit area overhead can be sufficiently suppressed. The NMOS transistors constituting the switches SWt, SWn, and SWb may be configured with a gate width larger than the gate width W1, for example. It is also possible to have the same size ratio as that of the transistors MN1t, MN1n, and MN1b.

<< Main effects of the second embodiment >>
As described above, by using the voltage monitoring circuit and the semiconductor device of the second embodiment, in addition to the various effects described in the first embodiment, it is possible to prevent erroneous detection of the voltage monitoring circuit and malfunction of various circuits. Can improve the performance. Further, such an effect can be obtained while suppressing the overhead of the circuit area.

(Embodiment 3)
<< Problems of voltage monitoring circuit (premise) >>
For example, when the reference voltage generation circuit VRG as shown in FIG. 4 is used, it is difficult to increase the power supply voltage VCC2 of the reference voltage generation circuit VRG, and the maximum reference voltage Vref that can be generated is, for example, In some cases, it is limited to about 2.0V. For example, such a situation may occur when it is necessary to monitor the power supply voltage VCC2 of the reference voltage generation circuit VRG itself using the determination threshold voltage from itself. As a result, voltage monitoring may be difficult when the monitoring target voltage is a high voltage such as 5.0V.

<< Outline of Voltage Monitoring Circuit (Embodiment 3) >>
FIG. 9A is a schematic diagram illustrating a configuration example of a voltage monitoring circuit according to the third embodiment of the present invention. Unlike the method of FIG. 1A, the voltage monitoring circuit VMNC3 shown in FIG. 9A uses a method in which the monitored voltage VMI side is changed while being stepped down instead of the determination threshold voltage VJD side. The voltage monitoring circuit VMNC3 includes a resistance element Rd2, a selection circuit SEL3, and a comparison circuit CMP. The resistance element Rd2 divides the monitoring target voltage VMI by resistance to generate a boost monitoring target voltage VMI_B, a normal monitoring target voltage VMI_N, and a self-diagnosis monitoring target voltage VMI_T. At this time, by sufficiently increasing the resistance value of the resistance element Rd2, power consumption at the monitoring target voltage VMI (for example, power supply voltage) can be sufficiently suppressed.

  The selection circuit SEL3 selects any one of the boost monitoring target voltage VMI_B, the normal monitoring target voltage VMI_N, and the self-diagnosis monitoring target voltage VMI_T. The comparison circuit CMP compares the selection voltage VMIS selected by the selection circuit SEL3 with the determination threshold voltage VJD to detect the presence or absence of a specification violation and outputs an output signal CMO representing the detection result.

  FIG. 9B is a schematic diagram illustrating an operation example during self-diagnosis in the voltage monitoring circuit of FIG. 9A. As shown in FIG. 9B, in the self-diagnosis, the voltage monitoring circuit VMNC3 controls the selection signal SS3 by a self-diagnosis control circuit (not shown), so that the normal mode MD1 is set to the initial state and the self-diagnosis mode MD2a, Transition to boost mode MD2b and normal mode MD3. In response to this, the selection circuit SEL3 selects the monitoring target voltage VMI_T for self-diagnosis, the monitoring target voltage VMI_B for boosting, and the monitoring target voltage VMI_N for normal use in order with the normal monitoring target voltage VMI_N as the initial state. To do.

  The monitoring target voltage VMI_T for self-diagnosis is a voltage having a polarity opposite to that of the normal monitoring target voltage VMI_N with reference to the determination threshold voltage VJD. The boost monitoring target voltage VMI_B is a voltage having the same polarity as the normal monitoring target voltage VMI_N on the basis of the determination threshold voltage VJD, and having a potential difference larger than the normal monitoring target voltage VMI_N. .

  In the example of FIG. 9B, as in the case of FIG. 1B, the voltage monitoring circuit VMNC3 uses the determination threshold voltage VJD as the monitoring target voltage VMI (that is, the normal monitoring target voltage VMI_N) at the normal time (in the normal mode). It is detected whether or not it has fallen below (that is, whether or not the lower limit specification is violated). In this case, with reference to the determination threshold voltage VJD, the normal monitoring target voltage VMI_N and the boost monitoring target voltage VMI_B are set to the positive side, and the self-diagnosis monitoring target voltage VMI_T is set to the negative side. . Furthermore, with reference to the determination threshold voltage VJD, the potential difference Vb of the boost monitoring target voltage VMI_B is larger than the potential difference Vd of the normal monitoring target voltage VMI_N.

<< Details of Voltage Monitoring Circuit (Embodiment 3) >>
For example, when the same configuration as the selection circuit SEL1a and the comparison circuit CMP1 shown in FIG. 4 is applied to the selection circuit SEL3 and the comparison circuit CMP in FIG. 9A, a noise problem may occur as in the case of the second embodiment. . Since the noise circulates to the monitoring target voltage VMI (for example, power supply voltage) via the resistance element Rd2, there is a possibility of causing a malfunction of a circuit that operates at the power supply voltage. Therefore, as in the case of the second embodiment, it is beneficial to configure the voltage monitoring circuit VMNC3 with a circuit as shown in FIG.

  FIG. 10 is a circuit diagram showing a detailed configuration example of the voltage monitoring circuit of FIG. 9A. The voltage monitoring circuit VMNC3a shown in FIG. 10 includes a resistance element Rd2 and a comparison circuit CMP3, and the comparison circuit CMP3 includes a selection circuit SEL1c as in the case of the comparison circuit CMP2 in FIG. However, unlike the comparison circuit CMP2, the comparison circuit CMP3 includes three NMOS transistors MN2t, MN2n, and MN2b instead of the NMOS transistor MN1 in FIG. NMOS transistors MN2t, MN2n, and MN2b have their drain nodes coupled in common. The NMOS transistor MN2t is driven by the self-diagnosis monitoring target voltage VMI_T, the NMOS transistor MN2n is driven by the normal monitoring target voltage VMI_N, and the NMOS transistor MN2b is driven by the boost monitoring target voltage VMI_B.

  The selection circuit SEL1c includes three switches (both NMOS transistors here) SWt, SWn, and SWb. The three switches SWt, SWn, SWb have one end coupled in common and the other end coupled to three NMOS transistors MN2t, MN2n, MN2b. That is, the three switches SWt, SWn, and SWb are inserted into the current paths of the three NMOS transistors MN2t, MN2n, and MN2b, respectively. The size relationship in the case of FIG. 8 can be applied to the transistor sizes of the three NMOS transistors MN2t, MN2n, MN2b and the three switches (NMOS transistors) SWt, SWn, SWb.

<< Main effects of Embodiment 3 >>
As described above, by using the voltage monitoring circuit and the semiconductor device according to the third embodiment, the various effects described in the first and second embodiments can be obtained even when the monitoring target voltage VMI is high. Become. Here, the case where the lower limit specification violation is detected is taken as an example, but it is of course possible to detect the upper limit specification violation or both in the same manner as in the first embodiment. .

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

《Appendix》
A voltage monitoring circuit capable of detecting the presence or absence of a specification violation of the monitoring target voltage by comparing the monitoring target voltage with a determination threshold voltage, and outputting a detection result of the specification violation upon request in a self-diagnosis; ,
A self-diagnosis control circuit for controlling the voltage monitoring circuit;
A reference voltage generation circuit for generating the determination threshold voltage;
A semiconductor device composed of one semiconductor chip,
The voltage monitoring circuit includes:
A resistance element that generates a first monitoring target voltage, a second monitoring target voltage, and a third monitoring target voltage by dividing the monitoring target voltage by resistance;
A selection circuit that selects one of the first monitoring target voltage, the second monitoring target voltage, and the third monitoring target voltage;
A comparison circuit that detects the presence or absence of the specification violation by comparing the selection voltage selected by the selection circuit and the determination threshold voltage;
Have
The self-diagnosis control circuit controls the selection circuit at the time of the self-diagnosis so that the first monitoring target voltage is set in the selection circuit as an initial state, and the second monitoring target voltage, The monitoring target voltage, the first monitoring target voltage is selected,
The second monitoring target voltage is a voltage having a polarity opposite to that of the first monitoring target voltage with reference to the determination threshold voltage.
The third monitoring target voltage is a voltage having the same polarity as the first monitoring target voltage with the determination threshold voltage as a reference, and has a potential difference larger than the first monitoring target voltage.
Semiconductor device.

CMP comparison circuit DEV semiconductor device MD1, MD3 normal mode MD2a self-diagnosis mode MD2b boost mode MN NMOS transistor MP PMOS transistor PGU power generation unit PMU power management unit PN external terminal Rd resistance element SEL selection circuit SS selection signal SW switch VDD, VCC power supply Voltage VGN Power generation circuit VJD determination threshold voltage VJD_B Determination threshold voltage (for boost)
VJD_N Judgment threshold voltage (for normal use)
VJD_T judgment threshold voltage (for self-diagnosis)
VJDS selection voltage VMI monitoring target voltage VMI_B monitoring target voltage (for boost)
VMI_N Voltage to be monitored (for normal use)
VMI_T Monitoring target voltage (for self-diagnosis)
VMIS selection voltage VMNC voltage monitoring circuit VRG reference voltage generation circuit

Claims (20)

A voltage that can detect whether there is a specification violation of the monitoring target voltage by comparing the monitoring target voltage with the first determination threshold voltage, and can output a detection result with the specification violation upon request in self-diagnosis A monitoring circuit,
The first determination threshold voltage, the second determination threshold voltage having a polarity opposite to that of the first determination threshold voltage with reference to the monitoring target voltage, and the monitoring target voltage As a reference, any one of the third determination threshold voltages having the same polarity as the first determination threshold voltage and having a potential difference larger than the first determination threshold voltage is selected. A selection circuit to
A comparison circuit that detects the presence or absence of the specification violation by comparing the selection voltage selected by the selection circuit and the monitoring target voltage;
Have
In the self-diagnosis, the selection circuit sets the first determination threshold voltage as an initial state, and sequentially selects the second determination threshold voltage, the third determination threshold voltage, and the first determination threshold voltage. Select the judgment threshold voltage,
Voltage monitoring circuit. The voltage monitoring circuit according to claim 1, wherein
The comparison circuit includes a differential amplifier circuit including a first transistor and a second transistor which are differential pair transistors;
The first transistor is driven by the selection voltage;
The second transistor is driven by the monitored voltage.
Voltage monitoring circuit. The voltage monitoring circuit according to claim 2,
The first transistor includes a first-A transistor, a first-B transistor, and a first-C transistor, one end of which is commonly coupled,
The first A transistor is driven by the first determination threshold voltage,
The first B transistor is driven by the second determination threshold voltage,
The first C transistor is driven by the third determination threshold voltage,
The selection circuit includes:
A 1A switch inserted into the current path of the 1A transistor;
A 1B switch inserted into the current path of the 1B transistor;
A 1C switch inserted in the current path of the 1C transistor;
Having
Voltage monitoring circuit. The voltage monitoring circuit according to claim 3,
The size of the first A transistor is equal to the size of the second transistor,
The size of the first B transistor or the first C transistor is smaller than the size of the first A transistor,
Voltage monitoring circuit. The voltage monitoring circuit according to claim 3,
The size of the first A transistor is equal to the size of the second transistor,
The size of the first B transistor and the first C transistor are both smaller than the size of the first A transistor,
Voltage monitoring circuit. The voltage monitoring circuit according to claim 5,
The size of the first C transistor is smaller than the size of the first B transistor,
Voltage monitoring circuit. The voltage monitoring circuit according to claim 1, wherein
As the first determination threshold voltage, a 1A determination threshold voltage having a lower potential than the monitoring target voltage and a 1B determination threshold voltage having a higher potential than the monitoring target voltage are provided. And
The selection circuit and the comparison circuit are:
A first selection circuit and a first comparison circuit configured to detect whether or not the monitoring target voltage is lower than the determination threshold voltage of the first A based on the determination threshold voltage of the first A;
A second selection circuit and a second comparison circuit for detecting whether or not the monitoring target voltage is higher than the first B determination threshold voltage based on the first B determination threshold voltage;
Having
Voltage monitoring circuit. A voltage monitoring circuit that detects the presence or absence of specification violation of the monitoring target voltage by comparing the monitoring target voltage with the judgment threshold voltage, and can output the detection result of specification violation when requested. There,
A resistance element that generates a first monitoring target voltage, a second monitoring target voltage, and a third monitoring target voltage by dividing the monitoring target voltage by resistance;
A selection circuit that selects one of the first monitoring target voltage, the second monitoring target voltage, and the third monitoring target voltage;
A comparison circuit that detects the presence or absence of the specification violation by comparing the selection voltage selected by the selection circuit and the determination threshold voltage;
Have
In the self-diagnosis, the selection circuit selects the second monitoring target voltage, the third monitoring target voltage, and the first monitoring target voltage in order with the first monitoring target voltage as an initial state. ,
The second monitoring target voltage is a voltage having a polarity opposite to that of the first monitoring target voltage with reference to the determination threshold voltage.
The third monitoring target voltage is a voltage having the same polarity as the first monitoring target voltage with the determination threshold voltage as a reference, and has a potential difference larger than the first monitoring target voltage.
Voltage monitoring circuit. The voltage monitoring circuit according to claim 8, wherein
The comparison circuit includes a differential amplifier circuit including a first transistor and a second transistor which are differential pair transistors;
The first transistor is driven by the determination threshold voltage;
The second transistor is driven by the selection voltage;
Voltage monitoring circuit. The voltage monitoring circuit according to claim 9, wherein
The second transistor includes a 2A transistor, a 2B transistor, and a 2C transistor, one end of which is commonly coupled,
The second A transistor is driven by the first monitored voltage,
The second B transistor is driven by the second monitored voltage,
The second C transistor is driven by the third monitored voltage;
The selection circuit includes:
A 2A switch inserted into the current path of the 2A transistor;
A 2B switch inserted into the current path of the 2B transistor;
A 2C switch inserted in the current path of the 2C transistor;
Having
Voltage monitoring circuit. The voltage monitoring circuit according to claim 10, wherein
The size of the second A transistor is equal to the size of the first transistor;
The size of the second B transistor or the second C transistor is smaller than the size of the second A transistor,
Voltage monitoring circuit. The voltage monitoring circuit according to claim 10, wherein
The size of the second A transistor is equal to the size of the first transistor;
The size of the second B transistor and the second C transistor are both smaller than the size of the second A transistor,
Voltage monitoring circuit. The voltage monitoring circuit according to claim 12,
The size of the second C transistor is smaller than the size of the second B transistor,
Voltage monitoring circuit. A voltage that can detect whether there is a specification violation of the monitoring target voltage by comparing the monitoring target voltage with the first determination threshold voltage, and can output a detection result with the specification violation upon request in self-diagnosis A monitoring circuit;
A self-diagnosis control circuit for controlling the voltage monitoring circuit;
The first determination threshold voltage, the second determination threshold voltage having a polarity opposite to that of the first determination threshold voltage with reference to the monitoring target voltage, and the monitoring target voltage Reference voltage generation for generating a third determination threshold voltage having a potential that is the same polarity as that of the first determination threshold voltage and having a larger potential difference than the first determination threshold voltage. Circuit,
A semiconductor device composed of one semiconductor chip,
The voltage monitoring circuit includes:
A selection circuit that selects any one of the first determination threshold voltage, the second determination threshold voltage, and the third determination threshold voltage;
A comparison circuit that detects the presence or absence of the specification violation by comparing the selection voltage selected by the selection circuit and the monitoring target voltage;
Have
The self-diagnosis control circuit controls the selection circuit at the time of the self-diagnosis, so that the selection circuit has the first determination threshold voltage as an initial state, and the second determination threshold voltage in order. , Selecting the third determination threshold voltage and the first determination threshold voltage,
Semiconductor device. The semiconductor device according to claim 14.
The comparison circuit includes a differential amplifier circuit including a first transistor and a second transistor which are differential pair transistors;
The first transistor is driven by the selection voltage;
The second transistor is driven by the monitored voltage.
Semiconductor device. The semiconductor device according to claim 15, wherein
The first transistor includes a first-A transistor, a first-B transistor, and a first-C transistor, one end of which is commonly coupled,
The first A transistor is driven by the first determination threshold voltage,
The first B transistor is driven by the second determination threshold voltage,
The first C transistor is driven by the third determination threshold voltage,
The selection circuit includes:
A 1A switch inserted into the current path of the 1A transistor;
A 1B switch inserted into the current path of the 1B transistor;
A 1C switch inserted in the current path of the 1C transistor;
Having
Semiconductor device. The semiconductor device according to claim 16.
The size of the first A transistor is equal to the size of the second transistor,
The size of the first B transistor and the first C transistor are both smaller than the size of the first A transistor,
Semiconductor device. The semiconductor device according to claim 14.
A plurality of the voltage monitoring circuits are provided according to a plurality of the monitoring target voltages.
Semiconductor device. The semiconductor device according to claim 14.
The monitoring target voltage is a power supply voltage supplied from the outside of the semiconductor device.
Semiconductor device. The semiconductor device according to claim 14.
The self-diagnosis is executed when the semiconductor device is activated.
Semiconductor device.

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