JP2018093627A - Power conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power conversion device capable of highly accurately detecting an average output current of the power conversion device in only one sample in one cycle of a PWM carrier signal.SOLUTION: A power conversion device 1 comprises: a power converter 12 including an upper arm switching element 121 and a lower arm switching element 122; a gate generating unit 11 which generates an upper arm gate signal which controls the upper arm switching element 121 and a lower arm gate signal which controls the lower arm switching element 122; a current detector 13 which detects an output current of the power converter 12; an analog integrator 14 which calculates an analog integral value of the output current and resets the analog integral value at a first timing; a sample hold circuit 15 which holds the analog integral value at a second timing; and an average current calculation unit 17 which calculates an average value of the analog integral values integrated during the time lasting from the first timing to the second timing.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power conversion device that performs power conversion by PWM (Pulse Width Modulation) control.

  Generally, the voltage command value input to the power converter is determined based on the output current value of the power converter. If there is a large error between the average output current value during the actual control cycle and the detected output current value, the control performance will deteriorate, so it is necessary to obtain the average output current value during the control cycle accurately. It has been.

  The output current of the power converter that performs power conversion by PWM control pulsates at the switching frequency. For example, Patent Document 1 discloses a method for acquiring such a pulsating output current. With reference to FIG.5, 6, the power converter device (motor drive device) of patent document 1 is demonstrated. When the current detection unit for one phase is extracted, the configuration shown in FIG. 5 is obtained, and control is performed at the timing shown in FIG. The power conversion apparatus 100 controls the upper arm switching element 121 and the lower arm switching element 122 by the PWM controller 101, and drives the inductive load 20 such as a motor using the DC power source 123. Then, the average output current is obtained by correcting the output current values sampled by the current acquirer 104 at the two peaks and valleys of the PWM carrier signal.

  At time Ti1 when the carrier signal becomes a peak, the timing generator 102 issues a command for the offset calculator 105 to sample the current I (Ti1). Command to sample I (Ti2). The offset calculator 105 outputs ½ of the absolute value of the difference between the sampled current values I (Ti1) and I (Ti2) as a correction amount. The current value corrector 103 uses a value obtained by adding or subtracting the correction amount output from the offset calculator 105 to the detected current sampled by the current acquirer 104 as an average output current for current control.

JP 2013-2105030 A

  However, in the method described in Patent Document 1, at least two samples are required during the PWM carrier signal period, and an upper limit is generated in the carrier signal frequency. Further, since the current value is corrected from the two points of the sample, an error occurs between the average output current of a strict PWM carrier signal period.

  An object of the present invention made in view of such circumstances is to provide a power converter capable of detecting an average output current with high accuracy only by one sample per one period of a PWM carrier signal.

  In order to solve the above problems, a power converter according to the present invention includes a power converter having an upper arm switching element and a lower arm switching element, an upper arm gate signal for controlling the upper arm switching element, and the lower arm switching. A gate generation unit that generates a lower arm gate signal for controlling the element; a current detector that detects an output current of the power converter; and an analog integrated value of the output current detected by the current detector; An analog integrator that resets the integration value at a first timing, a sample-and-hold circuit that holds the analog integration value at a second timing, and an integration over time from the first timing to the second timing An average current calculation unit for calculating an average value of the output current from the analog integral value; And wherein to obtain.

  Further, in the power converter according to the present invention, the analog integrator is reset at a first timing when one of the upper arm switching element and the lower arm switching element is turned on, and the sample hold circuit is The value is held at a second timing at which the other of the upper arm switching element and the lower arm switching element is turned off.

  Furthermore, in the power conversion device according to the present invention, the analog integrator is reset at a first timing that becomes a peak or valley of a carrier signal, and the sample and hold circuit converts the analog integration value to the first timing. To hold at a second timing one cycle after the carrier signal.

  According to the present invention, an average output current can be obtained with only one sample per period of the PWM carrier signal, and the carrier frequency can be increased. In addition, since analog integration is performed, no measurement error due to the number of samples occurs, and the average output current can be detected with high accuracy.

It is a block diagram which shows the structural example of the power converter device which concerns on the 1st Embodiment of this invention. It is a timing diagram which shows the operation example of the power converter device which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structural example of the power converter device which concerns on the 2nd Embodiment of this invention. It is a timing diagram which shows the operation example of the power converter device which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the power converter device of patent document 1. FIG. 10 is a timing chart showing the operation of the power conversion device described in Patent Literature 1. FIG.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(First embodiment)
The power conversion device according to the first embodiment of the present invention will be described below. FIG. 1 is a block diagram illustrating a configuration example of a power conversion device according to the first embodiment of the present invention. The power converter 1 is a voltage-type power converter that supplies power to an inductive load 20 such as a three-phase AC motor based on a voltage command value generated by a current control system or the like. FIG. 1 shows a processing block that performs average current detection for one phase.

  The power conversion apparatus 1 includes a gate generation unit 11, a power converter 12, a current detector 13, an analog integrator 14, a sample hold circuit 15, an AD converter 16, an average current calculation unit 17, and a timer. 18.

  The power converter 12 has switching elements (upper arm switching element 121 and lower arm switching element 122), and converts DC power into AC power. FIG. 1 shows only one phase.

  The gate generation unit 11 generates an upper arm gate signal and a lower arm gate signal for controlling the switching elements of the power converter 12 by PWM control using a triangular wave comparison method or the like from the input voltage command value, and performs power conversion To the device 12. Specifically, an upper arm gate signal for switching the on and off states of the upper arm switching element 121 and a lower arm gate signal for switching the on and off states of the lower arm switching element 122 are generated. Further, in order to prevent a short circuit between the upper and lower arms when switching is switched, the gate generator 11 calculates a dead time in which both the upper and lower arm switching elements are simultaneously turned off to generate a gate signal.

  Each of the upper arm switching element 121 and the lower arm switching element 122 has a configuration in which a diode is connected in antiparallel to a semiconductor switch such as an IGBT or a MOSFET. In this embodiment, the switching element is described as being turned off when a high level signal is input as a gate signal and turned on when a low level signal is input.

  The upper arm switching element 121 and the lower arm switching element 122 are connected in series, and the connection point serves as an output and is connected to the load 20. A DC power source 123 is connected to both ends of the upper arm switching element 121 and the lower arm switching element 122 connected in series, and one of the upper arm switching element 121 and the lower arm switching element 122 is turned on to make a DC The voltage of either the high voltage side or the low voltage side of the power supply 123 is output. During the above-described dead time, the upper arm switching element 121 and the lower arm switching element 122 are simultaneously turned off.

  The current detector 13 detects the output current of the power converter 12 and outputs it to the analog integrator 14.

  The analog integrator 14 analog-integrates the output current detected by the current detector 13 to obtain an analog integrated value, and outputs it to the sample hold circuit 15. Further, the analog integrator 14 has a function of resetting an integrated value by a pulse signal. Specifically, a reset signal is input at a first timing when one of the upper arm switching element 121 and the lower arm switching element 122 (in this embodiment, the lower arm switching element 122) is turned on, and the analog integrated value is reset.

  The sample hold circuit 15 has an input, an output, and a hold signal input. When the hold signal is input, the sample hold circuit 15 continues to output the input signal level at the moment when the hold signal is input for a period during which the hold signal is input. Specifically, the hold signal is input at the second timing when the other of the upper arm switching element 121 and the lower arm switching element 122 (the upper arm switching element 121 in this embodiment) is turned off, and is input from the analog integrator 14. Hold the analog integration value. The sample hold circuit 15 needs to continue outputting the level of the input signal for the time required for the AD converter 16 to perform the conversion process.

  The AD converter 16 converts the analog integrated value input from the sample hold circuit 15 into a digital value and outputs the digital value to the average current calculation unit 17. The AD conversion timing is controlled by a digital control system.

  The timer 18 has two control inputs, a control input 1 and a control input 2, and outputs a time from when a reset signal is input to the control input 1 to when a hold signal is input to the control input 2. Once the control input 2 is input, the output value is held until the next control input 1 is input.

  The average current calculation unit 17 calculates the average value of the output current of the power converter 12 by dividing the analog integrated value input from the AD converter 16 by the time output by the timer 18, and Output to the control system. That is, the average output is obtained by dividing the analog integrated value integrated over the time from the first timing (reset) to the second timing (hold) described above by the time from the first timing to the second timing. Calculate the current.

  Next, the calculation operation of the average output current will be described with reference to FIG. FIG. 2 is a timing diagram showing waveforms of the upper arm gate signal and the lower arm gate signal output from the gate generation unit 11 and the output current of the power converter 12. The output current repeatedly rises and falls at the timing when the switching element switches.

  In the example shown in FIG. 2, the reset pulse is input to the analog integrator 14 at the first timing when the lower arm switching element 122 is turned on, that is, at the time t1 when the lower arm gate signal is switched to the low level. Then, the analog integrator 14 is reset, and analog integration of the output current detected by the current detector 13 is started. At time t1, a reset signal is input to the control input 1 of the timer 18. The sample and hold circuit 15 releases the hold state as soon as AD conversion by the AD converter 16 is completed.

  Thereafter, the lower arm gate signal becomes high level at time t2, and the upper arm gate signal becomes low level at time t3 after a dead time period. During this time, the analog integrator 14 continues to integrate.

  Next, the hold signal is input to the sample hold circuit 15 at the second timing when the upper arm switching element 121 is turned off, that is, at time t4 when the upper arm gate signal is switched to the high level. By this operation, the sample hold circuit 15 continues to output the integral value of the output current in an analog amount. At time t4, a hold signal is input to the control input 2 of the timer 18, and the time during which integration is continued is measured.

  The AD converter 16 AD-converts the analog integral value of the output current to obtain a digital value. The average current calculation unit 17 obtains the average output current by dividing the analog integrated value by the integration time measured by the timer 18. By repeating this operation, the power conversion device 1 can obtain the average output current of the power converter 12 (that is, the average output current of the power conversion device 1).

  Thus, the power conversion apparatus 1 obtains the average output current by dividing the value obtained by analog integration of the output current over one period of the PWM carrier signal by the integration time. It is only necessary to convert the integral value of the output current once and the carrier frequency can be increased. In addition, since the output current is analog integrated, no measurement error due to the number of samples occurs, and the average output current can be detected with high accuracy.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 3 is a block diagram illustrating a configuration example of the power conversion device according to the second embodiment of the present invention. 3 includes a gate generation unit 11, a power converter 12, a current detector 13, an analog integrator 14, a sample hold circuit 15, an AD converter 16, and an average current calculation unit. 17 and a timing generator 19. The power converter 2 of the second embodiment is different from the power converter 1 of the first embodiment in that a timing generator 19 is used instead of the timer 18. Since other configurations are the same as those of the first embodiment, the same reference numerals are given and description thereof is omitted as appropriate.

  The timing generator 19 outputs a reset signal to the analog integrator 14 at a first timing that becomes a peak or valley (in this embodiment, a peak) of the carrier signal. The timing generator 19 outputs a hold signal to the sample hold circuit 15 at a second timing one cycle after the carrier signal from the first timing.

  The average current calculation unit 17 calculates the average value of the output current of the power converter 12 by dividing the analog integrated value input from the AD converter 16 by the time of one cycle of the carrier signal. Output to external control system. That is, the average output is obtained by dividing the analog integrated value integrated over the time from the first timing (reset) to the second timing (hold) described above by the time from the first timing to the second timing. Calculate the current.

  Next, the calculation operation of the average output current will be described with reference to FIG. FIG. 4 is a timing chart when a reset signal and a hold signal are output at the peak of the carrier signal.

  The analog integrator 14 is reset at time T1 when the carrier signal becomes a peak and starts analog integration of the output current. Thereafter, the integration is continued until time T2 after one cycle of the carrier signal. At time T2, the sample-and-hold circuit 15 holds the output of the analog integrator 14, and at the same time, the analog integrator 14 resets the analog integration value and starts integration in the next section.

  The sample hold circuit 15 continues to output the analog integration value integrated over the period from the time T1 to the time T2 while the hold signal is input.

  The output held in this way is AD-converted by the AD converter 16 and is divided by the time of one cycle of the carrier signal by the average current calculation unit 17, whereby the average output current of the power converter 12 is obtained. By repeating this operation, the power conversion device 2 can obtain the average output current of the power converter 12 (that is, the average output current of the power conversion device 2).

  Thus, since the power converter 2 strictly calculates the average value of the output current in one cycle of the carrier signal, the average output current can be obtained with higher accuracy than the power converter 1. However, in the power conversion device 1, the PWM control method is not limited, but in the power conversion device 2, it is essential to perform PWM control using a carrier signal having peaks and valleys.

  Although the above embodiment has been described as a representative example, it will be apparent to those skilled in the art that many changes and substitutions can be made within the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited by the above-described embodiments, and various modifications and changes can be made without departing from the scope of the claims. For example, it is possible to combine a plurality of constituent blocks described in the configuration diagram of the embodiment into one, or to divide one constituent block.

DESCRIPTION OF SYMBOLS 1, 2 Power converter 11 Gate generation part 12 Power converter 13 Current detector 14 Analog integrator 15 Sample hold circuit 16 AD converter 17 Average current calculation part 18 Timer 19 Timing generator 20 Load 121 Upper arm switching element 122 Below Arm switching element 123 DC power supply

Claims (3)

A power converter having an upper arm switching element and a lower arm switching element;
A gate generation unit for generating an upper arm gate signal for controlling the upper arm switching element and a lower arm gate signal for controlling the lower arm switching element;
A current detector for detecting an output current of the power converter;
An analog integrator for obtaining an analog integral value of the output current detected by the current detector, and resetting the analog integral value at a first timing;
A sample and hold circuit for holding the analog integrated value at a second timing;
An average current calculation unit that calculates an average value of the output current from the analog integrated value integrated over the time from the first timing to the second timing;
A power conversion device comprising: The analog integrator is reset at a first timing when one of the upper arm switching element and the lower arm switching element is turned on,
2. The power conversion device according to claim 1, wherein the sample hold circuit holds the analog integrated value at a second timing at which the other of the upper arm switching element and the lower arm switching element is turned off. . The analog integrator is reset at a first timing that becomes a peak or valley of a carrier signal,
2. The power conversion apparatus according to claim 1, wherein the sample hold circuit holds the analog integration value at a second timing one cycle after the carrier signal from the first timing.

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