JP2018093480A - Solid state image sensor, driving method, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve gray scale of a composite pixel value obtained from a pixel including multiple photoelectric conversion parts having different light receiving sensitivity.SOLUTION: Pixels including multiple photoelectric conversion parts having different light receiving sensitivities are arranged in a pixel array. An AD conversion part performs analog to digital (AD) conversion of an electric signal, by comparing an electric signal corresponding to the charges of the photoelectric conversion part of low light receiving sensitivity, out of the multiple photoelectric conversion parts included in the pixels of the pixel array, with a nonlinear reference signal changing nonlinearly. For example, this technique is applicable to a complementary metal-oxide semiconductor (CMOS) image sensor.SELECTED DRAWING: Figure 6

Description

  The present technology relates to a solid-state imaging device, a driving method, and an electronic apparatus. In particular, for example, the gradation in the case where the output of two PDs (photodiodes) having different light receiving sensitivities is combined to widen the pixel value is set. The present invention relates to a solid-state imaging device, a driving method, and an electronic apparatus that can be improved.

  For example, in an image sensor, as a technology that combines the outputs of multiple PDs with different light receiving sensitivities to widen the pixel value, the output of a large PD with a large size and a small PD with a smaller size than a large PD There is a technology to synthesize.

  For example, when the gradation of pixel values obtained from large PD and small PD is expressed by 12 bits (0 to 4096) (approximately 72 dB), the sensitivity ratio between large PD and small PD is (approximately) 240 times By setting it to (47 dB), a pixel value having a gradation of (about) 120 dB (≈72 dB + 47 dB) can be realized as a combined pixel value obtained by combining the outputs of the large PD and the small PD.

  In the synthesis of the output of the large PD and the small PD, for example, until the output of the large PD is saturated, the output of the large PD is adopted as the synthesized pixel value, and after the large PD output is saturated, The output is multiplied by 240 times the digital gain and used as a composite pixel value.

  Therefore, after the output of the large PD is saturated, a value obtained by multiplying the output of the small PD by 240 times the digital gain is adopted as the composite pixel value, so compared with the case where the output of the large PD is adopted. The gradation of the synthesized pixel value becomes coarse.

  In an image sensor, it has been proposed to perform gamma correction by making the waveform of a ramp wave used for AD (Analog to Digital) conversion of PD output nonlinear (see, for example, Patent Document 1).

JP 2006-33454 A

  As described above, since the synthesized pixel value after saturation of the output of the large PD is a value obtained by applying a predetermined digital gain to the output of the small PD, the gradation of the synthesized pixel value is the large PD. Compared to the gradation of the synthesized pixel value when the output is adopted, it becomes rough.

  The present technology has been made in view of such a situation, and makes it possible to improve gradation.

  A first solid-state imaging device according to an embodiment of the present technology includes a pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are disposed, and a plurality of photoelectric conversion units included in the pixels of the pixel array unit. Among them, an AD converter that performs AD (Analog to Digital) conversion of the electrical signal by comparing the electrical signal corresponding to the electric charge of the photoelectric conversion unit having a low light receiving sensitivity with a nonlinear reference signal that changes nonlinearly A solid-state imaging device.

  In the first driving method of the present technology, the light receiving sensitivity of the plurality of photoelectric conversion units included in the pixel of the pixel array unit in which the pixels including the plurality of photoelectric conversion units having different light receiving sensitivities are arranged. The driving method includes AD (Analog to Digital) conversion of the electrical signal by comparing an electrical signal corresponding to a low charge of the photoelectric conversion unit with a nonlinear reference signal that varies nonlinearly.

  A first electronic device according to an embodiment of the present technology includes a solid-state imaging device and a control unit that controls the solid-state imaging device, and the solid-state imaging device includes pixels including a plurality of photoelectric conversion units having different light receiving sensitivities. Of the plurality of photoelectric conversion units included in the pixels of the pixel array unit, and an electric signal corresponding to the charge of the photoelectric conversion unit having a low light receiving sensitivity, and a nonlinear reference that changes nonlinearly The electronic apparatus includes an AD conversion unit that performs AD (Analog to Digital) conversion on the electrical signal by comparing the signal.

  In the first solid-state imaging device, the driving method, and the electronic device of the present technology, the plurality of photoelectric elements included in the pixel of the pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are arranged. By comparing an electrical signal corresponding to the charge of the photoelectric conversion unit having a low light receiving sensitivity in the conversion unit with a nonlinear reference signal that changes nonlinearly, the electrical signal is subjected to AD (Analog to Digital) conversion. The

  A second solid-state imaging device of the present technology includes a pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are arranged, and a plurality of photoelectric conversion units included in the pixels of the pixel array unit. Among these, an AD conversion unit that performs AD (Analog to Digital) conversion of the electrical signal by comparing an electrical signal corresponding to the charge of the photoelectric conversion unit with low light receiving sensitivity and a linear reference signal that changes linearly The AD converter includes: a comparator that compares the electrical signal with the linear reference signal; and the electrical signal and the linear reference signal according to a comparison result between the electrical signal and the linear reference signal. Is a solid-state imaging device having a counter that outputs a count value obtained by counting the time required for the change of the reference signal until the two coincide with each other according to a clock whose frequency changes.

  According to the second driving method of the present technology, the light receiving sensitivity of the plurality of photoelectric conversion units included in the pixel of the pixel array unit in which pixels including the plurality of photoelectric conversion units having different light receiving sensitivities are arranged. The solid-state imaging device including an AD conversion unit that performs AD (Analog to Digital) conversion on the electrical signal by comparing an electric signal corresponding to a low charge of the photoelectric conversion unit with a linear reference signal that changes linearly. The AD conversion unit compares the electrical signal and the linear reference signal, and the electrical signal and the linear reference signal are matched according to a comparison result between the electrical signal and the linear reference signal. This is a driving method including outputting a count value obtained by counting the time required for the change of the reference signal according to a clock whose frequency changes.

  A second electronic device of the present technology includes a solid-state imaging device and a control unit that controls the solid-state imaging device, and the solid-state imaging device includes pixels including a plurality of photoelectric conversion units having different light receiving sensitivities. Of the plurality of photoelectric conversion units included in the pixels of the pixel array unit, and an electric signal corresponding to the electric charge of the photoelectric conversion unit having a low light receiving sensitivity, and a linear reference that changes linearly An AD conversion unit that performs AD (Analog to Digital) conversion on the electrical signal by comparing the signal, and the AD conversion unit compares the electrical signal with the linear reference signal; and According to the comparison result between the electric signal and the linear reference signal, the time required for the change of the reference signal until the electric signal and the linear reference signal match is counted according to the clock whose frequency changes. And an electronic device having a counter that outputs a count value obtained.

  In the second solid-state imaging device, the driving method, and the electronic device of the present technology, the plurality of photoelectric elements included in the pixel of the pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are arranged. By comparing an electric signal corresponding to the charge of the photoelectric conversion unit having a low light receiving sensitivity in the conversion unit with a linear reference signal that changes linearly, the electric signal is subjected to AD (Analog to Digital) conversion. The In AD conversion, the electrical signal and the linear reference signal are compared, and the reference until the electrical signal and the linear reference signal match according to a comparison result between the electrical signal and the linear reference signal. A count value obtained by counting the time required for the change of the signal according to the clock whose frequency changes is output.

  According to the present technology, gradation can be improved.

It is a figure which shows an example of the technique which synthesize | combines the output of a large pixel and a small pixel, and makes a pixel value a wide dynamic range. It is a figure which shows the linear output by a DA converter. It is a figure which shows the nonlinear output by the DA converter to which this technique is applied. FIG. 4 is an enlarged view of FIG. 3. It is a figure which shows the waveform of the Ramp wave at the time of the D-phase reading in the CDS drive of SP1 and the output of the AD converter being non-linear during the P-phase read in the DDS drive of SP2. It is a block diagram showing an example of composition of an image sensor to which this art is applied. It is a circuit diagram which shows the structural example of the pixel arrange | positioned at the pixel array part. It is a figure which shows the drive timing of a pixel. It is a figure which shows the example of arrangement | positioning of SP1 and SP2 in a pixel. It is a block diagram which shows the structural example of an AD conversion part. It is a figure which shows the drive timing of an AD conversion part. It is a circuit diagram which shows the structural example of the DA converter of an AD conversion part. It is a circuit diagram which shows the structural example of the shift register which comprises Ramp DAC. It is a figure which shows the level shifter output corresponding to the 1st example of a drive of a DA converter. It is a figure which shows the Ramp waveform corresponding to the level shifter output of FIG. It is a figure which shows the level shifter output corresponding to the 2nd example of a DA converter drive. It is a figure which shows the Ramp waveform corresponding to the level shifter output of FIG. It is a figure for demonstrating the settling failure of a Ramp wave. It is a figure for demonstrating the settling failure of a Ramp wave. It is a figure which shows Ramp Stable which changes with column positions. It is a block which shows the example of application to a column-column type image sensor. It is a block diagram which shows the example of arrangement | positioning of the correction | amendment part which correct | amends the output of an AD conversion part. It is a figure which shows a mode that nonlinear data is correct | amended to linear data. It is a figure which shows the change of the drive frequency of the counter in a 1st modification. It is a figure which shows the Ramp waveform corresponding to the 1st modification. It is a figure which shows the change of the drive frequency of the DA converter in a 2nd modification. It is a figure which shows the Ramp waveform corresponding to the 2nd modification. It is a block diagram which shows an example of a schematic structure of an in-vivo information acquisition system. It is a block diagram which shows an example of a schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of a vehicle exterior information detection part and an imaging part.

  <Wide dynamic range of pixel values by combining the outputs of multiple PDs with different photosensitivity>

  A technique for widening a pixel value in a wide dynamic range by combining outputs of a plurality of PDs having different light receiving sensitivities in an image sensor will be described.

  As the plurality of PDs having different light receiving sensitivities, for example, a plurality of PDs having different sizes can be employed.

  FIG. 1 shows a technique for widening the pixel value by combining the outputs of a large PD (also referred to as SP1 in the drawing) and a small PD (also referred to as SP2 in the drawing) that are smaller than the large PD. An example is shown.

  For example, as shown in A of the figure, the sensitivity ratio of large PD to small PD is 240 times, and the gradation of both PDs before synthesis is 4096 (12 bits) up to 1048576 (20 bits) This is achieved by applying a 240 times digital gain to the output of a small PD in the case of wide dynamic range (when 120 dB is realized). However, in the area where the output of the small PD is synthesized by applying the digital gain, the gradation is 240 times that of the area where the output of the large PD is adopted, as shown in B of FIG. It becomes rough.

  Thus, when the gradation of the pixel value becomes rough, the required resolution may not be satisfied in applications such as in-vehicle sensing.

  For example, in-vehicle sensing requires 1% or less to be achieved for Con Res. (Constant resolution) = ΔLSB / Digital code. In the example of Fig. 1, Con Res. (Constant resolution) at the point where large PD switches to small PD. = 5.85 (= 240/4095 × 100)%, and the above-mentioned requirement cannot be achieved.

  As a method of reducing the Con Res., When the PD output is AD-converted, the waveform of the Ramp wave for comparison with the PD output is made non-linear. For example, Japanese Patent Application Laid-Open No. H10-133707 describes making the waveform of the Ramp wave non-linear.

  According to the technique described in Patent Document 1, the waveform of the Ramp wave can be made nonlinear. However, its application is gamma correction, and it is not possible to improve Con res when combining the output of large PD and small PD.

  Therefore, in the present technology, it is possible to improve Con res when combining the outputs of a plurality of PDs.

  FIG. 1 is a diagram for explaining a wide dynamic range of pixel values by combining outputs of two PDs as a plurality of photoelectric conversion units having different light receiving sensitivities.

  FIG. 1A illustrates the brightness of light incident on SP1 and SP2, SP1 which is a large PD having a large size and high light receiving sensitivity, and SP2 which is a small PD having a smaller size and lower light receiving sensitivity than SP1 and SP1 and SP2. It is a figure which shows the example of the relationship with the digital code which is the AD conversion result which AD-converted the output of SP2.

  In FIG. 1A, the outputs of SP1 and SP2 are both AD converted to 12 bits. Hereinafter, AD conversion to N bits is also referred to as N bit AD conversion. A digital code obtained by performing 12-bit AD conversion on the outputs of SP1 and SP2 has a value in the range of 0 to 4095.

  Hereafter, the digital code obtained by AD-converting the output of SP1 is also referred to as the SP1 digital code. Similarly, a digital code obtained by AD converting the output of SP2 is also referred to as a SP2 digital code.

  In A of FIG. 1, the ratio of the light receiving sensitivity between SP1 and SP2 is (about) 240 times (47 dB). That is, the light receiving sensitivity of SP1 is 240 times higher than the light receiving sensitivity of SP2.

  Accordingly, the LSB (Least Significant Bit) of the SP2 digital code corresponds to 240 times the brightness corresponding to the LSB of the SP1 digital code.

  FIG. 1B is a diagram illustrating an example of the relationship between the brightness of light incident on SP1 and SP2 and a digital code as a combined pixel value obtained by combining the outputs of SP1 and SP2.

  When combining the outputs of SP1 and SP2 to achieve a wide dynamic range, the SP1 and SP2 outputs are combined, for example, until the SP1 output is saturated, the SP1 digital code is used as the combined pixel value ( After the output of SP1 is saturated, the digital code of SP2 is applied as a composite pixel value by applying a digital gain of 240 times that is the ratio of the light receiving sensitivity of SP1 and SP2. Hereinafter, obtaining the combined pixel value in this way is also referred to as combining digital codes of SP1 and SP2.

  Here, the SP1 and SP2 digital codes are both 12 bits (about 72 dB), and the ratio of light receiving sensitivity between SP1 and SP2 is 240 times (about 47 dB) (about 8 bits). According to the synthesized pixel value obtained by synthesizing the output of, the pixel value of the gradation of (about) 120 dB (≈72 dB + 47 dB), that is, in the range of 0 to 1048675 represented by 20 bits (≈12 bits + 8 bits) A wide (high) dynamic range of values can be achieved.

  According to the synthesis of the digital code of SP1 and SP2, the S / N (Signal to Noise Ratio) when the synthesized pixel value is low in illuminance can be improved by the digital code of SP1. Further, the SP2 digital code can improve the saturation illuminance (characteristic) of the pixel and achieve a wide dynamic range of the combined pixel value. Furthermore, motion artifacts can be suppressed.

  By the way, in the synthesis of the digital code of SP1 and SP2, the digital code of SP2 is multiplied by 240 to obtain the synthesized pixel value, so the change in the LSB (1LSB) of the digital code of SP2 Appears as a change of 240LSB.

  Therefore, when the SP2 digital code (240 times as large) is employed in the synthesized pixel value, the gradation becomes 240 times coarser than when the SP1 digital code is employed.

  Now, for example, a value represented by ΔLSB / digital code is adopted as an index of the fineness (roughness) of the gradation of the pixel value.

  Here, “digital code” in ΔLSB / digital code represents a digital code as a composite pixel value, and “ΔLSB” represents a composite pixel value when the LSB of the SP1 digital code or the SP2 digital code changes. Represents the amount of change in the digital code.

  Further, a value represented by ΔLSB / digital code is called “Constant resolution” and is hereinafter abbreviated as “Con Res.”.

  Con Res. Is most deteriorated at the switching point between when the SP1 digital code is employed and when the SP2 digital code is employed in the composite pixel value. That is, in FIG. 1, Con Res. Is most deteriorated when the digital code as the synthesized pixel value is 4095, and when the digital code as the synthesized pixel value is 4095 and the digital code of SP2 increases by 1. Since the digital code as the synthesized pixel value increases by 1 × 240, 240 / 4095≈5.85%.

  For example, for an in-vehicle image sensor, a Con Res. Of 1% or less may be required. However, in the synthesis of digital codes of SP1 and SP2 shown in FIG. 1, a Con Res. Of 1% or less is required. Cannot be achieved.

  Therefore, in the present technology, the gradation of the composite pixel value is improved, and Con Res. Below a predetermined value such as 1% or less is achieved.

  In an image sensor to which the present technology is applied, a high-sensitivity PD (for example, a large-size PD; hereinafter referred to as SP1) and a low-sensitivity PD (for example, a small-size PD. ) And a pixel internal capacitance (FC). SP1 employs CDS (correlated double sampling) driving in which D-phase data is read after P-phase data is read. On the other hand, SP2 employs DDS (double data sampling) driving in which P-phase data is read after D-phase data is read.

  Here, in an image sensor to which the present technology is applied, a pixel has a plurality of PDs (SP1, SP2) as photoelectric conversion units that perform photoelectric conversion, and AD conversion of an electrical signal output from the pixel is referred to This is done by signal comparison AD conversion.

  In the reference signal comparison type AD conversion, for example, a reference signal that changes with time, such as a ramp signal (Ramp wave), is compared with an electric signal to be converted. Then, the time until the magnitude relationship between the reference signal and the electric signal changes is counted, and the count value obtained by counting the time is used as a digital code as an AD conversion result of the electric signal.

  Further, in an image sensor to which the present technology is applied, AD conversion of a noise signal and AD conversion of a data signal are performed as AD conversion of an electric signal output from a pixel.

  In the AD conversion of the noise signal, the FD voltage immediately after resetting the FD (Floating Diffusion) constituting the pixel to the power supply voltage is AD converted as a noise signal. In the AD conversion of the data signal, it is obtained by the photoelectric conversion of the PD. Immediately after the generated charge is transferred to the FD, the voltage of the FD is AD converted as a data signal.

  In AD conversion of a noise signal, a reference signal to be compared with the noise signal is changed for a predetermined period, and this predetermined period is also referred to as a P (Preset) phase. Similarly, in AD conversion of a data signal, a reference signal to be compared with the data signal is changed for a predetermined period, and this predetermined period is also referred to as a D (Data) phase.

  Furthermore, in an image sensor, outputting an electric signal from a pixel, performing AD conversion of the electric signal, and obtaining a digital code as a result of the AD conversion is referred to as reading of the digital code from the pixel. In addition, operating a pixel so as to read a digital code from the pixel is referred to as pixel driving. Further, of the digital code read from the pixel, the data read in the P phase (AD signal conversion result of the noise signal) is also referred to as P phase data, and the data read in the D phase is referred to as D phase data (data signal (AD conversion result) is also called D-phase data.

  Pixel driving methods include CDS driving and DDS driving. In CDS driving, P-phase data is read first, and then D-phase data is read. In DDS driving, D-phase data is read first, and then P-phase data is read.

  In both CDS driving and DDS driving, the difference between the D-phase data and the P-phase data is obtained as an AD conversion result of a signal component corresponding to an electric signal photoelectrically converted by the PD of the pixel. Noise can be reduced by taking the difference between the D-phase data and the P-phase data.

  In pixel driving, a reference signal used for AD conversion of an electrical signal (noise signal, data signal) output from a pixel can be generated by, for example, a DAC (Digital to Analog Converter) (DA converter).

  FIG. 2 shows a linear output (Ramp wave) by a DA converter in DDS driving. FIG. 3 shows an output (Ramp wave) by the DA converter of the image sensor to which the present technology is applied in the DDS drive. As shown in FIG. 3, the output from the DA converter of the image sensor to which the present technology is applied is made non-linear, for example, 24 dB to -6 dB.

  In this case, Con Res. = 0.36 (= (240/16) / 4095 × 100)%, and the requirement to set Con Res. To 1% or less can be achieved.

  That is, FIG. 2 is a waveform diagram showing a first example of a reference signal used for DDS-driven AD conversion. FIG. 3 is a waveform diagram showing a second example of a reference signal used for DDS-driven AD conversion.

  2 and 3, the horizontal axis represents time, and the vertical axis represents voltage (or level).

  In the first example of the reference signal of FIG. 2, the reference signal (voltage) decreases linearly (with a constant slope) in the D phase, and then the voltage at the start of the D phase immediately before the P phase. It rises to a voltage higher by 1000 mV and then decreases linearly in the P phase.

  In FIG. 2, the D phase corresponds to the count value of 2048 counts of the counter that counts the time until the magnitude relationship between the electrical signal output from the pixel and the reference signal changes (according to a constant frequency clock). The reference signal decreases by 500 mV during that 2048 count.

  Here, the gain (analog gain) of AD conversion performed using the reference signal linearly decreasing by 500 mV during 2048 counts is set to 0 dB.

  In FIG. 2, the P phase is started after the reference signal rises to a voltage higher by 1000 mV than the voltage at the start of the D phase. Therefore, the voltage difference between the reference signal at the start of the P phase and the reference signal at the start of the D phase is 1000 mV (here, equivalent to a voltage of 4096 counts). The voltage difference of 1000mV is the AD conversion dynamic range (D-range). In CDS driving, the voltage difference between the reference signal at the end of the P phase and the reference signal at the end of the D phase is the dynamic range of AD conversion.

  In FIG. 2, in the P phase, the reference signal decreases linearly by 1500 mV during 6144 counts. Therefore, in FIG. 2, the slopes of the D-phase and P-phase reference signals are the same and constant, and are −500 mV / 2048 count = −1500 mV / 6614 count≈−244 μV / count (LSB). The gain of AD conversion performed using such a reference signal is 0 dB.

  Here, since the AD conversion gain corresponds to, for example, the slope of the reference signal, a reference signal on which AD conversion with a certain gain x [dB] is performed is also referred to as an x [dB] reference signal.

  In addition, in the D phase and the P phase, the reference signal can be changed so as to increase or increase so as to decrease. However, in this specification, in order to simplify the description, the case where the reference signal is changed to decrease is referred to, and the case where the reference signal is changed to increase is not referred to.

  In the second example of the reference signal in FIG. 3, the reference signal decreases linearly in the D phase as in the first example, and then the voltage at the start of the D phase immediately before the P phase. It rises to a voltage higher by 1000 mV and then decreases in the P phase. Further, in FIG. 3, as in FIG. 2, the D phase has a period of 2048 counts, and the P phase has a period of 6144 counts.

  However, in the P phase, in the first example of the reference signal, the reference signal decreases linearly, but in the second example of the reference signal, the reference signal changes nonlinearly. In FIG. 3, the reference signal changes in a so-called concave shape in the P phase.

  That is, for the sake of convenience, the P phase is divided into six sub-periods of P1, P2, P3, P4, P5, and P6 phases in order of increasing time. In the P phase for 6144 counts, the P1, P2, P3, P4, P5, and P6 phases from the beginning are the period for 1024 counts, the period for the next 1024 counts, the next A period for 1024 counts, a period for the next 1024 counts, a period for the next 1024 counts, and a period for the last 2048 counts.

  And the reference signals of P1, P2, P3, P4, P5, and P6 are -6dB reference signal, 0dB reference signal, 6dB reference signal, 12dB reference signal, 18dB, respectively. And a reference signal of 24 dB.

  Since the slope of the 0 dB reference signal in the P2 phase is −500 mV / 2048 count = −250 mV / 1024 count, the reference signal is decreased by 250 mV in the 1024 count P2 phase.

  Since the slope of the -6 dB reference signal in the P1 phase is twice the slope of the 0 dB reference signal, the reference signal decreases by 500 mV = 250 Mv × 2 in the 1024 count P1 phase.

  Since the slope of the 6 dB reference signal in the P3 phase is 1/2 times the slope of the 0 dB reference signal, the reference signal decreases by 125 mV = 250 mV / 2 in the 1024 count P3 phase.

  Since the slope of the 12 dB reference signal in the P4 phase is 1/4 times the slope of the 0 dB reference signal, the reference signal is reduced by 62.5 mV = 250 mV / 4 in the 1024 count P4 phase.

  Since the slope of the 18 dB reference signal in the P5 phase is 1/8 times the slope of the 0 dB reference signal, the reference signal decreases by 31.25 mV = 250 mV / 8 in the 1024 count P5 phase.

  Since the slope of the 24dB reference signal for P6 phase is 1/16 times the slope of the 0dB reference signal, the reference signal is reduced by 31.25mV = 250mV / 16x2 in the P6 phase with 2048 = 1024 x 2 counts. .

  In the second example of the reference signal in FIG. 3, the D phase has a period of 2048 counts as in the case of FIG. However, in FIG. 3, the D-phase reference signal is not a 0 dB reference signal, but a 24 dB reference signal similar to the last P6 phase of the P phase.

  Con Res. Can be improved by adopting a reference signal having a higher gain in the period when the voltage of the P-phase reference signal during DDS driving is lower, that is, in the period on the P6 phase side in FIG. .

  In FIG. 3, 24 dB reference signal is adopted in the P6 phase, and compared to the case of FIG. 2 where 0 dB reference signal is adopted in the same period, Con Res. It can be improved by 1/16 times.

  Therefore, for example, if the Con Res. When adopting the reference signal of FIG. 2 is 5.85% as explained in FIG. 1, for example, if the reference signal of FIG. Can be improved to 0.36% ≈5.85% / 16.

  That is, for SP2, the gradation of the combined pixel value can be improved by performing AD conversion using the reference signal of FIG.

  A reference signal that changes linearly as in the first example of the reference signal in FIG. 2 is also referred to as a linear reference signal, and a reference signal that changes nonlinearly as in the second example of the reference signal in FIG. Is also referred to as a nonlinear reference signal.

  For the gain in the P1 phase to P6 phase of the nonlinear reference signal, determine the gain in the last P6 phase of the P phase, and gradually decrease from the gain in the P6 phase in the P5 to P1 phase. Gain can be determined. The gain in the last P6 phase of the P phase can be determined, for example, according to the required gradation of the composite pixel value, that is, the required Con Res.

  Here, in FIG. 3, the P phase is divided into six sub-periods of P1 phase to P6 phase, and a reference signal that changes linearly is adopted in each sub-period, and the reference signal of P1 phase to P6 phase By gradually increasing the gain, the reference signal is changed nonlinearly for the entire P phase. However, the number of sub-periods for dividing the P phase is not limited to six. That is, the P phase can be divided into an arbitrary number of sub-periods of two or more.

  FIG. 4 is an enlarged view of the slope of the Ramp wave in the P-phase reading of FIG. As shown in FIG. 4, the slope of the Ramp wave (Ramp slope) is realized by changing the voltage by ΔV at 1 count (ΔT). Therefore, if ΔT or ΔV is changed with the inflection point of the RAMP wave as a boundary, the slope of the Ramp wave can be changed.

  Note that, as described above, CDS drive is adopted for SP1, DDS drive is adopted for SP2, and the objective of the present application is achieved if the output of the DA converter at the P-phase readout in SP2 DDS drive is nonlinear. To do. However, the DA converter output may be made non-linear also during D-phase reading in the CDS drive of SP1.

  That is, FIG. 4 is an enlarged view showing a nonlinear reference signal.

  At least one of the unit time ΔT for changing the voltage of the nonlinear reference signal and the change amount ΔV of the voltage of the reference signal for each unit time ΔT is set to a P-phase sub-period (P # i phase (here, i = 1, 2,..., 6)), the gain (slope) of the reference signal can be changed for each sub period.

  In FIG. 4, ΔT and ΔV are changed from ΔT1 and ΔV1 to ΔT2 and ΔV2.

  The inflection point that changes the gain of the reference signal is the timing at which the sub-period starts.

  FIG. 5 shows the waveform of the Ramp wave when the output of the DA converter is made non-linear at the time of D-phase reading in the SP1 CDS driving and at the time of P-phase reading in the SP2 DDS driving.

  As shown in the figure, the Ramp wave at the P-phase reading in the SP2 DDS driving is a concave nonlinear shape, but the Ramp wave at the D-phase reading in the SP1 CDS driving is a convex non-linearity. In this case, the gradation at low illuminance in SP1 can also be improved.

  That is, FIG. 5 is a diagram illustrating an example of a reference signal used for SP1 CDS driving and a reference signal used for SP2 DDS driving.

  In FIG. 5, a solid line represents a linear reference signal, and a dotted line represents a non-linear reference signal.

  In the SP2 DDS drive, the non-linear reference signal that changes in a concave shape is used as the P-phase reference signal, so that the gradation of the combined pixel value can be improved as described with reference to FIG.

  In the CDS driving of SP1, a non-linear reference signal that changes in a convex shape can be used as the D-phase reference signal. In this case, the gradation of the combined pixel value at the time of low illuminance can be improved.

<Configuration example of image sensor according to an embodiment of the present technology>
Next, FIG. 6 illustrates a configuration example of an image sensor that is an embodiment of the present technology.

  That is, FIG. 6 is a diagram illustrating a configuration example of an embodiment of an image sensor to which the present technology is applied.

  The image sensor 10 includes a pixel array unit 11, an address decoder 12, a pixel timing driving unit 13, an AD conversion unit 14, and a sensor controller 15.

  In the pixel array unit 11, a plurality of pixels 11 </ b> P that output an electric (voltage) signal corresponding to the electric charge obtained by photoelectric conversion are two-dimensionally arranged. The address decoder 12 and the pixel timing driving unit 13 control the driving of each pixel 11P arranged in the pixel array unit 11. That is, the address decoder 12 supplies a control signal for designating the pixel 11P to be driven to the pixel timing driving unit 13 in accordance with the address and latch signal supplied from the sensor controller 15. The pixel timing driving unit 13 drives the pixel 11P (the FET that constitutes the pixel 11P) in accordance with the driving timing signal supplied from the sensor controller 15 and the control signal supplied from the address decoder 12. The AD conversion unit 14 AD-converts the electrical signal output from the pixel array unit 11 and supplied via the vertical signal line VSL, and outputs it to the subsequent stage. The sensor controller 15 controls the entire image sensor 10. That is, for example, the sensor controller 15 supplies an address and a latch signal to the address decoder 12 and supplies a drive timing signal to the pixel timing driver 13. In addition, the sensor controller 15 supplies a control signal for controlling AD conversion to the AD conversion unit 14. Among the components of the image sensor 10 described above, the present technology particularly relates to the AD conversion unit 14.

  Details of the configuration of the pixel 11P and the configuration of the AD conversion unit 14 will be described later.

<Configuration Example of Pixel 11P>
FIG. 7 shows a configuration example of the pixel 11 </ b> P arranged in the pixel array unit 11. The pixel 11P is a 7Tr. (Transistor) type single pixel type pixel, and has SP1 which is a high sensitivity PD, SP2 which is a low sensitivity PD, and a pixel internal capacity FC. Further, the pixel 11P includes a transfer gate (transfer transistor) TG1 corresponding to SP1, a transfer gate (transfer transistor) TG2 corresponding to SP2, an amplifier gate (amplifier transistor) AMP, a selection gate (selection transistor) SEL, and a reset gate (reset). Transistor) RST, FD gate (FD transistor) FDG, and FC gate (FC transistor) FCG.

  The intra-pixel capacitor FC is a capacitor that accumulates charges overflowing from SP2, and the low sensitivity / high D-range (saturation expansion) of SP2 can be realized by reading the charges of SP2 and FC. Since FC is reset when P-phase data is read, SP2 is DDS-driven to read D-phase data first and read P-phase data later as described above.

  In the pixel 11P, the charge read from SP1 or SP2 is held in the FD, and then output to the vertical signal line VSL via the AMP and SEL as an electrical signal.

  That is, in the pixel 11P, the transfer transistors TG1 and TG2, the amplifier transistor AMP, the selection transistor SEL, the reset transistor RST, the FD transistor FDG, and the FC transistor FCG are configured by FETs (Field Effect Transistors). In the pixel 11P, the drain of the transfer transistor TG1 and the gate of the amplifier transistor AMP are connected, and an FD is formed at the connection point between the drain of the transfer transistor TG1 and the gate of the amplifier transistor AMP.

  In the pixel 11P, the cathode of SP1, whose anode is grounded, is connected to the FD via the transfer transistor TG1. The FD is connected to the power supply via the FD transistor FDG and the reset transistor RST. The FD transistor FDG is a transistor for controlling the conversion efficiency of the pixel 11P (for example, the conversion efficiency from charge to voltage).

  The connection point between the FD transistor FDG and the reset transistor RST, that is, the connection point between the drain of the FD transistor FDG and the source of the reset transistor RST is connected to the other end of the intra-pixel capacitance FC, one end of which is grounded via the FC transistor FCG. And the anode is connected to the cathode of the grounded SP2 via the transfer transistor TG2.

  In the pixel 11P, the drain of the amplifier transistor AMP is connected to the power supply, and the source of the amplifier transistor AMP is connected to the vertical signal line VSL via the selection transistor SEL.

  The pixel timing driver 13 (FIG. 6) drives the pixel 11P by controlling on / off of the transfer transistors TG1 and TG2, the selection transistor SEL, the reset transistor RST, the FD transistor FDG, and the FC transistor FCG.

  In the pixel 11P configured as described above, SP1 photoelectrically converts and accumulates light incident on the pixel 11P. The charge photoelectrically converted and stored in SP1 is transferred to and stored in FD via the transfer transistor TG1.

  The charge obtained by photoelectric conversion of SP1 (hereinafter also referred to as SP1 charge) is accumulated in the FD to be converted into a voltage corresponding to the charge, and the vertical signal is passed through the amplifier transistor AMP and the selection transistor SEL. Output to line VSL.

  In the pixel 11P, SP2 photoelectrically converts and accumulates the light incident on the pixel 11P. Since SP2 is a PD with a small size, the charge of SP2 (charge obtained by the photoelectric conversion of SP2) overflows from SP2 even if the light incident on the pixel 11P is not so strong.

  The electric charge overflowing from SP2 is accumulated in the pixel internal capacity FC.

  The charge stored in SP2 and the charge stored in the pixel internal capacitor FC are transferred to and stored in the FD via the FC transistor FCG and the FD transistor FDG.

  As described above, the charge accumulated in SP2 and the charge accumulated in the pixel internal capacitor FC are converted into a voltage by being accumulated in FD, and the vertical signal is passed through the amplifier transistor AMP and the selection transistor SEL. Output to line VSL.

  Therefore, in the pixel 11P, the charge of SP2 (charge obtained by photoelectric conversion of SP2) is accumulated in SP2 and the pixel capacitance FC, and a voltage corresponding to the charge is output from the pixel 11P.

  Since SP2 is a small PD, it has low sensitivity. However, since the charge overflowing from SP2 is accumulated in the pixel capacitance FC, the amount of charge until SP2 is saturated (saturated charge) is apparently It becomes large and a wide (high) dynamic range can be realized.

  Note that if CDS drive is used for reading SP2 charge (output of a voltage corresponding to SP2 charge), that is, reading the charge accumulated in SP2 and the charge accumulated in the pixel capacitance FC, P The FD is reset to the power supply voltage via the reset transistor RST and the FD transistor FDG immediately before the P phase that is performed earlier of the phase and the D phase. At that time, the FC is also reset.

  For this reason, the DDS drive with the D phase first and the P phase later is adopted for reading the charges of SP2.

  FIG. 8 shows the drive timing of the pixel 11P. As shown in the figure, in the pixel 11P, after the P-phase data of SP1 is read, the D-phase data of SP1 is read. Next, after the D-phase data of SP2 is read, the P-phase data of SP2 is read. Note that the Ramp wave in FIG. 8 does not apply the present technology, and shows a linear waveform.

  FIG. 8 shows ON / OFF timings of the selection transistor SEL, the FD transistor FDG, the reset transistor RST, the transfer transistors TG2 and TG1, and the FC transistor FCG.

  Further, FIG. 8 shows VSL voltages VSL1 and VSL2 as signals read from the pixel 11P, and a reference signal (currently) input to the input terminal of the comparator 23 constituting the AD converter 14 (FIGS. 6 and 10). In addition, an output (comparator output) VCO of the comparator 23 is shown.

  In addition, in FIG. 8, the horizontal synchronizing signal XHS is also shown. In FIG. 8, a linear reference signal is shown as a reference signal for the sake of simplicity.

  Further, in FIG. 8, a VSL voltage VSL1 represents a VSL voltage (VSL potential) on the vertical signal line VSL. The VSL voltage VSL2 is the VSL voltage (CM (Comparator) internal potential) that is (currently) input to the input terminal of the comparator 23 constituting the AD converter 14 (FIGS. 6 and 10), that is, the VSL voltage VSL1. Represents a voltage offset according to the voltage of the capacitor C1 immediately before the input terminal of the comparator 23.

  In the AD conversion unit 14, so-called auto-zero processing is performed, and when the auto-zero processing is performed, the voltage input to the two input terminals of the comparator 23 (currently) is equalized. The voltages of the immediately preceding capacitors C1 and C2 (FIG. 10) are adjusted. The VSL voltage VSL2 represents the VSL voltage input to the input terminal of the comparator 23 after the voltages of the capacitors C1 and C2 are adjusted by the auto-zero process as described above. For the VSL voltages VSL1 and VSL2, the VSL voltage when dark is represented by a solid line, and the VSL voltage when bright is represented by a dotted line.

  As the driving of the pixel P11, for example, first, CDS driving for reading a digital code corresponding to the charge of SP1 is performed, and then DDS driving for reading the digital code corresponding to the charge of SP2.

  That is, first, the selection transistor SEL is turned on, the FD transistor FDG is turned on, the reset transistor RST is turned off, the transfer transistors TG2 and TG1 are turned off, and the FC transistor FCG is turned off.

  In CDS driving, at time t1, the reset transistor RST is temporarily turned on and the FD is reset. The VSL voltages VSL1 and VSL2 change due to the reset of the FD and the subsequent reset feedthrough.

  In addition, auto-zero processing is performed, so that at time t2, the VSL voltage VSL2 (input to the input terminal of the comparator 23) and the reference signal (voltage is input to the comparator 23) are input to the comparator 23. The reference signal offset in accordance with the voltage of the capacitor C2 immediately before the input terminal of the input terminal), and the reference signal is increased by a predetermined value.

  At time t3, the P1 phase of the CDS drive of SP1 is started, and the reference signal starts to fall (decrease). The decrease in the reference signal continues until time t4 when the P phase of the CDS drive of SP1 ends.

  In the P1 phase of SP1 CDS drive, when the magnitude relationship between the reference signal and the VSL voltage VSL2 is reversed from the start of the P phase, the comparator output VCO of the comparator 23 is inverted, for example, from H (High) level to L (Low ) Become a level.

  The counter 24 constituting the AD converter 14 (FIGS. 6 and 10) starts counting the count value from the start of the P phase of the CDS drive of SP1, and when the comparator output VCO is inverted, the comparator output VCO In response to this, the count value is counted. The count value at this time is P-phase data as the AD conversion result of the noise signal for SP1.

  As described above, in the AD conversion unit 14, the count value obtained by counting the time required for the change of the reference signal until the VSL voltage VSL2 (electric signal) matches the reference signal according to the comparator output VCO. Is obtained as the AD conversion result of the VSL voltage.

  Thereafter, at time t5, the transfer transistor TG1 is temporarily turned on, and the charge of SP1 is transferred to the FD and stored. The VSL voltages VSL1 and VSL2 change (decrease) to voltages corresponding to the charges of SP1 accumulated in the FD. Note that the amount of SP1 charge (the amount of negative charge) increases at high illuminance (when bright), so the VSL voltage VSL1 is lower than at low illuminance (when dark). .

  On the other hand, after the end of the P phase of the CDS drive of SP1, the reference signal is raised to the voltage at the start of the P phase.

  Then, at time t6 after the transfer transistor TG1 is temporarily turned on, the D phase of the CDS drive of SP1 is started, and the reference signal starts to fall. The decrease in the reference signal continues until time t7 when the D phase of the CDS drive of SP1 ends.

  In the D phase of CDS drive of SP1, when the magnitude relationship between the reference signal and the VSL voltage VSL2 is reversed from the start of the D phase, the comparator output VCO of the comparator 23 is inverted, for example, from H level to L level.

  The counter 24 constituting the AD conversion unit 14 starts counting the count value from the start of the D phase of CDS driving of SP1, and ends the counting of the count value when the comparator output VCO is inverted. The count value at this time is D-phase data as the AD conversion result of the data signal for SP1.

  After time t7 when the D phase of the CDS drive of SP1 ends, the DDS drive of SP2 is started.

  In the DDS driving of SP2, the selection transistor SEL is temporarily turned off. Further, during a part of the period in which the selection transistor SEL is turned off, the reset transistor RST is temporarily turned on and the FD is reset.

  Then, in the period in which the selection transistor SEL is turned off, the FC transistor FCG is turned on after the period in which the reset transistor RST is turned on.

  When the FC transistor FCG is turned on, the electric charge accumulated in the pixel capacitance FC is transferred to the FD and accumulated.

  Thereafter, at time t8 after the selection transistor SEL is turned on, the transfer transistor TG2 is temporarily turned on, and the charge accumulated in the SP2 is transferred to the FD via the FC transistor FCG and the FD transistor FDG. Accumulated.

  As a result, the charge accumulated in the intra-pixel capacitor FC and the charge accumulated in the SP2 are accumulated in the FD, and the VSL voltages VSL1 and VSL2 change to voltages corresponding to the charges accumulated in the FD.

  Note that the amount of charge accumulated in SP2 and the pixel capacitance FC (the amount of negative charge) increases at high illumination (when bright), so the VSL voltage VSL1 is low (when dark). Compared to

  Thereafter, auto-zero processing is performed, whereby the VSL voltage VSL2 (input to the input terminal of the comparator 23) and the reference signal (voltage is input to the input terminal of the comparator 23) are input to the input terminal of the comparator 23. The reference signal offset according to the voltage of the immediately preceding capacitor C2), and at time t9, the reference signal is increased by a predetermined value.

  At time t10, the D phase of the DDS driving of SP2 is started, and the reference signal starts to fall. The decrease in the reference signal continues until time t11 when the D phase of the DDS driving of SP2 ends.

  In the D phase of SP2 DDS drive, when the magnitude relationship between the reference signal and the VSL voltage VSL2 is reversed from the start of the D phase, the comparator output VCO of the comparator 23 is inverted and changes from the H level to the L level.

  The counter 24 included in the AD conversion unit 14 starts counting the count value from the start of the D phase of SP2 DDS driving, and ends the count value counting when the comparator output VCO is inverted. The count value at this time is D-phase data as the AD conversion result of the data signal for SP2.

  Thereafter, at time t12, the reset transistor RST is temporarily turned on, and the FD is reset.

  In the reset of FD, the charges accumulated in FD and accumulated in SP2 and in-pixel capacitance FC are released to the power supply, so that the VSL voltages VSL1 and VSL2 increase by the amount corresponding to the charge. That is, at high illuminance (when bright), the VSL voltages VSL1 and VSL2 rise more than at low illuminance (when dark).

  On the other hand, after completion of the D phase of SP2 DDS driving, the reference signal is raised to a voltage higher by the dynamic range of the AD conversion unit 14 than the voltage at the start of the D phase.

  Then, at time t13 after the reset transistor RST is temporarily turned on, the P phase of the DDS drive of SP2 is started, and the reference signal starts to fall. The decrease in the reference signal continues until time t14 when the P phase of the DDS driving of SP2 ends.

  In the P phase of the DDS drive of SP2, when the magnitude relationship between the reference signal and the VSL voltage VSL2 is reversed from the start of the P phase, the comparator output VCO of the comparator 23 is inverted and changes from the H level to the L level.

  The counter 24 constituting the AD converter 14 starts counting the count value from the start of the P phase of the DDS driving of SP2, and ends the count value when the comparator output VCO is inverted. The count value at this time is P-phase data as the AD conversion result of the noise signal for SP2.

  In the driving of the pixel 11P as described above, the image sensor 10 (FIG. 6) uses the nonlinear reference signal described in FIG. 3 as the P-phase reference signal for the DDS driving of SP2.

  FIG. 9 shows an arrangement example of SP1 and SP2 in the pixel 11P. In the figure, SP2 is arranged at the upper left in the area of one pixel, but SP2 can be arranged at an arbitrary position in the area of one pixel.

  9A is a plan view showing an outline of the layout of SP1 and SP2 in the pixel 11P.

  FIG. 9B is a plan view showing details of the layout of SP1 and SP2 in the pixel 11P.

  In FIG. 9B, R, G, and B are SP1 or PD as a PD that photoelectrically converts R (Red), G (Green), and B (Blue) light through a Bayer array color filter, respectively. Represents SP2.

  As shown in FIG. 9B, one pixel 11P may be configured by arranging SP2 which is a small size PD in the upper right, upper left, lower right and lower left of SP1 which is a large size PD. it can.

  Here, in FIG. 9B, a Bayer array color filter is employed, and in the horizontal × vertical 2 × 2 pixels 11P, the upper left pixel 11P receives the R light, and the upper right pixel 11P The pixel that receives the G light, the lower left pixel 11P is the pixel that receives the G light, and the lower right pixel 11P is the pixel that receives the B light. It is not limited to the Bayer array.

  Now, in the 2 × 2 pixels 11P, as described above, the upper left pixel 11P has the R light, the upper right pixel 11P has the G light, the lower left pixel 11P has the G light, and the lower right pixel. The array of color filters for receiving the light of 11P by B is described as an RGGB array by arranging the light received by the pixels 11P in the order of the upper left, upper right, lower left, and lower right pixels 11P.

  As the color filter array, not only the RGGB array but also an array in which an RCCC array, an RCCB array, an RCCC array, an RCCB array, and an RGGB array are mixed can be employed. Here, in the RCCC array and the RCCB array, C (Clear) represents a pixel that has no color filter and receives light of all wavelengths.

<Configuration example of AD converter>
Next, FIG. 10 illustrates a configuration example of the AD conversion unit 14. The AD conversion unit 14 includes a constant current circuit 21, a single slope type DA converter 22 for performing AD conversion on the output of the pixel array unit 11 input via the VLS, a comparator 23, and a counter 24.

  The constant current circuit 21 is connected to the vertical signal line VSL and constitutes a source follower circuit together with the amplifier transistor AMP of the pixel 11P.

  The DA converter 22 generates and outputs a reference signal (as a voltage) by performing DA conversion. The reference signal output from the DA converter 22 is supplied to one input terminal of the comparator 23 via the capacitor C2.

  The comparator 23 has two input terminals, and one of the input terminals is supplied with the reference signal output from the DA converter 22 via the capacitor C2 as described above. The other input terminal of the comparator 23 is supplied with a VSL voltage as an electric signal output from the pixel 11P from the vertical signal line VSL via the capacitor C1.

  The comparator 23 compares the VSL voltage (VSL2) supplied to the two input terminals with the reference signal, and outputs a comparator output VCO representing the comparison result. That is, the comparator 23 outputs a comparator output VCO that represents the magnitude relationship between the VSL voltage (VSL2) and the reference signal. The comparator output VCO of the comparator 23 is supplied to the counter 24.

  The counter 24 counts the count value in synchronization with a predetermined clock. That is, the counter 24 starts counting the count value from the start of the P phase or the D phase, and counts the count value until the magnitude relationship between the VSL voltage and the reference signal changes and the comparator output VCO is inverted. The counter 24 stops counting the count value when the comparator output VCO is inverted, and outputs the count value at that time as an AD conversion result (output data) of the VSL voltage.

  The AD conversion unit 14 includes a constant current circuit 21, a comparator 23 including capacitors C1 and C2, and a counter 24, for example, for each column of the pixels 11P of the pixel array unit 11.

  The reference signal output from the DA converter 22 is supplied to the comparator 23 in each column of the pixel 11P.

  FIG. 11 shows the drive timing of the AD conversion unit 14. As described above, AD conversion is performed by CDS driving for SP1 and DDS driving for SP2.

  That is, FIG. 11 shows the horizontal synchronization signal XHS, the reference signal, the VSL voltage VSL2, the comparator output VCO, and the count operation of the counter 24 (FIG. 10).

  In FIG. 11, the horizontal synchronization signal XHS, the reference signal, the VSL voltage VSL2, and the comparator output VCO are the same as those in FIG. 8, and description thereof is omitted.

  The counter 24 starts to count down the count value from the start of the P1 phase of CDS driving of SP1, and finishes counting the count value when the comparator output VCO is inverted.

  Then, the counter 24 sets a value obtained by inverting the sign of the current count value as an initial value, starts counting the count value from the start of the D phase of the SP1 CDS drive, and the comparator output VCO is inverted. Then, the count of the count value is finished.

  The count value at this time is a subtraction value (PD phase count value) obtained by subtracting the D phase data that is the AD conversion value of the data signal from the P phase data that is the AD conversion value of the noise signal for SP1. For example, a value obtained by inverting the sign of the subtraction value becomes a digital code corresponding to the charge of SP1.

  Thereafter, the counter 24 resets the count value to zero. Then, the counter 24 starts to count down the count value from the start of the D phase of DDS driving of SP2, and ends the count value when the comparator output VCO is inverted.

  The counter 24 sets a value obtained by inverting the sign of the current count value as an initial value, starts counting down from the start of the P phase of SP2 DDS drive, and the comparator output VCO is inverted. Then, the count of the count value is finished.

  The count value at this time is the value obtained by inverting the sign of the subtraction value obtained by subtracting the D phase data that is the AD conversion value of the data signal from the P phase data that is the AD conversion value of the noise signal ((PD phase count) Value) × (−1)). For example, a value obtained by inverting the sign of this value is a digital code corresponding to the charge of SP2.

<Configuration example of DA converter 22>
FIG. 12 shows a configuration example of the DA converter 22 of the AD conversion unit 14. The DA converter 22 generates an IREF circuit 31 that generates a reference current, a PGC DAC 32 that changes a current ratio according to a gain, a CLP DAC 33 that outputs a dark current of the pixel array unit 11 by offset, and a ramp slope. Ramp DAC 34 for this purpose. Among the components of the DA converter 22 described above, the present technology particularly relates to the PGC DAC 32 and the Ramp DAC 34.

  In FIG. 12, the DA converter 22 includes an IREF (I-reference) circuit 31, a PGC (Programmable Gain Control) DAC 32, a CLP (Clamp) DAC 33, a Ramp DAC 34, and a termination resistor R.

  The IREF circuit 31 includes an operational amplifier 101, an FET 102, and a resistor 103, and generates a current corresponding to a voltage supplied to the IREF circuit 31. The current generated by the IREF circuit 31 is output as a reference current.

  The PGC DAC 32 includes FETs 111 and 112 and switches 113 and 114.

  The FETs 111 and 112 constitute a current mirror having the FET 111 as a mirror source of the current mirror and the FET 112 as a mirror destination of the current mirror. Therefore, a current corresponding to a current flowing through the FET 111 that is the mirror source (a current that is a mirror ratio times the current flowing through the FET 111) flows through the FET 112 that is the mirror destination.

  Here, in FIG. 12, the arrows described in the mirror destination FET 112 indicate that the FET 112 is a plurality of FETs, and the plurality of FETs are connected in parallel to the mirror source FET 111. There are a plurality of sets of switches 113 and 114 connected to the FET 112 in accordance with the fact that the FET 112 is a plurality of FETs.

  Switches 113 and 114 are exclusively turned on or off. That is, when one of the switches 113 and 114 is on, the other switch is off.

  When the switch 113 is on (thus, when the switch 114 is off), the current flowing through the FET 112 is discarded to the power supply VSS such as GND (ground). When the switch 114 is on (and therefore the switch 113 is off), the current that flows through the FET 112 flows through FETs 151 and 152, which will be described later, constituting the Ramp DAC 34.

  Here, when the switches 113 and 114 are exclusively turned on or off, the current flowing from the power supply VDD in the DA converter 22 does not change and remains constant by turning the switches 113 and 114 on and off. Can be prevented from changing as a reference signal due to a change in the current flowing from.

  In the PGC DAC 32, the current flowing through the mirror FETs 151 and 152 constituting the Ramp DAC 34 can be controlled by controlling the number of FETs that turn on the switch 114 among the plurality of FETs as the FET 112. By changing the currents flowing through the mirror FETs 151 and 152 constituting the Ramp DAC 34, the gain (slope) of the reference signal can be changed to generate a nonlinear reference signal.

  The CLP DAC 33 includes FETs 121 and 122, FETs 123 and 124, FETs 125 and 126, FETs 127 and 128, FETs 129 and 130, switches 131 and 132, FETs 133 and 134, FETs 135 and 136, switches 137 and 138, FETs 141, FET 142, and FET 143. Composed.

  The FETs 121 to 126 constitute current mirrors having the FETs 121 and 122 as mirror sources and the FETs 123 and 124 and FETs 125 and 126 as mirror destinations, respectively.

  The reference current generated by the IREF circuit 31 flows in the mirror source FETs 121 and 122, and the reference currents flowing in the mirror source FETs 121 and 122 are respectively transmitted to the mirror destination FETs 123 and 124 and the FETs 125 and 126. A corresponding current flows.

  The current flowing through the FETs 123 and 124 flows through the FET 112 of the PGC DAC 32, and the current flowing through the FETs 125 and 126 flows through the FET 141.

  Here, the FETs 141 to 143 constitute a current mirror having the FET 141 as a mirror source and the FET 142 and the FET 143 as mirror destinations, respectively.

  Accordingly, a current corresponding to the current flowing in the mirror-source FET 141 flows in the FET 142 and FET 143 which are mirror destinations.

  The current that flows in the FET 142 flows in FETs 127 and 128 that constitute a COARSE CLP circuit described later, and the current that flows in the FET 143 flows in FETs 133 and 134 that configure a FINE CLP circuit described later.

  The FETs 127 and 128 and the FETs 129 and 130 constitute a current mirror having the FETs 127 and 128 as mirror sources of the current mirror and the FETs 129 and 130 as mirror destinations of the current mirror. Therefore, a current corresponding to the current flowing through the FETs 127 and 128 as the mirror sources flows through the FETs 129 and 130 as the mirror destinations.

  Here, in FIG. 12, the arrows described in the mirror destination FETs 129 and 130 indicate that each of the FETs 129 and 130 is a plurality of FETs as in the case of the FET 112, and the plurality of FETs are the mirror source FETs 127 and 130. 128 is connected in parallel. Note that there are a plurality of sets of switches 131 and 132 connected to the FETs 129 and 130 according to the fact that each of the FETs 129 and 130 is a plurality of FETs.

  Like the switches 113 and 114, the switches 131 and 132 are exclusively turned on or off.

  When the switch 131 is on (and therefore the switch 132 is off), the current flowing through the FETs 129 and 130 is discarded to the power supply VSS such as GND. When switch 132 is on (and therefore switch 131 is off), the current through FETs 129 and 130 flows through the reference signal output line. The current flowing through the reference signal output line flows through the termination resistor R, and a voltage drop caused by the current flowing through the termination resistor R is output from the DA converter 22 as a reference signal (voltage).

  Similar to the switches 113 and 114, when the switches 131 and 132 are exclusively turned on or off, the current flowing from the power supply VDD in the DA converter 22 does not change by the on / off of the switches 131 and 132, and is constant. Thus, it is possible to prevent the fluctuation of the voltage as the reference signal due to the change in the current flowing from the power supply VDD.

  The FETs 133 and 134 and the FETs 135 and 136 constitute a current mirror having the FETs 133 and 134 as mirror sources of the current mirror and the FETs 135 and 136 as mirror destinations of the current mirror. Therefore, a current corresponding to the current flowing in the FETs 133 and 134 that are mirror sources flows through the FETs 135 and 136 that are mirror destinations.

  Here, in FIG. 12, the arrows described in the mirror destination FETs 135 and 136 indicate that each of the FETs 135 and 136 is a plurality of FETs, as in the case of the FET 112, and the plurality of FETs are the mirror source FETs 133 and 136. 134 is connected in parallel. Note that there are a plurality of sets of switches 137 and 138 connected to the FETs 135 and 136 according to the fact that each of the FETs 135 and 136 is a plurality of FETs.

  Switches 137 and 138 are exclusively turned on or off, similar to switches 113 and 114.

  When switch 137 is on (and therefore switch 138 is off), the current flowing through FETs 135 and 136 is discarded to power supply VSS such as GND. When switch 138 is on (and therefore switch 137 is off), the current through FETs 135 and 136 flows through the reference signal output line. The current flowing through the reference signal output line flows through the termination resistor R, and a voltage drop caused by the current flowing through the termination resistor R is output from the DA converter 22 as a reference signal (voltage).

  Similar to the switches 113 and 114, when the switches 137 and 138 are exclusively turned on or off, the current flowing from the power supply VDD in the DA converter 22 does not change by the on / off of the switches 137 and 138, and is constant. Thus, it is possible to prevent the fluctuation of the voltage as the reference signal due to the change in the current flowing from the power supply VDD.

  The CLP DAC 33 controls the number of FETs that turn on the switch 132 among the plurality of FETs as the FETs 129 and 130, and turns on the switch 138 among the plurality of FETs as the FETs 135 and 136, respectively. By controlling the number of FETs, a current for adjusting (clamping) a voltage as a reference signal is supplied to the reference signal output line in order to cancel the dark current flowing through the pixel 11P.

  Here, in the CLP DAC 33, FETs 127 and 128, FETs 129 and 130, and switches 131 and 132 constitute a COARSE CLP circuit, and FETs 133 and 134, FETs 135 and 136, and switches 137 and 138 constitute a FINE CLP circuit. Configure.

  According to the COARSE CLP circuit, the current on the reference signal output line for canceling the dark current flowing through the pixel 11P is roughly adjusted. According to the FINE CLP circuit, the dark current flowing through the pixel 11P is canceled. Fine adjustment of the current on the reference signal output line is performed.

  The Ramp DAC 34 includes FETs 151 and 152, FETs 153 and 154, and switches 155 and 156.

  The FETs 151 and 152 and the FETs 153 and 154 constitute a current mirror having the FETs 151 and 152 as the mirror source of the current mirror and the FETs 153 and 154 as the mirror destination of the current mirror. Therefore, a current corresponding to the current flowing through the FETs 151 and 152 that are mirror sources flows through the FETs 153 and 154 that are mirror destinations.

  Here, in FIG. 12, the arrows described in the mirror destination FETs 153 and 154 indicate that each of the FETs 153 and 154 is a plurality of FETs as in the case of the FET 112, and the plurality of FETs are the mirror source FETs 151 and 154. 152 is connected in parallel. Note that there are a plurality of sets of switches 155 and 156 connected to the FETs 153 and 154 according to the fact that each of the FETs 153 and 154 is a plurality of FETs.

  Switches 155 and 156 are exclusively turned on or off, similar to switches 113 and 114.

  When the switch 155 is on (and therefore the switch 156 is off), the current flowing through the FETs 153 and 154 is discarded to the power supply VSS such as GND. When switch 156 is on (and therefore switch 155 is off), the current through FETs 153 and 154 flows through the reference signal output line. The current flowing through the reference signal output line flows through the termination resistor R, and a voltage drop caused by the current flowing through the termination resistor R is output from the DA converter 22 as a reference signal (voltage).

  Similar to the switches 113 and 114, when the switches 155 and 156 are exclusively turned on or off, the current flowing from the power supply VDD in the DA converter 22 does not change by the on / off of the switches 155 and 156, and remains constant. Thus, it is possible to prevent the fluctuation of the voltage as the reference signal due to the change in the current flowing from the power supply VDD.

  In the Ramp DAC 34, the current flowing through the reference signal output line is increased or decreased by controlling the number of FETs that turn on or off the switch 156 among the plurality of FETs as the FETs 153 and 154, respectively.

  That is, in the P phase and the D phase, among the plurality of FETs as the FETs 153 and 154, the number of FETs with the switch 156 turned on is gradually reduced, so that the current flowing through the reference signal output line is gradually reduced. Is done. As a result, the reference signal (voltage) gradually decreases in the P phase and the D phase.

  In the DA converter 22 configured as described above, in the Ramp DAC 34, a current (hereinafter also referred to as a unit current) according to the number of switches 114 that are turned on flows in the FETs 151 and 152 that are mirror sources.

  Here, in order to simplify the explanation, the mirror ratio of the current mirror composed of the FETs 151 to 154 is assumed to be 1: 1. In this case, in the Ramp DAC 34, a current obtained by multiplying, for example, the unit current flowing in the FETs 151 and 152, which are mirror sources, by several times the switch 156 that is turned on flows in the reference signal output line.

  In the P phase and the D phase, the number of switches 156 that are turned on is sequentially reduced, that is, the plurality of switches 156 are sequentially turned from on to off, so that the reference signal output line is changed. The flowing current and thus the reference signal is gradually reduced.

  As described above, in the reference signal output line, a current obtained by multiplying the unit current by several times the ON switch 156 flows, and the current flowing in the reference signal output line does not change if the unit current does not change. As the number of switches 156 that are turned on decreases linearly in time, the reference signal decreases linearly.

  Therefore, the reference signal can be changed nonlinearly by, for example, changing (decreasing) the number of switches 156 that are turned on nonlinearly.

  Further, changing the reference signal in a non-linear manner changes the amount of change in the reference signal (voltage) every time the number of switches 156 turned on changes by changing the unit current, for example. Can be performed.

  That is, in the DA converter 22, for example, the non-linear reference signal (voltage) is linearly decreased by sequentially turning off one half of the plurality of switches 156. Further, the DA converter 22 performs clearing to turn on all of the plurality of switches 156, reduces the current flowing through one switch 156 to ½, and switches half of the plurality of switches 156 156. By sequentially turning off, it is possible to change the slope of the nonlinear reference signal before and after clearing by linearly decreasing the nonlinear reference signal.

  The switches 113 and 114, the switches 131 and 132, the switches 137 and 138, and the switches 155 and 156 (a plurality of switches respectively) are controlled by, for example, the sensor controller 15 (FIG. 6).

<Configuration example of Ramp DAC 34>
FIG. 13 shows a configuration example of the shift register that forms the Ramp DAC 34. In the Ramp DAC 34, the shift register becomes Hi output in the order of Q1, Q2, Q3,..., Q # N (N is an arbitrary integer) according to the clock (CLK), and this Hi output is the current source of the Ramp DAC 34. And the ramp slope is generated. Regarding N of Q # N, when the ramp slope is nonlinear (when the P phase of SP2 is AD converted), N is when the ramp slope is linear (for example, when the D phase of SP1 is AD converted) ) And N can be set to a large value.

  That is, FIG. 13 is a circuit diagram showing a detailed configuration example of the Ramp DAC 34 of FIG.

  In FIG. 13, the Ramp DAC 34 includes FETs 151 and 152, FETs 171-1 to 171-N and 172-1 to 172-N, FETs 173-1 to 173-N and 174-1 to 174-N, and DFF (D flip-flop). B) 181-1 to 181-N.

  In FIG. 12, illustration of DFFs 181-1 to 181-N is omitted in order to avoid the drawing from being complicated.

  The FETs 151 and 152 and the FETs 171-1 to 171-N and 172-1 to 172-N constitute a current mirror.

  The FETs 151 and 152 constitute the mirror source of the current mirror as described with reference to FIG.

  FETs 171-1 to 171-N and 172-1 to 172-N are a plurality of FETs as FETs 153 and 154, which are mirror destinations of the current mirror in FIG. That is, the FETs 171-1 to 171-N are a plurality of FETs as the FET 153 in FIG. 12, and the FETs 172-1 to 172-N are a plurality of FETs as the FET 154 in FIG.

  The mirror destination FETs 171-n and 172-n (n = 1, 2,..., N) are connected to the power supply VSS such as GND through the FET 173-n and also through the FET 174-n. Connected to the reference signal output line.

  The FETs 173-1 to 173-N are a plurality of switches as the switch 155 in FIG. 12, and the FETs 174-1 to 174-N are a plurality of switches as the switch 156 in FIG.

  The output signal Q # n of DFF181-n is supplied to the gate of the FET 173-n (n = 1, 2,..., N). Therefore, the FET 173-n is turned on or off according to the output signal Q # n.

  An inverted signal XQ # n obtained by inverting the output signal Q # n of DFF181-n is supplied to the gate of the FET 174-n. Therefore, the FET 174-n is turned on or off according to the inverted signal XQ # n.

  As described above, the FET 173-n is turned on or off according to the output signal Q # n, and the FET 174-n is turned on or off according to the inverted signal XQ # n, so that the FETs 173-n and 174- n is exclusively turned on or off.

  DFFs 181-1 to 181-N are connected in series and constitute a shift register.

  A clock CLK and a clear signal CLR are supplied to the DFF 181 -n, and an output signal Q # n-1 is supplied from the preceding stage DFF 181-(n−1).

  The DFF 181-n receives the output signal Q # n-1 supplied from the preceding stage DFF181- (n-1) as an input signal, latches the input signal Q # n-1 in synchronization with the clock CLK, and outputs it. Output as signal Q # n.

  A predetermined drive signal D is supplied as an input signal, for example, from the sensor controller 15 to the first DFF 181-1 among the DFFs 181-1 to 181-N. In the shift register composed of DFF 181-1 to 181-N, the drive signal D is sequentially latched from the first DFF 181-1 to the subsequent DFF 181-n.

  When the clear signal CLR (L level) is supplied, the DFF 181 -n clears (resets) the inside and outputs the L level as the output signal Q # n. In this case, all the inverted signals XQ # n are at the H level, and the FETs 174-1 to 174-N as the switch 156 in FIG. 12 are all turned on. As described above, turning on all the N FETs 174-1 to 174-N as all the switches 156 by supplying the clear signal CLR to the DFF 181-n is also referred to as clearing the Ramp DAC 34. .

  In the Ramp DAC 34 configured as described above, the output signal Q1 of the first DFF 181-1 becomes H level in the shift register composed of DFFs 181-1 to 181-N, and then the output of the subsequent DFF 181-n. The signal Q # n sequentially becomes H level. Therefore, the inversion signal XQ # n sequentially becomes L level from n = 1.

  As a result, the FET 174-n as the switch 156 in FIG. 12 is sequentially turned off from n = 1 in accordance with the inverted signal XQ # n, and the current flowing from the FET 174-n through the reference signal output line is reduced. As a result, the reference signal (voltage) decreases.

  That is, in the DA converter 22, the nonlinear reference signal (voltage) is linearized by sequentially turning off, for example, the FETs 174-1 to 174 -N / 2 as the ½ switch 156 of the plurality of switches 156. Reduce to. Further, the DA converter 22 clears the Ramp DAC 34 that turns on all the N FETs 174-1 to 174-N as the plurality of switches 156, and the current flowing through the FET 174-n as one switch 156, That is, by reducing the unit current to 1/2 and sequentially turning off, for example, the FETs 174-1 to 174 -N / 2 as the ½ switch 156 among the plurality of switches 156, the nonlinear reference signal By linearly decreasing the slope of the nonlinear reference signal before and after clearing.

  The Ramp DAC 34 can be cleared by supplying a clear signal CLR to the DFFs 181-1 to 181-N. The unit current flowing through the FET 174-n as the switch 156 can be reduced by turning off one or more of the switches 114 that are turned on in the PGC DAC 32 of FIG.

<First Driving Example of DA Converter 22>
FIG. 14 shows the level shifter output corresponding to the first driving example of the DA converter 22. FIG. 15 shows a ramp waveform corresponding to the level shifter output shown in FIG.

  The output of the shift register shown in FIG. 13 corresponds to Q1 to Q96 in FIG. Q1 to Q96 all output Lo because the level shifter is reset when the CLR signal is output Lo. Therefore, if the current source is reset by outputting the CLR signal Lo every time the gain is switched in order to make the Ramp waveform non-linear, a non-linear Ramp waveform as shown in FIG. 15 can be obtained.

  Accordingly, Con res can be improved when the outputs of SP1 and SP2 are combined while maintaining the frame rate and dynamic range.

  However, in the case of the first driving example described above, an erroneous output (unintended output) may occur at the gain switching point due to the influence of the inversion delay of the comparator 23 and the like. Hereinafter, a second driving example for dealing with this will be described.

<Second Driving Example of DA Converter 22>
FIG. 16 shows the level shifter output corresponding to the second driving example of the DA converter 22. FIG. 17 shows a ramp waveform corresponding to the level shifter output shown in FIG.

  In the case of the second driving example, the CLR signal is output Lo every time the gain is switched, and then a WAIT (waiting time) is inserted. Thereby, even if an inversion delay or the like occurs in the comparator 23 or the like, a normal output (intended output) can be obtained, and a code error at the time of gain switching can be avoided.

<Third driving example of DA converter 22>
In the first driving example shown in FIG. 14, the CLR signal is output Lo every time the gain is switched. However, in the third driving example, the timing at which the CLR signal is output Lo can be appropriately changed. Thereby, since the gain switching point becomes variable, it is possible to cope with the situation (light quantity or variation).

  <Driving example of DA converter 22>

  An example of driving the DA converter 22 will be described again.

  FIG. 14 shows a first example of the output signal Q # n of the DFF 181-n supplied to the gate of the FET 173-n (the inverted signal XQ # n supplied to the gate of the FET 174-n) when the DA converter 22 is driven. It is a timing chart which shows the example of.

  FIG. 14 also shows the horizontal synchronization signal XHS, the clear signal CLR, and the drive signal D in addition to the output signal Q # n.

  The drive signal D is a pulse that is at H level during the period of 1 (horizontal) line, and this drive signal D is sequentially latched by, for example, DFF 181-1 to DFF 181-N in FIG. 13 in synchronization with the clock CLK. As a result, the output signals Q1 to Q # N sequentially change from the L level to the H level in synchronization with the clock CLK.

  As described above, when the output signals Q1 to Q # N are sequentially changed from the L level to the H level, the FETs 173-1 to 173-N are sequentially turned from OFF to ON in synchronization with the clock CLK. The FETs 174-1 to 174-N are sequentially turned from on to off in synchronization with the clock CLK.

  The FETs 173-1 to 173-N are sequentially turned from OFF to ON, and the FETs 174-1 to 174-N are sequentially turned from ON to OFF so that a current is supplied to the reference signal output line. The number of −n decreases in synchronization with the clock CLK. As a result, the current flowing through the reference signal output line, and hence the reference signal (voltage), decreases in synchronization with the clock CLK.

  In FIG. 14, the clear signal CLR is received after the count value to be counted in the P # i phase (FIG. 3), which is a sub-period constituting the P phase, before the start of the next P # i + 1 phase. Temporarily changed from H level to L level. When the clear signal CLR becomes L level, the Ramp DAC 34 is cleared as described in FIG.

  The drive signal D becomes H level during the period from the start of the P # i phase until the clear signal CLR becomes the L level, and after the clear signal CLR becomes the L level, until the start of the next P # i phase , Become L level.

  With respect to the drive signal D as described above, the output signal Q # n of the DFF 181-n is as shown in FIG.

  Assuming that N is 96, for example, among P1 phase to P6 phase constituting the P phase, each of P1 phase to P5 phase is 1/2 of DFF 181-1 to 181-96. The output signals Q1 to Q48 of the DFFs 181-1 to 181 to 48 sequentially change from L level to H level in synchronization with the clock.

  Therefore, the inversion signals XQ1 to XQ48 sequentially change from H level to L level in synchronization with the clock, and the FETs 174-1 to 174-48 as the switch 156 (FIG. 12) are sequentially turned off.

  After that, when the clear signal CLR becomes L level and the P # i + 1 phase which is the next sub-period is started, the PGC DAC 32 reduces the unit current flowing in the FET 174-n as one switch 156 to 1 / Reduce to 2.

  As described above, in the P # i + 1 phase, output signals Q1 to Q48 of DFFs 181-1 to 181-48, which are half of DFFs 181-1 to 181 to 96, are sequentially synchronized with the clock. Change from L level to H level.

  In the P6 phase, all the output signals Q1 to Q96 of the DFFs 181-1 to 181 to 96 are sequentially changed from the L level to the H level in synchronization with the clock.

  Therefore, the inversion signals XQ1 to XQ96 sequentially change from H level to L level in synchronization with the clock, and the FETs 174-1 to 174-96 as the switch 156 (FIG. 12) are sequentially turned off.

  FIG. 15 is a waveform diagram showing a nonlinear reference signal when the output signal Q # n of DFF 181-n (inverted signal XQ # n supplied to the gate of FET 174-n) is the signal described in FIG.

  FIG. 15 is a view similar to FIG.

  Now, in the PGC DAC 32, the unit current of the P1 phase is set so that the voltage drop of the termination resistor R becomes 1000 mV when all of the FETs 174-1 to 174-96 as the switch 156 (FIG. 12) are turned on. Shall be washed away. In addition, here, in order to simplify the explanation, it is assumed that the nonlinear reference signal (voltage) is equal to the voltage drop of the termination resistor R.

  In this case, in the P1 phase, the output signals Q1 to Q48 of DFFs 181-1 to 181-48, which are half of DFFs 181-1 to 181 to 96, sequentially change from L level to H level in synchronization with the clock. That is, the inversion signals XQ1 to XQ48 are sequentially changed from the H level to the L level in synchronization with the clock, and the FETs 174-1 to 174-48 as the switch 156 (FIG. 12) are sequentially turned off.

  When one FET 174-n is turned off, the current flowing through the termination resistor R is reduced by the unit current. Therefore, when the FETs 174-1 to 174-48 are sequentially turned off, the non-linear reference signal is in units of unit current. Decrease.

  Since the voltage drop of the terminating resistor R when all of the FETs 174-1 to 174-96 are on is 1000 mV, 1/2 of the FETs 174-1 to 174-96 is 174-1 to 174-48. When is turned off, the nonlinear reference signal drops by 500 mV to 500 mV.

  Thereafter, before the start of the P2 phase, the Ramp DAC 34 is cleared, so that the output signals Q1 to Q96 of the DFFs 181-1 to 181 to 96 all become L level, that is, the inverted signals XQ1 to XQ96 become H level. , FETs 174-1 to 174-96 as switches 156 (FIG. 12) are all turned on.

  At the same time, the PGC DAC 32 (FIG. 12) reduces the unit current flowing in the FET 174-n as one switch 156 by half.

  Before the unit current is reduced to 1/2, the voltage drop of the terminating resistor R when the FETs 174-1 to 174-96 are all on is 1000mV, so the unit current is reduced to 1/2. After that, the voltage drop of the terminating resistor R when all of the FETs 174-1 to 174-96 are turned on becomes 500 mV = 1000 mV / 2.

  Therefore, in the P1 phase, the non-linear reference signal that has decreased from 1000 mV to 500 mV and has reached 500 mV maintains the value that has decreased by 500 mV after the Ramp DAC 34 is cleared and the unit current is decreased.

  After that, when the P2 phase is started, output signals Q1 to Q48 of DFFs 181-1 to 181 to 48, which are half of DFFs 181-1 to 181 to 96, are sequentially shifted from L level to H level in synchronization with the clock. That is, the inverted signals XQ1 to XQ48 are sequentially changed from H level to L level in synchronization with the clock, and the FETs 174-1 to 174-48 as the switch 156 (FIG. 12) are sequentially turned off.

  When one FET 174-n is turned off, the current flowing through the termination resistor R is reduced by the unit current. Therefore, when the FETs 174-1 to 174-48 are sequentially turned off, the non-linear reference signal is in units of unit current. Decrease.

  In the P2 phase, since the unit current is reduced to 1/2 compared to the P1 phase, the slope (the magnitude) of the nonlinear reference signal becomes 1/2. That is, in the P2 phase, the AD conversion gain is twice (6 dB) that in the P1 phase.

  At the start of the P2 phase, since the voltage drop of the termination resistor R when all of the FETs 174-1 to 174-96 are on is 500 mV, 1/2 of the FETs 174 to 174 to 174-96 When -1 through 174-48 are turned off, the nonlinear reference signal is reduced by 250 mV to 250 mV.

  Thereafter, before the start of the P2 phase, the Ramp DAC 34 is cleared, so that the output signals Q1 to Q96 of the DFFs 181-1 to 181 to 96 all become L level, that is, the inverted signals XQ1 to XQ96 become H level. , FETs 174-1 to 174-96 as switches 156 (FIG. 12) are all turned on.

  At the same time, the PGC DAC 32 reduces the unit current flowing through the FET 174-n as one switch 156 by half.

  Before the unit current is reduced to 1/2, the voltage drop of the termination resistor R when the FETs 174-1 to 174-96 are all turned on is 500mV, so the unit current is reduced to 1/2. After that, the voltage drop of the terminating resistor R when all of the FETs 174-1 to 174-96 are turned on becomes 250 mV = 500 mV / 2.

  Therefore, in the P2 phase, the non-linear reference signal which has decreased from 500 mV to 250 mV and becomes 250 mV maintains the value as it is after the Ramp DAC 34 is cleared and the unit current is decreased.

  Thereafter, when the P3 phase is started, the output signals Q1 to Q48 of DFFs 181-1 to 181 to 48, which are half of DFFs 181-1 to 181 to 96, are sequentially shifted from L level to H level in synchronization with the clock. That is, the inverted signals XQ1 to XQ48 are sequentially changed from H level to L level in synchronization with the clock, and the FETs 174-1 to 174-48 as the switch 156 (FIG. 12) are sequentially turned off.

  When one FET 174-n is turned off, the current flowing through the termination resistor R is reduced by the unit current. Therefore, when the FETs 174-1 to 174-48 are sequentially turned off, the non-linear reference signal is in units of unit current. Decrease.

  In the P3 phase, since the unit current is reduced to 1/2 compared to the P2 phase, the slope of the nonlinear reference signal becomes 1/2. That is, in the P3 phase, the AD conversion gain is twice (6 dB) that in the P2 phase.

  Similarly, the non-linear reference signal changes non-linearly so as to decrease at a half-fold gradient of the immediately preceding sub-period in each sub-period of the P1 phase to the P6 phase.

  In the last P6 phase, all the output signals Q1 to Q96 of DFFs 181-1 to 181 to 96 are sequentially changed from L level to H level in synchronization with the clock, that is, the inverted signals XQ1 to XQ96 are set to the clock. In synchronism, the H level sequentially changes to the L level, and the FETs 174-1 to 174-96 as the switch 156 (FIG. 12) are sequentially turned off.

  FIG. 16 shows the second output signal Q # n of the DFF 181-n supplied to the gate of the FET 173-n (the inverted signal XQ # n supplied to the gate of the FET 174-n) when the DA converter 22 is driven. It is a timing chart which shows the example of.

  FIG. 16 also shows the horizontal synchronization signal XHS, the clear signal CLR, and the drive signal D in addition to the output signal Q # n, as in FIG.

  In FIG. 16, the output signal Q # n, the horizontal synchronization signal XHS, the clear signal CLR, and the drive signal D are the same as those in FIG.

  However, in FIG. 16, in the P1 phase to the P5 phase other than the last P6 phase in the P1 phase to the P6 phase, half of the DFFs 181-1 to 181 to 96 of the DFFs 181-1 to 181 to 48 are included. After all of the output signals Q1 to Q48 are set to H level, that is, after all the FETs 174-1 to 174-48 as the switch 156 (FIG. 12) are turned off, the clear signal CLR is set to L level, and A waiting time (waiting time) WAIT is provided before the PGC DAC 32 reduces the unit current to ½.

  More specifically, all of the output signals Q1 to Q48 of DFFs 181-1 to 181-48 of the DFFs 181-1 to 181 to 96 are set to the H level, that is, the switch 156 (FIG. 12). The state in which all FETs 174-1 to 174-48 are turned off is maintained for a predetermined waiting time WAIT, and then the clear signal CLR is set to L level and the unit current is reduced to 1/2. And done.

  FIG. 17 is a waveform diagram showing a nonlinear reference signal when the output signal Q # n of the DFF 181-n (the inverted signal XQ # n supplied to the gate of the FET 174-n) is the signal described in FIG.

  As described with reference to FIG. 16, the waiting time WAIT is set so that the time between the end of the P # i phase, which is a certain sub-period, and the start time of the P # i + 1 phase, which is the next sub-period. Is inserted with a waiting time WAIT in which the nonlinear reference signal is maintained at the voltage at the end of the P # i phase.

  According to the insertion of the waiting time WAIT as described above, the magnitude relationship between the nonlinear reference signal and the VSL voltage is reversed just before the end of the P # i phase due to the influence of the inversion delay of the comparator output VCO of the comparator 23. In this case, it is possible to suppress the occurrence of a large error in the AD conversion result of the VSL voltage due to the difference between the inversion timing and the inversion timing of the comparator output VCO.

  In the waiting time WAIT, counting of the count value by the counter 24 is stopped.

  In the DA converter 22, the slope of the nonlinear reference signal is changed by changing the timing at which the Ramp DAC 34 is cleared (the clear signal CLR is set to L level) and the unit current flowing through the switch 156 is reduced. The change point (gain switching point), that is, the start position and the end position of the sub-period constituting the P phase can be changed.

  For example, in an environment where the amount of light is not so large, for example, in an environment where the output of SP1 is just saturated and the amount of light is such that the SP2 digital code is used as the composite pixel value, By setting the P6 phase, which is the period, to a longer period, a gain of 24 dB AD conversion is applied, and the range of the amount of light that can obtain a combined pixel value with improved gradation can be expanded.

  In addition, it is possible to appropriately adjust the length of each P # i phase, which is a sub-period, in accordance with the variation in the amount of light.

<Countermeasures against Ramp wave settling failure>
In the case of outputting a non-linear Ramp wave from the DA converter 22, the Ramp wave may not be settled when -6 dB is achieved.

  FIG. 18 and FIG. 19 are diagrams for explaining the cause of the Ramp wave settling failure. In the AD conversion unit 14, as shown in FIG. 18, a parasitic resistance 42 and a parasitic capacitance 43 that can be generated between the DA converter 22 and the comparator 23 act as the LPF 41. As a result, as shown in FIG. 19A, the waveform of the Ramp wave from the DA converter 22 is rounded after passing through the LPF 41, and settling failure may occur.

  As a countermeasure, an offset (hereinafter referred to as “Ramp Stable”) is provided in the Ramp potential immediately before the Ramp slope of the nonlinear Ramp wave output from the DA converter 22. As a result, as shown in FIG. 19B, the rounded waveform of the offset Ramp wave from the DA converter 22 is reduced after passing through the LPF 41, and settling is not achieved.

  That is, FIG. 18 is a diagram illustrating a state in which the reference signal is supplied from the DA converter 22 to the comparators 23 in each column of the pixels 11P.

  A reference signal is supplied from the DA converter 22 to the comparators 23 of each column via wiring. The wiring to which the reference signal is supplied has a parasitic resistance 42 and a parasitic capacitance 43. The parasitic resistance 42 and the parasitic capacitance 43 function as an LPF (Low Pass Filter) 41.

  FIG. 19 is a diagram for explaining the influence of the LPF 41 and countermeasures against the influence.

  FIG. 19A is a diagram for explaining the influence of the LPF 41.

  The reference signal (nonlinear reference signal, linear reference signal) decreases in the P phase and the D phase, but at the beginning of the decrease, the waveform of the reference signal is determined by the parasitic resistance 42 and the parasitic capacitance 43 due to the influence of the LPF 41. Depending on the time constant, a dull settling failure occurs from the original waveform (indicated by the dotted line in the figure).

  The non-linear reference signal used in the P phase of the DDS drive is a -6 dB reference signal with the steepest slope in the first P1 phase among the P1 phase and P6 phase, and the degree of waveform dullness is large .

  FIG. 19B is a diagram for explaining measures against the influence of the LPF 41.

  Now, in the P phase and the D phase, the original voltage when starting to decrease the reference signal is expressed as a voltage (predetermined voltage) VC.

  As a countermeasure against the influence of the LPF 41, in the P phase and the D phase, the decrease of the reference signal is not started from the voltage VC, but the reference signal is set to a voltage higher than the voltage VC before the start of the P phase and the D phase. There is a method of performing a stable offset (Ramp Stable) that offsets the voltage so as to decrease to the voltage VC at the start of the P phase or D phase.

  The DA converter 22 can output a reference signal subjected to a stable offset.

  According to the stable offset, the reference signal rapidly decreases to the voltage VC at the start of the P-phase and the D-phase, and then the reference signal decreases by a predetermined gradient. As described above, when the reference signal drops steeply to the voltage VC at the start of the P-phase or D-phase, the degree of the decrease is dull due to the influence of the LPF 41, but then decreases with a predetermined inclination. The degree to which the reference signal becomes dull due to the influence of the LPF 41 can be reduced.

  Here, in the stable offset, the offset amount that raises the reference signal to a voltage higher than the voltage VC before the start of the P phase or D phase, and the offset that drops to the voltage VC at the start of the P phase or D phase. The magnitude of the amount is also referred to as the offset amount of the stable offset.

  In addition, the P-phase and D-phase portions (waveform portions where the voltage is reduced) of the reference signal are also referred to as slopes hereinafter.

  According to the stable offset, the degree of dullness of the slope of the reference signal from the original waveform can be suppressed.

  FIG. 20 shows the difference in Ramp Stable effect for pixels having different column positions, that is, pixels having different distances from the DA converter 22.

  A in the figure shows the waveform of the Ramp wave after passing through the LPF 41 in the far-end pixel column farthest from the DA converter 22. B in the figure shows the waveform of the Ramp wave after passing through the LPF 41 in the pixel at the center of the column where the distance from the DA converter 22 is shorter than in the case of FIG. C in the figure shows the waveform of the Ramp wave after passing through the LPF 41 in the pixel at the near end of the column with the shortest distance from the DA converter 22.

  In the case of A in the figure, Ramp Stable is insufficient because the waveform of the Ramp wave after passing through LPF 41 has a smaller slope than the ideal shape. In the case of B in the figure, the Ramp Stable is appropriate because the waveform of the Ramp wave after passing through the LPF 41 is close to the ideal shape. In the case of C in the figure, the Ramp wave waveform after passing through the LPF 41 has a larger slope than the ideal shape, so that the Ramp Stable is excessive.

  As apparent from A to C in the figure, the effect of Ramp Stable varies depending on the position of the column. Therefore, Ramp Stable may be set to a value that provides the maximum effect for the entire column.

  That is, FIG. 20 is a diagram illustrating an example of the reference signal supplied from the DA converter 22 to the comparators 23 in each column of the pixels 11P when performing the stable offset of the reference signal.

  The offset amount of the stable offset of the reference signal can be determined so that the slope of the reference signal supplied to the comparator 23 in the center column (column center) of the pixel 11P is closer to the original (ideal) waveform. .

  FIG. 20 shows a case where the offset amount of the stable offset is determined from the DA converter 22 when the slope of the reference signal supplied to the comparator 23 in the center column is closer to the original waveform as described above. A reference signal supplied to the comparator 23 is shown.

  That is, A in FIG. 20 shows a reference signal supplied from the DA converter 22 to the comparator 23 in a column far from the center column (column far end), and B in FIG. 20 shows the center column (column center). The reference signal supplied to the comparator 23 in FIG. FIG. 20C shows a reference signal supplied from the DA converter 22 to the comparator 23 in a column (column near end) closer to the center column.

  When the offset amount of the stable offset is determined so that the slope of the reference signal supplied to the comparator 23 in the center column is closer to the original waveform, as shown in FIG. The slope of the reference signal supplied to 23 is a slope close to the original (ideal) waveform.

  On the other hand, when the offset amount of the stable offset is determined so that the slope of the reference signal supplied to the comparator 23 in the center column is closer to the original waveform, the offset amount is supplied to the comparator 23 in the column farther than the center column. For the reference signal, the offset amount of the stable offset is insufficient (small). Therefore, as shown in FIG. 20A, the slope of the reference signal supplied to the comparator 23 in the column farther from the center column becomes a slope with a gentler slope than the original (ideal) waveform.

  Further, the offset amount of the stable offset is excessive (large) for the reference signal supplied to the comparator 23 in the column closer to the center column. Therefore, as shown in FIG. 20C, the slope of the reference signal supplied to the comparator 23 in the column closer to the center column becomes a slope having a gentler slope than the original waveform.

  The non-linear reference signal falls most steeply in the P1 phase of the P1 phase to P6 phase constituting the P phase, and therefore, when the stable offset is not performed, the nonlinear reference signal is affected by the influence of the LPF 41. The dullness of the slope of the P1 phase becomes large. Therefore, it is useful to perform a stable offset on the nonlinear reference signal.

<Application to column column type image sensor>
The DA converter 22 described above can also be applied to a columnar column type image sensor.

  FIG. 21 shows a configuration example of a columnar column type image sensor to which the DA converter 22 is applied. In the case of the configuration example, two DA converters 22-1 and 22-2 are employed. For example, the above-described Ramp Stable value (offset value) is different between the DA converter 22-1 and the DA converter 22-2. If the value is set, a noise reduction effect can be obtained.

  That is, FIG. 21 is a diagram illustrating a configuration example of another embodiment of an image sensor to which the present technology is applied.

  In the figure, portions corresponding to those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  21, the image sensor 50 includes a pixel array unit 11, an address decoder 12, a pixel timing driving unit 13, AD conversion units 14-1 and 14-2, a sensor controller 15, and DA converters 22-1 and 22-2. Have

  Therefore, the image sensor 50 is common to the image sensor 10 of FIG. 6 in that the image sensor 50 includes the pixel array unit 11, the address decoder 12, the pixel timing driving unit 13, and the sensor controller 15.

  However, the image sensor 50 includes AD converters 14-1 and 14-2 instead of the AD converter 14, and includes DA converters 22-1 and 22-2 instead of the DA converter 22. Different from the image sensor 10.

In addition, the image sensor 50 includes a plurality of, for example, four vertical signal lines 211 ₁ , 211 ₂ , 211 ₃ , and 211 ₄ for one column of the pixels 11P constituting the pixel array unit 11. In the pixel array unit 11, pixel _{11P 4i + 1} is a pixel 11P of 4i + 1 th row (i = 0,1, ...) is connected to the vertical signal line 211 _1, pixel _{11P 4i + 2} are 4i + 2 row pixels 11P It is connected to the vertical signal line 211 _2. Further, 4i + 3-row pixel pixel _{11P 4i + 3} is 11P is connected to the vertical signal line 211 _3, 4i + pixel _{11P 4i + 4} is a fourth row of pixels 11P is connected to the vertical signal line 211 _4.

  The AD conversion unit 14-1 includes constant current circuits 21-1-1 and 21-1-2, comparators 23-1-1 and 23-1-2, counters 24-1-1 and 24-1-2, capacitors C1-1-1 and C2-1-1, capacitors C1-1-2 and C2-1-2, and switches 221-1-1 and 221-1-2 are pixels 11 P constituting the pixel array unit 11. For each column.

  In the AD conversion unit 14-1, the constant current circuit 21-1-1, the comparator 23-1-1, the counter 24-1-1, and the capacitors C1-1-1 and C2-1-1 14 (FIG. 10) corresponds to the constant current circuit 21, the comparator 23, the counter 24, and the capacitors C1 and C2, respectively. Similarly, the constant current circuit 21-1-2, the comparator 23-1-2, the counter 24-1-2, and the capacitors C1-1-2 and C2-1-2 are the constant current circuit of the AD conversion unit 14. 21, a comparator 23, a counter 24, and capacitors C 1 and C 2, respectively.

  Therefore, the AD conversion unit 14-1 has two systems similar to the constant current circuit 21, the comparator 23, the counter 24, and the capacitors C1 and C2 of the AD conversion unit 14, and the AD conversion performed by the AD conversion unit 14 is performed. Can be performed simultaneously in the two systems.

The switch 221-1-1 selects any one of the _four vertical signal lines 211 ₁ to 211 ₄ as an electric signal output from the pixel 11P _{4i + j} on the selected vertical signal line 211 _j . The VSL voltage is supplied to the comparator 23-1-1.

Similarly, the switch 221-1-2 selects any one of the _four vertical signal lines 211 ₁ to 211 ₄ , and the electricity output from the pixel 11P _{4i + j} on the selected vertical signal line 211 _j. The VSL voltage as a signal is supplied to the comparator 23-1-2.

  The AD conversion unit 14-2 includes constant current circuits 21-2-1 and 21-2-2, comparators 23-2-1 and 23-2-2, counters 24-2-1 and 24-2-2, capacitors C1-2-1 and C2-2-1, capacitors C1-2-2 and C2-2-2, and switches 221-2-1 and 221-2-2 are connected to the pixel 11P constituting the pixel array unit 11. For each column.

  In the AD converter 14-2, constant current circuits 21-2-1 and 21-2-2, comparators 23-2-1 and 23-2-2, counters 24-2-1 and 24-2-2, capacitors C1-2-1 and C2-2-1, capacitors C1-2-2 and C2-2-2, and switches 221-2-1 and 221-2-2 are constant currents of the AD converter 14-1. Circuits 21-1-1 and 21-1-2, comparators 23-1-1 and 23-1-2, counters 24-1-1 and 24-1-2, capacitors C1-1-1 and C2-1- 1 corresponds to capacitors C1-1-2 and C2-1-2, and switches 221-1-1 and 221-1-2, respectively.

  Therefore, since the AD conversion unit 14-2 is configured in the same manner as the AD conversion unit 14-1, the description thereof is omitted below.

  The image sensor 50 includes DA converters 22-1 and 22-2 instead of the DA converter 22 of the image sensor 10 of FIG. The DA converters 22-1 and 22-2 are configured in the same manner as the DA converter 22, and output a reference signal. Both reference signals output from the DA converters 22-1 and 22-2 are supplied to both the AD conversion units 14-1 and 14-2.

  In the AD conversion unit 14-1, the reference signal output from the DA converter 22-1 is supplied to the comparator 23-1-1, and the reference signal output from the DA converter 22-2 is supplied to the comparator 23-1-2. Is done.

  Therefore, in the AD conversion unit 14-1, the constant current circuit 21-1-1, the comparator 23-1-1, the counter 24-1-1, and the capacitors C1-1-1 and C2-1-1 (hereinafter, In the first AD conversion system), AD conversion of the VSL voltage supplied from the switch 221-1-1 can be performed using the reference signal output from the DA converter 22-1.

  Further, in the AD conversion unit 14-1, the constant current circuit 21-1-2, the comparator 23-1-2, the counter 24-1-2, and the capacitors C1-1-2 and C2-1-2 ( Hereinafter, in the second AD conversion system), AD conversion of the VSL voltage supplied from the switch 221-1-2 can be performed using the reference signal output from the DA converter 22-2.

For example, now, in the switches 221-1-1 and 221-1-2, the same vertical signal line 211 _j is selected, and as an electrical signal output from the same pixel 11P _{4i + j} on the vertical signal line 211 _j. The VSL voltage is AD-converted by each of the first and second AD conversion systems, whereby a pixel value with reduced noise can be obtained.

  That is, the DA converters 22-1 and 22-2 output the reference signal so that an offset is provided between the reference signal output by the DA converter 22-1 and the reference signal output by the DA converter 22-2. Generate.

  As a result, the first AD conversion system to which the reference signal output from the DA converter 22-1 is supplied and the second AD conversion system to which the reference signal output from the DA converter 22-2 is supplied are the same. The timing at which the magnitude relationship between the VSL voltage and the reference signal is inverted with respect to the VSL voltage is shifted according to the offset, and the values at different times of the VSL voltage are sampled as AD conversion results.

  As described above, in the first AD conversion system and the second AD conversion system, values at different times of the same VSL voltage are sampled. Therefore, sampling is performed by adding the sampled values. Noise contained in the value can be suppressed.

  Here, if the constant current circuit 21, the comparator 23, the counter 24, and the capacitors C1 and C2 of the AD conversion unit 14 (FIG. 10) are referred to as an AD conversion unit, the image sensor 50 includes one column of pixels 11P. Two AD conversion units are provided on each of the upper side and the lower side.

  As described above, an image sensor having a plurality of AD conversion units in at least one of the upper and lower sides of one column is called a column column type (image sensor).

<Nonlinear data correction method>
The output from the AD conversion unit 14 of the image sensor 10 according to the present embodiment is non-linear data, and in order to use this as image data, it is necessary to correct it to linear data.

  FIG. 22 shows an example of the arrangement of a correction unit that corrects the output (nonlinear data) from the AD conversion unit 14 to linear data.

  As the correction unit, as shown in the figure, a logic unit 61 is provided inside the image sensor 10 and subsequent to the AD conversion unit 14, or a DSP (Digital Signal Processor) 62 is provided outside the image sensor 10. Can be provided.

  FIG. 23 shows how nonlinear data is corrected to linear data by the correction unit (logic unit 61 or DSP 62).

  When the non-linear data is 6144 counts (1024 dB at -6 dB, 1024 counts at 0 dB, 1024 counts at 6 dB, 1024 counts at 12 dB, 1024 counts at 18 dB, 2048 counts at 24 dB), 32 times, 16 times, 8 If it is multiplied by 4, 4, 2, or 1, 65536 counts of linear data can be obtained.

  That is, FIG. 23 shows that the AD conversion unit 14 converts nonlinear data obtained by AD conversion using a nonlinear reference signal into linear data similar to the AD conversion result obtained by AD conversion using a linear reference signal. It is a figure which shows the example of the method of correct | amending (converting) to data.

  FIG. 23A shows non-linear data as AD conversion results obtained when the DDS-driven (P phase) AD conversion is performed using the non-linear reference signal of FIG.

  For the non-linear reference signal in FIG. 3, the reference signals for the P1, P2, P3, P4, P5, and P6 phases are the -6 dB reference signal, the 0 dB reference signal, and the 6 dB reference signal, respectively. 12 dB reference signal, 18 dB reference signal, and 24 dB reference signal.

  In addition, the P1, P2, P3, P4, P5, and P6 phases, respectively, from the beginning, the period for 1024 counts, the period for the next 1024 counts, the period for the next 1024 counts, The period for the next 1024 counts, the period for the next 1024 counts, and the period for the last 2048 counts.

  Therefore, in the P phase of DDS drive, in the P1 phase, a maximum of 1024 counts for the reference signal of -6 dB, in the P2 phase, a maximum of 1024 counts for the reference signal of 0 dB, in the P3 phase, Up to 1024 counts for the 6dB reference signal, up to 1024 counts for the 12dB reference signal in the P4 phase, and up to 1024 counts for the 18dB reference signal in the P5 phase, In the P6 phase, a maximum of 2048 counts are performed for the reference signal of 24 dB.

  Therefore, in the P phase of DDS driving, 6144 counts can be performed at the maximum.

  B of FIG. 23 shows linear data obtained by correcting the non-linear data as the AD conversion result of A of FIG.

  In B of FIG. 23, the count values of the P1 phase to the P6 phase constituting the P phase of the DDS drive are converted into the count values for the reference signal having the maximum gain of 24 dB among the reference signals of the P1 phase to the P6 phase. As a result, the count value of the non-linear data is corrected to the count value of the linear data.

  In the conversion to the count value for the 24dB reference signal, the count value for the -6dB reference signal for the P1 phase is multiplied by 32 (≈24dB-(-6dB)), and the count value for the 0dB reference signal for the P2 phase is 16 times (≈24dB-0db). The count value for the 6 dB reference signal in the P3 phase is multiplied by 8 (≈24 dB-6 dB), and the count value for the 12 dB reference signal in the P4 phase is multiplied by 4 (≈24 dB-12 db). Further, the count value for the 18 dB reference signal of the P5 phase is doubled (≈24 dB-18 dB), and the count value for the 24 dB reference signal of the P6 phase is left as it is.

  Therefore, for linear data, the count value for the -6 dB reference signal in the P1 phase is 32768 = 1024 x 32 counts at maximum, and the count value for the 0 dB reference signal in the P2 phase is 16384 = 1024 x 16 counts at maximum. become. Further, the count value for the 6 dB reference signal for the P3 phase is 8192 = 1024 × 8 counts at the maximum, and the count value for the 12 dB reference signal for the P4 phase is 4096 = 1024 × 4 counts at the maximum. Further, the count value for the 18 dB reference signal of the P5 phase is 2048 = 1024 × 2 counts at the maximum, and the count value for the 24 dB reference signal of the P6 phase is 2048 counts at the maximum.

  As described above, the maximum number of linear data is 65536 = 32768 + 16384 + 8192 + 4096 + 2048 + 2048.

  As described above, the non-linear data is corrected (converted) to linear data by converting the count values obtained in the P1 phase to the P6 phase into the count values for the 24 dB reference signal and adding them.

  Since the linear data as described above is converted into the count value for the reference signal of 24 dB, the value becomes finer by 24 dB compared to the count value for the reference signal of 0 dB.

  As a result, Con Res. When using a non-linear reference signal can be improved by 24 dB (≈16 times) over Con Res. When using a 0 dB linear reference signal. That is, 5.85% Con Res. As described in FIG. 1 can be improved to 0.36% ≈5.85% / 16.

  The linear data obtained as described above is data with a gain of 24 dB, and is a data with a gain of 240 times (47 dB), which is the ratio of the light reception sensitivity of SP1 and SP2. Therefore, it is multiplied by 16 (≈47 dB-24 dB) and used as the SP2 digital code as described in FIG.

<First Modification>
In the above description, a nonlinear ramp wave is output by switching the gain from the DA converter 22 of the AD conversion unit 14. In the first modified example, a linear Ramp wave is output from the DA converter 22 with a constant gain, and the drive frequency of the counter 24 is made variable, thereby enabling non-linear AD conversion.

  FIG. 24 shows changes in the drive frequency of the counter 24 in the first modification. FIG. 25 shows a Ramp wave in the first modification.

  As shown in FIG. 24, the drive frequency of the counter 24 is set to 20 MHz for a period corresponding to -6 dB, 40 MHz for a period corresponding to 0 dB, 80 MHz for a period corresponding to 6 dB, 160 MHz for a period corresponding to 12 dB, and 18 dB. If the corresponding period is 320 MHz and the period corresponding to 24 dB is 640 MHz, the same nonlinear AD conversion as that when the DA converter 22 outputs a nonlinear ramp wave can be performed.

  That is, FIG. 24 is a diagram for explaining a second AD conversion method for AD-converting a VSL voltage nonlinearly.

  In the reference signal comparison type AD conversion, a method of AD converting a VSL voltage nonlinearly, that is, a method of AD converting a VSL voltage with a nonlinear quantization width uses a nonlinear reference signal as described in FIG. In addition to the first AD conversion method, there is a second AD conversion method using a linear reference signal.

  In the second AD conversion method, a linear reference signal is used, but the frequency of the clock CNCLK used (synchronized) when the counter 24 counts the count value is changed.

  Therefore, in the second AD conversion method, the counter 24 counts the count value according to the clock CNCLK whose frequency changes (synchronously).

  FIG. 24 shows how the frequency of the clock CNCLK is gradually increased in the P phase of DDS driving.

  FIG. 25 is a diagram illustrating an example of the reference signal and the frequency of the clock CNCLK when the VSL voltage is AD converted nonlinearly by the second AD conversion method.

  In the second AD conversion method, a linear reference signal is used as the reference signal.

  The reference signal in FIG. 25 is a reference signal used for DDS driving (the D phase and the P phase) in the second AD conversion method, and is, for example, a linear reference signal similar to the reference signal in FIG.

  In the second AD conversion method, the frequency of the clock CNCLK of the counter 24 changes every sub-period (P # i phase) constituting the P phase.

  In FIG. 25, the frequency of the clock CNCLK in the D phase of DDS driving is 640 MHz.

  For example, if the AD conversion gain is 0 dB when the count value is counted with the 40 MHz clock CNCLK, the AD conversion gain when the count value is counted with the 640 MHz clock CNCLK is 24 dB (≈ (640/40 times).

  In FIG. 25, the frequencies of the clocks CNCLK of the P1 phase to the P6 phase constituting the P phase of the DDS drive are 20 MHz, 40 MHz, 80 MHz, 160 MHz, 320 MHz, and 640 MHz, respectively.

  By changing the frequency of the clock CNCLK as described above, nonlinear AD conversion similar to the case of using the nonlinear reference signal of FIG. 3 can be performed.

  In FIG. 25, the P1 phase to the P6 phase are respectively a sub-period for 128 counts, a sub-period for 256 counts, a sub-period for 512 counts, a sub-period for 1024 counts, a sub-period for 2048 counts, The sub-period is 4096 counts.

  In addition, the gains of AD conversion of P1 phase to P6 phase are -6dB, 0dB, 6dB, 12dB, 18dB and 24dB, respectively.

  Further, in FIG. 25, since the count value of the P phase of the DDS drive is 8064 (= 128 + 256 + 512 + 1024 + 2048 + 4096) at the maximum, as described in FIG. When AD conversion is performed, the D phase of DDS driving is a period of 3968 (= 8094-4096 (12 bits)) counts.

<Second Modification>
In the above description, a nonlinear ramp wave is output by switching the gain from the DA converter 22 of the AD conversion unit 14. In the second modified example, by making the gain of the DA converter 22 constant and making the drive frequency of the DA converter 22 variable, a nonlinear ramp wave can be output from the DA converter 22.

  FIG. 26 shows changes in the driving frequency of the DA converter 22 in the second modification. FIG. 27 shows a ramp wave in the second modification.

  As shown in FIG. 26, the driving frequency of the DA converter 22 is 640 MHz for a period corresponding to −6 dB, 320 MHz for a period corresponding to 0 dB, 160 MHz for a period corresponding to 6 dB, 80 MHz for a period corresponding to 12 dB, 18 dB. The period corresponding to is 40 MHz, and the period corresponding to 24 dB is 20 MHz. Thus, as shown in FIG. 27, the DA converter 22 can output a non-linear Ramp wave similar to that when the gain is switched.

  That is, FIG. 26 is a diagram for explaining a second generation method for generating a nonlinear reference signal used in the first AD conversion method.

  As a method for generating a nonlinear reference signal used in the first AD conversion method, as described with reference to FIGS. 12 to 15, in the Ramp DAC 34, the unit current flowing in the FET 174-n as the switch 156 is changed to change the nonlinear reference signal. In addition to the first generation method for generating the reference signal, there is a second generation method for generating the nonlinear reference signal by changing the frequency of the clock DACLK that drives the DA converter 22.

  FIG. 26 shows how the frequency of the clock DACLK of the DA converter 22 is gradually reduced in the P phase of DDS driving.

  Here, the clock CLK supplied to the DFF 181-n in FIG. 13 corresponds to the clock DACLK.

  FIG. 27 is a diagram illustrating an example of the nonlinear reference signal generated by the second generation method and the frequency of the clock DACLK.

  In the second generation method, the frequency of the clock DACLK of the DA converter 22 changes every sub-period (P # i phase) constituting the P phase.

  In FIG. 27, the frequency of the clock DACLK in the D phase of DDS driving is 20 MHz.

  For example, if the AD conversion gain when the DA converter 22 operates with the clock DACLK of 320 MHz is 0 dB, the AD conversion gain when the count value is counted with the clock DACLK of 20 MHz is 24 dB (≈320 / 20 times).

  In FIG. 27, the frequencies of the clocks DACLK of the P1 phase to the P6 phase constituting the P phase of DDS driving are 640 MHz, 320 MHz, 160 MHz, 80 MHz, 40 MHz, and 20 MHz, respectively.

  As described above, by changing the frequency of the clock DACLK, it is possible to generate a nonlinear reference signal that varies nonlinearly in the same manner as the nonlinear reference signal of FIG.

  In FIG. 27, as in the case of FIG. 3, the P1 phase to the P6 phase are sub-periods for 1024 counts, 1024 counts, 1024 counts, 1024 counts, and 1024 counts, respectively. There are sub-periods for count and 2048 counts. Further, the D phase has a period of 2048 counts as in the case of FIG.

  In addition, the gains of AD conversion of P1 phase to P6 phase are -6dB, 0dB, 6dB, 12dB, 18dB and 24dB, respectively.

<Application example>
In the present embodiment, SP1 and SP2 having different sizes are provided in one pixel cell, and a wide dynamic range of pixel values is achieved by combining these outputs. A technique for widening a pixel value by MLE (Multi-line exposure) is also known.

  Even in the case of MLE, since synthesis is generally performed with an exposure ratio gain of 16 to 24 times, there is a concern about a step difference at the time of synthesizing pixel values. Therefore, the DA converter 22 to which the present technology is applied is In some cases, it can be expected to produce an effect.

  That is, as a WD (Wide Dynamic range) technique, there is MLE in addition to the technique of combining the outputs of SP1 and SP2 as a plurality of PDs having different light receiving sensitivities described above.

  In MLE, imaging is performed by applying, for example, a long exposure time, a medium exposure time, or a short exposure time as different exposure times to the pixels of each (horizontal) line. Then, a long accumulation image Long composed of a line of pixels to which a long exposure time is applied obtained as a result of the imaging, a medium accumulation image composed of a line of pixels to which a medium exposure time is applied The short accumulation image Short composed of the pixel line to which the exposure time of the middle and the short time is applied is synthesized in the same manner as the case of synthesizing the outputs of SP1 and SP2, for example. Generated.

  That is, in the synthesis of the long accumulation image Long, the middle accumulation image Middle, and the short accumulation image Short, for the pixel in which the long accumulation image Long is not saturated, the pixel value of the long accumulation image Long is used as the pixel value of the synthesis image. Selected. For the pixels in which the long accumulation image Long is saturated but the middle accumulation image Middle is not saturated, the pixel value of the middle accumulation image Middle is selected as the pixel value of the composite image. Furthermore, for the pixels in which the long accumulation image Long and the middle accumulation image Middle are saturated, the pixel value of the short accumulation image Short is selected as the pixel value of the composite image.

  In the synthesis of the long accumulation image Long, the middle accumulation image Middle, and the short accumulation image Short, the pixel value of the middle accumulation image Middle depends on the exposure time of the middle accumulation image Middle relative to the exposure time of the long accumulation image Long, for example, A gain of 16 to 24 times (exposure ratio gain) is applied. The same applies to the short accumulation image Short.

  Therefore, in the composite image, a pixel in which the pixel value of one of the long accumulation image Long, the middle accumulation image Middle, and the short accumulation image Short is selected, and a pixel in which the pixel value of another image is selected. There is a possibility that a large level difference in pixel value may occur between the two.

  Therefore, by adopting non-linear AD conversion for AD conversion of middle storage image Middle and short storage image Short (VSL voltage as the pixel value thereof), it is possible to suppress the occurrence of the large step of the pixel value as described above. The gradation of the composite image can be improved.

  In addition, in MLE, when performing AD conversion of two images simultaneously among the long accumulation image Long, middle accumulation image Middle, and short accumulation image Shor +, it is referred for each AD conversion of the two images Two DA converters that generate signals are required. In addition, when AD conversion of the three images of the long accumulation image Long, the middle accumulation image Middle, and the short accumulation image Shor + is performed at the same time, three reference signals are generated for each of the AD conversion of the three images. A DA converter is required.

<Application example to in-vivo information acquisition system>
The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

  FIG. 28 is a block diagram illustrating an example of a schematic configuration of a patient in-vivo information acquisition system using a capsule endoscope to which the technology according to the present disclosure (present technology) can be applied.

  The in-vivo information acquisition system 10001 includes a capsule endoscope 10100 and an external control device 10200.

  The capsule endoscope 10100 is swallowed by a patient at the time of examination. The capsule endoscope 10100 has an imaging function and a wireless communication function, and moves inside the organ such as the stomach and the intestine by peristaltic motion or the like until it is spontaneously discharged from the patient. Images (hereinafter also referred to as in-vivo images) are sequentially captured at predetermined intervals, and information about the in-vivo images is sequentially wirelessly transmitted to the external control device 10200 outside the body.

  The external control device 10200 comprehensively controls the operation of the in-vivo information acquisition system 10001. Further, the external control device 10200 receives information about the in-vivo image transmitted from the capsule endoscope 10100 and, based on the received information about the in-vivo image, displays the in-vivo image on the display device (not shown). The image data for displaying is generated.

  In the in-vivo information acquisition system 10001, in this way, an in-vivo image obtained by imaging the state of the patient's body can be obtained at any time from when the capsule endoscope 10100 is swallowed until it is discharged.

  The configurations and functions of the capsule endoscope 10100 and the external control device 10200 will be described in more detail.

  The capsule endoscope 10100 includes a capsule-type casing 10101. In the casing 10101, a light source unit 10111, an imaging unit 10112, an image processing unit 10113, a wireless communication unit 10114, a power supply unit 10115, and a power supply unit 10116 and the control unit 10117 are stored.

  The light source unit 10111 is composed of a light source such as an LED (light emitting diode), for example, and irradiates the imaging field of the imaging unit 10112 with light.

  The imaging unit 10112 includes an imaging device and an optical system including a plurality of lenses provided in the preceding stage of the imaging device. Reflected light (hereinafter referred to as observation light) of light irradiated on the body tissue to be observed is collected by the optical system and enters the image sensor. In the imaging unit 10112, in the imaging element, the observation light incident thereon is photoelectrically converted, and an image signal corresponding to the observation light is generated. The image signal generated by the imaging unit 10112 is provided to the image processing unit 10113.

  The image processing unit 10113 is configured by a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), and performs various signal processing on the image signal generated by the imaging unit 10112. The image processing unit 10113 provides the radio communication unit 10114 with the image signal subjected to signal processing as RAW data.

  The wireless communication unit 10114 performs predetermined processing such as modulation processing on the image signal subjected to signal processing by the image processing unit 10113, and transmits the image signal to the external control apparatus 10200 via the antenna 10114A. In addition, the wireless communication unit 10114 receives a control signal related to drive control of the capsule endoscope 10100 from the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 provides a control signal received from the external control device 10200 to the control unit 10117.

  The power feeding unit 10115 includes a power receiving antenna coil, a power regeneration circuit that regenerates power from a current generated in the antenna coil, a booster circuit, and the like. In the power feeding unit 10115, electric power is generated using a so-called non-contact charging principle.

  The power supply unit 10116 is configured by a secondary battery and stores the electric power generated by the power supply unit 10115. In FIG. 28, in order to avoid complication of the drawing, illustration of an arrow indicating a power supply destination from the power supply unit 10116 is omitted, but the power stored in the power supply unit 10116 is stored in the light source unit 10111. The imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the control unit 10117 can be used for driving them.

  The control unit 10117 includes a processor such as a CPU, and a control signal transmitted from the external control device 10200 to drive the light source unit 10111, the imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the power feeding unit 10115. Control accordingly.

  The external control device 10200 includes a processor such as a CPU and a GPU, or a microcomputer or a control board in which a processor and a storage element such as a memory are mounted. The external control device 10200 controls the operation of the capsule endoscope 10100 by transmitting a control signal to the control unit 10117 of the capsule endoscope 10100 via the antenna 10200A. In the capsule endoscope 10100, for example, the light irradiation condition for the observation target in the light source unit 10111 can be changed by a control signal from the external control device 10200. In addition, an imaging condition (for example, a frame rate or an exposure value in the imaging unit 10112) can be changed by a control signal from the external control device 10200. Further, the contents of processing in the image processing unit 10113 and the conditions (for example, the transmission interval, the number of transmission images, etc.) by which the wireless communication unit 10114 transmits an image signal may be changed by a control signal from the external control device 10200. .

  Further, the external control device 10200 performs various image processing on the image signal transmitted from the capsule endoscope 10100, and generates image data for displaying the captured in-vivo image on the display device. As the image processing, for example, development processing (demosaic processing), high image quality processing (band enhancement processing, super-resolution processing, NR (Noise reduction) processing and / or camera shake correction processing, etc.), and / or enlargement processing ( Various signal processing such as electronic zoom processing can be performed. The external control device 10200 controls driving of the display device to display an in-vivo image captured based on the generated image data. Alternatively, the external control device 10200 may cause the generated image data to be recorded on a recording device (not shown) or may be printed out on a printing device (not shown).

  Heretofore, an example of the in-vivo information acquisition system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to the imaging unit 10112 among the configurations described above. For example, by applying the image sensor 10 or 50 to the imaging unit 10112, an easily viewable in-vivo image with improved gradation can be provided.

<Application examples to mobile objects>
The technology according to the present disclosure (present technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device that is mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, and a robot. May be.

  FIG. 29 is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a mobile control system to which the technology according to the present disclosure can be applied.

  The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 29, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound image output unit 12052, and an in-vehicle network I / F (Interface) 12053 are illustrated.

  The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 includes a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism that adjusts and a braking device that generates a braking force of the vehicle.

  The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a blinker, or a fog lamp. In this case, the body control unit 12020 can be input with radio waves transmitted from a portable device that substitutes for a key or signals from various switches. The body system control unit 12020 receives input of these radio waves or signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle.

  The vehicle outside information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The vehicle outside information detection unit 12030 may perform an object detection process or a distance detection process such as a person, a car, an obstacle, a sign, or a character on a road surface based on the received image.

  The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging unit 12031 can output an electrical signal as an image, or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared rays.

  The vehicle interior information detection unit 12040 detects vehicle interior information. For example, a driver state detection unit 12041 that detects a driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver is asleep.

  The microcomputer 12051 calculates a control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside / outside the vehicle acquired by the vehicle outside information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, tracking based on inter-vehicle distance, vehicle speed maintenance, vehicle collision warning, or vehicle lane departure warning. It is possible to perform cooperative control for the purpose.

  Further, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of automatic driving that autonomously travels without depending on the operation.

  Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare, such as switching from a high beam to a low beam. It can be carried out.

  The sound image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying information to a vehicle occupant or the outside of the vehicle. In the example of FIG. 29, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

  FIG. 30 is a diagram illustrating an example of the installation position of the imaging unit 12031.

  In FIG. 30, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

  The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper part of a windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The imaging units 12102 and 12103 provided in the side mirror mainly acquire an image of the side of the vehicle 12100. The imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield in the passenger compartment is mainly used for detecting a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

  FIG. 30 shows an example of the imaging range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively, and the imaging range 12114 The imaging range of the imaging part 12104 provided in the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image when the vehicle 12100 is viewed from above is obtained.

  At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

  For example, the microcomputer 12051, based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object in the imaging range 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100). In particular, it is possible to extract, as a preceding vehicle, a three-dimensional object that travels at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100, particularly the closest three-dimensional object on the traveling path of the vehicle 12100. it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Thus, cooperative control for the purpose of autonomous driving or the like autonomously traveling without depending on the operation of the driver can be performed.

  For example, the microcomputer 12051 converts the three-dimensional object data related to the three-dimensional object to other three-dimensional objects such as a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and a utility pole based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle. By outputting an alarm to the driver and performing forced deceleration or avoidance steering via the drive system control unit 12010, driving assistance for collision avoidance can be performed.

  At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is, for example, whether or not the user is a pedestrian by performing a pattern matching process on a sequence of feature points indicating the outline of an object and a procedure for extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras It is carried out by the procedure for determining. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 has a rectangular contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to be superimposed and displayed. Moreover, the audio | voice image output part 12052 may control the display part 12062 so that the icon etc. which show a pedestrian may be displayed on a desired position.

  Heretofore, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. For example, by applying the image sensor 10 or 50 to the imaging unit 12031, it is possible to obtain a captured image with sufficient gradation for driving support and perform appropriate driving support.

  The embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

  The present technology can also have the following configurations.

<1>
A pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are disposed;
Of the plurality of photoelectric conversion units included in the pixel of the pixel array unit, an electrical signal corresponding to the charge of the photoelectric conversion unit having a low light receiving sensitivity is compared with a nonlinear reference signal that changes nonlinearly. A solid-state imaging device comprising: an AD conversion unit that performs AD (Analog to Digital) conversion on the electrical signal.
<2>
A DA (Digital to Analog) converter that outputs the nonlinear reference signal;
The AD converter is
A comparator for comparing the electrical signal and the nonlinear reference signal;
In accordance with a comparison result between the electrical signal and the nonlinear reference signal, a count value obtained by counting the time required for the nonlinear reference signal to change until the electrical signal and the nonlinear reference signal match The solid-state imaging device according to <1>.
<3>
The solid-state imaging device according to <2>, wherein the comparator compares a noise signal of the electrical signal with the nonlinear reference signal.
<4>
The solid-state imaging device according to <3>, wherein the DA converter outputs the nonlinear reference signal that changes in a concave shape.
<5>
The solid-state imaging device according to <4>, wherein the DA converter raises the nonlinear reference signal to a voltage higher than a predetermined voltage, lowers the nonlinear reference signal to the predetermined voltage, and then nonlinearly changes the nonlinear reference signal.
<6>
The DA converter further outputs the nonlinear reference signal that changes in a convex shape,
The comparator compares a data signal of an electrical signal corresponding to a charge of the photoelectric conversion unit having a high light receiving sensitivity among the plurality of photoelectric conversion units included in the pixel and the nonlinear reference signal. <4> or <5> The solid-state imaging device according to <5>.
<7>
The DA converter is
A plurality of switches connected in parallel, in which a current flowing through a resistor that causes a voltage drop that becomes the nonlinear reference signal flows;
By sequentially turning off one half of the plurality of switches, the voltage as the nonlinear reference signal is reduced,
While performing the clear to turn on the plurality of switches, reduce the current flowing through the switch to 1/2,
By sequentially turning off one half of the plurality of switches, the voltage as the nonlinear reference signal is reduced, thereby generating the nonlinear reference signal in which the slope before and after the clearing changes. <2 > To <6>.
<8>
The solid-state imaging device according to <7>, wherein a predetermined standby time is provided before the clear and the reduction of the current flowing through the switch.
<9>
The solid-state imaging device according to <7>, wherein the timing for performing the clear and the reduction of the current flowing through the switch is changed.
<10>
The solid-state imaging device according to <2>, wherein the DA converter generates the nonlinear reference signal by changing a frequency of a clock that drives the DA converter.
<11>
A correction unit that corrects nonlinear data that is an AD conversion result of the electrical signal using the nonlinear reference signal to linear data that is an AD conversion result using a linear reference signal that changes linearly is provided. <2> to <10>.
<12>
Corresponding to the charge of the photoelectric conversion unit having the low light reception sensitivity among the plurality of photoelectric conversion units included in the pixel of the pixel array unit in which pixels including a plurality of photoelectric conversion units having different light reception sensitivity are arranged. A driving method including AD (Analog to Digital) conversion of the electrical signal by comparing the electrical signal with a nonlinear reference signal that varies nonlinearly.
<13>
A solid-state imaging device;
A control unit for controlling the solid-state imaging device,
The solid-state imaging device
A pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are disposed;
Of the plurality of photoelectric conversion units included in the pixel of the pixel array unit, an electrical signal corresponding to the charge of the photoelectric conversion unit having a low light receiving sensitivity is compared with a nonlinear reference signal that changes nonlinearly. An electronic device having an AD conversion unit that performs AD (Analog to Digital) conversion on the electrical signal.
<14>
A pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are disposed;
Of the plurality of photoelectric conversion units included in the pixel of the pixel array unit, the electric signal corresponding to the charge of the photoelectric conversion unit having a low light receiving sensitivity is compared with a linear reference signal that changes linearly. And an AD conversion unit for AD (Analog to Digital) conversion of the electrical signal,
The AD converter is
A comparator for comparing the electrical signal with the linear reference signal;
According to a comparison result between the electrical signal and the linear reference signal, the time required for the change of the reference signal until the electrical signal and the linear reference signal match is counted according to a clock whose frequency changes. And a counter that outputs a count value obtained by the solid-state imaging device.
<15>
Corresponding to the charge of the photoelectric conversion unit having the low light reception sensitivity among the plurality of photoelectric conversion units included in the pixel of the pixel array unit in which pixels including a plurality of photoelectric conversion units having different light reception sensitivity are arranged. The AD conversion unit of the solid-state imaging device including an AD conversion unit that performs AD (Analog to Digital) conversion of the electric signal by comparing the electric signal and a linear reference signal that changes linearly,
Comparing the electrical signal with the linear reference signal;
According to a comparison result between the electrical signal and the linear reference signal, the time required for the change of the reference signal until the electrical signal and the linear reference signal match is counted according to a clock whose frequency changes. A driving method including outputting a count value obtained by the above.
<16>
A solid-state imaging device;
A control unit for controlling the solid-state imaging device,
The solid-state imaging device
A pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are disposed;
Of the plurality of photoelectric conversion units included in the pixel of the pixel array unit, the electric signal corresponding to the charge of the photoelectric conversion unit having a low light receiving sensitivity is compared with a linear reference signal that changes linearly. And an AD conversion unit that performs AD (Analog to Digital) conversion on the electrical signal,
The AD converter is
A comparator for comparing the electrical signal with the linear reference signal;
According to a comparison result between the electrical signal and the linear reference signal, the time required for the change of the reference signal until the electrical signal and the linear reference signal match is counted according to a clock whose frequency changes. And a counter for outputting a count value obtained by the electronic device.

(B1)
A pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are disposed;
A solid-state imaging device comprising: an AD conversion unit that nonlinearly AD converts an electrical signal corresponding to the photoelectric conversion unit having a lower light receiving sensitivity among the plurality of photoelectric conversion units included in the pixel of the pixel array unit .
(B2)
The AD converter is
A DA converter that outputs a Ramp wave for comparison with the electrical signal output from the pixel of the pixel array unit;
A counter that counts according to a counter driving frequency based on a comparison result between the electrical signal and the ramp wave output from the pixel of the pixel array unit;
The DA converter outputs a nonlinear Ramp wave for comparison with the electrical signal corresponding to the photoelectric conversion unit having the lower light receiving sensitivity among the plurality of photoelectric conversion units included in the pixel,
The solid-state imaging device according to (B1), wherein the counter performs counting according to a constant counter driving frequency.
(B3)
The DA converter is a non-linear for comparing with the electrical signal of the P phase corresponding to the photoelectric conversion unit having the lower light receiving sensitivity driven by DDS among the plurality of photoelectric conversion units included in the pixel. The solid-state imaging device according to (B2), which outputs a Ramp wave.
(B4)
The DA converter is a non-linear for comparing with the electrical signal of the P phase corresponding to the photoelectric conversion unit having the lower light receiving sensitivity driven by DDS among the plurality of photoelectric conversion units included in the pixel. The solid-state imaging device according to (B2) or (B3), which outputs a concave ramp wave.
(B5)
The DA converter outputs the non-linear concave ramp wave by offsetting the slope start position upward. The solid-state imaging device according to (B4).
(B6)
The DA converter is a non-linear for comparing with the D-phase electrical signal corresponding to the photoelectric conversion unit having the higher light receiving sensitivity driven by CDS among the plurality of photoelectric conversion units included in the pixel. The solid-state imaging device according to any one of (B2) to (B5), which outputs a convex ramp wave.
(B7)
The DA converter includes a shift register. The solid-state imaging device according to any one of (B2) to (B6).
(B8)
The solid-state imaging device according to (B7), wherein a CLR signal is input to the shift register every time the gain is switched.
(B9)
The solid-state imaging device according to (B7) or (B8), in which a standby time is provided after a CLR signal is input to the shift register every time the gain is switched.
(B10)
The solid-state imaging device according to (B7), wherein a CLR signal is input to the shift register at an arbitrary timing.
(B11)
The DA converter is driven according to a changed DA converter drive frequency, and the electric signal corresponding to the photoelectric conversion unit having the lower light receiving sensitivity among the plurality of photoelectric conversion units included in the pixel A nonlinear Ramp wave for comparison is output. The solid-state imaging device according to (B2).
(B12)
The AD converter is
A DA converter that outputs a Ramp wave for comparison with the electrical signal output from the pixel of the pixel array unit;
A counter that counts according to a counter driving frequency based on a comparison result between the electrical signal and the ramp wave output from the pixel of the pixel array unit;
The DA converter outputs a linear ramp wave,
The solid-state imaging device according to (B1), wherein the counter performs counting according to the changed counter driving frequency.
(B13)
The solid-state imaging device according to any one of (B1) to (B12), further including: a correction unit that corrects nonlinear data output from the AD conversion unit into linear data.
(B14)
In a driving method of a solid-state imaging device including a pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are arranged.
A driving method that nonlinearly AD converts an electrical signal corresponding to the photoelectric conversion unit having the lower light receiving sensitivity among the plurality of photoelectric conversion units included in the pixel of the pixel array unit.
(B15)
In an electronic device equipped with a solid-state imaging device,
The solid-state imaging device
A pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are disposed;
An electronic apparatus comprising: an AD conversion unit that nonlinearly AD converts an electrical signal corresponding to the photoelectric conversion unit having a lower light receiving sensitivity among the plurality of photoelectric conversion units included in the pixel of the pixel array unit.

  10 image sensor, 11 pixel array unit, 11P pixel, 12 address decoder, 13 pixel timing drive unit, 14 AD conversion unit, 15 sensor controller, 21 constant current circuit, 22 DA converter, 23 comparator, 24 counter, 31 IREF, 32 PGC DAC, 33 CLP DAC, 34 RAMP DAC, 41 LPF, 61 Logic, 62 DSP

Claims (16)

A pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are disposed;
Of the plurality of photoelectric conversion units included in the pixel of the pixel array unit, an electrical signal corresponding to the charge of the photoelectric conversion unit having a low light receiving sensitivity is compared with a nonlinear reference signal that changes nonlinearly. A solid-state imaging device comprising: an AD conversion unit that performs AD (Analog to Digital) conversion on the electrical signal. A DA (Digital to Analog) converter that outputs the nonlinear reference signal;
The AD converter is
A comparator for comparing the electrical signal and the nonlinear reference signal;
In accordance with a comparison result between the electrical signal and the nonlinear reference signal, a count value obtained by counting the time required for the nonlinear reference signal to change until the electrical signal and the nonlinear reference signal match The solid-state imaging device according to claim 1, further comprising: a counter for outputting. The solid-state imaging device according to claim 2, wherein the comparator compares a noise signal of the electrical signal with the nonlinear reference signal. The solid-state imaging device according to claim 3, wherein the DA converter outputs the nonlinear reference signal that changes in a concave shape. The solid-state imaging device according to claim 4, wherein the DA converter raises the nonlinear reference signal to a voltage higher than a predetermined voltage, lowers the nonlinear reference signal to the predetermined voltage, and then changes the nonlinear reference signal nonlinearly. The DA converter further outputs the nonlinear reference signal that changes in a convex shape,
The comparator compares a data signal of an electrical signal corresponding to a charge of the photoelectric conversion unit having a high light receiving sensitivity among the plurality of photoelectric conversion units included in the pixel and the nonlinear reference signal. The solid-state imaging device according to claim 4. The DA converter is
A plurality of switches connected in parallel, in which a current flowing through a resistor that causes a voltage drop that becomes the nonlinear reference signal flows;
By sequentially turning off one half of the plurality of switches, the voltage as the nonlinear reference signal is reduced,
While performing the clear to turn on the plurality of switches, reduce the current flowing through the switch to 1/2,
The non-linear reference signal in which the slope before and after the clearing is changed is generated by sequentially turning off one half of the plurality of switches to reduce the voltage as the non-linear reference signal. 2. The solid-state imaging device according to 2. The solid-state imaging device according to claim 7, wherein a predetermined standby time is provided before the clear and a decrease in the current flowing through the switch. The solid-state imaging device according to claim 7, wherein timing for performing the clearing and a reduction of a current flowing through the switch is changed. The solid-state imaging device according to claim 2, wherein the DA converter generates the nonlinear reference signal by changing a frequency of a clock that drives the DA converter. The correction part which correct | amends the nonlinear data which is an AD conversion result of the said electric signal using the said nonlinear reference signal to the linear data which is an AD conversion result using the linear reference signal which changes linearly. Solid-state imaging device. Corresponding to the charge of the photoelectric conversion unit having the low light reception sensitivity among the plurality of photoelectric conversion units included in the pixel of the pixel array unit in which pixels including a plurality of photoelectric conversion units having different light reception sensitivity are arranged. A driving method including AD (Analog to Digital) conversion of the electrical signal by comparing the electrical signal with a nonlinear reference signal that varies nonlinearly. A solid-state imaging device;
A control unit for controlling the solid-state imaging device,
The solid-state imaging device
A pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are disposed;
Of the plurality of photoelectric conversion units included in the pixel of the pixel array unit, an electrical signal corresponding to the charge of the photoelectric conversion unit having a low light receiving sensitivity is compared with a nonlinear reference signal that changes nonlinearly. An electronic device having an AD conversion unit that performs AD (Analog to Digital) conversion on the electrical signal. A pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are disposed;
Of the plurality of photoelectric conversion units included in the pixel of the pixel array unit, the electric signal corresponding to the charge of the photoelectric conversion unit having a low light receiving sensitivity is compared with a linear reference signal that changes linearly. And an AD conversion unit for AD (Analog to Digital) conversion of the electrical signal,
The AD converter is
A comparator for comparing the electrical signal with the linear reference signal;
According to a comparison result between the electrical signal and the linear reference signal, the time required for the change of the reference signal until the electrical signal and the linear reference signal match is counted according to a clock whose frequency changes. And a counter that outputs a count value obtained by the solid-state imaging device. Corresponding to the charge of the photoelectric conversion unit having the low light reception sensitivity among the plurality of photoelectric conversion units included in the pixel of the pixel array unit in which pixels including a plurality of photoelectric conversion units having different light reception sensitivity are arranged. The AD conversion unit of the solid-state imaging device including an AD conversion unit that performs AD (Analog to Digital) conversion of the electric signal by comparing the electric signal and a linear reference signal that changes linearly,
Comparing the electrical signal with the linear reference signal;
According to a comparison result between the electrical signal and the linear reference signal, the time required for the change of the reference signal until the electrical signal and the linear reference signal match is counted according to a clock whose frequency changes. A driving method including outputting a count value obtained by the above. A solid-state imaging device;
A control unit for controlling the solid-state imaging device,
The solid-state imaging device
A pixel array unit in which pixels including a plurality of photoelectric conversion units having different light receiving sensitivities are disposed;
Of the plurality of photoelectric conversion units included in the pixel of the pixel array unit, the electric signal corresponding to the charge of the photoelectric conversion unit having a low light receiving sensitivity is compared with a linear reference signal that changes linearly. And an AD conversion unit that performs AD (Analog to Digital) conversion on the electrical signal,
The AD converter is
A comparator for comparing the electrical signal with the linear reference signal;
According to a comparison result between the electrical signal and the linear reference signal, the time required for the change of the reference signal until the electrical signal and the linear reference signal match is counted according to a clock whose frequency changes. And a counter for outputting a count value obtained by the electronic device.

Images