JP2018078312A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a performance of a semiconductor device.SOLUTION: A semiconductor device has: an insulation film IR1 formed on a principal surface of a semiconductor substrate SUB; and an insulation film LN1 formed on the insulation film IR1. The semiconductor device further has: an opening OP2 which pierces the insulation film LN1 to reach the insulation film IR1; an opening OP3 which pierces the insulation film IR1 to reach the semiconductor substrate SUB; and a trench part TP1 formed in the semiconductor substrate SUB. Each of an opening width WD2 of the opening OP2 and an opening width WD3 of the opening OP3 is wider than a trench width WD4 of the trench part TP1. The trench part TP1 is blocked by the insulation film IF2 with a space SP being left inside the trench part TP1.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and can be suitably used for, for example, a semiconductor device having a groove and a manufacturing method thereof.

  There is a semiconductor device having an element isolation structure in which an insulating film is formed in a groove formed on a surface as a main surface of a semiconductor substrate. A semiconductor device having an element isolation (Deep Trench Isolation; DTI) structure in which an insulating film is formed in a groove having a high aspect ratio higher than 1 as an aspect ratio that is a ratio of the depth of the groove to the width of the groove. is there.

  Japanese Patent Laying-Open No. 2011-66067 (Patent Document 1) discloses a groove formed on a main surface of a semiconductor substrate so as to surround the element formed on the main surface of the semiconductor substrate in a plan view, and on and within the element. A semiconductor device including an insulating film formed thereon and a method for manufacturing the same are disclosed. The technique described in Patent Document 1 describes that an insulating film is formed so as to cover the element and form a space in the groove.

  Japanese Patent Application Laid-Open No. 2013-222838 (Patent Document 2) and Japanese Patent Application Laid-Open No. 2011-151121 (Patent Document 3) describe a semiconductor substrate in which a supporting substrate, a buried insulating film, and a semiconductor layer are stacked in this order, and a semiconductor A semiconductor device including a groove formed on a main surface of a layer and an insulating film formed in the groove and a manufacturing method thereof are disclosed. In the technique described in Patent Document 2 and the technique described in Patent Document 3, the groove is formed so as to surround an element formed on the main surface of the semiconductor layer in a plan view. Further, the technique described in Patent Document 2 and the technique described in Patent Document 3 describe that an insulating film is formed so as to cover the element and form a space in the groove. Yes.

JP 2011-66067 A JP 2013-2222838 A JP 2011-151121 A

  Thus, when forming an insulating film in a trench having a high aspect ratio, for example, by forming an insulating film made of a silicon oxide film by a chemical vapor deposition (CVD) method, the inside of the trench is formed. The groove may be blocked leaving a space. In this case, the film thickness of the insulating film formed on the side surface of the groove part at the upper part of the groove part tends to be larger than the film thickness of the insulating film formed on the side surface of the groove part at the bottom of the groove part. Therefore, by forming an insulating film on the side surface of the groove portion, the groove portion can be closed while leaving a space in the groove portion. When there is a space in the groove, the element isolation characteristics for isolating elements from each other by the DTI structure are improved as compared to when there is no space in the groove.

  However, when an insulating film made of a silicon oxide film is formed by the CVD method, the closing position, which is the height position of the upper end of the space left inside the groove, is adjusted accurately so that it becomes a desired height position. It is difficult. For this reason, the closed position of the space left in the groove may be higher than the desired position.

  When the space closing position becomes higher than the desired position, after forming the insulating film, for example, when polishing the insulating film and flattening the surface of the insulating film, the height position of the surface of the insulating film is It becomes lower than the position, and the space may be exposed on the surface of the insulating film, and polishing slurry may enter the space, or cleaning liquid may enter the space in the subsequent cleaning process. Thereafter, the slurry or the cleaning liquid that has entered the space blows out of the space to generate foreign matter, which may cause a defect in the shape of the semiconductor device and reduce the performance of the semiconductor device.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device includes a first insulating film formed on a main surface of a semiconductor substrate and containing silicon and oxygen, and a second insulating film formed on the first insulating film. . The semiconductor device also includes a first opening that reaches the first insulating film through the second insulating film, and a second opening that reaches the semiconductor substrate through the portion of the first insulating film exposed in the first opening. An opening, and a groove formed in a portion of the semiconductor substrate exposed in the second opening. The second insulating film is made of a material different from that of the first insulating film. The opening width of the first opening and the opening width of the second opening are wider than the groove width of the groove. The groove is closed by the third insulating film leaving a space inside the groove.

  According to another embodiment, in the method of manufacturing a semiconductor device, the first insulating film containing silicon and oxygen is formed on the main surface of the semiconductor substrate, and the second insulating film is formed on the first insulating film. Form. Next, a first opening that reaches the first insulating film through the second insulating film is formed, and the semiconductor substrate passes through the first insulating film in a region where the first opening is formed in a plan view. A second opening reaching the first opening is formed, and a groove is formed in a portion of the semiconductor substrate exposed in the second opening. Next, by etching the portion of the first insulating film exposed to the second opening, the second opening width of the second opening is made wider than the groove width of the groove. Thereafter, the groove is closed by the third insulating film leaving a space inside the groove.

  According to one embodiment, the performance of a semiconductor device can be improved.

1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. 1 is a partially broken perspective view showing a configuration of a semiconductor device according to a first embodiment. 1 is a main part sectional view showing a configuration of a semiconductor device according to a first embodiment; 1 is a main part sectional view showing a configuration of a semiconductor device according to a first embodiment; FIG. 6 is a manufacturing process flow chart showing a part of the manufacturing process of the semiconductor device of the first embodiment. FIG. 6 is a manufacturing process flow chart showing a part of the manufacturing process of the semiconductor device of the first embodiment. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. It is principal part sectional drawing in the manufacturing process of the semiconductor device of a comparative example. It is principal part sectional drawing in the manufacturing process of the semiconductor device of a comparative example. It is principal part sectional drawing in the manufacturing process of the semiconductor device of a comparative example. FIG. 10 is a manufacturing process flow chart showing a part of the manufacturing process of the semiconductor device of the second embodiment. FIG. 10 is an essential part cross-sectional view during a manufacturing step of the semiconductor device of the second embodiment. FIG. 10 is an essential part cross-sectional view during a manufacturing step of the semiconductor device of the second embodiment. FIG. 10 is an essential part cross-sectional view during a manufacturing step of the semiconductor device of the second embodiment. FIG. 10 is an essential part cross-sectional view during a manufacturing step of the semiconductor device of the second embodiment. FIG. 10 is an essential part cross-sectional view during a manufacturing step of the semiconductor device of the second embodiment. FIG. 10 is an essential part cross-sectional view during a manufacturing step of the semiconductor device of the second embodiment. FIG. 10 is an essential part cross-sectional view during a manufacturing step of the semiconductor device of the second embodiment. FIG. 29 is a main-portion cross-sectional view during the manufacturing process of the semiconductor device of the first modification example of the second embodiment; FIG. 29 is a main-portion cross-sectional view during the manufacturing process of the semiconductor device of the first modification example of the second embodiment;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, typical embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view for easy viewing of the drawings.

(Embodiment 1)
<Configuration of semiconductor device>
First, the configuration of the semiconductor device of the first embodiment will be described. FIG. 1 is a plan view showing the configuration of the semiconductor device according to the first embodiment. FIG. 2 is a partially broken perspective view showing the configuration of the semiconductor device of the first embodiment. 3 and 4 are cross-sectional views of relevant parts showing the configuration of the semiconductor device of the first embodiment. FIG. 4 is an enlarged cross-sectional view showing a configuration around the DTI structure.

  FIG. 4 shows an example in which a DTI structure DS is formed around one n-channel MISFET QN for easy understanding. However, as shown in FIG. 3, the DTI structure DS may be formed between the LDMOSFET QH and the p-channel type MISFET QP, or may be formed around various other elements.

  In FIG. 4, the illustration of the portion above the insulating film IFT is omitted for easy understanding.

  As shown in FIG. 1, the semiconductor device of the first embodiment is a BiC-DMOS (Bipolar Complementary Double-diffused Metal Oxide Semiconductor) semiconductor chip CHP. The semiconductor chip CHP includes, for example, a semiconductor substrate SUB, an output driver unit HV, and a logic unit LG. The output driver unit HV includes a high breakdown voltage MOS transistor formed on the semiconductor substrate SUB. The logic unit LG includes a low breakdown voltage CMOS (Complementary Metal Oxide Semiconductor) transistor formed on the semiconductor substrate SUB. As will be described later with reference to FIG. 3, a region where a high breakdown voltage MOS transistor is formed is referred to as a high breakdown voltage MOS region HMA, and a region where a low breakdown voltage MOS transistor is formed is referred to as a low breakdown voltage MOS region LMA. .

  In the first embodiment, an example in which a lateral diffusion MOSFET (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor: LDMOSFET) is formed as a high breakdown voltage MOS transistor will be described. In the first embodiment, an example will be described in which a CMOS transistor including a p-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) and an n-channel MISFET is formed as a low breakdown voltage MOS transistor.

  In this specification, the term MOSFET or LDMOSFET includes not only a MISFET using an oxide film as a gate insulating film but also a MISFET using an insulating film other than an oxide film as a gate insulating film.

  As shown in FIG. 2, in the output driver unit HV, the high breakdown voltage MOS region HMA in which the high breakdown voltage MOS transistor is formed is surrounded by the trench structure TS included in the DTI structure in plan view. The trench structure TS is formed on the surface as the main surface of the semiconductor substrate SUB. Although not shown in FIG. 2, in the logic portion LG, the low breakdown voltage MOS region LMA (see FIG. 3) where the low breakdown voltage MOS transistor is formed is formed by the trench structure TS constituting the DTI structure in plan view. It may be surrounded.

  In the specification of the application, in the plan view, the term “when viewed from a direction perpendicular to the surface as the main surface of the semiconductor substrate SUB” is meant.

  As shown in FIG. 3, the semiconductor device of the first embodiment includes a high voltage MOS region HMA, a low voltage MOS region LMA, and a DTI region DTA between the high voltage MOS region HMA and the low voltage MOS region LMA. The semiconductor substrate SUB provided with. The semiconductor substrate SUB is made of, for example, p-type single crystal silicon (Si). In the DTI region DTA, a groove structure TS is formed on the surface as the main surface of the semiconductor substrate SUB. An insulating film IFT is formed inside the trench structure TS. The trench structure TS and the insulating film IFT form a DTI structure DS.

  Insulating film IFT includes insulating films IF1 and IF2. Among these, the insulating film IF1 is formed outside the trench structure TS, and the insulating film IF2 is formed inside the trench structure TS. Therefore, the DTI structure DS is formed by the trench structure TS and the insulating film IF2. In FIG. 3, the insulating film IF1 and the insulating film IF2 are shown as an integrated insulating film IFT.

As shown in FIG. 3, in the high breakdown voltage MOS region HMA and the low breakdown voltage MOS region LMA, an n-type buried region NBR is formed on the surface side as the main surface of the semiconductor substrate SUB. A p ⁻ type epitaxial layer EP is formed on the NBR.

In the high breakdown voltage MOS region HMA, the low breakdown voltage MOS region LMA, and the DTI region DTA, an insulating film as the element isolation region IR is formed on the surface as the main surface of the semiconductor substrate SUB, that is, the surface of the p ⁻ type epitaxial layer EP. Is formed. The insulating film as the element isolation region IR contains silicon and oxygen. The insulating film as the element isolation region IR electrically isolates semiconductor elements such as various MOS transistors described later.

  Preferably, the insulating film as the element isolation region IR is made of a silicon oxide film. Thereby, for example, an insulating film having high insulating properties can be easily formed on the surface of the semiconductor substrate SUB made of p-type single crystal silicon.

  Note that an insulating film as the element isolation region IR formed on the surface of the semiconductor substrate SUB in the DTI region DTA is referred to as an insulating film IR1.

In the high breakdown voltage MOS region HMA, an LDMOSFET QH is formed as a high breakdown voltage MOS transistor on the surface of the p ⁻ type epitaxial layer EP, that is, the surface of the semiconductor substrate SUB. The LDMOSFET QH includes a p ⁻ type epitaxial layer EP, a p type well region PWH, an n ⁺ type source region NSH, an n type offset drain region NODH, an n ⁺ type drain region NDH, a gate insulating film GI, and a gate electrode. GE.

The LDMOSFET employs a structure that ensures a high drain withstand voltage by providing a drain region with a high impurity concentration via an offset drain region with a low impurity concentration on the drain side. Therefore, the n-type impurity concentration in the n ⁺ -type drain region NDH is higher than the n-type impurity concentration in the n-type offset drain region NODH. Note that the gate electrode GE of the LDMOSFET QH is referred to as a gate electrode GEH.

The p-type well region PWH is formed in the upper layer portion of the p ⁻ -type epitaxial layer EP. The n ⁺ type source region NSH is formed in the upper layer portion of the p type well region PWH. The n ⁺ type source region NSH forms a pn junction with the p type well region PWH.

The n-type offset drain region NODH is formed in the upper layer portion of the p ⁻ -type epitaxial layer EP. The n-type offset drain region NODH forms a pn junction with the p ⁻ type epitaxial layer EP. The n ⁺ type drain region NDH is formed in the upper layer portion of the n type offset drain region NODH.

The n-type offset drain region NODH is formed at a position away from the p-type well region PWH in plan view. Therefore, between the n ⁺ type source region NSH and the n type offset drain region NODH, the p type well region PWH and the p ⁻ type epitaxial layer EP are sandwiched along the surface of the semiconductor substrate SUB.

The source-side portion of the gate electrode GEH is formed on the gate insulating film GI on the p-type well region PWH sandwiched between the n ⁺ -type source region NSH and the n-type offset drain region NODH and on the p ⁻ -type epitaxial layer EP. Is formed through. Further, the drain side portion of the gate electrode GEH is formed so as to run on the offset insulating film OIF formed on the surface of the n-type offset drain region NODH. Sidewall spacers SW are formed so as to cover the side walls of the gate electrode GEH.

A p ⁺ -type contact region PCH is formed in the upper layer portion of the p-type well region PWH and on the opposite side of the gate electrode GEH across the n ⁺ -type source region NSH. The p ⁺ type contact region PCH is for adjusting the potential of the p type well region PWH, for example.

A silicide layer SIL is formed on the surface of each of the n ⁺ type source region NSH, the n ⁺ type drain region NDH, and the p ⁺ type contact region PCH. The silicide layer SIL is a conductor part included in the LDMOSFETQH. Although illustration is omitted, a silicide layer may also be formed on the surface of the gate electrode GEH. Alternatively, the silicide layer SIL may not be formed on the surface of the n ⁺ type source region NSH, the n ⁺ type drain region NDH, or the p ⁺ type contact region PCH.

In the low breakdown voltage MOS region LMA, a p-channel type MISFET QP and an n-channel type MISFET QN are formed as low breakdown voltage MOS transistors on the surface of the p ⁻ type epitaxial layer EP, that is, the surface of the semiconductor substrate SUB. . A p-channel type MISFET QP and an n-channel type MISFET QN form a CMOS transistor.

The p-channel type MISFET QP has an n-type well region NWL, a p ⁺ -type source region PSL, a p ⁺ -type drain region PDL, a gate insulating film GI, and a gate electrode GE. Note that the gate electrode GE of the p-channel type MISFET QP is referred to as a gate electrode GEP.

The n-type well region NWL is a low breakdown voltage MOS region LMA, and is formed in the upper layer portion of the p ⁻ -type epitaxial layer EP in the region where the p-channel type MISFET QP is formed. The p ⁺ type source region PSL and the p ⁺ type drain region PDL are formed apart from each other in the upper layer portion of the n type well region NWL.

The gate electrode GEP of the p-channel type MISFETQP is formed on the n-type well region NWL sandwiched between the p ⁺ -type source region PSL and the p ⁺ -type drain region PDL via the gate insulating film GI. . Sidewall spacers SW are formed so as to cover the side walls of the gate electrode GEP.

A silicide layer SIL is formed on the surface of each of the p ⁺ type source region PSL and the p ⁺ type drain region PDL. The silicide layer SIL is a conductor part included in the p-channel type MISFET QP. Although illustration is omitted, a silicide layer may be formed on each surface of the gate electrode GEP. Further, the silicide layer SIL may not be formed on the surface of any of the p ⁺ type source region PSL and the p ⁺ type drain region PDL.

The n-channel type MISFET QN includes a p-type well region PWL, an n ⁺ -type source region NSL, an n ⁺ -type drain region NDL, a gate insulating film GI, and a gate electrode GE. Note that the gate electrode GE of the n-channel type MISFET QN is referred to as a gate electrode GEN.

The p-type well region PWL is a low breakdown voltage MOS region LMA, and is formed in the upper layer portion of the p ⁻ -type epitaxial layer EP in the region where the n-channel type MISFET QN is formed. The p-type well region PWL is formed at a position separated from the n-type well region NWL in plan view. The n ⁺ type source region NSL and the n ⁺ type drain region NDL are formed apart from each other in the upper layer portion of the p type well region PWL.

The gate electrode GEN of the n-channel type MISFET QN is formed on the portion of the p-type well region PWL sandwiched between the n ⁺ -type source region NSL and the n ⁺ -type drain region NDL via the gate insulating film GI. . Sidewall spacers SW are formed so as to cover the side walls of the gate electrode GEN.

A silicide layer SIL is formed on the surface of each of the n ⁺ type source region NSL and the n ⁺ type drain region NDL. The silicide layer SIL is a conductor portion included in the n-channel type MISFET QN. Although illustration is omitted, a silicide layer may be formed on each surface of the gate electrode GEN. Further, the silicide layer SIL may not be formed on the surface of any of the n ⁺ type source region NSL and the n ⁺ type drain region NDL.

  An insulating film LN1 is formed so as to cover the LDMOSFET QH, the p-channel type MISFET QP, and the n-channel type MISFET QN. In the DTI region DTA, an insulating film LN1 is also formed on the insulating film IR1 as the element isolation region IR.

  In the high voltage MOS region HMA, the insulating film LN1 formed so as to cover the LDMOSFET QH is referred to as an insulating film LN11. Further, in the low breakdown voltage MOS region LMA, the insulating film LN1 formed so as to cover the p-channel type MISFET QP and the n-channel type MISFET QN is referred to as an insulating film LN12. Further, in the DTI region DTA, the insulating film LN1 formed on the insulating film IR1 as the element isolation region IR is referred to as an insulating film LN13. At this time, the insulating films LN11, LN12, and LN13 are formed in the same layer.

  The insulating film LN1 is made of a material different from that of the insulating film IR1. Thereby, the etching rate of the insulating film LN1 with respect to the etching agent for etching the insulating film IR1 as the element isolation region IR can be made lower than the etching rate of the insulating film IR1 with respect to the etching agent. Therefore, the insulating film IR1 can be selectively etched without etching the insulating film LN1.

  An insulating film IF1 is formed on the insulating film LN1. The insulating film IF1 is formed so as to cover the LDMOSFET QH, the p-channel type MISFET QP, and the n-channel type MISFET QN via the insulating film LN1. The insulating film IF1 is formed so as to cover the insulating film IR1 as the element isolation region IR via the insulating film LN1. The insulating film IF1 contains silicon and oxygen.

  Preferably, the insulating film IF1 is made of a silicon oxide film. Thereby, for example, an insulating film having high insulating properties can be easily formed so as to cover the LDMOSFET QH, the p-channel type MISFET QP, and the n-channel type MISFET QN.

  In the high voltage MOS region HMA, the insulating film IF1 formed so as to cover the LDMOSFETQH through the insulating film LN1 is referred to as an insulating film IF11. Further, in the low breakdown voltage MOS region LMA, the insulating film IF1 formed so as to cover the p-channel type MISFETQP and the n-channel type MISFETQN through the insulating film LN1 is referred to as an insulating film IF12. Further, in the DTI region DTA, the insulating film IF1 formed over the insulating film IR1 as the element isolation region IR via the insulating film LN1 is defined as an insulating film IF13. At this time, the insulating films IF11, IF12, and IF13 are formed in the same layer.

  The insulating film IF1 contains silicon and oxygen similarly to the insulating film IR1. Therefore, as the etching agent for etching the insulating film IF1, the same kind of etching agent as that for etching the insulating film IR1 can be used.

  The insulating film LN1 is made of a material different from that of the insulating film IF1. Thereby, the etching rate of the insulating film LN1 with respect to the etching agent for etching the insulating film IR1 can be made lower than the etching rate of the insulating film IF1 with respect to the etching agent. Therefore, the insulating film IF1 can be selectively etched without etching the insulating film LN1 by using the same kind of etching agent as that for etching the insulating film IR1.

  When each of insulating films IR1 and IF1 contains silicon and oxygen, preferably, insulating film LN1 contains silicon and nitrogen. Further, when each of the insulating films IR1 and IF1 is made of a silicon oxide film, the insulating film LN1 is preferably made of a silicon nitride film or a silicon oxynitride film. Thereby, the etching rate of insulating film LN1 with respect to the etching agent for etching insulating films IR1 and IF1 can be made smaller than the etching rate of insulating films IR1 and IF1 with respect to the etching agent.

  In the case where each of the insulating films IR1 and IF1 contains silicon and oxygen, an etchant containing hydrofluoric acid can be used as an etchant for etching the insulating films IR1 and IF1. The etching rate of the insulating film LN1 with respect to the etching solution containing hydrofluoric acid is extremely smaller than the etching rate of the insulating films IR1 and IF1 with respect to the etching solution. Therefore, the insulating films IR1 and IF1 can be easily and selectively etched without etching the insulating film LN1.

  The DTI structure DS is formed so as to surround the LDMOSFET QH in plan view. As described above, the DTI structure DS includes the trench structure TS formed on the surface as the main surface of the semiconductor substrate SUB, and the insulating film IF2 formed in the trench structure TS.

As shown in FIG. 4, the groove structure TS has an opening OP1, an opening OP2, an opening OP3, and a groove TP1. The opening OP1 passes through the insulating film IF1 and reaches the upper surface of the insulating film LN1. The opening OP2 passes through the portion of the insulating film LN1 exposed on the bottom surface of the opening OP1, and reaches the upper surface of the insulating film IR1 as the element isolation region IR. The opening OP3 passes through the portion of the insulating film IR1 exposed at the bottom surface of the opening OP2, and reaches the p ⁻ type epitaxial layer EP including the p type well region PWL, for example, in the semiconductor substrate SUB. The groove portion TP1 is formed in the portion of the semiconductor substrate SUB exposed at the bottom surface of the opening OP3. The trench TP1 penetrates, for example, the p-type well region PWL, the p ⁻ -type epitaxial layer EP, and the n-type buried region NBR and reaches a portion of the semiconductor substrate SUB below the n-type buried region NBR. The openings OP1, OP2, OP3 and the groove TP1 are arranged in this order from the top to the bottom. The upper end of the opening OP2 communicates with the lower end of the opening OP1, and the upper end of the opening OP3 is the opening. It communicates with the lower end of OP2, and the upper end of the groove TP1 communicates with the lower end of the opening OP3.

Therefore, the trench structure TS includes the insulating film IF1, the insulating film LN1, the insulating film IR1 as the element isolation region IR, for example, the p ⁻ type epitaxial layer EP including the p type well region PWL, and the n type buried region NBR. It penetrates and reaches a portion of the semiconductor substrate SUB below the n-type buried region NBR.

  The DTI structure DS may be formed so as to surround one or more MISFETs of the p-channel type MISFET QP and the n-channel type MISFET QN in plan view.

  An insulating film IF2 is formed inside the trench structure TS. That is, the insulating film IF2 is formed inside the trench TP1, inside the opening OP3, inside the opening OP2, and inside the opening OP1. The trench structure TS is closed by the insulating film IF2 leaving a space SP inside the trench structure TS. That is, the inside of the trench structure TS is not completely filled with the insulating film IF2, and a space SP is formed inside the trench structure TS. At this time, at least the trench TP1 is closed by the insulating film IF2 leaving a space SP inside the trench TP1.

  By forming the space SP inside the trench structure TS, the leakage current of the element separated by the DTI structure DS is reduced, the breakdown voltage is increased, and the electric field strength at the portion in contact with the trench structure TS is reduced. Can do. When the LDMOSFET QH is formed in the high breakdown voltage MOS region HMA as in the first embodiment, the leakage current of the LDMOSFET QH separated by the DTI structure DS is reduced, the breakdown voltage is increased, and the trench structure TS It is possible to increase the effect of relaxing the electric field strength at the location in contact with the.

  In addition, by forming the space SP in the trench structure TS, it is possible to suppress the action of an electric field from an adjacent element that prevents the depletion layer from extending, that is, the reverse field plate effect, and as a result, the isolation breakdown voltage is increased. Can do. Moreover, since the stress in the groove structure TS can be reduced by forming the space SP in the groove structure TS, generation of crystal defects due to the stress can also be suppressed.

  In the first embodiment, the trench structure TS is formed in a region overlapping with the insulating film IR1 as the element isolation region IR in plan view. Thereby, since the DTI structure DS is formed in the element isolation region IR, it is possible to alleviate stress concentration on the upper portion of the trench TP1. Therefore, the generation of crystal defects can be further suppressed.

  The opening width of the opening OP1 is defined as an opening width WD1, the opening width of the opening OP2 is defined as an opening width WD2, the opening width of the opening OP3 is defined as an opening width WD3, and the groove width of the groove TP1 is defined as a groove width WD4. At this time, all of the opening widths WD1, WD2, and WD3 are wider than the groove width WD4. Thus, the upper end of a portion having a groove width equal to or smaller than the groove width WD4 in the groove structure TS, that is, the height position of the shoulder portion SH is set to the height of the lower surface of the insulating film IR1. Can be lowered to position. The higher the height position of the shoulder portion SH, the higher the height position at which the space SP starts to be closed when the insulating film IF2 is formed. Therefore, by reducing the height position of the shoulder portion SH, the height position at which the space SP starts to be closed when the insulating film IF2 is formed can be lowered, so that the height position of the upper end of the space SP is set. Can be lowered.

  Here, the height position of the upper end of the space SP is defined as the closing position CP of the space SP. At this time, the closing position CP of the space SP can be lowered by lowering the height position of the shoulder portion SH.

  The opening width at the upper end of the opening OP1 may be wider than the opening width at the lower end of the opening OP1, and the side surface of the opening OP1 may be inclined from a plane perpendicular to the main surface of the semiconductor substrate SUB. In such a case, the opening width WD1 of the opening OP1 is set as the opening width at the lower end of the opening OP1.

  When the opening width WD1 is wider than the groove width WD4, the side surface of the portion of the insulating film IF1 exposed inside the opening portion OP1 is the side surface of the portion of the semiconductor substrate SUB exposed inside the groove portion TP1 in the direction of the opening width WD1. Have retreated from. That is, the side surface of the opening OP1 recedes outward from the side surface of the groove TP1 in the direction of the opening width WD1.

  Further, when the opening width WD2 is wider than the groove width WD4, the side surface of the part of the insulating film LN1 exposed inside the opening OP2 is the part of the semiconductor substrate SUB exposed inside the groove TP1 in the direction of the opening width WD2. Retreating from the side. That is, the side surface of the opening OP2 recedes outward from the side surface of the groove TP1 in the direction of the opening width WD2.

  Further, when the opening width WD3 is wider than the groove width WD4, the side surface of the portion of the insulating film IR1 exposed inside the opening portion OP3 is the portion of the semiconductor substrate SUB exposed inside the groove portion TP1 in the direction of the opening width WD3. Retreating from the side. That is, the side surface of the opening OP3 recedes outward from the side surface of the groove TP1 in the direction of the opening width WD3.

  Preferably, the opening width WD1 of the opening OP1 is equal to or wider than the opening width WD2 of the opening OP2. In addition, the opening width WD3 of the opening OP3 is equal to or wider than the opening width WD2 of the opening OP2. As a result, when the opening width WD1 of the opening OP1 and the opening width WD3 of the opening OP3 are widened in the manufacturing process of the semiconductor device described later, the openings OP1, OP2, and OP3 between the plurality of DTI structures DS. It is possible to prevent or suppress the variation in the minimum opening width at, and to improve the shape accuracy.

  When the opening width WD1 of the opening OP1 is wider than the opening width WD2 of the opening OP2, the side surface of the insulating film IF1 exposed inside the opening OP1 is open in the direction of the opening width WD1. Is recessed from the side surface of the insulating film LN1 in the portion exposed inside. That is, the side surface of the opening OP1 recedes outward from the side surface of the opening OP2 in the direction of the opening width WD1.

  In addition, when the opening width WD3 of the opening OP3 is wider than the opening width WD2 of the opening OP2, the side surface of the insulating film IR1 exposed inside the opening OP3 is in the direction of the opening width WD3. Is recessed from the side surface of the insulating film LN1 in the portion exposed inside. That is, the side surface of the opening OP3 recedes outward from the side surface of the opening OP2 in the direction of the opening width WD3.

  A difference between the opening width WD2 of the opening OP2 and the groove width WD4 of the groove TP1 can be set to, for example, 200 to 500 nm. Thus, in the manufacturing process of the semiconductor device described later with reference to FIG. 16, for example, overexposure is performed using a photomask for forming the trench TP1, thereby forming the opening OP2 in the resist film PR1. An opening OR1 can be formed.

  The groove portion TP1, the opening portion OP3, the opening portion OP2 and the opening portion OP1 leave a space SP inside the groove portion TP1, inside the opening portion OP3, inside the opening portion OP2, and inside the opening portion OP1 by the insulating film IF2. The height position of the upper end of the space SP, that is, the closing position CP of the space SP is lower than the height position of the upper surface of the insulating film IF1. As a result, the closing position CP is separated downward from the upper surface of the insulating film IF1. Therefore, after forming the insulating film IF2 in the trench structure TS and on the insulating film IF1, the insulating film IF2 at a position higher than the upper surface of the insulating film IF1 is removed to remove the insulating film IF1. When flattening, it is possible to prevent or suppress the exposure of the space SP to the upper surface of the insulating film IF2.

  For example, when the thickness of the insulating film IF1 is 300 nm and the closing position CP of the space SP is lower than the height position of the upper surface of the insulating film IF1, the closing position CP of the space SP is lower than the upper surface of the insulating film LN1. Is lower than the height position higher by 300 nm.

  Preferably, the trench TP1 and the opening OP3 are closed by the insulating film IF2 while leaving the space SP inside the trench TP1 and inside the opening OP3, and the height position of the upper end of the space SP, that is, the space SP. The closing position CP is lower than the height position of the lower surface of the insulating film LN1. As a result, the closing position CP is further away from the upper surface of the insulating film IF1. Therefore, after forming the insulating film IF2 in the trench structure TS and on the insulating film IF1, the insulating film IF2 at a position higher than the upper surface of the insulating film IF1 is removed to remove the insulating film IF1. When flattening, the exposure of the space SP to the upper surface of the insulating film IF2 can be reliably prevented or suppressed.

  A contact hole CH is formed in the insulating films IF1 and LN1, and a plug PG is formed in the contact hole CH. The contact hole CH is a hole that penetrates the insulating films IF1 and LN1 and reaches the upper surface of the silicide layer SIL as a conductor. The plug PG is a connection electrode that is formed so as to fill the contact hole CH and is electrically connected to the silicide layer SIL.

  In the high voltage MOS region HMA, a contact hole CH is formed in the insulating film IF11 as the insulating film IF1 and the insulating film LN11 as the insulating film LN1, and inside the contact hole CH, the contact hole CH A plug PG is formed so as to embed the inside. In the low breakdown voltage MOS region LMA, a contact hole CH is formed in the insulating film IF12 as the insulating film IF1 and the insulating film LN12 as the insulating film LN1, and a contact hole is formed inside the contact hole CH. A plug PG is formed so as to embed the inside of CH.

In the high voltage MOS region HMA, the plug PG is electrically connected to each of the n ⁺ type source region NSH, the n ⁺ type drain region NDH, and the p ⁺ type contact region PCH via the silicide layer SIL. . In the low breakdown voltage MOS region LMA, the plug PG includes the p ⁺ type source region PSL, the p ⁺ type drain region PDL, the n ⁺ type source region NSL, and the n ⁺ type drain region NDL and the silicide layer SIL. Is electrically connected.

  Although not shown, in the high breakdown voltage MOS region HMA and the low breakdown voltage MOS region LMA, the plug PG is electrically connected to each of the gate electrodes GEH, GEP, and GEN.

  As shown in FIG. 3, a first-layer wiring M1 is formed on the insulating film IFT composed of the insulating films IF1 and IF2. The wiring M1 is electrically connected to the plug PG in the contact hole CH. An interlayer insulating film IL1 is formed over the insulating film IFT including the first layer wiring M1. In the interlayer insulating film IL1, a plug PG1 that penetrates the interlayer insulating film IL1 and reaches the wiring M1 is formed.

  A second-layer wiring M2 is formed on the interlayer insulating film IL1. The wiring M2 is electrically connected to the plug PG1 that penetrates the interlayer insulating film IL1. An interlayer insulating film IL2 is formed over the interlayer insulating film IL1 including the second-layer wiring M2. In the interlayer insulating film IL2, a plug PG2 that penetrates the interlayer insulating film IL2 and reaches the wiring M2 is formed.

  A third-layer wiring M3 is formed on the interlayer insulating film IL2. The wiring M3 is electrically connected to the plug PG2 that penetrates the interlayer insulating film IL2. An interlayer insulating film IL3 is formed over the interlayer insulating film IL2 including the third-layer wiring M3.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device of the present embodiment will be described. 5 and 6 are manufacturing process flowcharts showing a part of the manufacturing process of the semiconductor device of the first embodiment. FIG. 6 shows the manufacturing process included in step S17 of FIG. 7 to 31 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of First Embodiment. 12, 14, 22, 27, and 30 are enlarged cross-sectional views showing an enlarged configuration around the DTI structure. FIGS. 16 to 21, FIGS. 23 to 26, and 28 are diagrams showing DTI. It is an expanded sectional view which expands and shows the structure of a structure periphery further.

  12, 14, 22, 27, and 30 show examples in which the DTI structure DS is formed around one n-channel MISFET QN for easy understanding. However, as shown in FIGS. 15, 29, and 31, the DTI structure DS may be formed between the LDMOSFET QH and the p-channel type MISFET QP, or may be formed around other various elements. Good.

First, as shown in FIG. 7, a semiconductor substrate SUB is prepared (step S11 in FIG. 5). In this step S11, a semiconductor substrate SUB made of a low resistance substrate made of, for example, p-type single crystal silicon (Si) and having a resistivity (specific resistance) of, for example, about 1 to 10 mΩ · cm is prepared. The semiconductor substrate SUB includes a high breakdown voltage MOS region HMA, a low breakdown voltage MOS region LMA, and a DTI region DTA as regions on the surface side as the main surface of the semiconductor substrate SUB. An n-type buried region NBR is formed on the surface side as the main surface of the semiconductor substrate SUB. Thereafter, a p ⁻ type epitaxial layer EP made of, for example, p type single crystal Si is formed on the surface of the semiconductor substrate SUB by using a known epitaxial growth method.

Next, as shown in FIG. 8, an element isolation region IR is formed (step S12 in FIG. 5). In this step S12, the element isolation region IR is formed on the surface as the main surface of the semiconductor substrate SUB, that is, the surface of the p ⁻ type epitaxial layer EP by, for example, the STI (Shallow Trench Isolation) method or the LOCOS (Local Oxidization of Silicon) method. An insulating film is formed. Here, a case where an insulating film as the element isolation region IR is formed by the STI method will be described.

First, by dry etching using a photoresist pattern (not shown) as an etching mask, the p ⁻ type epitaxial layer EP in the region where the element isolation region IR is formed is removed to form an element isolation groove.

Next, an insulating film made of silicon oxide is deposited on the surface of the p ⁻ type epitaxial layer EP by using a CVD method or the like, thereby embedding the insulating film in the element isolation trench. In other words, an insulating film made of a silicon oxide film is formed on the surface of the semiconductor substrate SUB. As a material of the silicon oxide film, for example, a silicon oxide film formed by a CVD method using a gas containing ozone (O ₃ ) gas and tetraethoxysilane (TEOS) can be used.

  Next, the insulating film is polished using a CMP (Chemical Mechanical Polishing) method or the like to planarize the surface of the insulating film. Thereby, an insulating film as the element isolation region IR embedded in the element isolation trench is formed.

  As described above, the insulating film as the element isolation region IR formed on the surface of the semiconductor substrate SUB in the DTI region DTA is the insulating film IR1.

Further, in step S12, in the high breakdown voltage MOS region HMA, the surface of the p ⁻ type epitaxial layer EP is made of a silicon oxide film by a LOCOS method for performing a thermal oxidation process using a mask, for example, separately from the element isolation region IR. An offset insulating film OIF is formed. Note that the offset insulating film OIF can be formed by the STI method instead of the LOCOS method.

Next, a p-type well such as boron (B) is introduced into a part of the p ⁻ -type epitaxial layer EP by ion implantation using a photoresist pattern (not shown) as a mask, so that a p-type well is formed in the high breakdown voltage MOS region HMA. A region PWH is formed, and a p-type well region PWL is formed from the low breakdown voltage MOS region LMA. After ion implantation, annealing for activating the introduced impurity, that is, heat treatment may be performed.

Further, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced by ion implantation into a part of the p ⁻ type epitaxial layer EP using a photoresist pattern (not shown) as a mask, so that the high breakdown voltage MOS region HMA The n-type offset drain region NODH is formed, and the n-type well region NWL is formed in the low breakdown voltage MOS region LMA. At this time, the n-type offset drain region NODH is formed at a position away from the p-type well region PWH in plan view. After ion implantation, annealing for activating the introduced impurity, that is, heat treatment may be performed.

Next, as shown in FIG. 9, the gate electrode GE is formed (step S13 in FIG. 5). In this step S13, first, a gate insulating film GI made of a silicon oxide film or the like is formed on the surface of the p ⁻ type epitaxial layer EP by, for example, thermally oxidizing the semiconductor substrate SUB. As the gate insulating film GI, a silicon oxide film containing nitrogen, that is, a so-called oxynitride film can be used instead of the thermal oxide film.

  Next, a conductive film made of, for example, a polycrystalline silicon film into which an n-type impurity is introduced is formed on the gate insulating film GI by a CVD method or the like.

  Next, the conductor film and the gate insulating film GI are patterned by photolithography and dry etching. Thereby, the gate electrode GEH which is the gate electrode GE of the LDMOSFETQH (see FIG. 10) is formed in the high voltage MOS region HMA. Further, the gate electrode GEP which is the gate electrode GE of the p-channel type MISFET QP (see FIG. 10) is formed in the low breakdown voltage MOS region LMA, and the gate electrode of the n-channel type MISFET QN (see FIG. 10) is formed in the low breakdown voltage MOS region LMA. A gate electrode GEN which is GE is formed.

In the high breakdown voltage MOS region HMA, the gate electrode GEH is formed from the p-type well region PWH, the p ⁻ type epitaxial layer EP, and the offset insulating film OIF on the n-type offset drain region NODH. That is, the source side portion of the gate electrode GEH is formed on the p-type well region PWH and the p ⁻ -type epitaxial layer EP via the gate insulating film GI. The drain side portion of the gate electrode GEH is formed on the n-type offset drain region NODH via the offset insulating film OIF.

  On the other hand, in the low breakdown voltage MOS region LMA, the gate electrode GEP is formed on the n-type well region NWL via the gate insulating film GI, and the gate electrode GEN is formed on the p-type well region PWL with the gate insulating film GI. Formed through.

  Next, as shown in FIG. 10, an LDMOSFET QH is formed (step S14 in FIG. 5). In this step S14, a p-type impurity such as boron (B) is introduced into a part of the surface of the semiconductor substrate SUB by ion implantation, and phosphorus (P) or arsenic (As) or the like is introduced into another part of the surface of the semiconductor substrate SUB. N-type impurities are introduced by ion implantation.

  Further, sidewall spacers SW made of an insulating film such as a silicon oxide film are formed on the sidewalls of the gate electrodes GEH, GEP, and GEN. The sidewall spacer SW is formed, for example, by depositing an insulating film such as a silicon oxide film on the semiconductor substrate SUB by CVD or the like and then anisotropically etching the deposited insulating film.

  Further, after forming the sidewall spacer SW, a p-type impurity such as boron (B) is introduced into a part of the surface of the semiconductor substrate SUB by ion implantation, and phosphorus (P) is introduced into the other part of the surface of the semiconductor substrate SUB. Alternatively, an n-type impurity such as arsenic (As) is introduced by ion implantation.

As a result, in the high breakdown voltage MOS region HMA, an n ⁻ type source region NSH is formed in the upper layer portion of the p type well region PWH. The n ⁻ type source region NSH is formed so that the end of the n ⁻ type source region NSH is aligned with the gate electrode GEH. A p ⁺ type contact region PCH is formed in the upper layer portion of the p type well region PWH and on the opposite side of the gate electrode GEH across the n ⁻ type source region NSH.

In the high breakdown voltage MOS region HMA, an n ⁺ type drain region NDH is formed in the upper layer portion of the n type offset drain region NODH. The n ⁺ -type drain region NDH is formed in the upper layer portion of the n-type offset drain region NODH that is sandwiched between the element isolation region IR and the offset insulating film OIF.

Thereby, in the high breakdown voltage MOS region HMA, the p ⁻ type epitaxial layer EP, the p type well region PWH, the n ⁺ type source region NSH, the n type offset drain region NODH, the n ⁺ type drain region NDH, the gate An LDMOSFET QH having the insulating film GI and the gate electrode GEH is formed. The LDMOSFET employs a structure that ensures a high drain withstand voltage by providing a drain region with a high impurity concentration via an offset drain region with a low impurity concentration on the drain side. Therefore, the n-type impurity concentration in the n ⁺ -type drain region NDH is set higher than the n-type impurity concentration in the n-type offset drain region NODH.

On the other hand, in the low breakdown voltage MOS region LMA, ap ⁺ type source region PSL and ap ⁺ type drain region PDL are formed in the upper layer portion of the n type well region NWL. The p ⁺ type source region PSL and the p ⁺ type drain region PDL are aligned with the gate electrode GEP in the upper layer portion of each of the two n-type well regions NWL located on opposite sides of the gate electrode GEP. To be formed.

As a result, in the low breakdown voltage MOS region LMA, the p channel type MISFET QP having the n type well region NWL, the p ⁺ type source region PSL, the p ⁺ type drain region PDL, the gate insulating film GI, and the gate electrode GEP. Is formed.

In the low breakdown voltage MOS region LMA, an n ⁺ type source region NSL and an n ⁺ type drain region NDL are formed in the upper layer portion of the p type well region PWL. The n ⁺ -type source region NSL and the n ⁺ -type drain region NDL are aligned with the gate electrode GEN in the upper layer portion of each of the two p-type well regions PWL located on opposite sides of the gate electrode GEN. To be formed.

Thus, in the low breakdown voltage MOS region LMA, an n-channel type MISFET QN having a p-type well region PWL, an n ⁺ -type source region NSL, an n ⁺ -type drain region NDL, a gate insulating film GI, and a gate electrode GEN. Is formed.

Note that each of the n ⁺ type source region NSH, the n ⁺ type source region NSL, and the n ⁺ type drain region NDL includes an n ⁻ type semiconductor region and an n type impurity concentration higher than the n type impurity concentration in the n ⁻ type semiconductor region. Source / drain regions having an LDD (Lightly Doped Drain) structure composed of n ⁺ type semiconductor regions having n Further, each of the ^{p +} -type source region PSL and ^{p +} -type drain region PDL, p ^- -type semiconductor regions and, p ^{- p +} -type semiconductor region having a higher p-type impurity concentration than the p-type impurity concentration in the semiconductor region The source / drain regions of the LDD structure consisting of

Next, as shown in FIGS. 11 and 12, a silicide layer SIL is formed (step S15 in FIG. 5). In this step S15, silicide layers SIL are formed on the surfaces of the n ⁺ -type source region NSH, the n ⁺ -type drain region NDH, and the p ⁺ -type contact region PCH in the high breakdown voltage MOS region HMA. In the low breakdown voltage MOS region LMA, a silicide layer SIL is formed on each surface of the p ⁺ type source region PSL, p ⁺ type drain region PDL, n ⁺ type source region NSL, and n ⁺ type drain region NDL. The silicide layer SIL is made of a metal silicide film such as a cobalt silicide film. For example, the silicide layer SIL can be formed by using a salicide (Self Aligned Silicide) process.

Accordingly, the n ⁺ type source region NSH, the n ⁺ type drain region NDH, the p ⁺ type contact region PCH, the p ⁺ type source region PSL, the p ⁺ type drain region PDL, the n ⁺ type source region NSL, and the n ⁺ type drain region. The contact resistance between each NDL and the plug PG (see FIG. 31) can be reduced.

  Next, as shown in FIGS. 13 and 14, an insulating film LN1 is formed (step S16 in FIG. 5). In this step S16, the insulating film LN1 is formed by, for example, the CVD method so as to cover the LDMOSFET QH, the p-channel type MISFET QP, and the n-channel type MISFET QN. In addition, in the DTI region DTA, the insulating film LN1 is also formed on the insulating film IR1 as the element isolation region IR.

  In the high breakdown voltage MOS region HMA, the insulating film LN1 formed so as to cover the LDMOSFET QH is referred to as an insulating film LN11. In addition, in the low breakdown voltage MOS region LMA, the insulating film LN1 formed so as to cover the p-channel type MISFET QP and the n-channel type MISFET QN is referred to as an insulating film LN12. Further, in the DTI region DTA, the insulating film LN1 formed over the insulating film IR1 as the element isolation region IR is referred to as an insulating film LN13. At this time, the insulating films LN11, LN12, and LN13 are formed in the same layer.

  The etching rate of the insulating film LN1 with respect to the etching agent that etches the insulating film IR1 as the element isolation region IR is lower than the etching rate of the insulating film IR1 with respect to the etching agent. Therefore, the insulating film IR1 can be selectively etched without etching the insulating film LN1.

  Next, as shown in FIG. 15, a DTI structure DS is formed (step S17 in FIG. 5). In this step S17, the trench structure TS is formed on the surface of the semiconductor substrate SUB, and the insulating film IFT is formed so as to close the trench structure TS. Step S17 includes steps S21 to S27 in FIG. Below, the process of step S21-step S27 of FIG. 6 is demonstrated using FIGS. 16-28.

  First, as shown in FIGS. 16 and 17, an opening OP2 is formed (step S21 in FIG. 6). In this step S21, in the DTI region DTA, which is a region where the DTI structure DS is formed, an opening OP2 that penetrates the insulating film LN1 and reaches the upper surface of the insulating film IR1 is formed.

  First, a resist film PR1 made of a photoresist is formed on the insulating film LN1, and the formed resist film PR1 is subjected to pattern exposure and then developed. As a result, as shown in FIG. 16, an opening OR1 that penetrates the resist film PR1 and reaches the upper surface of the insulating film LN1 is formed.

  The opening width WR1 of the opening portion OR1 is determined according to the opening width WD2 of the opening portion OP2. For example, the opening width WR1 of the opening portion OR1 is equal to the opening width WD2 of the opening portion OP2. At this time, the opening OR1 is formed so that the opening width WR1 of the opening OR1 is wider than the opening width WD1 of the opening OP1 (see FIG. 20) formed in the step S23 of FIG. 6 described later. . The difference between the opening width WR1 of the opening OR1 and the opening width WD1 of the opening OP1 can be set to 200 to 500 nm, for example.

  For example, overexposure is performed using a photomask for forming the opening OP1, and the exposure amount when the resist film PR1 is subjected to pattern exposure is set to a normal exposure amount, that is, a resist film PR2 (described later using the photomask). The opening OR1 can be formed by increasing the exposure amount in the pattern exposure (see FIG. 19). Alternatively, the opening OR1 can be formed by using a photomask for forming the opening OP2 and making the exposure amount when the resist film PR1 is subjected to pattern exposure equal to the normal exposure amount.

  Next, using the resist film PR1 in which the opening OR1 is formed as an etching mask, the portion of the insulating film LN1 exposed on the bottom surface of the opening OR1 is etched. As a result, as shown in FIG. 17, an opening OP2 that penetrates the insulating film LN1 and reaches the upper surface of the insulating film IR1 is formed. At this time, the opening OP2 is formed so that the opening width WD2 of the opening OP2 is wider than the opening width WD1 of the opening OP1 (see FIG. 20) formed in a later step.

  Next, as shown in FIG. 18, an insulating film IF1 is formed (step S22 in FIG. 6). In this step S22, in the DTI region DTA, the insulating film IF1 is formed so as to embed the inside of the opening OP2 on the portion of the insulating film IR1 exposed on the bottom surface of the opening OP2 and on the insulating film LN1. The insulating film IF1 contains silicon and oxygen.

  At this time, although not shown, in the high voltage MOS region HMA, the insulating film IF1 is formed so as to cover the LDMOSFET QH via the insulating film LN1. In the low breakdown voltage MOS region LMA, the insulating film IF1 is formed so as to cover the p-channel type MISFETQP and the n-channel type MISFETQN via the insulating film LN1.

  In the high voltage MOS region HMA, the insulating film IF1 formed so as to cover the LDMOSFETQH is defined as an insulating film IF11 (see FIG. 15). In the low breakdown voltage MOS region LMA, the insulating film IF12 formed so as to cover the p-channel MISFET QP and the n-channel MISFET QN via the insulating film LN1 is referred to as an insulating film IF12 (see FIG. 15). In addition, in the DTI region DTA, the insulating film IF1 formed over the insulating film IR1 and the insulating film LN1 exposed at the bottom surface of the opening OP2 is referred to as an insulating film IF13. Further, at this time, the insulating films IF11, IF12, and IF13 are formed in the same layer.

  The insulating film IF1 contains silicon and oxygen similarly to the insulating film IR1. Therefore, as the etching agent for etching the insulating film IF1, the same kind of etching agent as that for etching the insulating film IR1 can be used.

  At this time, the etching rate of the insulating film LN1 with respect to the etching agent for etching the insulating film IR1 is lower than the etching rate of the insulating film IF1 with respect to the etching agent. Therefore, the insulating film IF1 can be selectively etched without etching the insulating film LN1 by using the same kind of etching agent as that for etching the insulating film IR1.

  When each of insulating films IR1 and IF1 contains silicon and oxygen, preferably, insulating film LN1 contains silicon and nitrogen. Further, when each of the insulating films IR1 and IF1 is made of a silicon oxide film, the insulating film LN1 is preferably made of a silicon nitride film or a silicon oxynitride film. Thereby, the etching rate of insulating film LN1 with respect to the etching agent for etching insulating films IR1 and IF1 can be made smaller than the etching rate of insulating films IR1 and IF1 with respect to the etching agent.

  In the case where each of the insulating films IR1 and IF1 contains silicon and oxygen, an etchant containing hydrofluoric acid can be used as an etchant for etching the insulating films IR1 and IF1. The etching rate of the insulating film LN1 with respect to the etching solution containing hydrofluoric acid is extremely smaller than the etching rate of the insulating films IR1 and IF1 with respect to the etching solution. Therefore, the insulating films IR1 and IF1 can be easily and selectively etched without etching the insulating film LN1.

  Next, as shown in FIGS. 19 and 20, openings OP1 and OP3 are formed (step S23 in FIG. 6). In step S23, in the DTI region DTA, an opening OP1 that penetrates the insulating film IF1 and reaches the upper surface of the insulating film IR1 is formed in a region where the opening OP2 is formed in plan view. In addition, an opening OP3 that penetrates the portion of the insulating film IR1 exposed on the bottom surface of the opening OP1 and reaches the upper surface of the semiconductor substrate SUB is formed. Therefore, the opening OP3 is formed in a region where the opening OP2 is formed in a plan view.

  First, a resist film PR2 made of a photoresist is formed on the insulating film IF1, and the formed resist film PR2 is subjected to pattern exposure and then developed. As a result, as shown in FIG. 19, an opening OR2 that penetrates the resist film PR2 and reaches the upper surface of the insulating film IF1 is formed.

  The opening width WR2 of the opening portion OR2 is determined according to the opening width WD1 of the opening portion OP1 and the opening width WD3 of the opening portion OP3. For example, the opening width WR2 of the opening portion OR2 is the opening formed in step S23. It is equal to the opening width WD1 of the part OP1 and the opening width WD3 of the opening OP3. At this time, the opening OR2 is formed so that the opening width WR2 of the opening OR2 is narrower than the opening width WD2 of the opening OP2. The difference between the opening width WR2 of the opening OR2 and the opening width WD2 of the opening OP2 can be set to, for example, 200 to 500 nm.

  For example, the opening OR2 can be formed by using a photomask for forming the opening OP1 and making the exposure amount when the resist film PR2 is subjected to pattern exposure equal to the normal exposure amount. Alternatively, underexposure is performed using a photomask for forming the opening OP2, and the exposure amount when the resist film PR2 is subjected to pattern exposure is set to a normal exposure amount, that is, the resist film PR1 is patterned using the photomask. The opening OR2 can be formed by reducing the exposure amount at the time of exposure.

Next, the insulating film IF1 and IR1 are etched using the resist film PR2 in which the opening OR2 is formed as an etching mask, and then, for example, ashing is performed to remove the resist film PR2 in which the opening OR2 is formed. . As a result, as shown in FIG. 20, the opening OP1 penetrating the insulating film IF1 and reaching the upper surface of the insulating film IR1 is formed in the region where the opening OP2 is formed in plan view. In addition, an opening OP3 that reaches the upper surface of the semiconductor substrate SUB such as the p ⁻ type epitaxial layer EP is formed through the insulating film IR1 exposed at the bottom surface of the opening OP1. The upper end of the opening OP3 communicates with the lower end of the opening OP1.

  As described above, the opening width WR2 of the opening OR2 is narrower than the opening width WD2 of the opening OP2. The opening width WD1 of the opening OP1 and the opening width WD3 of the opening OP3 are equal to the opening width WR2 of the opening OR2. Therefore, the opening width WD1 of the opening OP1 and the opening width WD3 of the opening OP3 are narrower than the opening width WD2 of the opening OP2.

Note that the insulating film IF1 need not be formed in the DTI region DTA. In this case, in plan view, the insulating film IR1 penetrates into the region where the opening OP2 is formed, for example, a p ⁻ type epitaxial layer. The opening OP3 reaching the upper surface of the semiconductor substrate SUB such as EP is formed.

Next, as shown in FIG. 21, a groove TP1 is formed (step S24 in FIG. 6). In this step S24, in the DTI region DTA, using the insulating film IF1 in which the opening OP1 is formed and the insulating film IR1 in which the opening OP3 is formed as an etching mask, the p ⁻ exposed at the bottom surface of the opening OP3. The semiconductor substrate SUB made of the type epitaxial layer EP or the like is etched by dry etching or the like. As a result, a trench portion TP1 is formed on the upper surface of the semiconductor substrate SUB, penetrating the p ⁻ type epitaxial layer EP exposed at the bottom surface of the opening OP3 and reaching partway in the thickness direction of the semiconductor substrate SUB. The upper end of the groove TP1 communicates with the lower end of the opening OP3.

When the trench portion TP1 having a high aspect ratio, which is the depth ratio to the trench width WD4, is formed by dry etching, for example, a step of etching the semiconductor substrate SUB using a gas containing sulfur hexafluoride (SF ₆ ) gas, for example, The step of covering the side surface of the groove TP1 with a gas containing a fluorocarbon gas such as C ₄ F ₈ gas is repeated.

  As described above, the opening width WD3 of the opening OP3 is narrower than the opening width WD2 of the opening OP2. Further, the groove width WD4 of the groove portion TP1 is equal to the opening width WD3 of the opening portion OP3. Therefore, in step S24, the groove portion TP1 is formed so that the groove width WD4 of the groove portion TP1 is narrower than the opening width WD2 of the opening portion OP2.

  The depth of the groove portion TP1 can be set to, for example, 15 μm, and the groove width WD4 of the groove portion TP1 can be set to, for example, 1 μm.

  Although not shown in FIG. 21, the trench TP1 may be formed so as to surround any of the LDMOSFET QH, the p-channel type MISFET QH, and the n-channel type MISFET QN in plan view.

  Next, as shown in FIGS. 22 and 23, the insulating films IF1 and IR1 are etched (step S25 in FIG. 6). In this step S25, in the DTI region DTA, the portion of the insulating film IF1 exposed in the opening OP1 and the portion of the insulating film IR1 exposed in the opening OP3 are etched with the same etching agent.

  As described above, the etching rate of insulating film LN1 with respect to the etching agent that etches insulating films IF1 and IR1 is lower than the etching rate of insulating films IF1 and IR1 with respect to the etching agent. Therefore, the insulating films IF1 and IR1 can be selectively etched without etching the insulating film LN1 by the etching agent that etches the insulating films IF1 and IR1.

  The portion of the insulating film IF1 exposed in the opening OP1 is etched with an etchant, thereby removing the insulating film IF1 inside the opening OP2 to expose the insulating film LN1, and opening the opening width WD1 of the opening OP1. It is made equal to the opening width WD2 of the part OP2, or wider than the opening width WD2 of the opening OP2. Further, by etching the insulating film IR1 in the portion exposed to the opening OP3 with an etching agent, the opening width WD3 of the opening OP3 is made equal to the opening width WD2 of the opening OP2, or the opening of the opening OP2 is opened. It is wider than the width WD2.

  Thereby, the minimum opening width in the openings OP1, OP2, and OP3 becomes equal to the opening width WD2 of the opening OP2. Therefore, it is possible to prevent or suppress variations in the minimum opening width in the openings OP1, OP2, and OP3 between the plurality of DTI structures DS, and to improve the shape accuracy.

  At this time, a groove structure TS is formed by the opening OP1, the opening OP2, the opening OP2, the opening OP3 having the opening WD3 widened, and the groove TP1. By such a groove structure TS, the height position of the upper end of the portion having a groove width equal to or smaller than the groove width WD4 in the groove structure TS, that is, the shoulder portion SH is set to the insulating film. It can be lowered to the height position of the lower surface of IR1.

  FIG. 24 shows a case where the opening width WD1 of the opening OP1 is wider than the opening width WD2 of the opening OP2, and the opening width WD3 of the opening OP3 is wider than the opening width WD2 of the opening OP2. Show.

  Further, in order to lower the height position of the shoulder portion SH to the height position of the lower surface of the insulating film IR1, the opening width WD1 of the opening portion OP1 only needs to be wider than the groove width WD4 of the groove portion TP1, and the opening portion OP1. The opening width WD1 may be narrower than the opening width WD2 of the opening OP2. Similarly, in order to lower the height position of the shoulder portion SH to the height position of the lower surface of the insulating film IR1, the opening width WD3 of the opening portion OP3 only needs to be wider than the groove width WD4 of the groove portion TP1. The opening width WD3 of OP3 may be narrower than the opening width WD2 of the opening OP2.

  Next, as shown in FIGS. 25 and 26, an insulating film IF2 is formed (step S26 in FIG. 6). In this step S26, in the DTI region DTA, the inside of the trench structure TS, that is, the inside of the trench TP1, the inside of the opening OP3, the inside of the opening OP2, the inside of the opening OP1, and the insulating film IF1, for example, The insulating film IF2 is formed by the CVD method. As a result, the trench TP1 is blocked by the insulating film IF2 while leaving the space SP inside the trench TP1. The insulating film IF2 contains silicon and oxygen.

  For example, in step S26, the insulating film IF2 made of a silicon oxide film may be formed by a plasma-enhanced chemical vapor deposition (PECVD) method using a gas containing tetraethoxysilane (TEOS) gas. it can. A silicon oxide film formed by PECVD using a gas containing TEOS gas is referred to as a PTEOS film.

Alternatively, in step S26, the insulating film IF2 made of a silicon oxide film can be formed by PECVD using a gas containing silane (SiH ₄ ) gas instead of the TEOS gas. A silicon oxide film formed by PECVD using a gas containing SiH ₄ gas is referred to as a P-SiO film.

  When the insulating film IF2 made of the PTEOS film or the P-SiO film is formed, the film thickness of the insulating film IF2 formed on the side surface of the trench structure TS that is located at a lower position than the shoulder SH is as follows. The upper side, that is, the closer to the shoulder SH of the groove structure TS, the thicker it becomes. Then, after the formation of the insulating film IF2 is started, as shown in FIG. 25, the interval between the insulating films IF2 formed on both side surfaces of the trench structure TS is narrowest in the vicinity of the shoulder portion SH. Therefore, when the insulating film IF2 is formed, the height position where the insulating film IF2 formed on both side surfaces of the trench structure TS comes into contact and the space SP starts to be closed is substantially equal to the height position of the shoulder portion SH. . Then, by subsequently forming the insulating film IF2, as shown in FIG. 26, the trench TP1 is blocked by the insulating film IF2 leaving a space SP inside the trench TP1.

  As described above, in the first embodiment, the height position of the shoulder portion SH can be lowered to the height position of the lower surface of the insulating film IR1. Further, the higher the height position of the shoulder portion SH, the higher the height position at which the space SP starts to be closed when the insulating film IF2 is formed. Therefore, by reducing the height position of the shoulder portion SH, the height position at which the space SP starts to be closed when the insulating film IF2 is formed can be lowered. Therefore, the height position of the upper end of the space SP, That is, the blocking position CP of the space SP can be lowered.

Instead of forming a single-layer film made of the PTEOS film or P-SiO film as the insulating film IF2, an insulating film is formed as a laminated film in which a plurality of insulating films such as three layers are laminated. You can also. For example, when forming a laminated film in which three insulating films are laminated, a gas containing ozone (O ₃ ) gas and tetraethoxysilane (TEOS) gas is formed on the inner wall of the trench structure TS as the first insulating film. An insulating film made of a silicon oxide film called a so-called O ₃ TEOS film is formed by the CVD method used. Next, an insulating film made of the above-described PTEOS film or P-SiO film is formed on the first insulating film as the second insulating film so as not to block the trench structure TS. Next, an insulating film made of an O ₃ TEOS film is formed on the second insulating film as the third insulating film, similarly to the first insulating film. The groove structure TS is closed while leaving a space SP inside the groove structure TS.

  At this time, since the step coverage of the first insulating film is relatively high, the thickness of the first insulating film on the inner wall of the trench TP1 is substantially uniform regardless of the height position. On the other hand, since the step coverage of the second insulating film is lower than the step coverage of the first insulating film, the thickness of the second insulating film on the inner wall of the trench TP1 is higher, that is, the shoulder portion. The closer to SH, the thicker it becomes, and the distance between the insulating films IF2 formed on both side surfaces of the trench TP1 is the narrowest in the vicinity of the shoulder SH. Furthermore, since the step coverage of the third insulating film is higher than the step coverage of the second insulating film, the closing position CP of the space SP can be lowered to the vicinity of the shoulder SH.

  Next, as shown in FIGS. 27 and 28, the insulating film IF2 is planarized (step S27 in FIG. 6). In step S27, the insulating film IF2 is polished using a CMP method or the like, and the surface of the insulating film IF2 is planarized. 27 and 28 show an example in which the insulating film IF2 over the insulating film IF1 is polished and removed. As a result, as shown in FIG. 15, the DTI structure DS is formed by the trench structure TS and the insulating film IF2.

Next, as shown in FIGS. 29 and 30, a contact hole CH is formed (step 18 in FIG. 5). In this step S18, in the high-breakdown-voltage MOS region HMA, holes that penetrate through the insulating films IF1 and LN1 and reach the n ⁺ type source region NSH, n ⁺ type drain region NDH, and p ⁺ type contact region PCH, Contact hole CH is formed. Further, in the low breakdown voltage MOS region LMA, a contact hole CH as a hole reaching each of the p ⁺ type source region PSL, the p ⁺ type drain region PDL, the n ⁺ type source region NSL and the n ⁺ type drain region NDL is formed. To do.

First, the insulating film IF1 is etched with an etching agent for etching the insulating film IF1, using a resist film (not shown) in which the opening is formed as an etching mask. Next, the insulating film LN1 is etched with an etching agent for etching the insulating film LN1, using a resist film (not shown) in which the opening is formed as an etching mask. Accordingly, the n ⁺ type source region NSH, the n ⁺ type drain region NDH, the p ⁺ type contact region PCH, the p ⁺ type source region PSL, the p ⁺ type drain region PDL, and the n ⁺ penetrate through the insulating films IF1 and LN1. Contact holes CH reaching each of type source region NSL and n ⁺ type drain region NDL are formed.

  At this time, the etching rate of the insulating film LN1 with respect to the etching agent for etching the insulating film IF1 is lower than the etching rate of the insulating film IF1 with respect to the etching agent. Thereby, in the high breakdown voltage MOS region HMA and the low breakdown voltage MOS region LMA, etching is performed to etch the insulating film IF1 when forming a portion of the contact hole CH that penetrates the insulating film IF1 and reaches the upper surface of the insulating film LN1. Etching with the agent can be accurately stopped on the upper surface of the insulating film LN1. Therefore, the contact hole CH can be formed with high shape accuracy.

  Next, as shown in FIGS. 31 and 4, a plug PG is formed (step S19 in FIG. 5). In this step S19, in the high breakdown voltage MOS region HMA and the low breakdown voltage MOS region LMA, a barrier film made of a titanium nitride film is formed in the contact hole CH as the hole and on the insulating film IF1 by the CVD method. Next, a conductor film made of a tungsten film is formed on the barrier film by a CVD method so as to fill the inside of the contact hole CH. Thereafter, unnecessary conductor films and barrier films on the insulating film IFT are removed by a CMP method or an etch back method. As a result, a plug PG that is formed so as to fill the inside of the contact hole CH and includes a conductor film made of, for example, a tungsten film can be formed.

n ⁺ type source region NSH, n ⁺ type drain region NDH, p ⁺ type contact region PCH, p ⁺ type source region PSL, p ⁺ type drain region PDL, n ⁺ type source region NSL and n ⁺ type drain region NDL, respectively A silicide layer SIL as a conductor portion is formed on the surface of the. That is, the contact hole CH reaches the upper surface of the silicide layer SIL. Therefore, the plug PG formed so as to fill the contact hole CH is electrically connected to the silicide layer SIL.

  Next, as shown in FIG. 3, a first-layer wiring M1 mainly composed of, for example, an aluminum (Al) alloy film is formed on the insulating film IFT made of the insulating films IF1 and IF2. The wiring M1 is electrically connected to the plug PG in the contact hole CH. Thereafter, an interlayer insulating film IL1 made of, for example, a silicon oxide film is formed on the insulating film IFT including the first layer wiring M1, and a plug PG1 penetrating the interlayer insulating film IL1 and reaching the wiring M1 is formed.

  Next, a second-layer wiring M2 mainly composed of, for example, an Al alloy film is formed on the interlayer insulating film IL1. The wiring M2 is electrically connected to the plug PG1 that penetrates the interlayer insulating film IL1. Thereafter, an interlayer insulating film IL2 made of, for example, a silicon oxide film is formed on the interlayer insulating film IL1 including the second layer wiring M2, and a plug PG2 penetrating the interlayer insulating film IL2 and reaching the wiring M2 is formed. .

  Next, a third-layer wiring M3 mainly composed of, for example, an Al alloy film is formed on the interlayer insulating film IL2. The wiring M3 is electrically connected to the plug PG2 that penetrates the interlayer insulating film IL2. Thereafter, an interlayer insulating film IL3 made of, for example, a silicon oxide film is formed on the interlayer insulating film IL2 including the third-layer wiring M3. In this way, the semiconductor device shown in FIG. 3 is formed.

<About the blocking position>
Next, the closing position of the space when the groove is closed while leaving a space in the groove will be described in comparison with the semiconductor device of the comparative example. 32 to 34 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the comparative example.

  In the semiconductor device of the comparative example, for example, in the manufacturing process similar to the manufacturing process of the semiconductor device of the first embodiment, when the opening OP2 is formed by performing the same process as the process of step S21 in FIG. The opening OP2 is formed so that the opening width WD2 of OP2 is equal to the groove width WD4 of the groove TP1 formed in a later step. Therefore, after that, the same processes as those in steps S22 to S24 in FIG. 6 are performed, and in the groove structure TS100 to be formed, as shown in FIG. 32, the opening width WD2 of the opening OP2 is the groove of the groove TP1. It is equal to the width WD4.

  Thereafter, the same process as step S25 of FIG. 6 is performed, and when the opening width WD1 of the opening OP1 and the opening width WD3 of the opening OP3 are widened, as shown in FIG. The opening width WD1 of the portion OP1 and the opening width WD3 of the opening OP3 are wider than the groove width WD4 of the groove portion TP1. However, since the opening width WD2 of the opening portion OP2 is equal to the groove width WD4 of the groove portion TP1, the upper end of the portion having a groove width equal to or smaller than the groove width WD4 in the groove structure TS100, That is, the height position of the shoulder portion SH100 is equal to the height position of the upper surface of the insulating film LN1, and is higher than the height position of the lower surface of the insulating film IR1.

  As described above, the higher the height position of the shoulder portion SH100, the higher the height position at which the space SP100 starts to be closed when the insulating film IF2 is formed. Therefore, in the comparative example, when the height of the shoulder portion SH100 is increased, the process similar to the process of step S26 of FIG. 6 is performed to form the insulating film IF2, as shown in FIG. The height position where the blockage of the space SP100 starts is increased. Therefore, in the comparative example, the height position of the upper end of the space SP100, that is, the closing position CP100 of the space SP100 cannot be lowered. Therefore, in the comparative example, by forming the insulating film IF2 inside the trench TP1, the trench TP1 can be closed while leaving the space SP100 in the trench TP1, but the closing position CP100 of the space SP100 is more than the desired position. May be high.

  When the blocking position CP100 of the space SP100 becomes higher than a desired position, after the insulating film IF2 is formed, for example, when the insulating film IF2 is polished and the surface of the insulating film IF2 is planarized, the surface of the insulating film IF2 is high. The position is lower than the closing position CP100 of the space SP100. Thereby, as shown in FIG. 34, the space SP100 may be exposed on the surface of the insulating film IF2. Therefore, there is a possibility that the polishing slurry enters the space SP100 or the cleaning liquid enters the space SP100 in the subsequent cleaning process. In addition, after that, the slurry or the cleaning liquid that has entered the space SP100 blows out from the space SP100, and foreign matter is generated. For this reason, defects may occur in the shape of the semiconductor device, and the performance of the semiconductor device may be deteriorated.

In order to prevent the space SP100 from being exposed to the surface of the insulating film IF2, it is necessary to raise the height position of the surface of the insulating film IF2 after the surface of the insulating film IF2 is planarized. Therefore, the aspect ratio that is the ratio of the depth to the width of the contact hole CH (see FIGS. 29 and 30) that penetrates the insulating films IF1 and LN1 and reaches, for example, the n ⁺ -type source region NSL and the like becomes high. Therefore, the contact hole CH and the plug PG (see FIGS. 31 and 4) cannot be formed with high shape accuracy, and the performance of the semiconductor device may be deteriorated.

<Main features and effects of the present embodiment>
The semiconductor device according to the first embodiment includes an insulating film IR1 formed on the main surface of the semiconductor substrate SUB and an insulating film LN1 formed on the insulating film IR1. In the semiconductor device of the first embodiment, the opening OP2 that reaches the insulating film IR1 through the insulating film LN1 and the opening that reaches the semiconductor substrate SUB through the insulating film IR1 exposed in the opening OP2 are provided. A portion OP3 and a groove portion TP1 formed in the portion of the semiconductor substrate SUB exposed to the opening OP3. The opening width WD2 of the opening OP2 and the opening width WD3 of the opening OP3 are wider than the groove width WD4 of the groove TP1. Further, the trench part TP1 is closed by the insulating film IF2 leaving a space SP inside the trench part TP1.

  Thereby, the height position of the upper end of the portion having a groove width equal to or smaller than the groove width WD4 in the groove structure TS, that is, the shoulder portion SH is set to the height of the lower surface of the insulating film IR1. The position can be lowered. The higher the height position of the shoulder portion SH, the higher the height position at which the space SP starts to be closed when the insulating film IF2 is formed. Therefore, by reducing the height of the shoulder portion SH, the height position at which the space SP starts to be closed when the insulating film IF2 is formed can be lowered. Therefore, the height position of the upper end of the space SP, that is, The closing position CP of the space SP can be lowered.

  Thus, according to the first embodiment, the closed position CP of the space SP can be easily lowered to a desired position. Therefore, for example, when the insulating film IF2 is polished and the surface of the insulating film IF2 is planarized, it is possible to prevent or suppress the height position of the surface of the insulating film IF2 from becoming lower than the closing position CP of the space SP. it can. In addition, it is possible to prevent or suppress the space SP from being exposed on the surface of the insulating film IF2 and the polishing slurry from entering the space SP and the cleaning liquid from entering the space SP in the subsequent cleaning step. Therefore, after that, the slurry or cleaning liquid that has entered the space SP blows out from the space SP, thereby preventing or suppressing the generation of foreign matter, and preventing or suppressing the occurrence of defects in the shape of the semiconductor device. Can be improved.

Further, since the height position of the surface of the insulating film IF2 after planarizing the surface of the insulating film IF2 can be lowered, the insulating film IF1 and LN1 are penetrated to reach, for example, the n ⁺ type source region NSL. The aspect ratio which is the ratio of the depth to the width of the contact hole CH (see FIGS. 29 and 30) can be reduced. Therefore, the contact hole CH and the plug PG (see FIGS. 31 and 4) can be formed with high shape accuracy, and the performance of the semiconductor device can be improved.

(Embodiment 2)
In the method of manufacturing the semiconductor device according to the first embodiment, the insulating film IF1 is formed after the opening OP2 is formed. On the other hand, in the method of manufacturing the semiconductor device of the second embodiment, the opening OP2 is formed after the insulating film IF1 is formed.

  The configuration of the semiconductor device according to the second embodiment is the same as the configuration of the semiconductor device according to the first embodiment, and the description thereof is omitted.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. FIG. 35 is a manufacturing process flow chart showing a part of the manufacturing process of the semiconductor device of Second Embodiment. FIG. 35 shows a manufacturing process included in step S17 of FIG. 5 when the manufacturing process flow shown in FIG. 5 is performed as a manufacturing process of the semiconductor device of the second embodiment. 36 to 42 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of Second Embodiment. 36 to 42 are enlarged sectional views showing the configuration around the DTI structure.

  Also in the second embodiment, as in the first embodiment, the DTI structure DS may be formed between the LDMOSFET QH and the p-channel type MISFET QP, or formed around other various elements. May be.

  Also in the second embodiment, the same process as the process described in the first embodiment with reference to FIGS. 7 to 14 (step S11 to step S16 in FIG. 5) is performed to form the insulating film LN1.

  Next, the DTI structure DS is formed (step S17 in FIG. 5). In the second embodiment, step S17 in FIG. 5 includes steps S31 to S38 in FIG. Hereinafter, steps S31 to S38 in FIG. 35 will be described with reference to FIGS. 36 to 42 and FIGS. 25 to 28.

  First, as shown in FIG. 36, an insulating film IF1 is formed (step S31 in FIG. 35). In this step S31, an insulating film IF1 is formed on the insulating film LN1 in the DTI region DTA, which is a region where the DTI structure DS is formed. The insulating film IF1 contains silicon and oxygen. Specifically, the insulating film IF1 can be formed by performing a process similar to the process of step S22 of FIG. 6 in the first embodiment. Although not shown, the insulating film IF1 is also formed in the high breakdown voltage MOS region HMA and the low breakdown voltage MOS region LMA (see FIG. 13) as in the first embodiment.

  Next, as shown in FIGS. 37 and 38, an opening OP1 is formed (step S32 in FIG. 35). In this step S32, an opening OP1 that penetrates the insulating film IF1 and reaches the upper surface of the insulating film LN1 is formed in the DTI region DTA.

  First, a resist film PR3 made of a photoresist is formed on the insulating film IF1, and the formed resist film PR3 is subjected to pattern exposure and then developed. As a result, as shown in FIG. 37, an opening OR3 that penetrates the resist film PR3 and reaches the upper surface of the insulating film IF1 is formed. The opening width WR3 of the opening OR3 is determined according to the opening width WD1 of the opening OP1, and for example, the opening width WR2 of the opening OR2 is the opening width WD1 of the opening OP1 formed in step S32 (see FIG. 38). ).

  Next, the portion of the insulating film IF1 exposed on the bottom surface of the opening OR3 is etched using the resist film PR3 in which the opening OR3 is formed as an etching mask. Thereafter, the resist film PR3 in which the opening OR3 is formed is removed by, for example, ashing. As a result, as shown in FIG. 38, an opening OP1 that penetrates the insulating film IF1 and reaches the upper surface of the insulating film LN1 is formed.

  Next, as shown in FIG. 39, an opening OP2 is formed (step S33 in FIG. 35). In this step S33, in the DTI region DTA, an opening OP2 that penetrates the portion of the insulating film LN1 exposed at the bottom surface of the opening OP1 and reaches the upper surface of the insulating film IR1 is formed.

  Specifically, using the insulating film IF1 in which the opening OP1 is formed as an etching mask, the portion of the insulating film LN1 exposed on the bottom surface of the opening OP1 is etched with an etching agent. As a result, an opening OP2 that penetrates the portion of the insulating film LN1 exposed on the bottom surface of the opening OP1 and reaches the upper surface of the insulating film IR1 is formed.

  In step S33, the insulating film LN1 is isotropically etched with an etchant. Further, the etching rate of the insulating film IF1 with respect to the etching agent used in step S33 and the etching rate of the insulating film IR1 with respect to the etching agent are lower than the etching rate of the insulating film LN1 with respect to the etching agent. Therefore, after the opening OP2 that reaches the upper surface of the insulating film IR1 through the portion of the insulating film LN1 exposed on the bottom surface of the opening OP1 is formed, the side surface of the portion of the insulating film LN1 exposed inside the opening OP2 is formed. However, in the direction of the opening width WD2, it recedes from the side surface of the insulating film IF1 at the portion exposed inside the opening OP1. That is, the side surface of the opening OP2 recedes outward from the side surface of the opening OP1 in the direction of the opening width WD2. Accordingly, the opening OP2 is formed so that the opening width WD2 of the opening OP2 is wider than the opening width WD1 of the opening OP1.

  When the insulating films IF1 and IR1 contain silicon and oxygen and the insulating film LN1 contains silicon and nitrogen, wet etching can be performed as isotropic etching, and phosphoric acid is contained as an etching agent. An etching solution can be used. Thereby, compared with the etching rate of the insulating film LN1, the etching rates of the insulating films IF1 and IR1 can be extremely reduced. Therefore, when the insulating film LN1 is etched to form the opening OP2, the insulating film IF1 exposed inside the opening OP1 and the insulating film IR1 exposed on the bottom surface of the opening OP2 are not etched. Can do.

  Next, as shown in FIG. 40, the opening OP3 is formed (step S34 in FIG. 35). In this step S34, the opening OP3 is formed by anisotropically etching the insulating film IR1 using the insulating film IF1 in which the opening OP1 is formed as an etching mask in the DTI region DTA.

  In this step S34, the opening OP3 is formed by anisotropically etching the insulating film IR1 so that the opening width WD3 of the opening OP3 is equal to the opening width WD1 of the opening OP1. Further, the opening width WD1 of the opening OP1 is narrower than the opening width WD2 of the opening OP2. Therefore, in this step S34, the opening OP3 is formed so that the opening width WD3 of the opening OP3 is narrower than the opening width WD2 of the opening OP2. That is, in step S34, the side surface of the portion of the insulating film LN1 exposed inside the opening OP2 is set back from the side surface of the portion of the insulating film IR1 exposed inside the opening OP3 in the direction of the opening width WD2. Thus, the opening OP3 is formed. In other words, the opening OP3 is formed such that the side surface of the opening OP2 is in a state of retreating outward from the side surface of the opening OP3 in the direction of the opening width WD2.

Next, as shown in FIG. 41, a groove TP1 is formed (step S35 in FIG. 35). In this step S35, in the DTI region DTA, using the insulating film IF1 in which the opening OP1 is formed and the insulating film IR1 in which the opening OP3 is formed as an etching mask, the p ⁻ exposed at the bottom surface of the opening OP3. The semiconductor substrate SUB made of the type epitaxial layer EP or the like is etched by dry etching or the like. As a result, a trench portion TP1 is formed on the upper surface of the semiconductor substrate SUB, penetrating the p ⁻ type epitaxial layer EP exposed at the bottom surface of the opening OP3 and reaching partway in the thickness direction of the semiconductor substrate SUB. The upper end of the groove TP1 communicates with the lower end of the opening OP3.

  The specific method for forming the groove TP1 in step S35 can be the same as the method for forming the groove TP1 in step S24 of FIG. 6 described in the first embodiment.

  As described above, the opening width WD3 of the opening OP3 is narrower than the opening width WD2 of the opening OP2. Further, the groove width WD4 of the groove portion TP1 is equal to the opening width WD3 of the opening portion OP3. Therefore, in step S35, the groove portion TP1 is formed so that the groove width WD4 of the groove portion TP1 is narrower than the opening width WD2 of the opening portion OP2. That is, the side surface of the portion of the insulating film LN1 exposed inside the opening OP2 is in a state of retreating from the side surface of the portion of the semiconductor substrate SUB exposed inside the trench TP1 in the direction of the opening width WD2. The groove portion TP1 is formed. In other words, the groove portion TP1 is formed so that the side surface of the opening portion OP2 is in a state of retreating outward from the side surface of the groove portion TP1 in the direction of the opening width WD2.

  Next, as shown in FIG. 42, the insulating films IF1 and IR1 are etched (step S36 in FIG. 35). In this step S36, in the DTI region DTA, the portion of the insulating film IF1 exposed in the opening OP1 and the portion of the insulating film IR1 exposed in the opening OP3 are etched with the same etching agent.

  Similar to the first embodiment, the etching rate of insulating film LN1 with respect to the etching agent for etching insulating films IF1 and IR1 is lower than the etching rate of insulating films IF1 and IR1 with respect to the etching agent. Therefore, the insulating films IF1 and IR1 can be selectively etched without etching the insulating film LN1 by the etching agent that etches the insulating films IF1 and IR1.

  The portion of the insulating film IF1 exposed at the opening OP1 is etched with an etchant so that the opening width WD1 of the opening OP1 is equal to the opening width WD2 of the opening OP2 or the opening width WD2 of the opening OP2. Than spread. Further, by etching the insulating film IR1 in the portion exposed to the opening OP3 with an etching agent, the opening width WD3 of the opening OP3 is made equal to the opening width WD2 of the opening OP2, or the opening of the opening OP2 is opened. It is wider than the width WD2.

  Thereby, the minimum opening width in the openings OP1, OP2, and OP3 becomes equal to the opening width WD2 of the opening OP2. Therefore, it is possible to prevent or suppress variations in the minimum opening width in the openings OP1, OP2, and OP3 between the plurality of DTI structures DS, and to improve the shape accuracy.

  At this time, a groove structure TS is formed by the opening OP1, the opening OP2, the opening OP2, the opening OP3 having the opening WD3 widened, and the groove TP1. By such a groove structure TS, the height position of the upper end of the portion having a groove width equal to or smaller than the groove width WD4 in the groove structure TS, that is, the shoulder portion SH is set to the insulating film. It can be lowered to the height position of the lower surface of IR1.

  The cross-sectional view when the opening width WD1 of the opening OP1 is wider than the opening width WD2 of the opening OP2 and the opening width WD3 of the opening OP3 is wider than the opening width WD2 of the opening OP2 is as follows. It is the same as the sectional view shown in FIG.

  In order to lower the height position of the shoulder portion SH to the height position of the lower surface of the insulating film IR1, the opening width WD1 of the opening portion OP1 only needs to be wider than the groove width WD4 of the groove portion TP1, and the opening portion OP2 It may be narrower than the opening width WD2. Similarly, in order to lower the height position of the shoulder portion SH to the height position of the lower surface of the insulating film IR1, the opening width WD3 of the opening portion OP3 only needs to be wider than the groove width WD4 of the groove portion TP1, and the opening portion OP2 It may be narrower than the opening width WD2.

  Next, the insulating film IF2 is formed (Step S37 in FIG. 35). In this step S37, the same process as the process of step S26 of FIG. 6 in the first embodiment is performed in the DTI region DTA, and as shown in FIG. 26, the trench TP1 is formed inside the trench TP1 by the insulating film IF2. To block the space SP. The insulating film IF2 contains silicon and oxygen.

  As described above, also in the second embodiment, the height position of the shoulder portion SH can be lowered to the height position of the lower surface of the insulating film IR1 as in the first embodiment. Further, the higher the height position of the shoulder portion SH, the higher the height position at which the space SP starts to be closed when the insulating film IF2 is formed. Therefore, by reducing the height position of the shoulder portion SH, the height position at which the space SP starts to be closed when the insulating film IF2 is formed can be lowered. Therefore, the height position of the upper end of the space SP, That is, the blocking position CP of the space SP can be lowered.

  Next, the insulating film IF2 is planarized (step S38 in FIG. 35). In step S38, the same process as step S27 of FIG. 6 in the first embodiment is performed to planarize the surface of insulating film IF2 as shown in FIGS. Thereby, the DTI structure DS is formed by the trench structure TS and the insulating film IF2.

  In the first embodiment, in the step of forming the DTI structure DS (step S21 to step S27 in FIG. 6), there are two steps (step S21 and step in FIG. 6) of forming the opening by pattern exposure of the resist film. S23). On the other hand, in the second embodiment, in the step of forming the DTI structure DS (steps S31 to S38 in FIG. 35), there is one step (step in FIG. 35) for pattern exposure of the resist film to form an opening. S32) only. Therefore, the number of manufacturing steps of the semiconductor device can be reduced.

  Thereafter, the steps described in the first embodiment with reference to FIGS. 29 to 31 and FIG. 4 (step S18 and step S19 in FIG. 5) and the subsequent steps are performed, and the semiconductor device shown in FIG. It is formed.

<First Modification of Semiconductor Device Manufacturing Method>
As a first modification of the method of forming the opening OP2 by performing the process of step S33 in FIG. 35, the following method can be performed.

  43 and 44 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the first modification example of the second embodiment.

  In the first modified example, when the opening OP1 is formed by performing the same process as the step S32 in FIG. 35, the resist film PR3 in which the opening OR3 is formed is used as an etching mask. After the portion of the insulating film IF1 exposed at the bottom surface of the OR3 is etched, the resist film PR3 is not removed as shown in FIG. Therefore, as shown in FIG. 43, after the opening OP1 that reaches the upper surface of the insulating film LN1 through the insulating film IF1 is formed, the opening OR3 is formed on the insulating film IF1 in which the opening OP1 is formed. The resist film PR3 thus left remains.

  Next, when the opening OP2 is formed by performing the same process as step S33 of FIG. 35, the resist film PR3 in which the opening OR3 is formed and the insulating film IF1 in which the opening OP1 is formed. Is used as an etching mask to etch the portion of the insulating film LN1 exposed at the bottom of the opening OP1 with an etchant. As a result, as shown in FIG. 44, an opening OP2 that penetrates through the portion of the insulating film LN1 exposed at the bottom surface of the opening OP1 and reaches the upper surface of the insulating film IR1 is formed.

  Next, the resist film PR3 in which the opening OR3 is formed is removed by, for example, ashing. Thereafter, similar to the second embodiment, the same processes as steps S34 to S38 in FIG. 35 are performed, and the processes described in the first embodiment with reference to FIGS. 29 to 31 and 4 (FIG. 5). Steps S18 and S19) and subsequent steps are performed to form the semiconductor device shown in FIG.

  Alternatively, after forming the opening OP2, without performing removal of the resist film PR3, the same process as step S34 in FIG. 35 is performed to form the resist film PR3 having the opening OR3 and the opening OP1. The opening OP3 may be formed using the insulating film IF1 as an etching mask. Thereby, since the upper surface of the insulating film IF1 is not etched when forming the opening OP3, the thickness of the insulating film IF1 used as an etching mask when forming the trench TP1 can be increased. Therefore, for example, it is advantageous when the trench portion TP1 having a high aspect ratio, which is the ratio of the depth to the trench width WD4, is formed by dry etching.

<Main features and effects of the present embodiment>
The semiconductor device according to the second embodiment has the same characteristics as those of the semiconductor device according to the first embodiment. For this reason, the semiconductor device of the second embodiment has the same effects as those of the semiconductor device of the first embodiment, such as being able to reduce the closing position CP of the space SP.

  In addition, in the method of manufacturing the semiconductor device of the second embodiment, in the step of forming the DTI structure DS, the number of times of performing the step of forming the opening by pattern exposure of the resist film is one time. In the manufacturing method of the semiconductor device according to the first embodiment, the number is less than twice, which is the number of times of performing the step of pattern exposure of the resist film to form the opening.

  That is, in the method of manufacturing the semiconductor device according to the second embodiment, when the opening OP2 is formed in the insulating film LN1 made of, for example, a silicon nitride film using, for example, an etchant containing phosphoric acid, the opening OP1 is formed. The insulating film LN1 is etched using the formed insulating film IF1 as an etching mask. The opening OP2 is formed in alignment with the opening OP1. Therefore, it is not necessary to form a resist film in which the opening is formed only for forming the opening OP2, and therefore it is not necessary to prepare a separate photomask only for forming the opening OP2. It is not necessary to separately perform exposure and development only for forming the film.

  Therefore, compared to the first embodiment, the number of manufacturing steps of the semiconductor device can be reduced, and the manufacturing cost of the semiconductor device can be reduced.

  On the other hand, in the method of manufacturing the semiconductor device of the first embodiment, as shown in FIG. 17, the resist film PR1 having the opening OR1 is formed only for forming the opening OP2, for example, an insulating film By anisotropically etching LN1, the opening width WD2 of the opening OP2 can be made equal to the opening width WR1 of the opening OR1. Therefore, by performing isotropic etching of the insulating film LN1, the opening OP2 is compared with the manufacturing method of the semiconductor device of the second embodiment in which the opening width WD2 of the opening OP2 is wider than the opening width WD1 of the opening OP1. The accuracy of the opening width WD2 can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

CH Contact hole CHP Semiconductor chip CP Blocking position DS DTI structure DTA DTI region EP p ^- type epitaxial layers GE, GEH, GEN, GEP Gate electrode GI Gate insulation film HMA High voltage MOS region HV Output driver part IF1, IF11-IF13, IF2 , IFT insulating film IL1 to IL3 Interlayer insulating film IR Element isolation region IR1 Insulating film LG Logic part LMA Low breakdown voltage MOS region LN1, LN11 to LN13 Insulating film M1 to M3 Wiring NBR n-type buried region NDH, NDL n ⁺ type drain region NODH n-type offset drain region NSH, NSL ^{n +} -type source region NWL n-type well region OIF offset insulating film OP1 to OP3, OR1 to OR3 opening PCH ^{p +} -type contact region PDL ^{p +} -type drain region PG, PG1, P 2 plugs PR1~PR3 resist film PSL ^{p +} -type source region PWH, PWL, p-type well region QH LDMOSFET
QN, QP MISFET
SH Shoulder SIL Silicide layer SP Space SUB Semiconductor substrate SW Side wall spacer TP1 Groove TS Groove structure WD1 to WD3, WR1 to WR3 Opening width WD4 Groove width

Claims (3)

(A) forming a first insulating film on the main surface of the semiconductor substrate;
(B) forming a second insulating film on the first insulating film;
(C) forming a first opening that reaches the first insulating film through the second insulating film;
(D) After the step (c), the first opening is buried on the first insulating film and the second insulating film in the portions exposed to the first opening. 3 forming an insulating film;
(E) forming a second opening that reaches the first insulating film through the third insulating film in a region where the first opening is formed;
(F) forming a third opening reaching the semiconductor substrate through the first insulating film in the first insulating film exposed in the second opening;
(G) forming a groove in the semiconductor substrate at a portion exposed in the third opening;
(H) After the step (g), the third insulating film exposed in the second opening and the first insulating film exposed in the third opening are etched with an etchant, and the third insulating film Forming a fourth opening wider than the second opening and forming a fifth opening wider than the third opening in the first insulating film;
(I) After the step (h), forming a fourth insulating film inside the groove, the fifth opening, the first opening, and the fourth opening;
Have
In the step (i), the groove is closed by the fourth insulating film, leaving a space inside the groove,
The opening width of the fourth opening is equal to the opening width of the first opening or wider than the opening width of the first opening,
The first insulating film and the third insulating film are made of a silicon oxide film,
The method for manufacturing a semiconductor device, wherein the second insulating film is made of a silicon nitride film or a silicon oxynitride film. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein an opening width of the fifth opening is equal to an opening width of the first opening or wider than an opening width of the first opening. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the etchant is an etchant containing hydrofluoric acid.

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