JP2018078227A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having stable electrical characteristics; and provide a semiconductor device having high reliability.SOLUTION: A semiconductor device has a gate electrode, a source electrode, a drain electrode, an oxide semiconductor having a channel formation region and a gate insulator, in which the gate insulator has a metal oxide and the metal oxide has a density of not less than 7.0 g/cmand not more than 9.0 g/cmor has route mean square (RMS) roughness equal to or less than 0.5 nm within a measurement range of 1 μm×1 μm.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to a semiconductor device and a method for driving the semiconductor device. Another embodiment of the present invention relates to an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may include a semiconductor device.

A technique for forming a transistor using a semiconductor thin film has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

For example, a technique for manufacturing a display device using a transistor including zinc oxide or an In—Ga—Zn-based oxide as an active layer as an oxide semiconductor is disclosed (see Patent Documents 1 and 2). .

In recent years, a technique for manufacturing an integrated circuit of a memory device using a transistor including an oxide semiconductor has been disclosed (see Patent Document 3). In addition to memory devices, arithmetic devices and the like have been manufactured using transistors including oxide semiconductors.

However, a transistor in which an oxide semiconductor is provided as an active layer is known to have a problem in that its electrical characteristics are likely to change due to impurities and oxygen vacancies in the oxide semiconductor, and reliability is low. For example, the threshold voltage of the transistor may fluctuate before and after the bias-thermal stress test (BT test).

JP 2007-123861 A JP 2007-96055 A JP 2011-119694 A

An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. An object of one embodiment of the present invention is to provide a highly reliable semiconductor device. An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. An object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long period of time. An object of one embodiment of the present invention is to provide a semiconductor device with high information writing speed. An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom. An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

One embodiment of the present invention includes a gate electrode, a source electrode, a drain electrode, an oxide semiconductor having a channel formation region, and a gate insulator. The gate insulator includes a metal oxide. The metal oxide has a density of 7.0 g / cm ³ or more and 9.0 g / cm ³ or less.

In the above structure, the metal oxide has a density of 8.0 g / cm ³ or more and 8.5 g / cm ³ or less.

One embodiment of the present invention includes a gate electrode, a source electrode, a drain electrode, an oxide semiconductor having a channel formation region, and a gate insulator. The gate insulator includes a metal oxide. The metal oxide has a root mean square roughness (RMS) of 0.5 nm or less in a measurement range of 1 μm × 1 μm.

One embodiment of the present invention includes a gate electrode, a source electrode, a drain electrode, an oxide semiconductor having a channel formation region, and a gate insulator. The gate insulator includes a metal oxide. The metal oxide has a root mean square roughness (RMS) of 1.0 nm or less in a measurement range of 10 μm × 10 μm.

In the above structure, the insulator has a stacked structure of a metal oxide and silicon oxide, and the metal oxide is provided in contact with the oxide semiconductor.

In the above structure, the metal oxide is hafnium oxide.

In the above structure, hafnium oxide is deposited at a deposition temperature of 200 to 280 ° C. by ALD.

In the above structure, the oxide semiconductor has a stacked structure of a first oxide semiconductor and a second oxide semiconductor, and the first oxide semiconductor and the second oxide semiconductor have the same atomic ratio. Or the number ratio of nearby atoms.

According to one embodiment of the present invention, in a semiconductor device including a transistor including an oxide semiconductor, a semiconductor device in which electrical characteristics and reliability of the transistor are stable can be provided.

According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a highly productive semiconductor device can be provided.

According to one embodiment of the present invention, a semiconductor device capable of retaining data for a long period can be provided. According to one embodiment of the present invention, a semiconductor device with high information writing speed can be provided. According to one embodiment of the present invention, a semiconductor device with high design freedom can be provided. According to one embodiment of the present invention, a semiconductor device that can reduce power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

4A and 4B are a top view and a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. 1 is a top view of a semiconductor wafer according to one embodiment of the present invention. 10A and 10B are a flowchart and a perspective schematic diagram illustrating an example of a manufacturing process of an electronic component. FIG. 14 illustrates an electronic device according to one embodiment of the present invention. The figure explaining the cross section of the sample which concerns on an Example. The figure explaining the result of the XRR measurement of the sample which concerns on an Example. The figure explaining the result of the XRD measurement of the sample which concerns on an Example. The figure explaining the result of the DFM measurement of the sample concerning an example. The figure explaining the cross section of the sample which concerns on an Example. The figure explaining the result of the SIMS measurement of the sample which concerns on an Example. The figure explaining the Id-Vg characteristic of an Example. The figure explaining the stress time dependence of (DELTA) Vsh of an Example. The figure explaining the cross-sectional photograph of the sample which concerns on an Example.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

In the drawings, the size, the layer thickness, or the region is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.

In this specification and the like, the ordinal numbers attached as the first, second, etc. are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

In addition, in this specification, terms indicating arrangement such as “above” and “below” are used for convenience to describe the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, channel region, and source. It is something that can be done. Note that in this specification and the like, a channel region refers to a region through which a current mainly flows.

In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width (hereinafter “apparently” shown in the top view of the transistor). Sometimes referred to as “channel width”). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may not be negligible. For example, in a fine transistor whose gate electrode covers a side surface of a semiconductor, the ratio of a channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

Therefore, in this specification, the apparent channel width may be referred to as “surrounded channel width (SCW)”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

In addition, in this specification and the like, “electrically connected” includes a case of being connected via “thing having some electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. For example, “thing having some electric action” includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

Note that in this specification and the like, a nitrided oxide refers to a compound having a higher nitrogen content than oxygen. Further, oxynitride refers to a compound having a higher oxygen content than nitrogen. The content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS).

In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

Further, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

Note that in this specification, a barrier film refers to a film having a function of suppressing permeation of impurities such as hydrogen or oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. Sometimes.

In this specification and the like, the normally on property of a transistor means that the transistor is on when no potential is applied by a power supply (0 V). For example, the normally-on characteristic of a transistor may refer to an electric characteristic in which the threshold voltage is negative when the voltage (Vg) applied to the gate of the transistor is 0V.

In this specification and the like, an oxide semiconductor is a kind of metal oxide. A metal oxide refers to an oxide having a metal element. Metal oxides may exhibit insulating properties, semiconductivity, and conductivity depending on the composition and formation method. A metal oxide exhibiting semiconductivity is referred to as a metal oxide semiconductor or an oxide semiconductor (also referred to as an oxide semiconductor or simply OS). A metal oxide exhibiting insulating properties is referred to as a metal oxide insulator or an oxide insulator. A metal oxide exhibiting conductivity is referred to as a metal oxide conductor or an oxide conductor. That is, a metal oxide used for a channel formation region or the like of a transistor can be called an oxide semiconductor.

(Embodiment 1)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

<Transistor structure 1>
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described. 1A, 1B, and 1C are a top view and a cross-sectional view of the transistor 200 and the periphery of the transistor 200 according to one embodiment of the present invention. 1A is a top view, FIG. 1B is a cross-sectional view corresponding to an alternate long and short dash line L1-L2 shown in FIG. 1A, and FIG. 1C is a cross-sectional view corresponding to an alternate long and short dash line W1-W2. . Note that in the top view of FIG. 1A, some elements are omitted for clarity.

The semiconductor device of one embodiment of the present invention includes the transistor 200 and the insulator 214 functioning as an interlayer film, the insulator 216, the insulator 272, the insulator 274, the insulator 280, the insulator 282, and the insulator 286. .

The transistor 200 includes a conductor 205 (a conductor 205a and a conductor 205b) that functions as a first gate electrode, and a conductor 260 (a conductor 260a, a conductor 260b, and a conductor that function as a second gate electrode). 260c), an insulator 220 functioning as a first gate insulating layer, an insulator 222, an insulator 224, an insulator 250 functioning as a second gate insulating film, and an oxide having a region where a channel is formed The material 230 (the oxide 230a, the oxide 230b, and the oxide 230c), the conductor 240a that functions as one of the source and the drain, the conductor 240b that functions as the other of the source and the drain, and the conductor 240 (the conductor) 240a and the conductor 240b) and the barrier layer 245 (the barrier layer 245a and the barrier) Having a 245b), an insulator 250, a barrier layer 270, a.

In the transistor 200, the oxide 230 is preferably formed using a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). Since a transistor including an oxide semiconductor has extremely low leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.

On the other hand, in a transistor including an oxide semiconductor, its electrical characteristics are likely to vary due to impurities and oxygen vacancies in the oxide semiconductor, and reliability may deteriorate. In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Therefore, a transistor including an oxide semiconductor containing oxygen vacancies is likely to be normally on. Therefore, oxygen vacancies in the oxide semiconductor are preferably reduced as much as possible.

In particular, when an oxygen deficiency or a danglin bond of Si or the like exists in an interface between a region where a channel is formed in the oxide 230 and the insulator 250 functioning as a gate insulating film, a change in electrical characteristics is likely to occur. In addition, reliability may be deteriorated. Therefore, it is preferable that dangling bonds and defects be reduced at the interface between the region where the channel is formed in the oxide 230 and the insulator 250 functioning as a gate insulating film.

Therefore, it is preferable to reduce dangling bonds and defects at the interface between the oxide 230c and the insulator 250 and to maintain favorable interface characteristics. For example, a film that does not contain Si as a main component may be used for the insulator 250 in contact with the film to be the oxide 230c. For example, it is preferable to use a metal oxide. As the metal oxide, one kind selected from hafnium, aluminum, yttrium, zirconium, gallium, tungsten, titanium, tantalum, nickel, germanium, or magnesium, or an oxide containing two or more kinds may be used. it can.

In addition, oxygen vacancies formed in the oxide 230 can be reduced by supplying oxygen. For example, an insulator containing oxygen may be provided in contact with the oxide 230 in contact with the oxide 230. Alternatively, an oxide having a property of diffusing oxygen may be used for the insulator 250. In the case where the insulator 250 has a property of diffusing oxygen, a structure in contact with the insulator 250 (eg, the insulator 252 functioning as a gate insulating film or the insulator 280 functioning as an interlayer film) has a stoichiometric amount. It is preferable to contain more oxygen than oxygen that satisfies the theoretical composition (hereinafter also referred to as excess oxygen). That is, excess oxygen diffuses into the oxide 230 through the insulator 250, so that oxygen vacancies in the oxide 230 can be reduced.

For example, as an insulator having a property of diffusing oxygen, an insulator having a density of 7.0 g / cm ³ or more and 9.0 g / cm ³ or less, preferably 8.0 g / cm ³ or more and 8.5 g / cm ³ or less. Should be used.

The insulator 250 is preferably a film with few crystals or a film including an amorphous structure. By using a film with few crystals or a film including an amorphous structure, the interface between the insulator 250 and the oxide 230c and the interface between the insulator 250 and the insulator 252 have a favorable state.

The insulator 250 is preferably a film with high flatness. By using a film having high flatness, the interface between the insulator 250 and the oxide 230c and the interface between the insulator 250 and the insulator 252 have a good state. For example, as a film having high flatness, an insulator having a root mean square roughness (RMS) of 0.5 nm or less in a measurement range of 1 μm × 1 μm or 1.0 nm or less in a measurement range of 10 μm × 10 μm Should be used.

As described above, a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

Hereinafter, a detailed structure of the semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

The conductor 205 functioning as the first gate electrode includes a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal containing any of the above elements as a component Nitride films (tantalum nitride, titanium nitride film, molybdenum nitride film, tungsten nitride film) and the like. In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and is difficult to oxidize (high oxidation resistance). Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.

For example, the conductor 205a may be formed using tantalum nitride, titanium nitride, or the like having a barrier property against hydrogen, and the conductor 205b may be stacked with tungsten having high conductivity. By using the combination, diffusion of hydrogen into the oxide 230 can be suppressed while maintaining conductivity as a wiring. Note that FIG. 1 illustrates a two-layer structure of the conductor 205a and the conductor 205b; however, the structure is not limited thereto, and may be a single layer or a stacked structure including three or more layers. For example, a conductor having a barrier property or a conductor having a high adhesion property may be formed between a conductor having a barrier property and a conductor having a high conductivity.

The insulator 220, the insulator 222, and the insulator 224 have a function as a first gate insulator.

For the insulator 222 and the insulator 224, for example, an insulator containing silicon oxide, silicon oxynitride, or silicon nitride oxide can be used as a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator. Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates.

For example, since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having high thermal stability and high relative dielectric constant can be obtained by combining with an insulator having high relative dielectric constant.

In particular, the insulator 224 in contact with the oxide 230 is preferably formed using an oxide insulator containing more oxygen than oxygen that satisfies the stoichiometric composition. That is, it is preferable that an excess oxygen region be formed in the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and reliability can be improved.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen atom is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3 in TDS (Thermal Desorption Spectroscopy) analysis. The oxide film has a thickness of 0.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.

Here, in the case where the insulator 224 has an excess oxygen region, the insulator 222 preferably has a barrier property against oxygen, hydrogen, and water. Note that the barrier property refers to a function of suppressing diffusion of hydrogen, impurities typified by water, or oxygen.

Since the insulator 222 has a barrier property against oxygen, oxygen in the excess oxygen region can be efficiently supplied to the oxide 230 without diffusing to the insulator 220 side. In addition, the conductor 205 can be prevented from reacting with oxygen in the excess oxygen region of the insulator 224.

The insulator 222 is, for example, so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). It is preferable to use an insulator including a -k material in a single layer or a stacked layer. In particular, an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide and hafnium oxide, is preferably used. In the case of using such a material, it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the periphery of the transistor 200.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

Note that the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, the present invention is not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials.

In addition, by including the insulator 222 including a high-k material between the insulator 220 and the insulator 224, the insulator 222 can capture electrons under a specific condition and increase the threshold voltage. . That is, the insulator 222 may be negatively charged.

For example, in the case where silicon oxide is used for the insulator 220 and the insulator 224 and a material with many electron capture levels such as hafnium oxide, aluminum oxide, or tantalum oxide is used for the insulator 222, the operating temperature of the semiconductor device Alternatively, under a temperature higher than the storage temperature (eg, 125 ° C. or higher and 450 ° C. or lower, typically 150 ° C. or higher and 300 ° C. or lower), the potential of the conductor 205 is higher than the potential of the source electrode or the drain electrode. By maintaining for 10 milliseconds or longer, typically 1 minute or longer, electrons move from the oxide included in the transistor 200 toward the conductor 205. At this time, some of the moving electrons are captured by the electron capture level of the insulator 222.

The threshold voltage of the transistor that captures an amount of electrons necessary for the electron trap level of the insulator 222 is shifted to the positive side. Note that the amount of electrons captured can be controlled by controlling the voltage of the conductor 205, and the threshold voltage can be controlled accordingly. With this structure, the transistor 200 is a normally-off transistor that is non-conductive (also referred to as an off state) even when the gate voltage is 0 V.

Further, the process for capturing electrons may be performed in the manufacturing process of the transistor. For example, either after the formation of the conductor connected to the source conductor or drain conductor of the transistor, after the completion of the previous process (wafer processing), after the wafer dicing process, after packaging, etc. This should be done in stages.

In addition, the threshold voltage can be controlled by appropriately adjusting the film thicknesses of the insulator 220, the insulator 222, and the insulator 224. For example, when the total thickness of the insulator 220, the insulator 222, and the insulator 220 is reduced, a voltage from the conductor 205 is efficiently applied, so that a transistor with low power consumption can be provided.

Accordingly, it is possible to provide a transistor with small leakage current when non-conducting. In addition, a transistor having stable electrical characteristics can be provided. Alternatively, a transistor with high on-state current can be provided. Alternatively, a transistor with a small subthreshold swing value can be provided. Alternatively, a highly reliable transistor can be provided.

The oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b. When the transistor 200 is turned on, a current flows mainly through the oxide 230b (a channel is formed). On the other hand, in the oxide 230a and the oxide 230c, a current may flow in the vicinity of the interface with the oxide 230b (which may be a mixed region), but the other region may function as an insulator. .

As shown in FIG. 1C, the oxide 230c is preferably provided so as to cover side surfaces of the oxide 230a and the oxide 230b. When the oxide 230c is interposed between the insulator 280 and the oxide 230b having a region where a channel is formed, impurities such as hydrogen, water, and halogen are transferred from the insulator 280 to the oxide 230b. Diffusion can be suppressed.

In addition, by including a region where the channel of the oxide 230b is formed over the oxide 230a, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230c and the oxide 230b can be performed. Can be suppressed.

The oxide 230a, the oxide 230b, and the oxide 230c are In-M-Zn oxides (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, It is formed of a metal oxide such as one or more selected from zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.

<< Metal oxide >>
Hereinafter, the oxide 230 according to the present invention will be described. As the oxide 230, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.

The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

Here, a case where the oxide semiconductor is InMZnO containing indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

[Composition of metal oxide]
A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

Note that in this specification and the like, they may be described as CAAC (c-axis aligned crystal) and CAC (Cloud-aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

The CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and the whole material has a function as a semiconductor. Note that in the case where a CAC-OS or a CAC-metal oxide is used for an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is an electron serving as carriers. It is a function that does not flow. By performing the conductive function and the insulating function in a complementary manner, a switching function (function to turn on / off) can be given to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Further, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[Structure of metal oxide]
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor). OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.

The CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. There is a tendency to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

The CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, since CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. In addition, since the crystallinity of an oxide semiconductor may be deteriorated due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor including a CAAC-OS are stable. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.

The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

Oxide semiconductors have various structures and different properties. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

<< Transistor with Oxide Semiconductor >>
Next, the case where the above oxide semiconductor is used for a transistor is described.

Note that by using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

For the transistor, an oxide semiconductor with low carrier density is preferably used. In the case where the carrier density of the oxide semiconductor film is decreased, the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the oxide semiconductor has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / What is necessary is just to be cm ³ or more.

In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states.

In addition, the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in an adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

<< Impurities >>
Here, the influence of each impurity in the oxide semiconductor is described.

In the oxide semiconductor, when silicon or carbon which is one of Group 14 elements is included, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level is formed and carriers may be generated in some cases. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier density is increased, and the oxide semiconductor is likely to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to be normally on. Accordingly, nitrogen in the oxide semiconductor is preferably reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5 × 10 ¹⁹ atoms / cm ^{3 in} SIMS, preferably 5 × 10 ^18. atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and even more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm 3. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using an oxide semiconductor in which impurities are sufficiently reduced for the channel region of the transistor, stable electrical characteristics can be imparted.

One of the conductor 240a and the conductor 240b functions as a source electrode, and the other functions as a drain electrode.

For the conductor 240a and the conductor 240b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same as a main component can be used. . In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance.

Further, although a single layer structure is shown in the figure, a stacked structure of two or more layers may be used. For example, a tantalum nitride and tungsten film may be stacked. In addition, a titanium film and an aluminum film are preferably stacked. Also, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, and a tungsten film A two-layer structure in which copper films are stacked may be used.

In addition, a titanium film or a titanium nitride film and a three-layer structure in which an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or There is a three-layer structure in which a molybdenum nitride film and an aluminum film or a copper film are stacked over the molybdenum film or the molybdenum nitride film and a molybdenum film or a molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

Further, the barrier layer 245a and the barrier layer 245b may be provided over the conductor 240a and the conductor 240b. The barrier layer 245a and the barrier layer 245b are preferably formed using a substance having a barrier property against oxygen or hydrogen. With this structure, the conductor 240a and the conductor 240b can be prevented from being oxidized when the oxide 230c is formed. In addition, oxygen in the excess oxygen region of the insulator 280 can be prevented from reacting with the conductors 240a and 240b and being oxidized.

For example, a metal oxide can be used for the barrier layer 245a and the barrier layer 245b. In particular, an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide, is preferably used. Alternatively, silicon nitride formed by a CVD method may be used.

By including the barrier layer 245, the range of material selection for the conductor 240 can be increased. For example, the conductor 240 can be made of a material that has low oxidation resistance but high conductivity, such as tungsten or aluminum. For example, a conductor that can be easily formed or processed can be used.

Further, oxidation of the conductor 240 can be suppressed, and oxygen released from the insulator 224 and the insulator 280 can be efficiently supplied to the oxide 230. In addition, by using a highly conductive conductor for the conductor 240, the transistor 200 with low power consumption can be provided.

The insulator 250 having a function as the second gate insulator includes, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, An insulator containing a so-called high-k material such as Sr) TiO ₃ (BST) can be used as a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided.

Oxygen vacancies formed in the oxide 230 can be reduced by supplying oxygen. Therefore, it is preferable to use an oxide having a property of diffusing oxygen for the insulator 250. That is, excess oxygen diffuses into the oxide 230 through the insulator 250, so that oxygen vacancies in the oxide 230 can be reduced. For example, as an insulator having a property of diffusing oxygen, an insulator having a density of 7.0 g / cm ³ or more and 9.0 g / cm ³ or less, preferably 8.0 g / cm ³ or more and 8.5 g / cm ³ or less. Should be used.

The insulator 250 is preferably a film with few crystals or a film including an amorphous structure. By using a film with few crystals or a film including an amorphous structure, the interface between the insulator 250 and the oxide 230c and the interface between the insulator 250 and the insulator 252 have a favorable state.

The insulator 250 is preferably a film with high flatness. By using a film having high flatness, the interface between the insulator 250 and the oxide 230c and the interface between the insulator 250 and the insulator 252 have a good state. For example, as a film having high flatness, an insulator having a root mean square roughness (RMS) of 0.5 nm or less in a measurement range of 1 μm × 1 μm or 1.0 nm or less in a measurement range of 10 μm × 10 μm Should be used.

The insulator 250 is preferably formed using an insulating film having a barrier property against hydrogen. As the insulating film having a barrier property against hydrogen, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, silicon nitride, or the like may be used. In the case of using such a material, it functions as a layer that prevents external impurities such as hydrogen from entering.

Further, an insulator 252 having a function as a second gate insulator may be stacked over the insulator 250. As the insulator 250, for example, an insulator including silicon oxide, silicon oxynitride, and silicon nitride oxide can be used as a single layer or a stacked layer. In particular, since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having high thermal stability and high relative dielectric constant can be obtained by combining with an insulator having high relative dielectric constant.

For example, the insulator 250 may be so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). When an insulator including a -k material is used as a single layer or a stacked layer, the thickness of the insulator 250 may be increased depending on the required design value of the transistor. In other words, the gate insulating film may be thick and difficult to be miniaturized or highly integrated.

Thus, as the insulator 252, an insulator having a dielectric breakdown voltage higher than that of the insulator 250 is used to form a stacked structure, whereby the thickness of the gate insulating film can be controlled. In other words, the insulator 250 in contact with the oxide 230 is a film which transmits oxygen and has low crystallinity or high flatness, and the insulator 252 is a film having high insulating properties, whereby gate insulation is achieved. The transistor 200 can be designed to have a sufficient function as a body and have a required film thickness. Therefore, miniaturization and high integration are possible.

The insulator 250 is preferably formed using an oxide insulator containing oxygen in excess of the stoichiometric composition, like the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, excess oxygen diffuses through the insulator 250, so that oxygen vacancies in the oxide 230 can be reduced.

Note that a further insulator may be stacked over the insulator 252. Examples of the insulator stacked over the insulator 252 include silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), and strontium titanate ( An insulator containing a so-called high-k material such as SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST) can be used in a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

The conductor 260 functioning as the second gate electrode is, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy containing the above-described metal as a component, or the above-described metal. It can be formed using an alloy or the like in combination. In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance. Further, a metal selected from one or more of manganese and zirconium may be used. Alternatively, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

For example, as the conductor 260a, an oxide typified by an In—Ga—Zn oxide can be used. An oxide semiconductor typified by an In—Ga—Zn oxide has higher carrier density when nitrogen or hydrogen is supplied. In other words, it functions as an oxide conductor (OC). Thus, by providing a metal nitride as the conductor 260b, the carrier density of the oxide semiconductor is increased, so that the conductor 260a functions as a gate electrode.

As the conductor 260a, indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin containing titanium oxide A light-transmitting conductive material such as an oxide, indium zinc oxide, or indium tin oxide containing silicon (In-Sn-Si oxide: also referred to as ITSO) can be used.

As a method for forming the conductor 260a, it is preferable to use a sputtering method and form it in an atmosphere containing oxygen gas at the time of formation. An excess oxygen region can be formed in the insulator 250 by forming the conductor 260a in an atmosphere containing oxygen gas at the time of formation. Note that the method for forming the conductor 260a is not limited to the sputtering method, and other methods such as an ALD method may be used.

By using a metal nitride as the conductor 260b, a constituent element (particularly nitrogen) in the metal nitride diffuses into the conductor 260a to reduce resistance, and damage (for example, when the conductor 260b is formed) The resistance can be reduced by sputtering damage or the like. Further, by stacking a low-resistance metal film as the conductor 260c, a transistor with a low driving voltage can be provided.

Further, the barrier layer 245 a and the barrier layer 270 may be provided over the conductor 260. The barrier layer 270 is preferably formed using a substance having a barrier property against oxygen or hydrogen.

For example, depending on the material used for the conductor 260, the conductor 260 may be oxidized in a subsequent process such as heat treatment, and the resistance value may be increased. Further, when excess oxygen is supplied to the oxide 230, oxygen may be absorbed by the conductor 260. By providing the barrier layer 270, oxidation of the conductor 260 can be suppressed, and a shortage of oxygen supplied to the oxide 230 can be suppressed.

For the barrier layer 270, for example, a metal oxide can be used. In particular, an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide, is preferably used. Alternatively, silicon nitride formed by a CVD method may be used.

By including the barrier layer 270, the range of material selection for the conductor 260 can be increased. For example, the conductor 260 can be made of a material that has low oxidation resistance but high conductivity, such as tungsten or aluminum. For example, a conductor that can be easily formed or processed can be used.

The insulator 214, the insulator 216, the insulator 272, the insulator 274, the insulator 280, the insulator 282, and the insulator 286 that function as interlayer films are formed using silicon oxide, silicon oxynitride, silicon nitride oxide, An insulator such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST) is used in a single layer or a stacked layer. be able to. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

For example, since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having high thermal stability and high relative dielectric constant can be obtained by combining with an insulator having high relative dielectric constant.

For example, the insulator 216, the insulator 280, and the insulator 286 preferably have a lower dielectric constant than the insulator 214 or the insulator 216. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

The insulator 214, the insulator 272, the insulator 274, and the insulator 282 include, for example, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), and strontium titanate ( An insulator containing a so-called high-k material such as SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST) is preferably used in a single layer or a stacked layer. In particular, an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide and hafnium oxide, is preferably used. In the case of using such a material, it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the outside.

Alternatively, the insulator 214, the insulator 216, the insulator 272, the insulator 274, the insulator 280, the insulator 282, and the insulator 286 can be formed using, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, or oxide. Titanium, tungsten oxide, yttrium oxide, or zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

The insulator 214, the insulator 216, the insulator 272, the insulator 274, the insulator 280, the insulator 282, and the insulator 286 may have a stacked structure of two or more layers. In that case, the present invention is not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials. Note that the insulator 280 that covers the transistor 200 may function as a planarization film that covers the uneven shape below the transistor 280.

With the above structure, a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

<Method for Manufacturing Transistor>
An example of a method for manufacturing a semiconductor device including the transistor 200 illustrated in FIGS. 1A to 1C is described below with reference to FIGS. Note that L1-L2 in the drawing is a cross-sectional view of the transistor 200 in the channel length direction. W1-W2 shown in the drawing is a cross-sectional view of the transistor 200 in the channel width direction.

First, a substrate is prepared (not shown). There is no particular limitation on a substrate that can be used as the substrate, but it is preferable that the substrate have heat resistance enough to withstand at least heat treatment performed later. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, gallium arsenide, indium arsenide, or indium gallium arsenide, an SOI (Silicon On Insulator) substrate, or a GOI (Germanium on Insulator). A substrate or the like can also be applied, and a substrate in which a semiconductor element is provided over these substrates may be used.

Further, a semiconductor device may be manufactured using a flexible substrate as the substrate. In order to manufacture a flexible semiconductor device, a transistor may be directly manufactured over a flexible substrate, or a transistor is manufactured over another manufacturing substrate, and then peeled off and transferred to the flexible substrate. Also good. Note that in order to separate the transistor from the manufacturing substrate and transfer it to the flexible substrate, a separation layer may be provided between the manufacturing substrate and the transistor including an oxide semiconductor.

Next, the insulator 214 and the insulator 216 are formed (FIGS. 2A and 2B).

The insulator 214 and the insulator 216 are formed by, for example, a sputtering method, a CVD method, a (thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method, a plasma enhanced chemical vapor deposition (PECVD) method). Etc.), molecular epitaxy (MBE) method, ALD method, pulsed laser deposition (PLD) method, or the like. In particular, it is preferable to form the insulator by a CVD method, preferably an ALD method, because coverage can be improved. In order to reduce damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable. Alternatively, a silicon oxide film with good step coverage formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane with oxygen, nitrous oxide, or the like can be used.

For example, as the insulator 214, aluminum oxide is formed by a sputtering method. Since the sputtering method has a higher deposition rate than the ALD method, productivity can be improved. For example, silicon oxynitride is formed as the insulator 216 by a CVD method. The insulator 216 preferably has a lower dielectric constant than the insulator 214. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

Subsequently, a resist mask is formed over the insulator 216 using a lithography method or the like. An unnecessary portion of the insulator 214 and the insulator 216 is removed. After that, an opening can be formed by removing the resist mask (FIG. 2C and FIG. 2D).

Here, a method for processing a film to be processed will be described. In the case of finely processing a film to be processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a lithography method or the like may be used. Alternatively, a dummy pattern may be formed by lithography or the like, a sidewall may be formed on the dummy pattern, the dummy pattern may be removed, and the processed film may be etched using the remaining sidewall as a resist mask. In order to realize a high aspect ratio, it is preferable to use anisotropic dry etching as etching of the film to be processed. Further, a hard mask made of an inorganic film or a metal film may be used.

As light used for forming the resist mask, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing them can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Further, exposure may be performed by an immersion exposure technique. Further, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used as light used for exposure. Further, an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or an electron beam because extremely fine processing is possible. Note that a photomask is not necessary when exposure is performed by scanning a beam such as an electron beam.

Further, an organic resin film having a function of improving the adhesion between the film to be processed and the resist film may be formed before forming the resist film to be a resist mask. The organic resin film can be formed, for example, by a spin coating method so as to cover the level difference below and flatten the surface, and variations in the thickness of the resist mask provided above the organic resin film Can be reduced. In particular, when performing fine processing, it is preferable to use a material that functions as an antireflection film for light used for exposure as the organic resin film. Examples of the organic resin film having such a function include a BARC (Bottom Anti-Reflection Coating) film. The organic resin film may be removed at the same time as the resist mask is removed or after the resist mask is removed.

Next, a conductive film 205A and a conductive film 205B are formed over the insulator 214 and the insulator 216 (FIGS. 2E and 2F). The conductive films 205A and 205B can be formed by a sputtering method, an evaporation method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like). In order to reduce damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable.

Subsequently, unnecessary portions of the conductive film 205A and the conductive film 205B are removed. For example, part of the conductive film 205A and the conductive film 205B is removed until the insulator 216 is exposed by an etch-back process or a mechanical chemical polishing (CMP) process. A conductor 205a and a conductor 205b are formed (FIGS. 2G and 2H, where arrows indicate CMP treatment). At this time, the insulator 216 can also be used as a stopper layer, and the insulator 216 may be thin.

Here, the CMP process is a technique for flattening the surface of a workpiece by a combined chemical and mechanical action. More specifically, a polishing cloth is attached on the polishing stage, and the polishing stage and the workpiece are rotated or swung while supplying slurry (abrasive) between the workpiece and the polishing cloth. In this method, the surface of the workpiece is polished by a chemical reaction between the slurry and the surface of the workpiece and by mechanical polishing between the polishing cloth and the workpiece.

The CMP process may be performed only once or a plurality of times. When performing the CMP process in a plurality of times, it is preferable to perform primary polishing at a low polishing rate after performing primary polishing at a high polishing rate. In this way, polishing with different polishing rates may be combined.

Next, the insulator 220, the insulator 222, and the insulator 224 are formed. Subsequently, an oxide film 230A and an oxide film 230B are formed, and heat treatment is performed (FIGS. 2I and 2J, where broken line arrows represent heat treatment).

Note that the insulator 220 and the insulator 222 are not necessarily provided. For example, when the insulator 224 has an excess oxygen region, a conductor having a barrier property against oxygen, hydrogen, and water may be formed over the conductor 205. By forming a conductor having a barrier property against oxygen, hydrogen, and water, the conductor 205 can be prevented from reacting with oxygen in an excess oxygen region to generate an oxide.

The insulator 220, the insulator 222, and the insulator 224 can be manufactured using a material and a method similar to those of the insulator 214 and the insulator 216. Note that the insulator 222 is preferably formed using a high-k material such as hafnium oxide or aluminum oxide.

The insulator 220, the insulator 222, and the insulator 224 are preferably formed continuously. By forming a film continuously, an insulator with high reliability can be formed without an impurity adhering to the interface between the insulator 220 and the insulator 222 and the interface between the insulator 222 and the insulator 224. it can.

For example, aluminum oxide is formed as the insulator 222 by an ALD method. By forming the insulating layer using the ALD method, a dense insulating layer with reduced defects such as cracks and pinholes or a uniform thickness can be formed.

For example, as the insulator 220 and the insulator 224, silicon oxynitride is formed by a CVD method. In particular, the insulator 224 is preferably an insulating layer containing excess oxygen. For example, an excess oxygen region may be formed in the insulator 224 by performing oxygen doping treatment after the insulator 224 is formed.

Subsequently, heat treatment is preferably performed in order to further reduce impurities such as moisture or hydrogen contained in the insulator 224.

Further, plasma treatment using an oxidizing gas may be performed before the heat treatment. For example, plasma treatment using nitrous oxide gas is performed. By performing the plasma treatment, the fluorine concentration in the exposed insulating layer can be reduced. In addition, an effect of removing organic substances on the sample surface can be obtained.

The heat treatment is, for example, moisture in an inert atmosphere containing nitrogen or a rare gas, in an oxidizing gas atmosphere, or when measured using a super dry air (CRDS (cavity ring down laser spectroscopy) type dew point meter). The amount is 20 ppm (-55 ° C. in terms of dew point) or less, preferably 1 ppm or less, preferably 10 ppb or less). The “oxidizing gas atmosphere” refers to an atmosphere containing 10 ppm or more of an oxidizing gas such as oxygen, ozone or oxygen nitride. The “inert atmosphere” refers to an atmosphere in which the above-described oxidizing gas is less than 10 ppm and is filled with nitrogen or a rare gas. There is no particular restriction on the pressure during the heat treatment, but the heat treatment is preferably performed under reduced pressure.

Note that after heat treatment in an inert atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 400 ° C. The processing time is within 24 hours. Heat treatment for more than 24 hours is not preferable because it causes a decrease in productivity.

For example, after heat treatment is performed at 400 ° C. for 1 hour in a nitrogen gas atmosphere, the heat treatment may be performed at 400 ° C. for 1 hour by replacing the nitrogen gas with oxygen gas. First, by performing heat treatment in a nitrogen gas atmosphere, impurities such as moisture or hydrogen contained in the insulator 224 are released, and the impurity concentration in the insulator 224 is reduced. Subsequently, oxygen is introduced into the insulator 224 by performing heat treatment in an oxygen gas atmosphere.

Subsequently, an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed. The oxide is preferably formed continuously without being exposed to the atmosphere.

For example, the oxide film 230A and the oxide film 230B are formed by a sputtering method. Further, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased.

In particular, part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed.

During film formation by sputtering, ions and sputtered particles exist between the target and the substrate. For example, the target is connected to a power source and is supplied with the potential E0. The substrate is given a potential E1 such as a ground potential. However, the substrate may be electrically floating. In addition, there is a region having the potential E2 between the target and the substrate. The magnitude relationship between the potentials is E2> E1> E0.

Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, whereby particles sputtered from the target are ejected. The sputtered particles adhere to and deposit on the film formation surface to form a film. Some ions recoil by the target and may be taken into the insulator 224 below the formed film through the film formed as recoil ions. Further, ions in the plasma are accelerated by the potential difference E2-E1, and impact the film formation surface. At this time, some of the ions reach the inside of the insulator 224. When the ions are taken into the insulator 224, a region into which the ions are taken is formed in the insulator 224. That is, when the ions are oxygen-containing ions, an excess oxygen region is formed in the insulator 224.

By introducing excess oxygen into the insulator 224, an excess oxygen region can be formed. Excess oxygen in the insulator 224 is supplied to the oxide 230, so that oxygen vacancies in the oxide 230 can be filled.

Accordingly, a region having excess oxygen can be formed in the insulator 224 at the same time that the oxide film 230A is formed. Note that as the amount of oxygen contained in the sputtering gas increases, the amount of oxygen supplied to the insulator 224 also increases. Further, part of oxygen supplied to the insulator 224 reacts with hydrogen remaining in the insulator 224 to be water, and is released from the insulator 224 by a subsequent heat treatment. Accordingly, the hydrogen concentration in the insulator 224 can be reduced.

Note that the ratio of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%. By using an oxide containing excess oxygen for the oxide film 230A, oxygen can be supplied to the oxide 230b by heat treatment performed later.

Subsequently, an oxide film 230B is formed by a sputtering method. At this time, when the film is formed so that the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%, an oxygen-deficient oxide semiconductor is formed. A transistor including an oxygen-deficient oxide semiconductor can have a relatively high field-effect mobility.

In the case where an oxygen-deficient oxide semiconductor is used for the oxide film 230B, an oxide film containing excess oxygen is preferably used for the oxide film 230A. Further, oxygen doping treatment may be performed after the formation of the oxide film 230B.

Note that in the case where an oxide is formed by a sputtering method, a film having an atomic ratio that deviates from the atomic ratio of the target may be formed. For example, depending on the substrate temperature during film formation, the atomic ratio of zinc (Zn) in the film may be smaller than the atomic ratio of zinc (Zn) in the target.

Specifically, the case where an In—M—Zn oxide film is formed is described. A film formed by sputtering using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio] as a target was In: Ga: Zn = 4: 2: 3 [number of atoms]. Ratio] above, In: Ga: Zn = 4: 2: 4.1 [atomic ratio] may be below. Even when a film is formed using a target having the same atomic ratio, strictly different films may be formed when other film formation conditions are different.

Subsequently, heat treatment is preferably performed to further reduce impurities such as moisture or hydrogen contained in the oxide film 230A and the oxide film 230B so that the oxide film 230A and the oxide film 230B are highly purified.

Further, by performing heat treatment, oxygen contained in the insulator 224 is diffused into the oxide film 230A and the oxide film 230B at the same time as the release of the impurities in the oxide film 230A and the oxide film 230B, and the oxides Oxygen deficiency contained can be reduced.

The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 400 ° C. The processing time is within 24 hours. Heat treatment for more than 24 hours is not preferable because it causes a decrease in productivity.

For example, after heat treatment is performed at 400 ° C. for 1 hour in a nitrogen gas atmosphere, the heat treatment may be performed at 400 ° C. for 1 hour by replacing the nitrogen gas with oxygen gas. First, by performing heat treatment in a nitrogen gas atmosphere, impurities such as moisture or hydrogen contained in the oxide film 230A and the oxide film 230B are released, and the impurity concentration in the oxide film 230A and the oxide film 230B is reduced. Is done. Subsequently, by performing heat treatment in an oxygen gas atmosphere, oxygen is introduced into the oxide film 230A and the oxide film 230B.

Further, plasma treatment using an oxidizing gas may be performed before the heat treatment. For example, plasma treatment using nitrous oxide gas is performed. By performing the plasma treatment, the fluorine concentration in the exposed insulating layer can be reduced. In addition, an effect of removing organic substances on the sample surface can be obtained.

Next, a conductive film 240A, a barrier film 245A, and a film 290A to be a hard mask are formed (FIGS. 3A and 3B).

For example, tantalum nitride is formed as the conductive film 240A by a sputtering method. Since tantalum nitride has high oxidation resistance, it is preferable when heat treatment is performed in a later step.

Further, when the conductive film 240A is in contact with the oxide film 230B, an impurity element may be introduced into the surface of the oxide film 230B. By adding an impurity to the oxide film 230B, the threshold voltage of the transistor 200 can be changed. Note that the impurity element may be introduced by ion implantation, plasma immersion implantation, plasma treatment using a gas containing an impurity element, or the like before the conductive film 240A is formed. Alternatively, the impurity element may be introduced by an ion implantation method or the like after the conductive film 240A is formed.

For example, aluminum oxide may be formed as the barrier film 245A by an ALD method. By forming using the ALD method, a dense film with reduced defects such as cracks and pinholes or a uniform thickness can be formed.

For example, tantalum nitride is formed by a sputtering method as the film 290A to be a hard mask. Note that since the hard mask is processed at the same time as the conductive film 240A in a later step, the hard mask is preferably formed using the same material as the conductive film 240A or a material with a similar etching rate.

Next, a resist mask is formed over the film 290A to be a hard mask by a photolithography method. A part of the film 290A to be a hard mask is selectively removed using the resist mask to form a film 290B to be a hard mask having an opening (FIGS. 3C and 3D). ). Note that it is preferable to form the opening using the resist mask by using the minimum processing dimension. Therefore, the barrier film 245B has an opening having a minimum processing dimension.

Note that when the opening is formed, the side surface on the opening side of the film 290B to be a hard mask preferably has an angle with respect to the upper surface of the conductive film 240A. The angle is 30 degrees or more and 90 degrees or less, preferably 45 degrees or more and 80 degrees or less.

Next, a resist mask is formed over the film 290B to be a hard mask and the barrier film 245A by photolithography. The resist mask is used to selectively remove part of the hard mask film 290B, the barrier film 245A, and the conductive film 240A, and the island-shaped conductive film 240B, the hard mask 290a, the hard mask 290b, and the barrier film 245B is formed (FIGS. 3E and 3F).

Subsequently, part of the barrier film 245B, the oxide 230a, and part of the oxide 230b are selectively removed using the island-shaped conductive film 240B, the hard mask 290a, and the hard mask 290b as masks. Note that in this step, part of the insulator 224 may be removed at the same time. After that, by removing the resist mask, an island-shaped oxide 230a and an island-shaped oxide 230b can be formed (FIGS. 3G and 3H).

At this time, a barrier layer 245a and a barrier layer 245b are formed from the barrier film 245B. That is, when the opening in the film 290B serving as the hard mask is the minimum processing dimension, the distance between the barrier layer 245a and the barrier layer 245b is the minimum dimension.

Subsequently, the hard mask 290a and the hard mask 290b are removed, and at the same time, a part of the island-shaped conductive film 240B is selectively removed. Through this step, the conductive film 240B is separated into the conductor 240a and the conductor 240b (FIGS. 4A and 4B).

Since the conductor 240a and the conductor 240b function as a source electrode and a drain electrode of the transistor 200, the length of the distance between the conductor 240a and the conductor 240b facing each other is referred to as a channel length of the transistor. Can do. That is, when the opening of the barrier film 245B is set to the minimum processing dimension, the distance between the barrier layer 245a and the barrier layer 245b is the minimum dimension, and therefore, a gate line width and a channel length smaller than the minimum processing dimension are formed. Can do.

Note that the oxide film 230A, the oxide film 230B, the conductive film 240A, and the barrier film 245A can be removed by a dry etching method, a wet etching method, or the like. Both dry etching and wet etching may be used.

In the case where the conductor 240a and the conductor 240b are formed by a dry etching method, an impurity element such as a residual component of an etching gas may adhere to the exposed oxide 230b. For example, when a chlorine-based gas is used as an etching gas, chlorine or the like may adhere. In addition, when a hydrocarbon-based gas is used as an etching gas, carbon or hydrogen may adhere. For this reason, it is preferable to reduce the impurity element adhering to the exposed surface of the oxide 230b. The reduction of the impurities may be performed by, for example, a cleaning process using dilute hydrofluoric acid, a cleaning process using ozone, or a cleaning process using ultraviolet rays. A plurality of cleaning processes may be combined.

Further, plasma treatment using an oxidizing gas may be performed. For example, plasma treatment using nitrous oxide gas is performed. By performing the plasma treatment, the fluorine concentration in the oxide 230b can be reduced. In addition, an effect of removing organic substances on the sample surface can be obtained.

Further, oxygen doping treatment may be performed on the exposed oxide 230b.

Next, an oxide film 230C, an insulating film 250A, a conductive film 260A, a conductive film 260B, and a conductive film 260C are formed (FIGS. 4C and 4D).

As the oxide film 230C, an oxide containing a large amount of excess oxygen is preferably used as in the oxide 230a. Similarly to the oxide 230a, when the oxide film 230C is formed, part of oxygen contained in the sputtering gas may be supplied to the insulator 224 to form an excess oxygen region. Further, part of oxygen supplied to the insulator 224 reacts with hydrogen remaining in the insulator 224 to be water, and is released from the insulator 224 by a subsequent heat treatment. Thus, the hydrogen concentration in the insulator 224 can be reduced.

Note that as the amount of oxygen contained in the sputtering gas increases, the amount of oxygen supplied to the insulator 224 also increases. Further, part of oxygen supplied to the insulator 224 reacts with hydrogen remaining in the insulator 224 to be water, and is released from the insulator 224 by a subsequent heat treatment. Accordingly, the hydrogen concentration in the insulator 224 can be reduced.

Note that the ratio of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%. By using an oxide containing excess oxygen for the oxide film 230A, oxygen can be supplied to the oxide 230b by heat treatment performed later.

Note that after the oxide film 230C is formed, one or both of oxygen doping treatment and heat treatment may be performed. By performing the heat treatment, oxygen contained in the oxide 230a and the oxide 230c can be supplied to the oxide 230b. By supplying oxygen to the oxide 230b, oxygen vacancies in the oxide 230b can be reduced. Therefore, in the case where an oxygen-deficient oxide semiconductor is used for the oxide 230b, a semiconductor containing excess oxygen is preferably used for the oxide 230c.

Subsequently, an insulating film 250A to be the insulator 250 is formed. For example, hafnium oxide is formed as the insulating film 250A by an ALD method. By forming the film using the ALD method, the insulating film 250A with reduced defects such as cracks and pinholes or a uniform thickness can be formed. Note that the insulating film 250A is preferably a film that transmits oxygen. The insulating film 250A is preferably a film with low crystallinity and high flatness.

When the insulating film 250A is formed, for example, the density, crystallinity, and flatness of the formed film can be adjusted by appropriately setting the substrate temperature.

For example, in the case where a hafnium oxide film is formed as the insulating film 520A by an ALD method, the substrate temperature may be 180 ° C. or higher and 300 ° C. or lower, preferably 200 ° C. or higher and 280 ° C. or lower.

By appropriately setting the substrate temperature, a hafnium oxide film having a density of 7.0 g / cm ³ or more and 9.0 g / cm ³ or less, preferably 8.0 g / cm ³ or more and 8.5 g / cm ³ or less is formed. can do. Alternatively, a film with few crystals or a hafnium oxide film including an amorphous structure can be formed. Alternatively, a hafnium oxide film having a root mean square roughness (RMS) of 0.5 nm or less in a measurement range of 1 μm × 1 μm or 1.0 nm or less in a measurement range of 10 μm × 10 μm may be formed. it can.

Subsequently, an insulating film 252A to be the insulator 252 is formed. For example, silicon oxynitride is formed as the insulating film 252A by a CVD method. Note that the insulating film 252A is preferably an insulating layer containing excess oxygen. The insulating film 252A may be subjected to oxygen doping treatment. Further, heat treatment may be performed after the insulating film 252A is formed.

Next, for example, an In—Ga—Zn oxide is formed as the conductive film 260 </ b> A by a sputtering method. For example, a metal nitride is used for the conductive film 260B by a sputtering method.

An oxide semiconductor typified by an In—Ga—Zn oxide has higher carrier density when nitrogen or hydrogen is supplied. In other words, it functions as an oxide conductor (OC). Therefore, by forming a metal nitride as the conductive film 260B by a sputtering method, a constituent element (particularly nitrogen) in the metal nitride diffuses into the conductive film 260A to reduce the resistance, and the conductive film 260B is formed. The resistance is lowered by film damage (for example, sputtering damage). Accordingly, since the conductive film 260A has a high carrier density, the conductivity of the conductive film 260A is increased.

As a method for forming the conductive film 260A, a sputtering method is preferably used in an atmosphere containing oxygen gas at the time of formation. An excess oxygen region can be formed in the insulator 250 by forming the conductive film 260A in an atmosphere containing oxygen gas at the time of formation. Note that the method for forming the conductive film 260A is not limited to the sputtering method, and other methods such as an ALD method may be used.

Further, by stacking a low-resistance metal film as the conductive film 260C, a transistor with a low driving voltage can be provided.

Next, a resist mask is formed over the conductive film 260C by a photolithography method. Part of the conductive film 260A, the conductive film 260B, and the conductive film 260C is selectively removed using the resist mask, so that the conductor 260 is formed (FIGS. 4E and 4F).

Subsequently, a resist mask is formed over the conductor 260 and the insulating film 250A by photolithography. By using the resist mask, part of the insulating film 250A and the oxide film 230C are selectively removed to form the insulator 250a and the oxide 230c (FIGS. 4G and 4H). ).

Here, the stacked structure including the oxide film 230C and the insulating film 250A is processed at the same time, whereby the oxide 230c and the insulator 250 are formed. Therefore, the oxide 230c and the insulator 250 can be formed at the interface between the oxide 230c and the insulator 250 without causing impurities or damage generated during processing. In other words, formation of oxygen vacancies at the interface between the oxide 230c and the insulator 250 is suppressed, and the reliability of the transistor 200 can be improved.

Next, a barrier film 270A is formed (FIGS. 5A and 5B). As the barrier film 270A, it is preferable to use a dense film with high coating properties. The barrier film 270A preferably has a barrier property against oxygen, hydrogen, and water. The barrier film 270A has a barrier property against oxygen, thereby suppressing the conductor 260 from absorbing oxygen in the excess oxygen region and suppressing the decrease in conductivity due to the oxidation of the conductor 260. Can do.

For example, aluminum oxide may be formed as the barrier film 270A by an ALD method. By forming a film using the ALD method, a dense barrier film 270A with reduced defects such as cracks and pinholes or a uniform thickness can be formed.

Next, a resist mask is formed over the barrier film 270A by photolithography. Using the resist mask, part of the barrier film 270A is selectively removed to form the barrier layer 270 (FIGS. 5C and 4D).

Through the above steps, the transistor 200 of one embodiment of the present invention can be manufactured.

Next, an insulator 272 and an insulator 274 are provided so as to cover the transistor 200.

In the case where the insulator 224 and the insulator 252 have an excess oxygen region, the stacked body of the insulator 272 and the insulator 274 preferably has a barrier property against oxygen, hydrogen, and water. Since the insulator 272 and the stacked body of the insulator 274 have a barrier property against oxygen, oxygen in the excess oxygen region can be efficiently supplied to the oxide 230 without diffusing outside the transistor 200. .

In addition, since the insulator 272 and the stacked body of the insulator 274 have a barrier property against hydrogen and water, hydrogen and water in the outer region of the transistor 200 are not diffused into the transistor 200 and oxide The generation of oxygen vacancies in 230 can be suppressed.

For example, the insulator 272 and the insulator 274 include silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), and strontium titanate (SrTiO _3). ) Or (Ba, Sr) TiO ₃ (BST) or the like is preferably used as a single layer or a stacked layer. In particular, an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide and hafnium oxide, is preferably used. In the case of using such a material, it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the outside.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-described insulator. Alternatively, nitriding treatment may be performed on the above-described insulator. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the insulator described above.

For example, the insulator 272 is preferably an oxide insulator having a barrier property against oxygen, hydrogen, and water. For example, the insulator 272 can be formed using aluminum oxide by a sputtering method. In the case of forming aluminum oxide, since the sputtering method has a higher film formation rate than the ALD method, the insulator 272 having a thickness that can secure a sufficient barrier property against oxygen, hydrogen, and water is used. It can be formed with a high yield.

Note that an excess oxygen region can be formed in the insulator 250 and the insulator 224 by using an oxide formed by a sputtering apparatus for the insulator 272.

For example, the insulator 274 is preferably a dense film with high coating properties. As the dense film having a high film property, for example, aluminum oxide using an atomic layer deposition (ALD) method can be used. By forming a film using the ALD method, a dense insulator 274 with reduced defects such as cracks and pinholes or a uniform thickness can be formed.

By stacking a dense insulator 274 with a high film property over the insulator 272 having a barrier property, an insulator with a high barrier property can be obtained. Further, by stacking aluminum oxide formed by an ALD method on aluminum oxide formed by a sputtering method, a stacked body with high reliability and productivity can be provided.

Subsequently, an insulator 280 is formed over the transistor 200. Further, after an insulator to be the insulator 280 is formed, a planarization process using a CMP method or the like may be performed in order to improve the planarity of the upper surface.

Subsequently, an insulator 282 is formed over the insulator 280. The insulator 282 is preferably formed with a sputtering apparatus. With this structure, entry of hydrogen into a structure below the insulator 282 can be prevented.

Next, the insulator 286 is formed over the insulator 282 (FIGS. 5E and 5F). For example, as the insulator 286, an insulator containing oxygen such as a silicon oxide film or a silicon oxynitride film is formed by a CVD method. The insulator 286 preferably has a lower dielectric constant than the insulator 282. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

Through the above steps, the semiconductor device of one embodiment of the present invention can be manufactured.

<Transistor structure 2>
FIG. 6 illustrates an example of a semiconductor device including the transistor 200. FIG. 6A illustrates the top surface of the semiconductor device. Note that some films are omitted in FIG. 6A for clarity. 6B is a cross-sectional view corresponding to the alternate long and short dash line L1-L2 illustrated in FIG. 6A, and FIG. 6C is a cross-sectional view corresponding to W1-W2.

Note that in the semiconductor device illustrated in FIG. 6, a structure having the same function as a structure of the semiconductor device illustrated in FIG.

In the structure illustrated in FIG. 6, the composition of the oxide 230c is equal to or close to the atomic ratio of the oxide 230b. With this structure, when a channel is formed in the oxide 230c and the oxide 230b, the current is not inhibited at the interface between the oxide 230c and the oxide 230b, and a favorable on characteristic is obtained. The transistor 200 can be obtained.

That is, in the oxide 230b, processing damage may occur when a source electrode or a drain electrode is formed on the upper surface and side surfaces of a region where a channel is formed. Therefore, when an oxide semiconductor that has the same atomic ratio as that of the oxide 230b or an atomic ratio in the vicinity of the oxide 230b is used for the oxide 230c, In 230b, processing damage generated on the upper surface and side surfaces of the region where the channel is formed may be compensated.

Therefore, in the structure shown in FIG. 6, when the transistor 200 is turned on, a current flows mainly through the oxide 230c and the oxide 230b (a channel is formed). On the other hand, in the oxide 230a, current may flow near the interface with the oxide 230b (which may be a mixed region), but the other region may function as an insulator.

As shown in FIG. 6C, the oxide 230c is preferably provided so as to cover the side surfaces of the oxide 230a and the oxide 230b. Therefore, in the region where the channel is formed, an interface between the insulator 250 and the oxide 230c and an interface between the oxide 230c and the oxide 230b are formed on the side surface of the oxide 230. That is, since the oxide 230c is interposed between the insulator 250 and the oxide 230b, the oxide 230b and the insulator 250 are not in contact with each other even on the side surface. The generation of oxygen vacancies can be suppressed at the interface.

In the structure illustrated in FIGS. 6A and 6B, a dense film with high coating properties is used for the insulator 272. As the dense film having a high film property, for example, aluminum oxide using an atomic layer deposition (ALD) method can be used. By forming a film using the ALD method, a dense insulator 272 with reduced defects such as cracks and pinholes or a uniform thickness can be formed.

As the insulator 274, aluminum oxide using a sputtering method can be used. In the case of forming aluminum oxide, since the sputtering method has a higher film formation rate than the ALD method, the insulator 274 having a thickness that can secure a sufficient barrier property against oxygen, hydrogen, and water is used. It can be formed with a high yield.

Note that the barrier layer 270 is not necessarily provided in the structure illustrated in FIG. By providing the insulator 272 before the insulator 274, the insulator 272 can reduce film formation damage to the transistor 200 that occurs when the insulator 274 is formed by a sputtering method.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

<Transistor structure 3>
FIG. 7 illustrates an example of a semiconductor device including the transistor 200. FIG. 7A illustrates the top surface of the semiconductor device. Note that some films are omitted in FIG. 7A for clarity. 7B is a cross-sectional view corresponding to the alternate long and short dash line L1-L2 illustrated in FIG. 7A, and FIG. 7C is a cross-sectional view corresponding to W1-W2.

Note that in the semiconductor device illustrated in FIG. 7, the structure having the same function as the structure of the semiconductor device illustrated in FIG.

In the structure shown in FIG. 7, the conductor 260 is provided in a two-layer structure. For example, the conductor 260a is formed using a thermal CVD method, an MOCVD method, or an ALD method. In particular, it is preferable to form using ALD. By forming by the ALD method or the like, damage during film formation on the insulator 250 can be reduced. Moreover, it is preferable because the coverage can be improved. Therefore, the transistor 200 with high reliability can be provided.

Subsequently, the conductor 260b is formed by a sputtering method. At this time, by including the conductor 260 a over the insulator 250, it is possible to prevent the damage on the insulator 250 from being damaged when the conductor 260 b is formed. Further, since the sputtering method has a higher film formation rate than the ALD method, the yield is high and the productivity can be improved.

The structure illustrated in FIG. 7 does not include the insulator 272 and the insulator 274. In this case, the insulator, the insulator 280 preferably has an excess oxygen region. Therefore, an insulator containing oxygen such as a silicon oxide film or a silicon oxynitride film is preferably used. As a method for forming an insulator containing excess oxygen, a film formation condition in a CVD method or a sputtering method can be set as appropriate to form a silicon oxide film or a silicon oxynitride film containing a large amount of oxygen in the film. .

Note that in order to make the insulator 280 contain excessive oxygen, for example, the insulator 280 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulator 280 after film formation to form a region containing excess oxygen, or both means may be combined.

For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator 280 after being formed, so that a region containing excess oxygen is formed. As a method for introducing oxygen, an ion implantation method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

In addition, a gas containing oxygen can be used as the oxygen introduction treatment. As the gas containing oxygen, oxygen, dinitrogen monoxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, in the oxygen introduction treatment, a rare gas may be included in the gas containing oxygen. For example, a mixed gas of carbon dioxide, hydrogen, and argon can be used.

In the structure illustrated in FIG. 7, the end portion of the barrier layer 270 and the end portions of the insulator 250, the insulator 252, and the oxide 230 c overlap. That is, the barrier layer 270, the insulator 250, the insulator 252, and the oxide 230c can be processed in the same step. When the barrier layer 270, the oxide 230c, and the insulator 250 are processed in the same process, the process can be simplified.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

(Embodiment 2)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

[Storage device 1]
The semiconductor device illustrated in FIGS. 8 and 9 includes the transistor 300, the transistor 200, and the capacitor 100.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, stored data can be held for a long time by using the transistor 200 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.

8 and 9, the wiring 3001 is electrically connected to the source of the transistor 300, and the wiring 3002 is electrically connected to the drain of the transistor 300. The wiring 3003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 3004 is electrically connected to the first gate of the transistor 200, and the wiring 3006 is electrically connected to the second gate of the transistor 200. It is connected to the. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 3005 is electrically connected to the other of the electrodes of the capacitor 100. .

The semiconductor device illustrated in FIGS. 8 and 9 has the characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read as described below.

Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge is held at the node FG (holding).

When the off-state current of the transistor 200 is small, the charge of the node FG is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 300 is an n-channel type, the apparent threshold voltage V _{th_H} when the gate of the transistor 300 is _supplied with a high level charge is the low level charge applied to the gate of the transistor 300. This is because it becomes lower than the apparent threshold voltage V _{th_L in the} case of being present. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 300 into a “conductive state”. Therefore, by _setting the potential of the fifth wiring 3005 to a potential V ₀ between V _{th_H} and V _{th_L} , the charge given to the node FG can be determined. For example, in writing, when a high-level charge is applied to the node FG, the transistor 300 is turned “on” when the potential of the fifth wiring 3005 is V ₀ (> V _{th_H} ). On the other hand, when a low-level charge is _{supplied to} the node FG, the transistor 300 remains in a “non-conduction state” even when the potential of the fifth wiring 3005 becomes V ₀ (<V _{th_L} ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.

<Structure of Semiconductor Device 1>
The semiconductor device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

The transistor 300 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a which functions as a source region or a drain region, and a low resistance region 314b. Have.

The transistor 300 may be either a p-channel type or an n-channel type.

The region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

The low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.

The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

Note that the threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.

Note that the transistor 300 illustrated in FIGS. 8A and 8B is an example, and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 300.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.

The insulator 322 may function as a planarization film that planarizes a step generated by the transistor 300 or the like provided thereunder. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.

The insulator 324 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 to a region where the transistor 200 is provided.

As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

The amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorbed from the insulator 324 is 10 × 10 5 in terms of the amount of desorbed hydrogen atoms converted to hydrogen atoms per area of the insulator 324 in the range of 50 ° C. to 500 ° C. in TDS analysis. It may be ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 324 is preferably equal to or less than 0.7 times that of the insulator 326, and more preferably equal to or less than 0.6 times. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

The insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like. Note that the conductor 328 and the conductor 330 function as plugs or wirings. In addition, a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures. In this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

As a material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.

A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 8, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

For example, as the insulator 350, an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

For example, tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

A wiring layer may be provided over the insulator 350 and the conductor 356. For example, in FIG. 8, an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked. Further, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Note that for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 8, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 370. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 8, an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked. A conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 380. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked over the insulator 384. Any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216 is preferably formed using a substance having a barrier property against oxygen or hydrogen.

For example, the insulator 210 and the insulator 214 are each formed using a film having a barrier property such that hydrogen or an impurity does not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 200 is provided. Is preferred. Therefore, a material similar to that of the insulator 324 can be used.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

As the film having a barrier property against hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210 and the insulator 214.

In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

For example, the insulator 212 and the insulator 216 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulating film as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 212 and the insulator 216, a silicon oxide film, a silicon oxynitride film, or the like can be used.

The insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (conductor 205) included in the transistor 200, and the like. Note that the conductor 218 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300. The conductor 218 can be provided using a material similar to that of the conductor 328 and the conductor 330.

In particular, the insulator 210 and the conductor 218 in a region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 200 are layers having a barrier property against oxygen, hydrogen, and water and can be completely separated from each other, so that diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed. .

A transistor 200 is provided above the insulator 216. Note that as the structure of the transistor 200, a transistor included in the semiconductor device described in the above embodiment may be used. The transistor 200 illustrated in FIGS. 8A and 8B is an example, and is not limited to the structure. An appropriate transistor may be used depending on a circuit configuration or a driving method.

An insulator 280 is provided above the transistor 200. It is preferable that an excess oxygen region be formed in the insulator 280. In particular, in the case where an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region is provided in an interlayer film or the like in the vicinity of the transistor 200, so that oxygen vacancies in the oxide 230 included in the transistor 200 are reduced. Can be improved. Further, the insulator 280 that covers the transistor 200 may function as a planarization film that covers the uneven shape below the transistor 200.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide which desorbs oxygen by heating means that the amount of desorbed oxygen converted to oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ in TDS analysis. An oxide film having atoms / cm ³ or more. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates.

An insulator 282 is provided over the insulator 280. The insulator 282 is preferably formed using a substance having a barrier property against oxygen or hydrogen. Therefore, the insulator 282 can be formed using a material similar to that of the insulator 214. For example, the insulator 282 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

An insulator 286 is provided over the insulator 282. The insulator 286 can be formed using a material similar to that of the insulator 320. In addition, by using a material having a relatively low dielectric constant for the insulating film as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 286, a silicon oxide film, a silicon oxynitride film, or the like can be used.

A conductor 246, a conductor 248, and the like are embedded in the insulator 220, the insulator 222, the insulator 224, the insulator 280, the insulator 282, and the insulator 286.

The conductor 246 and the conductor 248 function as plugs or wirings that are electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 246 and the conductor 248 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Subsequently, the capacitor element 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110, a conductor 120, and an insulator 130.

Further, the conductor 112 may be provided over the conductor 246 and the conductor 248. The conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 110 functions as an electrode of the capacitor 100. Note that the conductor 112 and the conductor 110 can be formed at the same time.

The conductor 112 and the conductor 110 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-described element as a component. (Tantalum nitride, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.

In FIG. 8, the conductor 112 and the conductor 110 have a single-layer structure; however, the structure is not limited thereto, and a stacked structure of two or more layers may be used. For example, a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.

Further, an insulator 130 is provided as a dielectric of the capacitor 100 over the conductor 112 and the conductor 110. Examples of the insulator 130 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, and hafnium nitride. What is necessary is just to use, and it can provide by lamination | stacking or single layer.

For example, the insulator 130 may be formed using a material having high dielectric strength such as silicon oxynitride. With this configuration, the capacitor 100 includes the insulator 130, whereby the dielectric strength is improved and electrostatic breakdown of the capacitor 100 can be suppressed.

A conductor 120 is provided over the insulator 130 so as to overlap with the conductor 110. Note that the conductor 120 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.

An insulator 150 is provided over the conductor 120 and the insulator 130. The insulator 150 can be provided using a material similar to that of the insulator 320. Further, the insulator 150 may function as a planarization film that covers the concave and convex shapes below the insulator 150.

The above is the description of the configuration example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Variation 1 of Storage Device 1>
Moreover, an example of the modification of this Embodiment is shown in FIG. FIG. 9 is different from FIG. 8 in the configuration of the transistor 300.

In the transistor 300 illustrated in FIG. 9, a semiconductor region 313 where a channel is formed (a part of the substrate 311) has a convex shape. In addition, a conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material that adjusts a work function. Such a transistor 300 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is described here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

The above is the description of the modified example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Modification 2 of storage device 1>
An example of a modification of the storage device is shown in FIG. 10 differs from FIGS. 8 and 9 in the arrangement of the capacitor element 100 and the like.

A capacitor 100 illustrated in FIG. 10 is formed using the same layer as the transistor 200. 10 includes a barrier layer 122, a conductor 120, an insulator 250, an oxide 230c, a barrier layer 245b, and a conductor 240b. The conductor 120 and the conductor 240b function as electrodes of the capacitor 100, and the barrier layer 245b, the oxide 230c, and the insulator 250 function as a dielectric of the capacitor 100. Note that the barrier layer 122 has a function of preventing the conductor 120 from being oxidized.

The conductor 120 is the same layer as the conductor 260, and the barrier layer 122 is the same layer as the barrier layer 270. Therefore, the conductor 120 can be formed in the same process as the conductor 260. The barrier layer 122 can be formed in the same process as the barrier layer 270. That is, since the process can be shortened, productivity can be improved.

Further, by using the structure illustrated in FIG. 10, the process can be shortened by forming the transistor 200 and the capacitor 100 together.

By using this structure, in a memory device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a memory device with reduced power consumption can be provided.

The above is the description of the modified example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Structure of memory cell array>
An example of the memory cell array of this embodiment is illustrated in FIG. A memory cell array can be formed by arranging the semiconductor devices shown in FIGS. 8 and 9 in a matrix. FIG. 11 is a cross-sectional view of a part of a row in the case where the storage device illustrated in FIG. 8 is arranged in a matrix.

In FIG. 11, a semiconductor device including the transistor 300, the transistor 200, and the capacitor 100 and a semiconductor device including the transistor 340, the transistor 201, and the capacitor 101 are arranged in the same row. Yes.

As shown in FIG. 11, the memory cell array has a plurality of transistors (a transistor 200 and a transistor 201 in the figure).

Note that when memory cells are arranged in an array, information of a desired memory cell must be read at the time of reading. For example, when the memory cell array has a NOR structure, only information on a desired memory cell can be read by turning off the transistor 300 of the memory cell from which information is not read. In this case, a fifth wiring which is connected to a memory cell from which information is not read with a potential at which the transistor 300 becomes “non-conductive” regardless of the charge applied to the node FG, that is, a potential lower than V _{th_H.} It may be given to 3005. Alternatively, for example, when the memory cell array has a NAND configuration, information on a desired memory cell can be read only by turning on the transistor 300 of the memory cell from which information is not read. In this case, a fifth wiring 3005 connected to a memory cell from which information is not read with a potential at which the transistor 300 is in a “conducting state” regardless of the charge applied to the node FG, that is, a potential higher than V _{th_L.} To give.

[Storage device 2]
FIG. 12 illustrates an example of a memory device using the semiconductor device which is one embodiment of the present invention.

The memory device illustrated in FIG. 12 includes a transistor 345 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 illustrated in FIG.

The transistor 345 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 345 are diode-connected to the source, and the source of the transistor 345 is connected to the second gate of the transistor 200. When the negative potential of the second gate of the transistor 200 is held with this structure, the voltage between the first gate and the source of the transistor 345 and the voltage between the second gate and the source are 0V. In the transistor 345, since the drain current when the second gate voltage and the first gate voltage are 0 V is very small, the power supply to the transistor 200 and the transistor 345 is not supplied, so that the second gate voltage of the transistor 200 Negative potential can be maintained for a long time. Thus, the memory device including the transistor 200 and the transistor 345 can hold stored data for a long time.

Accordingly, in FIG. 12, the wiring 3001 is electrically connected to the source of the transistor 300, and the wiring 3002 is electrically connected to the drain of the transistor 300. The wiring 3003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 3004 is electrically connected to the gate of the transistor 200, and the wiring 3006 is electrically connected to the back gate of the transistor 200. . The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 3005 is electrically connected to the other of the electrodes of the capacitor 100. . The wiring 3007 is electrically connected to the source of the transistor 345, the wiring 3008 is electrically connected to the gate of the transistor 345, the wiring 3009 is electrically connected to the back gate of the transistor 345, and the wiring 3010 is connected to the drain of the transistor 345. And are electrically connected. Here, the wiring 3006, the wiring 3007, the wiring 3008, and the wiring 3009 are electrically connected.

The memory device illustrated in FIG. 12 has a characteristic that the potential of the gate of the transistor 300 can be held; thus, information can be written, held, and read as described below.

The memory device illustrated in FIG. 12 can form a memory cell array by being arranged in a matrix like the memory device illustrated in FIG. Note that one transistor 345 can control the second gate voltage of the plurality of transistors 200. Therefore, the transistor 345 may be provided in a smaller number than the transistor 200.

<Structure of storage device 2>
The transistor 345 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 345 includes a conductor 460 (a conductor 460a and a conductor 460b) that functions as a first gate electrode, a conductor 405 (a conductor 405a and a conductor 405b) that functions as a second gate electrode, A barrier layer 470 in contact with the conductor 460, an insulator 220 functioning as a gate insulating layer, an insulator 222, an insulator 224, and an insulator 450, an oxide 430c having a region where a channel is formed, a source or a drain The conductor 440a, the oxide 431a, and the oxide 431b functioning as one of the above, the conductor 440b, the oxide 432a, and the oxide 432b functioning as the other of the source and the drain, and the conductor 440 (the conductor 440a, and Conductor 440b) barrier layer 445 (barrier layer 445a and barrier layer 4) Having 5b).

In the transistor 345, the conductor 405 is in the same layer as the conductor 205. The oxide 431a, the oxide 432a, and the oxide 230a are the same layer, and the oxide 431b, the oxide 432b, and the oxide 230b are the same layer. The conductor 440 is the same layer as the conductor 240. The oxide 430c is the same layer as the oxide 230c. The insulator 450 is the same layer as the insulator 250. The conductor 460 is the same layer as the conductor 260. The barrier layer 470 is the same layer as the barrier layer 270.

In the oxide 430c functioning as an active layer of the transistor 345, oxygen vacancies are reduced and impurities such as hydrogen or water are reduced as in the oxide 230 and the like. Accordingly, the threshold voltage of the transistor 345 can be made higher than 0 V, the off-current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made extremely small.

A dicing line (which may be referred to as a scribe line, a dividing line, or a cutting line) provided when a plurality of semiconductor devices are taken out in a chip shape by dividing the large-area substrate into semiconductor elements will be described. As a dividing method, for example, a groove (dicing line) for dividing a semiconductor element may first be formed on a substrate, and then cut in the dicing line to be divided (divided) into a plurality of semiconductor devices. For example, the structure 500 shown in FIG. 12 shows a cross-sectional view near the dicing line.

For example, as illustrated in the structure 500, the insulator 280, the insulator 224, the insulator 222, the insulator 220, and the insulator are formed in the vicinity of a region overlapping with a dicing line provided on the outer edge of the memory cell including the transistor 200 or the transistor 345 An opening is provided in the body 216. The insulator 282 is provided so as to cover side surfaces of the insulator 280, the insulator 224, the insulator 222, the insulator 220, and the insulator 216.

That is, the insulator 222, the insulator 210, and the insulator 282 are in contact with each other in the opening. At this time, adhesion can be improved by forming at least one of the insulator 222 and the insulator 210 and the insulator 282 using the same material and the same method. For example, aluminum oxide can be used.

With this structure, the insulator 280, the transistor 200, and the transistor 345 can be wrapped with the insulator 210, the insulator 222, and the insulator 282. Since the insulator 210, the insulator 222, and the insulator 282 have a function of suppressing diffusion of oxygen, hydrogen, and water, a circuit region including a plurality of substrates over which the semiconductor element described in this embodiment is formed By dividing each of them, even when processed into a plurality of chips, impurities such as hydrogen or water can be prevented from being mixed into the transistor 200 or the transistor 345 from the side surface direction of the divided substrate. .

Further, with this structure, excess oxygen in the insulator 280 can be prevented from diffusing outside the insulator 282 and the insulator 222. Accordingly, excess oxygen in the insulator 280 is efficiently supplied to the oxide in which the channel in the transistor 200 or the transistor 345 is formed. With the oxygen, oxygen vacancies in the oxide in which a channel in the transistor 200 or the transistor 345 is formed can be reduced. Accordingly, an oxide in which a channel is formed in the transistor 200 or the transistor 345 can be an oxide semiconductor having a low defect level density and stable characteristics. That is, variation in electrical characteristics of the transistor 200 or the transistor 345 can be suppressed and reliability can be improved.

<Modification 1 of Storage Device 2>
An example of a modification of the present embodiment is shown in FIG. FIG. 13 is different from FIG. 12 in the structure of the transistor 345.

A transistor 345 illustrated in FIG. 13 includes a conductor 440a, a conductor 441a, a conductor 440b, and a conductor 441b provided in the same layer as the conductor 405. That is, in the transistor 345, the source electrode or the drain electrode can be provided at the same time as the second gate electrode.

The above is the description of the modified example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

(Embodiment 3)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

<Semiconductor wafer, chip>
FIG. 14A shows a top view of the substrate 711 before the dicing process is performed. As the substrate 711, for example, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used. A plurality of circuit regions 712 are provided on the substrate 711. The circuit region 712 can be provided with a semiconductor device according to one embodiment of the present invention.

Each of the plurality of circuit regions 712 is surrounded by the isolation region 713. A separation line (also referred to as “dicing line”) 714 is set at a position overlapping with the separation region 713. By cutting the substrate 711 along the separation line 714, the chip 715 including the circuit region 712 can be cut out from the substrate 711. FIG. 14B shows an enlarged view of the chip 715.

Further, a conductive layer, a semiconductor layer, or the like may be provided in the separation region 713. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, ESD that may occur in the dicing process can be reduced, and a reduction in yield due to the dicing process can be prevented. In general, the dicing step is performed while supplying pure water having a specific resistance lowered by dissolving carbon dioxide gas or the like for the purpose of cooling the substrate, removing shavings, and preventing charging. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, the amount of pure water used can be reduced. Thus, the production cost of the semiconductor device can be reduced. In addition, productivity of the semiconductor device can be increased.

<Electronic parts>
An example of an electronic component using the chip 715 will be described with reference to FIGS. 15A and 15B. Note that the electronic component is also referred to as a semiconductor package or an IC package. Electronic parts have a plurality of standards, names, and the like depending on the terminal take-out direction, the terminal shape, and the like.

Electronic components are completed by combining the semiconductor device described in the above embodiment and components other than the semiconductor device in an assembly process (post-process).

The post-process will be described with reference to the flowchart shown in FIG. After the semiconductor device or the like according to one embodiment of the present invention is formed over the substrate 711 in the previous step, a “back surface grinding step” of grinding the back surface (the surface where the semiconductor device or the like is not formed) of the substrate 711 is performed (step S721). . By reducing the thickness of the substrate 711 by grinding, the electronic component can be downsized.

Next, a “dicing process” for separating the substrate 711 into a plurality of chips 715 is performed (step S722). Then, a “die bonding step” is performed in which the separated chip 715 is bonded onto each lead frame (step S723). For the bonding of the chip 715 and the lead frame in the die bonding step, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. Note that the chip 715 may be bonded on the interposer substrate instead of the lead frame.

Next, a “wire bonding process” is performed in which the lead of the lead frame and the electrode on the chip 715 are electrically connected with a thin metal wire (step S724). A silver wire, a gold wire, etc. can be used for a metal fine wire. For wire bonding, for example, ball bonding or wedge bonding can be used.

The chip 715 that has been wire bonded is subjected to a “sealing process (molding process)” that is sealed with an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, the wire connecting the chip 715 and the lead can be protected from mechanical external force, and deterioration of characteristics due to moisture, dust, etc. (reliability Reduction) can be reduced.

Next, a “lead plating process” for plating the leads of the lead frame is performed (step S726). The plating process prevents rusting of the lead, and soldering when mounted on a printed circuit board later can be performed more reliably. Next, a “molding process” for cutting and molding the lead is performed (step S727).

Next, a “marking process” is performed in which a printing process (marking) is performed on the surface of the package (step S728). An electronic component is completed through an “inspection process” (step S729) for checking whether the external shape is good or not, and whether there is a malfunction.

FIG. 15B is a schematic perspective view of the completed electronic component. FIG. 15B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 750 illustrated in FIG. 15B includes a lead 755 and a chip 715. The electronic component 750 may have a plurality of chips 715.

An electronic component 750 illustrated in FIG. 15B is mounted on a printed board 752, for example. A plurality of such electronic components 750 are combined and each is electrically connected on the printed circuit board 752 to complete a substrate (mounting substrate 754) on which the electronic components are mounted. The completed mounting board 754 is used for an electronic device or the like.

(Embodiment 4)
<Electronic equipment>
The semiconductor device according to one embodiment of the present invention can be used for various electronic devices. FIG. 16 illustrates a specific example of an electronic device including the semiconductor device according to one embodiment of the present invention.

FIG. 16A is an external view illustrating an example of an automobile. The automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like. The automobile 2980 includes an antenna, a battery, and the like.

An information terminal 2910 illustrated in FIG. 16B includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like. The display portion 2912 includes a display panel using a flexible substrate and a touch screen. In addition, the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.

A laptop personal computer 2920 illustrated in FIG. 16C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like. The laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.

A video camera 2940 illustrated in FIG. 16D includes a housing 2941, a housing 2942, a display portion 2944, operation switches 2944, a lens 2945, a connection portion 2946, and the like. The operation switch 2944 and the lens 2945 are provided on the housing 2941, and the display portion 2944 is provided on the housing 2942. In addition, the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941. The housing 2941 and the housing 2942 are connected to each other by a connection portion 2946. The angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.

FIG. 16E illustrates an example of a bangle information terminal. The information terminal 2950 includes a housing 2951, a display portion 2952, and the like. In addition, an antenna, a battery, and the like are provided inside the information terminal 2950 and the housing 2951. The display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel using a flexible substrate, an information terminal 2950 that is flexible, light, and easy to use can be provided.

FIG. 16F illustrates an example of a wristwatch-type information terminal. The information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like. Further, an antenna, a battery, and the like are provided inside the information terminal 2960 and the housing 2961. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games.

The display surface of the display portion 2962 is curved, and display can be performed along the curved display surface. The display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be started by touching an icon 2967 displayed on the display unit 2962. The operation switch 2965 can have various functions such as time setting, power on / off operation, wireless communication on / off operation, manner mode execution and release, and power saving mode execution and release. . For example, the function of the operation switch 2965 can be set by an operating system incorporated in the information terminal 2960.

In addition, the information terminal 2960 can execute short-range wireless communication that is a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. Further, the information terminal 2960 includes an input / output terminal 2966, and can directly exchange data with other information terminals via a connector. Charging can also be performed via the input / output terminal 2966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 2966.

For example, a memory device including the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the above electronic devices for a long period. With the use of the semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be realized.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and examples.

In this example, the density, crystallinity, and flatness of the hafnium oxide film formed using the ALD method were analyzed. In addition, the density was measured using the X-ray reflectivity analysis method (XRR: X-ray Reflectometry Analysis). The crystallinity was analyzed using X-ray diffraction (XRD: X-Ray Diffraction). The flatness was measured and observed using an atomic force microscope (AFM).

In this example, Sample 1A, Sample 1B, Sample 1C, Sample 1D, and Sample 1E were prepared, and analyzed before and after the heat treatment of each sample.

<Sample configuration and production method>
FIG. 17 shows a stacked structure of Sample 1A, Sample 1B, Sample 1C, Sample 1D, and Sample 1E. Sample 1A, Sample 1B, Sample 1C, Sample 1D, and Sample 1E each include a substrate 910, an insulator 912 over the substrate 910, and an insulator 914 over the insulator 912.

Note that for the samples 1A, 1B, 1C, 1D, and 1E, hafnium oxide films having different film formation temperatures were used as the insulator 914. The following table shows the film formation temperature of the insulator 914 in Samples 1A to 1E.

Next, a method for manufacturing each sample will be described.

First, a silicon wafer was prepared as the substrate 910. Next, a silicon oxide film having a thickness of 100 nm was formed as the insulator 912 over the substrate 910 by a thermal oxidation method.

Subsequently, a hafnium oxide film having a thickness of 50 nm was formed as the insulator 914 over the insulator 912 by using an ALD apparatus. Incidentally, hafnium oxide film, by a thermal ALD process, TEMAH as precursor _{(Tetrakis (ethymethylamino) hafnium: Hf} [N (C2H 5) (CH 3)] 4) and was deposited with the ozone, the.

In Sample 1A, a hafnium oxide film was formed at 200 ° C. In sample 1B, a hafnium oxide film was formed at 250 ° C. In sample 1C, a hafnium oxide film was formed at 300 ° C. In sample 1D, a hafnium oxide film was formed at 350 ° C. In Sample 1E, a hafnium oxide film was formed at 400 ° C.

Through the above steps, Sample 1A to Sample 1E of this example were manufactured.

Further, heat treatment was performed on the samples 1A to 1E. The heat treatment was performed for 1 hour at 400 ° C. in a nitrogen atmosphere.

<Measurement of sample density>
For Samples 1A to 1E, the density of the insulator 914 before heat treatment and the density of the insulating layer 914 after heat treatment were measured using an X-ray reflectance analysis method. A D8 ADVANCE manufactured by Bruker was used as the XRR apparatus.

FIG. 18 shows the measurement results of the density before and after the heat treatment in Samples 1A to 1E.

The density of the insulator 914 in Sample 1A was 7.2 g / cm ³ before the heat treatment and 8.4 g / cm ³ after the heat treatment. The density of the insulator 914 in Sample 1B was 8.4 g / cm ³ before the heat treatment and 8.5 g / cm ³ after the heat treatment. The density of the insulator 914 in Sample 1C was 9.7 g / cm ³ before the heat treatment and 9.8 g / cm ³ after the heat treatment. The density of the insulator 914 in the sample. 1D, before the heat treatment is 9.8 g / cm ^3, after the heat treatment was 9.8 g / cm ^3. The density of the insulator 914 in Sample 1E was 9.9 g / cm ³ before the heat treatment and 10.0 g / cm ³ after the heat treatment.

Therefore, it was found that the insulator 914 tends to increase in density as the film formation temperature increases. In particular, it was found that in Sample 1A, Sample 1B, and Sample 1C in which the film formation temperature of the insulator 914 is 300 ° C. or lower, the higher the film formation temperature, the higher the density. On the other hand, Sample 1C, Sample 1D, and Sample 1E in which the film formation temperature of the insulator 914 is 300 ° C. or higher have a density of 9.5 g / cm ³ or higher, and it was found that there is not much difference.

In addition, in Sample 1B, Sample 1C, Sample 1D, and Sample 1E in which the film formation temperature of the insulator 914 is 250 ° C. or higher, change in density of the insulator 914 before and after the heat treatment performed after the film formation of the insulator 914 It was found that the film formation temperature of the insulator 914 was smaller than that of the sample 1A having a temperature of 200 ° C. or lower.

From the above, it was found that the hafnium oxide film formed by the ALD method has a density of 9.5 g / cm ³ or less at a film forming temperature of 300 ° C. or lower. Further, it was found that the hafnium oxide film formed by the ALD method has a density of 7.0 g / cm ³ or more and 9.0 g / cm ³ or less at a film forming temperature of 200 ° C. or higher and 250 ° C. or lower. Furthermore, the hafnium oxide film formed by the ALD method has a film formation temperature of 200 ° C. or higher and 250 ° C. or lower, and a density of 8.0 g / cm ³ or more and 8.5 g / cm even when heat treatment is performed after the film formation. It was found to be cm ³ or less.

<Analysis of crystallinity of sample>
For the samples 1A to 1E, the insulator 914 was measured by X-ray diffraction (XRD). Note that Bruker D8 ADVANCE was used as the XRD apparatus. The condition is that the scanning range is 15 deg. In θ / 2θ scanning by the out-of-plane method. To 50 deg. , The step width is 0.02 deg. The scanning speed is 3.0 deg. / Min.

FIG. 19 shows the results of measuring the XRD spectrum using the out-of-plane method. Note that FIG. 19A shows the result of measuring the XRD spectrum before the heat treatment, and FIG. 19B shows the result of measuring the XRD spectrum after the heat treatment.

In the XRD spectra shown in FIGS. 19A and 19B, peak intensities around 2θ = 24.2 ° and 2θ = 28.4 ° are detected in sample 1D and sample 1E. It was. Therefore, it is considered that the insulator 914 is crystallized as the deposition temperature increases.

The peaks near 2θ = 24.2 ° and 2θ = 28.4 ° are peaks derived from monoclinic crystals. Further, it is considered that the peak around 2θ = 31.7 ° is a peak derived from the silicon wafer.

From the above, it was found that the hafnium oxide film formed by the ALD method has a monoclinic crystal structure when the film forming temperature is higher than 300 ° C.

Next, the flatness evaluation of Samples 1A to 1E was performed using a scanning probe microscope system SPA-500 manufactured by SII Nano Technology Co., Ltd. The measurement range was 1 μm × 1 μm and 10 μm × 10 μm. The measurement conditions with the scanning probe microscope were a scanning speed of 1.0 Hz, a number of data of X = 512, Y = 512, and a number of measurement points of 10. Further, for the measurement, a method was used in which the surface shape was measured while controlling the distance between the probe and the sample so that the vibration amplitude of the lever was constant while the cantilever was resonated.

The flatness of Samples 1A to 1E was evaluated by the root sum square of surface roughness (RMS). The result is shown in FIG. In addition, as a result of evaluating the square sum square root (RMS) of the surface roughness before the heat treatment in FIG. 20A, the square sum square root (RMS) of the surface roughness after the heat treatment was evaluated in FIG. 20B. Results are shown.

From FIG. 20A, in the measurement range of 1 μm × 1 μm, the root mean square roughness (RMS) of sample 1A is 3.780 × 10 ⁻¹ nm (before heating) and 2.968 × 10 ⁻¹ nm. (After heating). The root mean square roughness (RMS) of Sample B was 3.793 × 10 ⁻¹ nm (before heating) and 3.544 × 10 ⁻¹ nm (after heating). The root mean square roughness (RMS) of Sample 1C was 1.761 nm (before heating) and 2.143 nm (after heating). Sample 1D had a root mean square roughness (RMS) of 1.792 nm (before heating). The root mean square roughness (RMS) of Sample 1E was 2.070 nm (before heating).

From FIG. 20B, in the measurement range of 10 μm × 10 μm, the root mean square roughness (RMS) of the sample 1A is 8.764 × 10 ⁻¹ nm (before heating) and 3.181 × 10 ⁻¹ nm. (After heating). Sample B had a root mean square roughness (RMS) of 8.238 × 10 ⁻¹ nm (before heating) and 7.649 × 10 ⁻¹ nm (after heating). Sample 1C had a root mean square roughness (RMS) of 3.12 nm (before heating) and 3.636 nm (after heating). The root mean square roughness (RMS) of Sample 1D was 2.920 nm (before heating). The root mean square roughness (RMS) of Sample 1E was 2.779 nm (before heating).

Therefore, it was found that Sample 1A and Sample 1B can be formed with higher flatness than Sample 1C, Sample 1D, and Sample 1E. In addition, when heat treatment was performed after film formation, Sample 1A and Sample 1B had lower root mean square roughness (RMS) values than before heat treatment. On the other hand, Sample 1C had a high root mean square roughness (RMS) value.

From the above, it is found that the hafnium oxide film formed by the ALD method has a root mean square roughness (RMS) of 0.50 nm or less at a film forming temperature of less than 300 ° C. in a measurement range of 1 μm × 1 μm. It was. Further, it was found that the hafnium oxide film formed by the ALD method has a smaller root mean square roughness (RMS) value when the film formation temperature is less than 300 ° C. and heat treatment is performed after the film formation. .

Further, it was found that the hafnium oxide film formed by the ALD method has a root mean square roughness (RMS) of 1.0 nm or less at a film forming temperature of less than 300 ° C. in a measurement range of 10 μm × 10 μm. . Further, the hafnium oxide film formed by the ALD method has a root mean square roughness (RMS) value of less than 300 ° C. when the heat treatment is performed after the film formation. It was found that when the temperature was 200 ° C., it was 0.5 nm or less.

From this example, the hafnium oxide film formed by the ALD method has a density of 7.0 g / cm ³ or more and 9.0 g / cm ³ or less and a root mean square roughness (RMS) when the film forming temperature is less than 300 ° C. ) Was 0.5 nm or less in the measurement range of 1 μm × 1 μm, or 1.0 nm or less in the measurement range of 10 μm × 10 μm.

The structure described in this example can be used in appropriate combination with any of the other examples or the other embodiments.

In this example, analysis was performed using SIMS using a stacked structure of an oxide and an insulator which is one embodiment of the present invention. In this example, samples 2A to 2E were manufactured.

<Sample configuration and production method>
Hereinafter, Sample 2A, Sample 2B, Sample 2C, Sample 2D, and Sample 2E according to one embodiment of the present invention will be described. Samples 2A to 2E have a stacked structure shown in FIG. The structure shown in FIG. 21 includes a substrate 920, an insulator 922 over the substrate 920, an insulator 924 over the insulator 922, an insulator 926 over the insulator 924, an insulator 928 over the insulator 926, Have

Note that hafnium oxide films having different film formation temperatures were used as the insulator 924 for 3A, Sample 2B, Sample 2C, Sample 2D, and Sample 2E. The following table shows the film formation temperature of the insulator 924 in Samples 2A to 2E.

Next, a method for manufacturing each sample will be described.

First, a silicon substrate was prepared as the substrate 920. Subsequently, a thermal oxide film having a thickness of 100 nm was formed as an insulator 922 over the substrate 920.

Subsequently, a hafnium oxide film having a thickness of 50 nm was formed as the insulator 924 over the insulator 922 by using an ALD apparatus. Note that the hafnium oxide film was formed by thermal ALD using TEMAH (Tetrakis (ethylmethylamino) hafnium: Hf [N (C2H ₅ ) (CH ₃ )] ₄ ) as a precursor and ozone as an oxidizing gas. .

In Sample 2A, a hafnium oxide film was formed at 200 ° C. In sample 2B, a hafnium oxide film was formed at 250 ° C. In sample 2C, a hafnium oxide film was formed at 300 ° C. In sample 2D, a hafnium oxide film was formed at 350 ° C. In Sample 2E, a hafnium oxide film was formed at 400 ° C.

Next, a silicon oxynitride film to be the insulator 924 was formed to a thickness of 20 nm by a CVD method.

Next, an aluminum oxide film having a thickness of 40 nm was formed as an insulator 928 over the oxide 926 by an RF sputtering method. The insulator 928 uses an Al ₂ O ₃ target, uses argon (Ar) at a flow rate of 25 sccm and oxygen ( ¹⁸ O ₂ ) at a flow rate of 25 sccm as a film formation gas, forms a film formation pressure at 0.4 Pa, and forms a film. The film was formed with an electric power of 2500 W and a target-substrate distance of 60 mm.

Through the above steps, Sample 2A to Sample 2E of this example were manufactured.

<Measurement result of SIMS of sample>
Next, SIMS analysis was performed from the substrate side using the oxide 924 of Samples 2A to 2H as a quantitative layer, and the result of detecting the oxygen ( ¹⁸ O) concentration is shown in FIG. The oxygen concentration was evaluated by secondary ion mass spectrometry (SIMS), and a dynamic SIMS device IMS-7f manufactured by CAMECA was used as an analyzer.

FIG. 22 shows sample 2A (solid line (thick)), sample 2B (broken line (thick)), sample 2C (solid line (thin)), sample 2D (dashed line (thin)), and sample 2E (single dotted line (thin)). 2 shows a depth profile of oxygen ( ¹⁸ O) concentration in the insulator 924 film. In addition, the double arrow in a figure shows the range of each insulator.

Here, since the main component of the insulator 924 which is a hafnium oxide film is ¹⁶ O, it can be seen that ¹⁸ O is oxygen diffused from the oxide 928.

Therefore, as shown in FIG. 22, the sample 2A with a film formation temperature of 200 ° C. and the sample 2B with a film formation temperature of 250 ° C. are formed with an insulator 928, whereby oxygen is transferred to the insulator 924 through the insulator 926. Was found to diffuse. In particular, in Sample 2A, it was found that oxygen diffused to the interface between the insulator 924 and the insulator 922. In Sample 2B, it was found that oxygen diffused in the thickness direction of the insulator 924 in the range of 10 nm to 20 nm. On the other hand, it was found that Samples 2C to 2D having a film formation temperature of 300 ° C. or higher have less oxygen diffusion into the insulator 924.

Here, in the previous embodiment, it has been found that the hafnium oxide film formed by the ALD method has a low density and low crystallinity when the film forming temperature is lowered. For example, it has been found that a hafnium oxide film formed by the ALD method has a density of 9.5 g / cm ³ or less at a film forming temperature of 300 ° C. or lower. Further, it was found that the hafnium oxide film formed by the ALD method has a density of 7.0 g / cm ³ or more and 9.0 g / cm ³ or less at a film forming temperature of 200 ° C. or higher and 250 ° C. or lower. Furthermore, the hafnium oxide film formed by the ALD method has a film formation temperature of 200 ° C. or higher and 250 ° C. or lower, and a density of 8.0 g / cm ³ or more and 8.5 g / cm even when heat treatment is performed after the film formation. It was found to be cm ³ or less.

From the above, it is considered that a film having a lower density or lower crystallinity is more likely to diffuse oxygen. For example, a hafnium oxide film with a density of 7.0 g / cm ³ or more and 9.0 g / cm ³ or less, preferably a density of 8.0 g / cm ³ or more and 8.5 g / cm ³ or less can diffuse oxygen. It could be confirmed.

As described above, the structure described in this example can be combined as appropriate with any of the other examples or the other embodiments.

In this example, as the sample 3A, the sample 3B, and the sample 3C, a semiconductor device including the transistor 200 illustrated in FIG. 1, which is one embodiment of the present invention, was manufactured, and electrical characteristics and reliability tests of the transistor 200 were performed. Note that the channel length of the transistor 200 was 0.18 μm and the channel width was 0.35 μm. Sample 3A, sample 3B, and sample 3C formed 36 transistors 200 in the same process.

Note that hafnium oxide films having different film formation temperatures were used as the insulator 250 in the samples 3A, 3B, and 3C. The following table shows the film formation temperature of the insulator 250 in the samples 3A to 3C.

Here, it is assumed from the previous embodiment that the hafnium oxide film formed by the ALD method used for the insulator 250 has different density, crystallinity, and flatness depending on the film formation temperature. .

<Sample preparation method>
Hereinafter, a method for manufacturing Sample 3A, Sample 3B, and Sample 3C will be described.

First, a silicon oxide film having a thickness of 400 nm was formed as an insulator 212 on a p-type silicon single crystal wafer by a thermal oxidation method. Subsequently, an aluminum oxide film having a thickness of 40 nm was formed as an insulator 214 over the insulator 212 by a sputtering method. Further, a silicon oxynitride film with a thickness of 160 nm was formed as the insulator 216 over the insulator 214 by a CVD method.

Next, a tungsten film was formed to a thickness of 35 nm over the insulator 216 by a sputtering method. Next, using a resist mask formed by a lithography method, the tungsten film was processed to form a hard mask having the tungsten film.

Next, the insulator 216 was processed by a damascene method to form an opening and a groove to be a wiring. Note that as shown in the drawing, in this step, part of the insulator 214 may be removed.

Subsequently, a tantalum nitride film is formed in the opening and the groove by a sputtering method, a titanium nitride film is formed on the tantalum nitride film by an ALD method, and a CVD method is formed on the titanium nitride film. A tungsten film was formed. Next, by CMP treatment, the tungsten film, titanium nitride film, and tantalum nitride film are polished until the upper surface of the silicon oxynitride film is reached, and unnecessary portions of tungsten, titanium nitride, and tantalum nitride are removed in the openings and in the grooves. By removal, a conductor corresponding to the conductor 205 (the conductor 205a, the conductor 205b, and the conductor 205c) was formed.

Next, as the insulator 220, the insulator 222, and the insulator 224, a silicon oxynitride film, a hafnium oxide film, and a silicon oxynitride film were sequentially formed. The silicon oxynitride film is formed with a thickness of 10 nm by a CVD method, the hafnium oxide film is formed with a thickness of 20 nm by an ALD method, and the silicon oxynitride film is formed with a thickness of 30 nm by a CVD method. A film was formed.

Next, heat treatment was performed. The heat treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing nitrogen.

Next, an In—Ga—Zn oxide film was formed to a thickness of 5 nm by a sputtering method with the first oxide to be the oxide 230a. The first oxide was formed using an In: Ga: Zn = 1: 3: 4 [atomic ratio] target under conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200 ° C. .

Next, an In—Ga—Zn oxide was formed to a thickness of 20 nm over the first oxide by a sputtering method to form the second oxide to be the oxide 230b. The second oxide uses a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio], an argon gas flow rate of 30 sccm, an oxygen gas flow rate of 15 sccm, a pressure of 0.7 Pa, and a substrate temperature of 130 ° C. The film was formed under the following conditions. Note that the first oxide and the second oxide were continuously formed.

Next, heat treatment was performed. The heat treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing nitrogen, and then at a temperature of 400 ° C. for 1 hour in an atmosphere containing oxygen.

Next, a tantalum nitride film with a thickness of 30 nm was formed over the second oxide by a sputtering method. Next, an aluminum oxide film having a thickness of 5 nm was formed on the tantalum nitride film by ALD. Next, a tungsten film with a thickness of 15 nm was formed on the aluminum oxide film by a sputtering method.

Next, the tungsten film in a region where a channel is to be formed was etched using a resist mask formed by a lithography method. For this etching, a dry etching method was used.

Next, unnecessary portions of the tungsten film, the aluminum oxide, and the tantalum nitride film were etched using a resist mask formed by a lithography method. The etching was performed using a dry etching method.

Subsequently, the tungsten film from which unnecessary regions are removed and aluminum oxide are used as a hard mask, and the second oxide and the first oxide are etched to form an island having a region where a channel of the transistor is formed. Formed. Simultaneously with the etching, the aluminum oxide film in the region where the channel is formed was etched. The etching was performed using a dry etching method. Through the processing, the oxide 230a, the oxide 230b, the barrier layer 245a, and the barrier layer 245b were formed.

Next, the tungsten film from which the unnecessary region was removed was used as a hard mask, and the tantalum nitride film in the region where the channel was formed was etched. The etching was performed using a dry etching method. By the processing, the conductor 240a and the conductor 240b were formed. Note that the tungsten film used as the hard mask disappeared by the etching.

Next, a third oxide to be the oxide 230c was formed to a thickness of 5 nm by sputtering using an In—Ga—Zn oxide. The third oxide uses an In: Ga: Zn = 1: 1: 1 [atomic ratio] target, an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, a substrate temperature of R.P. T.A. The film was formed under the following conditions.

Next, a hafnium oxide film to be the insulator 250 was formed to a thickness of 10 nm by a thermal ALD method using TEMAH and ozone as a precursor by an ALD method.

In Sample 3A, a hafnium oxide film was formed at 200 ° C. In Sample 3B, a hafnium oxide film was formed at 250 ° C. In Sample 3C, a hafnium oxide film was formed at 350 ° C.

Next, a silicon oxynitride film to be the insulator 252 was formed to a thickness of 10.5 nm by a CVD method.

Next, heat treatment was performed. The heat treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing nitrogen.

Next, an In—Ga—Zn oxide with a thickness of 10 nm was formed over the silicon oxynitride film to be the insulator 252 by a sputtering method with a metal oxide to be the oxide 260a. The metal oxide was formed using an In: Ga: Zn = 4: 2: 4.1 [atomic ratio] target under conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200 ° C. .

Subsequently, a titanium nitride film to be a conductor 260b is formed to a thickness of 5 nm by a sputtering method, and a tungsten film to be a conductor 260c is formed to a thickness of 50 nm on the titanium nitride film by a sputtering method. Filmed. Note that the titanium nitride film and the tungsten film were continuously formed.

Next, heat treatment was performed. The heat treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing nitrogen.

Next, the tungsten film and the titanium nitride film were etched using a resist mask formed by a lithography method. A dry etching method was used for etching the tungsten film and the titanium nitride film. The conductor 260 was formed by the processing.

Next, a hafnium oxide film to be the insulator 250, a silicon oxynitride film to be the insulator 252 and part of the third oxide were etched using a resist mask formed by a lithography method. The etching was performed using a dry etching method. In addition, the insulator 252, the insulator 250, and the oxide 230c were formed by the processing.

Next, an aluminum oxide film to be the barrier layer 270 was formed to a thickness of 7 nm by the ALD method. Subsequently, a part of the aluminum oxide film was etched using a resist mask formed by a lithography method. A dry etching method was used for etching the aluminum oxide film. A barrier layer 270 was formed by the processing.

Next, a silicon oxynitride film to be the insulator 280 was formed to a thickness of 450 nm by a CVD method. Next, CMP is performed, the silicon oxynitride film is polished, and the surface of the silicon oxynitride film is planarized so that the film thickness on the conductor 260 functioning as the gate electrode is 60 nm. It formed so that it might become thick.

Next, an aluminum oxide film having a thickness of 40 nm is formed over the insulator 280 by sputtering as an insulator 282 under the conditions of an argon gas flow rate of 25 sccm, an oxygen gas flow rate of 25 sccm, a pressure of 0.4 Pa, and a substrate temperature of 250 ° C. A film was formed.

Next, heat treatment was performed. The heat treatment was performed at a temperature of 400 ° C. for 1 hour in an atmosphere containing nitrogen, and then at a temperature of 400 ° C. for 1 hour in an atmosphere containing oxygen.

Next, a silicon oxynitride film with a thickness of 150 nm was formed as the insulator 286 by a CVD method.

Through the above steps, Sample 3A to Sample 3C were prepared.

<Electrical characteristics and cross-sectional observation of transistor>
Next, as the electrical characteristics of Samples 3A to 3C, Id-Vg characteristics were measured, and cross-sectional observation was performed. Further, a GBT stress test was performed on the sample 3A.

Note that in the measurement of Id-Vg characteristics, a potential applied to the conductor 260 functioning as the first gate electrode of the transistor 200 (hereinafter also referred to as a gate potential (Vg)) is changed from a first value to a second value. The change in the current (hereinafter also referred to as drain current (Id)) between the conductor 240a functioning as the source electrode and the conductor 240b functioning as the drain electrode is measured.

Here, the potential between the conductor 240a and the conductor 240b (hereinafter also referred to as the drain potential Vd) is set to + 0.1V and + 3.3V, and the potential between the conductor 240a and the conductor 260 is set to −3. The change in drain current (Id) was measured when the voltage was changed from 3V to + 3.3V.

Note that in this measurement, the potential of the conductor 205 functioning as the second gate electrode (back gate electrode) (hereinafter also referred to as a back gate potential (Vbg)) is 0.00 V, −1.00 V, or − It was set to 3.00 V and each case was measured.

FIG. 23 shows the results of measuring initial characteristics of the Id-Vg characteristics for 36 transistors of Sample 3A, Sample 3B, and Sample 3C.

Sample 3A and sample 3B were found to have excellent electrical properties. On the other hand, Sample 3C became conductive regardless of the gate potential. It can be considered that the sample 3C has a high oxygen barrier property of the insulator 250, so that the supply of oxygen to the channel portion is cut off, resulting in insufficient oxygenation.

Next, cross sections of Sample 3A, Sample 3B, and Sample 3C were observed. FIG. 25 is a bright-field image obtained by a scanning transmission electron microscope (STEM) at the position indicated by D1-D2 in FIG. 1A in Samples 3A to 3C. Note that FIG. 25A is a sample 3A, FIG. 25B is a sample 3B, and FIG. 25C is a cross-section of the sample 3C. Since the sample 3A and the sample 3B have low oxygen barrier properties, the side surfaces of the SD electrode are oxidized. However, since the sample 3C has high oxygen barrier properties, it can be confirmed that the side surfaces of the SD electrodes are not oxidized. Moreover, crystallinity can be confirmed only in the material 3C.

FIG. 25A clearly shows the interface between the insulator 250 and the oxide 230c in the sample 3A. Further, from FIG. 25B, in the sample 3B, the interface between the insulator 250 and the oxide 230c was observed in a state that was less clear than in the sample 3A. From FIG. 25C, in the sample 3C, part of the insulator 250 is crystallized, and the interface between the oxide 230 and the insulator 252 and the interface between the insulator 250 and the insulator 252 can be clearly observed. There wasn't.

In addition, in order to examine the reliability of the transistor, a GBT (Gate Bias Temperature) stress test was performed on one transistor in the sample 3A. The GBT stress test is a kind of reliability test and can evaluate a change in characteristics of a transistor caused by long-term use.

In the GBT stress test, the substrate on which the transistor is formed is maintained at a constant temperature, the source potential and the drain potential of the transistor are set to the same potential, and the first gate potential is set to a potential different from the source potential and the drain potential. Give time.

Note that a case where the first gate potential of the transistor is higher than the source potential and the drain potential of the transistor is defined as plus (+) stress (+ GBT). Further, a negative (−) stress was defined as a case where the gate potential of the transistor was lower than the source potential and drain potential of the transistor (−GBT).

In addition, one of the first gate potential, the second gate potential, and the source potential or the drain potential is set to the same potential, and the other of the source potential or the drain potential is the first gate potential, the second gate potential, and the source potential. A stress test in which a potential higher than one of the potential and the drain potential is applied for a certain period of time is referred to as a + DBT (+ Drain Bias Temperature) stress test. Further, the first gate potential, the source potential, and the drain potential are set to the same potential, and the first gate potential, the source potential, and the drain potential that are lower than the same potential are applied to the second gate potential for a certain period of time. The stress test is a -BGBT (-BackGate Bias Temperature) stress test.

In this embodiment, as the + GBT stress test, the first gate potential Vg = + 3.63 V, the drain potential Vd = 0 V, the source potential Vs = 0 V, and the second gate potential Vbg = 0 V at the sample temperature = 150 ° C. Set to. As the -GBT stress test, the first gate potential Vg = -3.63 V, the drain potential Vd = 0 V, the source potential Vs = 0 V, and the second back gate potential Vbg = 0 V at the sample temperature = 150 ° C. Set to.

Further, as the + DBT stress test, the drain potential Vd = + 3.63 V, the first gate potential Vd = 0 V, the source potential Vs = 0 V, and the second gate potential Vbg = 0 at the sample temperature = 150 ° C. . Further, as the -BGBT stress test, the second gate potential Vbg = -5 V, the drain potential Vd = 0 V, the source potential Vs = 0 V, and the first gate potential Vbg = 0 V at the sample temperature = 150 ° C. .

As an index of the amount of change in the electrical characteristics of the transistor, a change with time (hereinafter also referred to as ΔVsh) of the threshold voltage (hereinafter also referred to as Vsh) of the transistor was used. Vsh is defined as the value of Vg when Id = 1.0 × 10 ⁻¹² [A] in the Id−Vg characteristic. Here, ΔVsh is, for example, that Vsh at the start of stress is +0.50 V, and Vsh at the time of stress 100 sec is −0.55 V, ΔVsh at the time of stress 100 sec is −1.05 V Become.

FIG. 24 shows the test result of Sample 3A in the GBT stress test. In FIG. 24, the left axis indicates the amount of change in threshold voltage (ΔVsh) of the transistor.

From the results shown in FIG. 24, Sample 1A had a threshold voltage change amount (ΔVsh) within ± 0.03 V in each BT test. Therefore, it was found that Sample 3A has high reliability.

Here, in the previous embodiment, it is considered that a film having a lower density or lower crystallinity is more likely to diffuse oxygen. For example, a hafnium oxide film with a density of 7.0 g / cm ³ or more and 9.0 g / cm ³ or less, preferably a density of 8.0 g / cm ³ or more and 8.5 g / cm ³ or less can diffuse oxygen. Confirmed.

In the previous embodiment, it has been found that the hafnium oxide film formed by the ALD method has a high flatness when the film forming temperature is lowered. For example, a hafnium oxide film formed by the ALD method has a density of 7.0 g / cm ³ or more and 9.0 g / cm ³ or less and a root mean square roughness (RMS) when the film forming temperature is less than 300 ° C. It has been confirmed that it is 0.5 nm or less in the measurement range of 1 μm × 1 μm, or 1.0 nm or less in the measurement range of 10 μm × 10 μm.

As described above, by using a film that easily diffuses oxygen as the insulator 250 that functions as a gate insulating film, excess oxygen added when the insulator 282 is formed is interposed through the insulator 280 and the insulator 252. Thus, it is estimated that it has diffused into the insulator 250. In addition, excess oxygen supplied to the insulator 250 compensates for oxygen vacancies formed at the interface between the insulator 250 and the oxide 230, thereby suppressing fluctuations in the electrical characteristics of the transistor 200 and stabilizing electricity. It is considered that it has characteristics and improved reliability.

Further, by using a highly flat film as the insulator 250 functioning as a gate insulating film, interface characteristics between the insulator 250 and the oxide 230 are improved and generation of oxygen vacancies is suppressed; It is considered that the fluctuation of characteristics is suppressed, the electric characteristics are stable, and the reliability is improved.

From the above, it was confirmed that the transistor using one embodiment of the present invention was a semiconductor device including a transistor with excellent reliability. Further, it was found that a transistor using one embodiment of the present invention has favorable electrical characteristics and small variation.

This embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.

100 capacitive element 101 capacitive element 110 conductor 112 conductor 120 conductor 122 barrier layer 130 insulator 150 insulator 200 transistor 201 transistor 205 conductor 205a conductor 205A conductor film 205b conductor 205B conductor film 210 insulator 212 insulator 214 Insulator 216 insulator 218 conductor 220 insulator 222 insulator 224 insulator 230 oxide 230a oxide 230A oxide film 230b oxide 230B oxide film 230c oxide 230C oxide film 240 conductor 240a conductor 240A conductor 240A conductor 240b conductor 240B Conductive film 245 Barrier layer 245a Barrier layer 245A Barrier film 245b Barrier layer 245B Barrier film 246 Conductor 248 Conductor 250 Insulator 250a Insulator 250A Insulating film 252 Insulator 252A Insulating film 60 conductor 260a conductor 260A conductive film 260b conductor 260B conductive film 260c conductor 260C conductive film 270 barrier layer 270A barrier film 272 insulator 274 insulator 280 insulator 282 insulator 286 insulator 290a hard mask 290A film 290b hard mask 290B film 300 transistor 311 substrate 313 semiconductor region 314a low resistance region 314b low resistance region 315 insulator 316 conductor 320 insulator 322 insulator 324 insulator 326 insulator 328 conductor 330 conductor 340 transistor 345 transistor 350 insulator 352 insulation Body 354 insulator 356 conductor 360 insulator 362 insulator 364 insulator 366 conductor 370 insulator 372 insulator 374 insulator 376 conductor 380 insulator 382 insulator 384 insulation Body 386 conductor 405 conductor 405a conductor 405b conductor 430c oxide 431a oxide 431b oxide 432a oxide 432b oxide 440 conductor 440a conductor 440b conductor 441a conductor 441b conductor 445 barrier layer 445a barrier layer 445b Barrier layer 450 Insulator 460 Conductor 460a Conductor 460b Conductor 470 Barrier layer 500 Structure 520A Insulating film 711 Substrate 712 Circuit region 713 Separation region 714 Separation line 715 Chip 750 Electronic component 752 Printed circuit board 754 Mounting substrate 755 Lead 2910 Information terminal 2911 Housing 2912 Display unit 2913 Camera 2914 Speaker unit 2915 Operation switch 2916 External connection unit 2917 Microphone 2920 Notebook personal computer 2921 Housing 2922 Display 2923 Keyboard 2924 Pointing device 2940 Video camera 2941 Housing 2942 Housing 2943 Display unit 2944 Operation switch 2945 Lens 2946 Connection unit 2950 Information terminal 2951 Housing 2952 Display unit 2960 Information terminal 2961 Housing 2962 Display unit 2963 Band 2964 Buckle 2965 Operation switch 2966 Input / output terminal 2967 Icon 2980 Car 2981 Car body 2982 Wheel 2983 Dashboard 2984 Light 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3006 Wiring 3007 Wiring 3008 Wiring 3009 Wiring 3010 Wiring

Claims (8)

A gate electrode, a source electrode, a drain electrode, an oxide semiconductor having a channel formation region, and a gate insulator;
The gate insulator comprises a metal oxide;
The metal oxide has a density of 7.0 g / cm ³ or more and 9.0 g / cm ³ or less. In claim 1,
The metal oxide has a density of 8.0 g / cm ³ or more and 8.5 g / cm ³ or less. A gate electrode, a source electrode, a drain electrode, an oxide semiconductor having a channel formation region, and a gate insulator;
The gate insulator comprises a metal oxide;
The metal oxide has a root mean square roughness (RMS) of 0.5 nm or less in a measurement range of 1 μm × 1 μm. A gate electrode, a source electrode, a drain electrode, an oxide semiconductor having a channel formation region, and a gate insulator;
The gate insulator comprises a metal oxide;
The metal oxide has a root mean square roughness (RMS) of 1.0 nm or less in a measurement range of 10 μm × 10 μm. In any one of Claims 1 thru | or 4,
The insulator has a stacked structure of the metal oxide and silicon oxide,
The semiconductor device, wherein the metal oxide is provided in contact with the oxide semiconductor. In any one of Claims 1 thru | or 5,
The semiconductor device, wherein the metal oxide is hafnium oxide. In claim 6,
The semiconductor device is characterized in that the hafnium oxide is formed at a film formation temperature of 200 to 280 ° C. by an ALD method. In claim 7,
The oxide semiconductor has a stacked structure of a first oxide semiconductor and a second oxide semiconductor,
The semiconductor device, wherein the first oxide semiconductor and the second oxide semiconductor have the same atomic ratio or a nearby atomic ratio.