JP2018077583A - Electronic control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic control device capable of relatively easily realizing systematic fault correspondence of a control software for exerting a control function.SOLUTION: An abnormal state detection unit 16 of a monitoring microcomputer 14 detects an occurrence of an abnormal state transition to switch directly from the high speed stage (forth speed) to the low speed stage (first speed) on the basis of the detection signals of a high speed stage detection circuit 25 and a low speed stage detection circuit 26. Upon detecting such an abnormal state transition, the abnormal state detection unit 16 cuts off the control signal from a control microcomputer 11 and outputs a reset signal to the control microcomputer 11 to reset the control microcomputer 11.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic control device that controls a controlled object to one of a plurality of states corresponding to a combination of a plurality of control signals.

  As an electronic control device of the kind described above, for example, a vehicle electronic control device described in Patent Document 1 is known. This electronic control device for a vehicle is for automatically controlling the shift of a transmission, and includes a control microcomputer that forms the center of automatic shift control and a monitoring microcomputer for monitoring the control microcomputer. The monitoring microcomputer has a function of calculating the control shift speed by the same method as the control microcomputer. The monitoring microcomputer detects an abnormality of the control microcomputer when the calculated control shift speed does not coincide with the actual shift speed indicated by the control signal output from the control microcomputer to the transmission. When an abnormality of the control microcomputer is detected, the monitoring microcomputer outputs an initialization signal to the control microcomputer in order to initialize RAM data related to solenoid output in the control microcomputer.

  Further, the above-described vehicle electronic control device is provided with a watchdog monitoring circuit, and the control microcomputer outputs a watchdog pulse to the watchdog monitoring circuit. After receiving the initialization signal notification, the control microcomputer expands the range of RAM data to be initialized and stops the output of the watchdog pulse if the abnormal state continues even after a predetermined time has elapsed. . Then, the watchdog monitoring circuit outputs a reset signal to the control microcomputer.

Patent No. 4007038

  In recent years, ISO 26262, a functional safety standard for automobiles, has been established in order to ensure safety when electronically controlling automobiles. In this ISO 26262, each system is classified according to three parameters of danger level, occurrence frequency, controllability (difficulty of avoidance) from dangerous events (hazards) when a function of the electronically controlled system fails. Ranking using an index called (Automotive Safety Integrity Level). In ASIL, five ranks of QM (Quality Management), A, B, C, and D are defined in order from the lowest risk level. The system designer needs to determine which rank the system corresponds to and to implement safety measures according to the determined rank.

  For example, if a vehicle electronic control unit that electronically controls a system is ranked with an ASIL of “C” or higher, the vehicle electronic control unit is divided into three levels, and higher level operations are monitored at a lower level. It is required to adopt a configuration that does this. For example, the first level is responsible for the control function of the system. At the second level, the correct operation of the control function at the first level is checked based on the selected input / output signal. At the third level, the monitoring tests performed at the second level are performed. Specifically, for example, a RAM test, a ROM test, an operation inspection, and the like are performed.

  On the other hand, Part 6 of ISO 26262 defines a method for product development at the software level. When ASIL is ranked “D” or higher, for example, various software designs, independent parallel Software systematic failure handling such as redundancy is required as one of the design requirements (see Part 6 7.4.14 Error Detection).

  Here, for example, as the second level, the one that calculates the control target by the same method as the first level (control microcomputer), such as the vehicle electronic control device described in Patent Document 1 described above, is used. In other words, if the first level and the second level are configured by using the same software component, there is a concern about the influence of a systematic failure due to a specification error or a bug in the software component. . Therefore, in order to meet the requirements for systematic failure handling required by ISO 26262, it is necessary to fully verify the safety of software components specified at the first and second levels. There is a problem that enormous verification man-hours are required.

  The present invention has been made in view of the above points, and provides an electronic control device capable of relatively easily realizing systematic failure handling of control software for exerting a control function. With the goal.

In order to achieve the above-described object, an electronic control device (10) according to the present invention controls a controlled object to one of a plurality of states corresponding to a combination of a plurality of control signals,
A control microcomputer (11) that generates a plurality of control signals by executing control software in order to control the control target to a target state;
Monitor a plurality of control signals or a plurality of drive signals output to the control object in response to the plurality of control signals, and generate a state transition from the first state to the second state, which is predetermined as an abnormal state transition. An abnormality detection circuit (16, 25, 26) to detect, and
The abnormality detection circuit is configured to take a predetermined safety measure when detecting the occurrence of an abnormal state transition.

  As described above, the control target of the electronic control device according to the present invention is controlled to one of a plurality of states corresponding to a combination of a plurality of control signals. However, even if the control target can take multiple states, the control microcomputer will control if the control software is normal in consideration of preventing adverse effects such as overload and impact on the control target. The target is not directly switched from a specific state (first state) to another specific state (second state). The abnormality detection circuit detects the occurrence of such an abnormal state transition that cannot normally occur. When the occurrence of an abnormal state transition is detected, the abnormality detection circuit takes a predetermined safety measure.

  Therefore, even if there is a systematic failure in the control software in the control microcomputer and a control signal that causes an abnormal state transition is output, the abnormal state transition can be detected by the abnormality detection circuit, and the predetermined safety By taking measures, it is possible to reduce the adverse effects caused by the abnormal state transition. Further, since the abnormality detection circuit simply detects a state transition from the first state to the second state, the abnormality detection circuit can have a simple configuration.

  The reference numerals in the parentheses merely show an example of a correspondence relationship with a specific configuration in an embodiment described later in order to facilitate understanding of the present invention, and are intended to limit the scope of the present invention. Not intended.

  Further, the technical features described in the claims of the claims other than the features described above will become apparent from the description of embodiments and the accompanying drawings described later.

It is the block diagram which showed an example of the whole structure of the electronic controller which concerns on embodiment. It is a figure for demonstrating an example by which the gear stage of a transmission is controlled by the gear stage in any one of several gear speed according to the combination of solenoid drive current. It is a block diagram which shows an example of a circuit structure of a high-speed stage detection circuit. It is a timing chart for demonstrating the basic control content of the transmission by the automatic transmission control apparatus for vehicles. It is a flowchart which shows an example of the control processing of an abnormal transition detection program. It is a timing chart which shows operation of each part when abnormal state transition occurs in a transmission. It is a block diagram which shows the structure of the automatic transmission control apparatus for vehicles by a modification.

  Hereinafter, as an embodiment, an example in which the electronic control device of the present invention is embodied as a vehicle automatic shift control device for automatically controlling a shift of a vehicle transmission will be described with reference to the drawings. FIG. 1 is a block diagram illustrating an example of the overall configuration of the vehicle automatic transmission control device 10.

  First, the transmission will be briefly described. The output torque of the engine is transmitted to the transmission (transmission gear mechanism) via the torque converter, is shifted by a plurality of gears (such as planetary gears) of the transmission, and is transmitted to the drive wheels of the vehicle.

  The transmission is provided with a plurality of clutches and brakes which are friction engagement elements for switching between a plurality of shift speeds. And it is comprised so that each engagement / release of a clutch and a brake may be switched by driving the solenoids 31-34 shown in FIG. 1, and controlling hydraulic pressure. Therefore, the combination of gears for transmitting power is switched in accordance with the drive current to the solenoids 31 to 34, and the gear ratio is switched.

  The vehicle automatic shift control device 10 includes a control microcomputer 11, a monitoring microcomputer 14, output circuits 21 to 24, a high speed detection circuit 25, a low speed detection circuit 26, and the like.

  The control microcomputer 11 includes a shift control unit 12 and a shift monitoring unit 13. However, in practice, the control microcomputer 11 functions as the shift control unit 12 by executing a control program designed to perform automatic shift control and stored in advance in a storage device such as a ROM. The same applies to the shift monitoring unit 13. The control microcomputer 11 functions as the shift monitoring unit 13 by executing a shift monitoring program that is designed to monitor automatic shift control and stored in advance in a storage device. To do.

  The shift monitoring unit 13 takes in the control signal output from the shift control unit 12 and grasps the control target shift stage calculated by the shift control unit 12 based on the taken-in control signal.

  The control program and the monitoring program described above both input vehicle driving information (sensor detection signal) such as vehicle speed and accelerator opening, and calculate a target gear position based on the input vehicle driving information. It is. However, in the present embodiment, the target shift speed calculation method in the control program is different from the target shift speed calculation method in the monitoring program. As a result, it is possible to prevent the occurrence of an abnormality due to a common failure cause which is a concern when the same calculation method is used.

  For example, each calculation method can be made different by simplifying the target shift speed calculation process in the monitoring program as compared with the target shift speed calculation process in the control program. If the calculation method is simplified, the error due to the simplification should be taken into account when comparing the control target shift speed calculated by the control program and the monitoring target shift speed calculated by the monitoring program. Is preferred. That is, if the difference between the control target shift speed and the monitoring target shift speed is within the error, the shift monitoring section 13 determines that the shift control section 12 has normally calculated the control target shift speed. Just do it.

  On the other hand, if the difference between the control target shift speed and the monitoring target shift speed is greater than or equal to the error, the shift monitoring section 13 determines whether the shift control section 12 is abnormal. In this case, the shift monitoring unit 13 initializes RAM data used by the shift control unit 12 to calculate the control target shift stage, or resets the control microcomputer 11 itself, for example. Try to return to normal. However, when the abnormality continues, the shift monitoring unit 13 instructs the shift control unit 12 to stop outputting the control signal. In this case, the vehicle is in the retreat mode, and the transmission is fixed at a predetermined gear position.

  Although not shown, the control microcomputer 11 is not limited to the above-described automatic shift control, but includes engine control for controlling the operating state of the engine, motor control for controlling the driving of the driving motor in the case of a hybrid vehicle, and the like. May also be executed.

  The output circuits 21 to 24 output drive currents to the solenoids 31 to 34 as drive signals for driving the controlled object in accordance with control signals output from the shift control unit 12 of the control microcomputer 11.

  The control microcomputer 11 outputs either an ON signal (high level control signal) or an OFF signal (low level control signal) to each of the output circuits 21 to 24 as a control signal.

  The output circuits 21 to 24 have power transistors such as IGBTs that turn on and off the solenoid drive current according to the above-described on signal or off signal, and keep the power transistor off even when the on signal is output as a control signal. And a cut-off switch. The cut-off switch is configured to operate according to an output cut signal output from an abnormal transition detection unit 16 of the monitoring microcomputer 14 described later. Note that the power transistor may be turned on in response to the ON signal of the control signal, or the power transistor may be turned off in response to the OFF signal of the control signal.

  The transmission corresponds to a combination of a plurality of control signals output from the shift control unit 12, in other words, according to a combination of solenoid drive currents output from the output circuits 21 to 24. It is controlled to one of the gear positions. For example, in the example shown in FIG. 2, when the drive current is supplied to the solenoids 31 and 34 and the drive current is not supplied to the solenoids 32 and 33, the transmission gear stage is the first speed on the lowest speed side. When the drive current is supplied to the solenoids 31 and 33 and the drive current is not communicated to the solenoids 32 and 34, the transmission gear is in the second speed. When the drive current is supplied to the solenoids 31 and 32 and the drive current is not supplied to the solenoids 33 and 34, the transmission gear is in the third speed. When the drive current is supplied to the solenoids 32 and 33 and the drive current is not supplied to the solenoids 31 and 34, the transmission gear position is the fourth speed.

  The high-speed stage detection circuit 25 in FIG. 1 is based on the drive currents output from the output circuits 21 to 24 to the solenoids 31 to 34 so that the transmission is at the highest speed stage (fourth speed in the example of FIG. 2). Is detected. An example of the circuit configuration of the high-speed stage detection circuit 25 will be described with reference to FIG. However, the high speed stage detection circuit 25 may monitor the control signal output from the shift control unit 12 to each of the output circuits 21 to 24 and detect that the transmission is controlled to the high speed stage. .

  As shown in FIG. 3, the high-speed stage detection circuit 25 is configured as a hard logic circuit, and includes, for example, four comparators 41 to 44, two inverters 45 and 46, and one AND circuit 47. Is done. The four comparators 41 to 44 compare the solenoid voltage corresponding to the drive current output from the output circuits 21 to 24 with a predetermined reference voltage, and output a high level signal if the solenoid voltage is higher than the reference voltage. If the solenoid voltage does not reach the reference voltage, a low level signal is output.

  Regarding the reference voltage, for example, in the example shown in FIG. 2, the drive current to each of the solenoids 31 to 34 is 1 A or 0 A. In this case, the reference voltage is the solenoid voltage by the drive current of 0 A and the current of 1 A. It is set to a value that can distinguish the solenoid voltage due to the drive current.

  The two inverters 45 and 46 are inserted into the output line of the comparator 41 that compares the solenoid voltage of the solenoid 31 and the reference voltage, and the output line of the comparator 44 that compares the solenoid voltage of the solenoid 34 and the reference voltage, respectively. ing. The output lines of the comparators 41 to 44 are connected to the input terminal of the AND circuit 47.

  Therefore, the comparators 41 and 44 output a low level signal when the drive currents of the solenoids 31 and 34 are 0 A. However, since the inverters 45 and 46 are inserted in the output lines, the input terminals of the AND circuit 47 are not connected. A high level signal is input. The comparators 42 and 43 output high level signals when the drive currents of the solenoids 31 and 34 are 1 A, and these high level signals are input to the input terminal of the AND circuit 47 as they are. As a result, the AND circuit 47 of the high speed stage detection circuit 25 outputs a high speed stage detection signal (fourth speed detection signal) while the transmission gear stage is at the fourth speed.

  The low speed stage detection circuit 26 shown in FIG. 1 is based on the drive currents output from the output circuits 21 to 24 to the solenoids 31 to 34 so that the transmission is the lowest speed stage (first speed in the example of FIG. 2). Is detected. The low speed stage detection circuit 26 is also configured as a hard logic circuit, like the high speed stage detection circuit 25. Since it is clear from the description of the high speed stage detection circuit 25 described above, a detailed description of the circuit configuration of the low speed stage detection circuit 26 is omitted.

  The monitoring microcomputer 14 includes a monitoring unit 15 and an abnormal transition detection unit 16. However, in practice, the monitoring microcomputer 14 is designed to monitor whether the shift monitoring unit 13 in the control microcomputer 11 can normally operate, and executes a monitoring program stored in a storage device such as a ROM in advance. Therefore, it functions as the monitoring unit 15. The same applies to the abnormal transition detection unit 16, and the monitoring microcomputer 14 is designed to detect an abnormal state transition that switches directly from the high speed stage (fourth speed) to the low speed stage (first speed), and is stored in the storage device in advance. The abnormal transition detection unit 16 functions by executing the abnormal transition detection program.

  In order to check whether the shift monitoring unit 13 can operate normally, the monitoring unit 15 executes, for example, an arithmetic function check of an arithmetic processing unit that executes the shift monitoring program in the control microcomputer 11, The RAM and ROM used by the processing unit are tested.

  Next, with reference to the timing chart of FIG. 4, basic control contents of the transmission by the vehicle automatic transmission control device 10 will be described. The control microcomputer 11 of the vehicle automatic shift control device 10 determines a control target shift stage based on vehicle operation information such as the vehicle speed and the accelerator opening. And the control signal corresponding to the determined control target gear stage is output to each output circuit 21-24.

  As shown in the example of FIG. 4, the transmission gears are basically switched from the low-speed gear to the high-speed gear in the order of 1st speed → 2nd speed → 3rd speed → 4th speed. Or in order from the high-speed gear to the low-speed gear. At this time, the low speed stage detection circuit 26 outputs a low speed stage detection signal while the transmission gear stage is at the first speed. Further, the high speed stage detection circuit 25 outputs a high speed stage detection signal while the transmission speed stage is the fourth speed.

  Further, when the transmission gear stage is switched, the control microcomputer 11 maintains the gear stage after the switching for a certain minimum time. In this way, the control microcomputer 11 prevents abrupt switching of the gear position.

  Next, an example of the control process of the abnormal transition detection program that causes the monitoring microcomputer 14 to function as the abnormal transition detection unit 16 will be described with reference to the flowchart of FIG. Note that the control processing shown in the flowchart of FIG. 5 is repeatedly executed at a predetermined control cycle.

  First, in a first step S100, a high speed stage detection signal and a low speed stage detection signal are input from the high speed stage detection circuit 25 and the low speed stage detection circuit 26, respectively. In the subsequent step S110, it is determined whether or not the high speed detection signal has changed from on to off based on the input high speed detection signal and low speed detection signal. That is, it is determined whether or not the high-speed stage detection signal input in the previous control cycle is on, but the low-speed stage detection signal input in the current control cycle is off.

  When the transmission speed is switched from the fourth speed to another speed, it is determined in step S110 that the high speed detection signal has changed from on to off. In this case, the process proceeds to step S120. On the other hand, if it is determined in step S110 that the high-speed stage detection signal has not changed from on to off, the process proceeds to step S130.

  In step S120, a timer is started to measure the elapsed time from when the high-speed stage detection signal changes from on to off. Thereafter, the process proceeds to step S140. On the other hand, in step S130, it is determined whether the timer is counting. If it is determined in step S130 that the timer is counting, the process proceeds to step S140. If it is determined that the timer is not counting, the control process shown in the flowchart of FIG.

  The processes in steps S120 and S130 described above are for waiting for the time required for the gear change since a certain amount of time is required until the gear position of the transmission is switched from the high gear to another gear.

  In step S140, it is determined whether or not the low speed detection signal has changed from off to on in order to check whether or not the speed change destination is the low speed when the speed is changed. If it is determined in step S140 that the low speed detection signal has changed from OFF to ON, the process proceeds to step S150. On the other hand, if it is determined that the low speed stage detection signal has not changed from OFF to ON, the control processing shown in the flowchart of FIG.

  In step S150, it is determined whether the count time of the timer is within a predetermined time. This predetermined time is set so as to correspond to the time required for the transmission described above to shift. Accordingly, when a positive determination is made in the determination process of step S150, the new gear position is the low speed stage when the time required for the shift has elapsed, and the transmission speed stage is changed directly from the high speed stage to the low speed stage. It means that it has been switched.

  The direct shift from the high speed stage to the low speed stage corresponds to an abnormal state transition that cannot occur in normal transmission control. If a shift corresponding to such an abnormal state transition is left unattended, the drivability of the vehicle deteriorates and an excessive load may be applied to the transmission. Therefore, the process proceeds to step S160, and an output cut signal is output to each of the output circuits 21 to 24, and the control signal is shut off. Thus, as shown in the timing chart of FIG. 6, even if the control microcomputer 11 continues to output a control signal for shifting to a low speed (first speed), the control signal is output from the output circuits 21 to 24. Blocked.

  When the control signal is interrupted in the output circuits 21 to 24 or when the control signal is not input to the output circuits 21 to 24, the output circuits 21 to 24 drive the transmission gear stage to be fixed at the third speed. A signal is output to each solenoid 31-34.

  Further, the monitoring microcomputer 14 resets the control microcomputer 11 by outputting a reset signal to the control microcomputer 11 in step S170. Thereby, the control signal output from the control microcomputer 11 is turned off.

  In the present embodiment, since the control microcomputer 11 controls the engine, the driving motor and the like in addition to the transmission, when the above abnormal state transition occurs, a serious abnormality occurs in the control microcomputer 11. Therefore, after resetting, the mode is shifted to the evacuation travel mode. In the retreat travel mode, the control signal output from the control microcomputer 11 is kept off, and the state where the transmission gear position is fixed at the third speed is continued. Further, in the retreat travel mode, the control microcomputer 11 controls the engine and the travel motor in a state where the vehicle speed and torque are limited so as not to increase to a predetermined value or more. However, when the control microcomputer 11 performs only automatic shift control, the normal mode may be executed after the reset to attempt normal return of the control microcomputer 11.

  On the other hand, in the determination process of step S150, if it is determined that the count time of the timer is not within the predetermined time, the shift from the high speed stage to the low speed stage has not been made directly. Reset. The timer may be reset when it is determined that the speed change destination from the high speed stage is a speed stage other than the low speed stage.

  According to the vehicle automatic transmission control device 10 according to the present embodiment, the high-speed stage detection circuit 25 and the low-speed stage detection circuit 26 configured as hard logic circuits monitor the drive current supplied to the solenoids 31 to 34, It detects that the transmission has reached a predetermined high speed or low speed. For this reason, even if any abnormality occurs in the output port of the control microcomputer 11 or the output circuits 21 to 24, it is possible to detect with high accuracy that the transmission gear stage has actually become a high speed stage or a low speed stage. Can do. Therefore, it is possible to improve the monitoring level of the unintended shift corresponding to the abnormal state transition.

  Further, since the monitoring microcomputer 14 only inputs the high speed stage detection signal from the high speed stage detection circuit 25 and the low speed stage detection signal from the low speed stage detection circuit 26, the number of input ports of the monitoring microcomputer 14 is reduced. be able to.

  Furthermore, the abnormal transition detection unit 16 of the monitoring microcomputer 14 basically only determines a direct shift from the high speed stage to the low speed stage based on the high speed stage detection signal and the low speed stage detection signal. Judgment logic can be simplified. As a result, the processing load on the monitoring microcomputer 14 can be reduced, and abnormality monitoring can be realized even with an inexpensive microcomputer.

  In the shift control unit 12, when an abnormality having a slight influence occurs, the shift monitoring unit 13 returns to normal. Further, the shift monitoring unit 13 is monitored to operate normally by the monitoring unit 15 of the monitoring microcomputer 14. For this reason, the abnormal state transition to be detected by the above-described high-speed stage detection circuit 25, low-speed stage detection circuit 26, and abnormal transition detection unit 16 is a state transition that significantly affects the transmission subject to be controlled and the vehicle occupant. It can be limited. Therefore, it is possible to prevent the configuration for detecting the abnormal state transition from becoming excessively complicated.

  Further, in the vehicle automatic transmission control device 10 according to the present embodiment, the respective levels of the solenoid drive current detected by the high speed stage detection circuit 25 and the respective levels of the solenoid drive current detected by the low speed stage detection circuit 26 are determined. It is set to invert. Thereby, even if the solenoid drive level fluctuates due to the influence of noise or the like, it is possible to prevent erroneous detection of abnormal state transition.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  For example, in the above-described embodiment, the example in which the abnormal transition detection unit 16 is provided in the monitoring microcomputer 14 has been described. However, the abnormal transition detection unit 16 can also be configured by a hard logic circuit. In that case, the abnormal transition detection unit 16 includes a high-speed stage detection circuit 25 and a low-speed stage detection circuit 26, as shown in FIG. The semiconductor integrated circuit 27 may be integrally configured.

  Further, in the above-described embodiment, the case where the speed is changed from the fourth speed to the first speed as the speed change corresponding to the abnormal state transition has been described. However, a plurality of shifts corresponding to the abnormal state transition may be set, for example, when the transmission is configured to have more shift stages. For example, when the transmission gear stage is configured to be five speeds, a shift of 5th speed → 2nd speed, 5th speed → 1st speed, 4th speed → 1st speed may be detected as a shift corresponding to the abnormal state transition. .

  In the above-described embodiment, the example in which the electronic control device according to the present invention controls the shift of the transmission of the vehicle has been described. However, the control target of the electronic control device according to the present invention is not limited to the vehicle transmission. For example, if it is controlled in any of a plurality of states corresponding to a combination of a plurality of control signals, such as a robot having movable parts such as a plurality of joints, it becomes a control target of the electronic control device according to the present invention. obtain.

10: Automatic transmission control device for vehicle 11: Control microcomputer 12: Shift control unit 13: Shift monitoring unit 14: Monitoring microcomputer 15: Monitoring unit 16: Abnormal transition detection units 21 to 24: Output circuit 25: High speed stage detection circuit 26: Low speed detection circuit

Claims (12)

An electronic control device (10) for controlling a control target to any one of a plurality of states corresponding to a combination of a plurality of control signals,
A control microcomputer (11) that generates the plurality of control signals by executing control software in order to control the control target to a target state;
State transition from the first state to the second state, which is predetermined as an abnormal state transition, by monitoring the plurality of control signals or the plurality of drive signals output to the control target in response to the plurality of control signals An abnormality detection circuit (16, 25, 26) for detecting the occurrence of
The abnormality control circuit is an electronic control device configured to take a predetermined safety measure when detecting the occurrence of an abnormal state transition.   The electronic control apparatus according to claim 1, wherein the abnormality detection circuit blocks the plurality of control signals output from the control microcomputer as the predetermined safety measure.   The electronic control device according to claim 1, wherein the abnormality detection circuit outputs a reset signal to the control microcomputer as the predetermined safety measure. The abnormality detection circuit is
A first detection circuit (25) for outputting a first detection signal when detecting a combination of the plurality of drive signals in which the control target is in the first state;
A second detection circuit (26) for outputting a second detection signal when detecting a combination of the plurality of drive signals in which the control target is in the second state;
When the first detection signal is input from the first detection circuit, and the second detection signal is input from the second detection circuit following the first detection signal, the first detection signal is input. The electronic control device according to claim 1, further comprising: a detection unit (16) that detects occurrence of an abnormal state transition from a state to the second state.   The detection unit measures an elapsed time from the end of the first state when the first state ends and is switched to the next state, and before the elapsed time reaches a predetermined time, The electronic control device according to claim 4, wherein the occurrence of the abnormal state transition is detected when the state is switched to the second state.   The electronic control device according to claim 4, wherein the first detection circuit and the second detection circuit are configured as hard logic circuits.   The electronic control device according to claim 6, wherein the detection unit is also configured by a hard logic circuit, and is configured integrally as the first detection circuit, the second detection circuit, and a semiconductor integrated circuit (27).   The electronic control device according to claim 4, wherein the detection unit is configured by a monitoring microcomputer. The control microcomputer includes a control unit (12) that executes a control process for controlling the control target, and a first monitoring unit (13) that monitors whether the control unit is operating normally. And
The electronic control device according to claim 8, wherein the monitoring microcomputer includes a second monitoring unit (15) that further monitors whether the first monitoring unit is normally performing a monitoring operation. The control microcomputer outputs a control signal of a high level or a low level, respectively, as the plurality of control signals.
The drive signal is also switched to a high level or a low level according to the level of the control signal,
10. The plurality of drive signals in the first state and the plurality of drive signals in the second state are set so that the respective levels of the plurality of drive signals are inverted. The electronic control apparatus in any one. The object to be controlled is a transmission that is used in a vehicle and whose shift position is controlled in response to energization of a drive current to a plurality of solenoids,
The abnormality detection circuit sets a state at a predetermined high speed shift position as the first state, a state at a predetermined low speed shift position as the second state, and the predetermined high speed shift position. 11. The electronic control device according to claim 1, wherein the electronic control device detects that the switching to the predetermined low-speed shift position is performed as an abnormal state transition. When the abnormality detection circuit detects the occurrence of an abnormal state transition, the abnormality detection circuit blocks the plurality of control signals output from the control microcomputer;
The electronic control device according to claim 11, wherein when the plurality of control signals from the control microcomputer are interrupted, the speed change position is fixed at a predetermined position that enables the vehicle to be retracted.

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