JP2018074796A - Image processing device and power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing device and a power supply that can suppress occurrence of failure in a rush current prevention circuit due to heat generation of a field effect transistor.SOLUTION: An image forming device comprises a power supply 7. The power supply 7 comprises a rush current prevention circuit 8. The rush current prevention circuit 8 comprises a field effect transistor 81 and a drive stop unit 83. The field effect transistor 81 prevents a rush current. The drive stop unit 83 is connected to a gate of the field effect transistor 81, and stops driving of the field effect transistor 81 when temperature of the field effect transistor 81 is predetermined abnormal overheat temperature.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an image processing apparatus and a power supply apparatus including an inrush current prevention circuit.

  An inrush current prevention circuit may be provided in a power supply device of an image processing apparatus such as a printer. For example, an inrush current prevention circuit using a field effect transistor as a switching element or an inrush current prevention element is known (see, for example, Patent Documents 1 and 2).

JP 2000-224845 A JP 2004-129419 A

  By the way, in the field effect transistor, current flows between the source and the drain when the gate voltage is larger than the gate threshold voltage. In a field effect transistor, the smaller the difference between the gate voltage and the gate threshold voltage, the greater the channel resistance between the source and drain.

  On the other hand, in an inrush current prevention circuit using a field effect transistor, the gate voltage of the field effect transistor may be reduced when an input / output abnormality of a mounted component occurs. For this reason, in the inrush current prevention circuit, the field effect transistor generates heat due to the reduced gate voltage, and problems such as open defects and burnout may occur in the field effect transistor and its peripheral mounting components.

  An object of the present invention is to provide an image processing apparatus and a power supply apparatus that can suppress the occurrence of problems in an inrush current prevention circuit due to heat generation of a field effect transistor.

  An image processing apparatus according to one aspect of the present invention includes a power supply device. The power supply device has an inrush current prevention circuit. The inrush current prevention circuit includes a field effect transistor and a drive stop unit. The drive stop unit is connected to the gate of the field effect transistor and stops driving the field effect transistor when the temperature of the field effect transistor is a predetermined abnormal overheat temperature.

  A power supply device according to another aspect of the present invention includes an inrush current prevention circuit. The inrush current prevention circuit includes a field effect transistor and a drive stop unit. The drive stop unit is connected to the gate of the field effect transistor, and stops driving the field effect transistor when the temperature of the field effect transistor is a predetermined abnormal overheating temperature.

  According to the present invention, there are provided an image processing apparatus and a power supply apparatus capable of suppressing the occurrence of problems in an inrush current prevention circuit due to heat generation of a field effect transistor.

FIG. 1 is a cross-sectional view schematically showing an image forming apparatus according to the first embodiment of the present invention. 2 is a block diagram showing a system configuration of the image forming apparatus shown in FIG. FIG. 3 is a circuit diagram illustrating the power supply unit of the image forming apparatus together with the control unit. FIG. 4 is a flowchart illustrating an example of the FET monitoring process executed by the control unit of the image forming apparatus. FIG. 5 is a flowchart showing an example of the temperature monitoring process in the FET monitoring process shown in FIG. FIG. 6 is a flowchart showing an example of normal temperature processing in the temperature monitoring processing shown in FIG. FIG. 7 is a flowchart showing an example of warning processing in the temperature monitoring processing shown in FIG. FIG. 8 is a flowchart illustrating an example of image processing stop processing in the temperature monitoring processing illustrated in FIG. 5. FIG. 9 is a flowchart showing an example of a voltage monitoring process in the FET monitoring process shown in FIG. FIG. 10 is a flowchart illustrating an example of a normal voltage process in the voltage monitoring process illustrated in FIG. 9. FIG. 11 is a flowchart showing an example of warning processing in the voltage monitoring processing shown in FIG. FIG. 12 is a circuit diagram showing a power supply unit and a control unit in the second embodiment of the present invention. FIG. 13 is a flowchart showing an example of the FET monitoring process by the control unit shown in FIG. FIG. 14 is a circuit diagram showing a power supply unit and a control unit in the third embodiment of the present invention. FIG. 15 is a flowchart showing an example of the FET monitoring process by the control unit shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings for understanding of the present invention. The following embodiment is an example embodying the present invention, and does not limit the technical scope of the present invention.

[First Embodiment]
First, the configuration of the image forming apparatus 10 according to the first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIGS. 1 and 2, the image forming apparatus 10 includes an ADF 1, an image reading unit 2, an image forming unit 3, a paper feeding unit 4, a control unit 5, an operation display unit 6, and a power supply device 7. The image forming apparatus 10 is a multifunction machine having a plurality of functions such as a facsimile function and a copy function, as well as a scan function for reading image data from a document and a print function for forming an image based on the image data. Here, the image forming apparatus 10 is an example of an image processing apparatus according to the present invention. The present invention can also be applied to image processing apparatuses such as a scanner apparatus, a printer apparatus, a facsimile apparatus, and a copier.

  The ADF 1 is an automatic document conveyance device that includes a document setting unit, a plurality of conveyance rollers, a document pressing unit, and a paper discharge unit, and conveys a document read by the image reading unit 2. The image reading unit 2 includes a document table, a light source, a plurality of mirrors, an optical lens, and a CCD (Charge Coupled Device), and can read image data from the document.

  The image forming unit 3 can execute an image forming process for forming an image by an electrophotographic method based on image data read by the image reading unit 2 or image data input from an information processing apparatus such as an external personal computer. It is. Specifically, as shown in FIG. 1, the image forming unit 3 includes a photosensitive drum 31, a charger 32, an optical scanning unit 33, a developing unit 34, a transfer roller 35, a cleaning device 36, a fixing unit 37, and a discharge unit. A paper tray 38 is provided.

  The paper feed unit 4 includes a paper feed cassette and a plurality of transport rollers, and supplies sheets stored in the paper feed cassette to the image forming unit 3. The sheets are paper, coated paper, postcards, envelopes, OHP sheets, and the like.

  In the image forming unit 3, an image is formed on the sheet supplied from the paper feeding unit 4 according to the following procedure, and the sheet after the image formation is discharged to a paper discharge tray 38.

  First, the surface of the photosensitive drum 31 is uniformly charged to a predetermined potential by the charger 32. Next, the light scanning unit 33 irradiates the surface of the photosensitive drum 31 with light based on the image data. Thereby, an electrostatic latent image corresponding to the image data is formed on the surface of the photosensitive drum 31. The electrostatic latent image on the photosensitive drum 31 is developed as a toner image by the developing device 34. The developing device 34 is supplied with toner from a toner container 34 </ b> A that can be attached to and detached from the image forming unit 3.

  Subsequently, the toner image formed on the photosensitive drum 31 is transferred onto the sheet by the transfer roller 35. Thereafter, the toner image transferred to the sheet is heated and fused by the fixing roller when the sheet passes between the fixing roller and the pressure roller of the fixing unit 37. The toner remaining on the surface of the photosensitive drum 31 is removed by the cleaning device 36.

  The control unit 5 includes control devices such as a CPU, ROM, RAM, and EEPROM (registered trademark) (not shown). The CPU is a processor that executes various arithmetic processes. The ROM is a non-volatile storage unit in which information such as a control program for causing the CPU to execute various processes is stored in advance. The RAM is a volatile storage unit, and the EEPROM is a non-volatile storage unit. The RAM and the EEPROM are used as temporary storage memories for various processes executed by the CPU. In the control unit 5, various control programs stored in advance in the ROM are executed by the CPU. As a result, the image forming apparatus 10 is comprehensively controlled by the control unit 5. The control unit 5 may be configured by an electronic circuit such as an integrated circuit, or may be an engine control unit provided separately from the main control unit that controls the image forming apparatus 10 in an integrated manner. Good. Details of the control unit 5 will be described later.

  The operation display unit 6 is a display unit such as a liquid crystal display that displays various types of information in response to control instructions from the control unit 5, and an operation key or touch panel that inputs various types of information to the control unit 5 in response to user operations. And so on.

  The display unit of the operation display unit 6 notifies that a field effect transistor 81 (see FIG. 3) described later is in a warning state, is in an abnormal state, cannot perform image processing, and the like. In addition, the display part of the operation display part 6 is an example of the alerting | reporting part of this invention. Another example of the notification unit of the present invention is a speaker (not shown). When the notification unit is a speaker, the field effect transistor 81 is in a warning temperature state, an abnormal state, or image processing can be performed by outputting a warning sound or a message determined in advance corresponding to the notification content. Notifying is notified.

  As shown in FIG. 3, the power supply device 7 includes a first power supply 71, a second power supply 72, a third power supply 73, an interlock switch 74, and an inrush current prevention circuit 8. The power supply device 7 can be detached independently from the image forming apparatus 10, for example.

  The first power supply 71 is an AC-DC converter that converts an AC voltage (for example, 100V) supplied from the external power supply 91 into a DC voltage of a predetermined first voltage V1 (for example, 24V) and outputs the same. The first power supply 71 supplies a first voltage V1 to the load 92, the third power supply 73, and an inrush current prevention circuit 8 described later. The load 92 is, for example, the ADF 1, the image reading unit 2, the image forming unit 3, the paper feeding unit 4, the control unit 5, and the operation display unit 6.

  The second power supply 72 is a DC power supply that supplies a second voltage V2 to an inrush current prevention circuit 8 described later. The second power source 72 is connected to the inrush current prevention circuit 8 and the load 93.

  The third power source 73 is a DC-DC converter that converts the DC voltage supplied from the first power source 71 into a predetermined third voltage V3 and outputs the third voltage V3. The third power supply 73 supplies the third voltage V3 to the gate of the field effect transistor 81 of the inrush current prevention circuit 8 described later. The third power source 73 can change and output the third voltage V3 within a specific range (for example, 0 V to 5 V) by a voltage designation signal from a third power supply control unit 52 of the control unit 5 described later.

  The interlock switch 74 is selected between an on state and an off state by a selection processing unit 51 of the control unit 5 described later, and puts the power supply unit 7 into a driving state or a stopped state according to the on state and the off state. On the other hand, the driving state or the stopping state of the inrush current prevention circuit 8 is selected according to the driving state or the stopping state of the power supply unit 7. The interlock switch 74 is turned on when a later-described field effect transistor 81 is in a normal state or a warning state, and puts the power supply unit 7 and the inrush current prevention circuit 8 into a driving state. The interlock switch 74 is an example of the circuit drive selection unit of the present invention. Further, the circuit drive selection unit of the present invention may be a switching unit provided separately from the interlock switch 74.

  The inrush current prevention circuit 8 includes a field effect transistor 81, a thermistor 82, and a switching element 83. The inrush current prevention circuit 8 prevents the current exceeding the rated current from being supplied to the first power source 71 and the interlock switch 74.

  The field effect transistor 81 is a P-channel MOSFET (metal oxide semiconductor field effect transistor). The field effect transistor 81 may be an N-channel MOSFET.

The field effect transistor 81 has a gate connected to the output line 731 of the third power supply 73, a source connected to the output line 711 of the first power supply 71, and a drain connected to the output line 721 of the second power supply 72. In the field effect transistor 81, when the gate voltage V _GS is equal to or higher than the gate threshold voltage, the source and the drain are brought into conduction to be in a driving state. On the other hand, when the gate voltage V _GS is less than the gate threshold voltage, the field effect transistor 81 is cut off between the source and the drain and is in a stopped state.

  The inrush current prevention circuit 8 can shunt the output current of the first power supply 71 to the load 93 side when the field effect transistor 81 is in a driving state. Thereby, the field effect transistor 81 prevents the inrush current from flowing into the first power supply 71 and the interlock switch 74, and the current exceeding the rated current is supplied to the first power supply 71 and the interlock switch 74. To prevent.

  The thermistor 82 is disposed in the vicinity of the field effect transistor 81 and measures the temperature T of the field effect transistor 81. The thermistor 82 is connected to the output line 711 of the first power supply 71 and the ground (GND). Therefore, the first voltage V1 is applied to the thermistor 82. The thermistor 82 is connected to the temperature detection unit 53 of the control unit 5, and outputs a voltage corresponding to the temperature T of the field effect transistor 81 to the temperature detection unit 53. The thermistor 82 is an example of the temperature sensor of the present invention. Another example of the temperature sensor of the present invention is a thermocouple.

  The switching element 83 selects a state where the third voltage V3 is applied to the gate of the field effect transistor 81 and a state where it is not applied by switching between the on state and the off state. That is, the switching element 83 selects the driving state and the driving stop state of the field effect transistor 81 by switching between the on state and the off state. The switching element 83 is turned on when the field effect transistor 81 is in a normal state or a warning state, and the field effect transistor 81 is driven. On the other hand, the switching element 83 is turned off when the field effect transistor 81 is in an abnormal state, and the field effect transistor 81 is brought into a drive stop state.

In the present embodiment, the switching element 83 is an N-channel MOSFET. In this case, the switching element 83 has a gate connected to the switching control unit 54, a source connected to the output line 731 of the third power supply 73, and a drain connected to the gate of the field effect transistor 81. When the gate voltage V _GS is equal to or higher than the gate threshold voltage, the switching element 83 is in an on state in which the source and the drain are conducted. As a result, the third voltage V <b> 3 is applied to the gate of the field effect transistor 81. On the other hand, when the gate voltage V _GS is less than the gate threshold voltage, the source and drain are cut off. As a result, the third voltage V3 is not applied to the gate of the field effect transistor 81.

  The switching element 83 is an example of a drive stop unit according to the present invention. Other examples of the drive stop unit of the present invention include other types of transistors that are generally used as switching elements, such as P-channel MOSFETs, PNP transistors, and NPN transistors.

The control unit 5 controls the power supply device 7. Specifically, the control unit 5 monitors the temperature T and the gate voltage V _GS of the field effect transistor 81, and controls the third power source 73, the interlock switch 74, and the switching element 83. The control unit 5 includes a selection processing unit 51, a third power supply control unit 52, a temperature detection unit 53, a switching control unit 54, a gate voltage detection unit 55, an abnormality determination unit 56, and a notification control unit 57.

  The selection processing unit 51 controls switching of the interlock switch 74 between an on state and an off state, and selects a state where the first voltage V1 is input to the inrush current prevention circuit 8 and a state where it is not input. Specifically, the selection processing unit 51 turns on the interlock switch 74 to input the first voltage V1 to the inrush current prevention circuit 8 and put the inrush current prevention circuit 8 in a driving state. On the other hand, the selection processing unit 51 turns off the interlock switch 74 so that the first voltage V1 is not input to the inrush current prevention circuit 8, and the inrush current prevention circuit 8 is stopped.

Third power supply control unit 52, in response to the temperature T and / or the gate voltage V _GS of the switching element 83, to adjust the third voltage V3 output from the third power source 73. In addition, the third power supply control unit 52 adjusts the gate voltage V _GS of the switching element 83 by adjusting the third voltage V3 output from the third power supply 73. For example, when the abnormality determining unit 56 determines that the temperature T of the field effect transistor 81 or the gate voltage V _GS is the warning temperature or the warning voltage, the third power supply control unit 52 sets the temperature T of the field effect transistor 81 to normal. The third voltage V3 is adjusted so that the temperature can be maintained. That is, in the field effect transistor 81, since the gate voltage _VGS is increased by decreasing the third voltage V3, the channel resistance is decreased. Thereby, the temperature rise in the field effect transistor 81 is suppressed.

The adjustment of the third voltage V3 by the third power supply control unit 52 is, for example, the difference between the temperature T detected by the temperature detection unit 53 or the gate voltage V _GS detected by the gate voltage detection unit 55 and the reference temperature or the reference voltage. This is done based on the value. The reference temperature or the reference voltage is, for example, the first threshold temperature Tth1 or the first threshold voltage Vth1. Then, the third power supply control unit 52 generates a voltage designation signal corresponding to a control amount determined according to the difference value, for example, and transmits it to the third power supply 73.

The third power source controller 52 outputs the third power source 73 output from the third power source 73 even when the abnormality determining unit 56 determines that the temperature T or the gate voltage V _GS of the field effect transistor 81 is a normal temperature or a normal voltage. The three voltage V3 may be adjusted. Thereby, the temperature T or the gate voltage V _GS of the field effect transistor 81 is controlled within the optimum range.

The voltage designation signal is also generated when the power supply device 7 is activated. The voltage designation signal at the time of starting up the power supply device 7 becomes the same every time of starting up. Therefore, the third voltage V3 at the time of starting up the power supply device 7 becomes the same every time of starting up. In the following, it referred to a third voltage V3 during startup and initial set value V3 _0.

  The temperature detection unit 53 detects the temperature T of the field effect transistor 81 based on the voltage output from the thermistor 82.

The switching control unit 54 controls switching of the switching element 83 between the on state and the off state. The switching control unit 54 adjusts the voltage applied to the gate of the switching element 83 and sets the switching element 83 to the on state by setting the gate voltage V _GS to be equal to or higher than the gate threshold voltage. As a result, the third voltage V3 is applied to the gate of the field effect transistor 81, and the field effect transistor 81 is turned on in which the source and the drain are conducted. On the other hand, the switching control unit 54 does not apply a voltage to the gate of the switching element 83 so that the gate voltage V _GS is less than the gate threshold voltage, and the switching element 83 is turned on. As a result, the third voltage V3 is not applied to the gate of the field effect transistor 81, and the field effect transistor 81 enters an off state in which the source and drain are blocked.

The gate voltage detector 55 detects the gate voltage V _GS of the field effect transistor 81. Here, when the gate voltage V _GS exceeds the gate threshold voltage, the source and the drain are electrically connected. On the other hand, the channel resistance between the source and drain of the field effect transistor 81 increases as the difference between the gate voltage V _GS and the gate threshold voltage _decreases, and tends to increase rapidly as the difference approaches zero. For this reason, if the difference is small, the temperature T of the field effect transistor 81 rises, which may cause an irrecoverable abnormality in the inrush current prevention circuit 8. Therefore, the gate voltage detection unit 55 detects the gate voltage V _GS of the field effect transistor 81 to grasp the temperature rise of the field effect transistor 81 and its possibility.

Here, in a P-channel MOSFET, a channel resistance value is reduced by applying a voltage smaller than the source by a predetermined value to the gate, and a current flows from the source to the drain. Therefore, when a P-channel MOSFET is used as the field effect transistor 81, the gate voltage V _GS is a value obtained by subtracting the third voltage V3 applied to the gate from the first voltage V1 applied to the source. Therefore, the gate voltage detector 55 detects the gate voltage V _GS as the difference (V1−V3) between the first voltage V1 and the third voltage V3.

  The abnormality determination unit 56 determines whether the temperature T of the field effect transistor 81 is a normal temperature, a warning temperature, or an abnormal overheat temperature. Specifically, the abnormality determination unit 56 compares the temperature T of the field effect transistor 81 detected by the temperature detection unit 53 with the first threshold temperature Tth1 and the second threshold temperature Tth2 to determine whether the temperature is normal. No, whether it is a warning temperature, and whether it is an abnormal overheating temperature.

  Here, the abnormal overheating temperature is determined in advance as a temperature that can cause a serious abnormality in the inrush current prevention circuit 8. Severe abnormality means that, for example, problems such as open defects and burnout occur in the field-effect transistor 81 and its surrounding mounting components. The normal temperature is determined in advance as a temperature at which the field effect transistor 81 and its surrounding mounting components can be driven without any problem. The normal temperature is determined by the specification of the field effect transistor 81, for example. The alert temperature is defined as a temperature between a normal temperature and an abnormal superheat temperature.

  The first threshold temperature Tth1 is set as the boundary temperature between the normal temperature and the warning temperature, and the second threshold temperature Tth2 is set as the boundary temperature between the warning temperature and the abnormal overheating temperature. Therefore, the abnormality determination unit 56 determines that the temperature T of the field effect transistor 81 is a normal temperature when the temperature detected by the temperature detection unit 53 is lower than the first threshold temperature Tth1. The abnormality determination unit 56 determines that the temperature T of the field effect transistor 81 is a warning temperature when the temperature detected by the temperature detection unit 53 is equal to or higher than the first threshold temperature Tth1 and lower than the second threshold temperature Tth2. The abnormality determination unit 56 determines that the temperature T of the field effect transistor 81 is an abnormal overheat temperature when the temperature detected by the temperature detection unit 53 is equal to or higher than the second threshold temperature Tth2.

The abnormality determination unit 56 determines whether the gate voltage V _GS of the field effect transistor 81 is a normal voltage, a warning voltage, or an abnormal low voltage. Specifically, the abnormality determination unit 56 compares the gate voltage V _GS of the field effect transistor 81 detected by the gate voltage detection unit 55 with the first threshold voltage Vth1 and the second threshold voltage Vth2, so that the normal voltage It is determined whether it is a warning voltage, an abnormally low voltage, or not.

  Here, the abnormally low voltage is determined in advance as a voltage at which the channel resistance between the source and the drain is large and the temperature T of the field effect transistor 81 can become an abnormal overheating temperature. The normal voltage is determined in advance as a voltage with which the channel resistance between the source and the drain is small and the field effect transistor 81 can be driven without any problem. The warning voltage is defined as the temperature between the normal voltage and the abnormal low voltage.

The first threshold voltage Vth1 is set as a boundary voltage between the normal voltage and the warning voltage, and the second threshold voltage Vth2 is set as a boundary voltage between the warning voltage and the abnormal low voltage. Therefore, the abnormality determination unit 56 determines that the gate voltage V _GS of the field effect transistor 81 is a normal voltage when the gate voltage V _GS of the field effect transistor 81 exceeds the first threshold voltage Vth1. The abnormality determining unit 56 determines that the gate voltage V _GS of the field effect transistor 81 is a warning voltage when the gate voltage V _GS of the field effect transistor 81 exceeds the second threshold voltage Vth2 and is equal to or lower than the first threshold voltage Vth1. . The abnormality determination unit 56 determines that the gate voltage V _GS of the field effect transistor 81 is an abnormally low voltage when the gate voltage V _GS of the field effect transistor 81 is equal to or lower than the second threshold voltage Vth2.

The abnormality determination unit 56 repeatedly determines abnormality of the temperature T of the field effect transistor 81 and the gate voltage V _GS every predetermined time. The predetermined time is not particularly limited, and may be determined in consideration of the frequency at which the temperature T of the field effect transistor 81 or the gate voltage V _GS is abnormal, the temperature rise characteristic of the field effect transistor 81, or the like.

The notification control unit 57 causes a notification unit such as a display unit of the operation display unit 6 to give a warning. For example, the notification control unit 57 displays a message that the temperature T of the field effect transistor 81 is a warning temperature, the gate voltage V _GS of the field effect transistor 81 is a warning voltage, and that image processing cannot be performed. 6 is displayed on the display unit. Further, the notification control unit 57 may cause a notification unit such as a speaker (not shown) or the like to output a warning sound or a message for notifying that the warning temperature or the warning voltage is reached.

In addition, the notification control unit 57 determines that the abnormality determination unit 56 determines that the temperature T of the field effect transistor 81 is the warning temperature, and / or determines that the gate voltage V _GS of the field effect transistor 81 is the warning voltage. Count the number of times Hereinafter, the number of times determined to be the warning temperature is referred to as a first count value N1, and the number of times determined to be a warning voltage is referred to as a second count value N2. The first count value N1 is reset when the abnormality determination unit 56 determines that the temperature T of the field effect transistor 81 is a normal temperature after a predetermined time has elapsed from a predetermined starting point. The second count value N2 is reset when the abnormality determination unit 56 determines that the gate voltage V _GS is a normal voltage after a predetermined time has elapsed from a predetermined starting point. For example, the notification control unit 57 starts from when the first count value N1 or the second count value N2 is initially determined to be the alert temperature or alert voltage until a predetermined time elapses. The number of times that the warning temperature or the warning voltage is determined within the specific period is counted.

  When the abnormality determination unit 56 determines that the alarm temperature or the alarm voltage is the alarm temperature, the notification control unit 57 sets a predetermined number of times that the first count value N1 or the second count value N2 is determined in advance within the specific period. On the condition that it exceeds, a notification unit such as a display unit of the operation display unit 6 is made to notify that it is in a warning state.

[FET monitoring process]
Hereinafter, an example of the procedure of the monitoring process (FET monitoring process) of the field effect transistor 81 executed by the control unit 5 in the image forming apparatus 10 will be described with reference to FIGS. Here, the FET monitoring process is a process of monitoring the temperature T and the gate voltage V _GS of the field effect transistor 81 and controlling the inrush current prevention circuit 8. The notations such as step S11 and step S12 represent the numbers of processing procedures (steps) executed by the control unit 5.

<Step S11>
First, in step S <b> 11 shown in FIG. 4, the control unit 5 determines whether or not the input of the first voltage V <b> 1 to the inrush current prevention circuit 8 is started. That is, the control unit 5 determines whether or not the driving of the inrush current prevention circuit 8 has been started. Specifically, the control unit 5 performs the determination in step S11 based on whether the selection processing unit 51 has switched the interlock switch 74 from the off state to the on state.

  The inrush current prevention circuit 8 starts to be driven when a main power supply (not shown) of the image forming apparatus 10 is turned on or when the power supply device 7 is restarted.

  Here, if the control part 5 judges that the input of the 1st voltage V1 was started to the inrush current prevention circuit 8 (step S11: Yes), it will transfer a process to step S12. On the other hand, when the control unit 5 determines that the input of the first voltage V1 to the inrush current prevention circuit 8 has not been started (step S11: No), the FET monitoring process ends.

<Step S12>
In step S <b> 12, the control unit 5 applies the third voltage V <b> 3 to the gate of the field effect transistor 81. Here, the process of step S <b> 12 is executed by turning on the switching element 83 by the switching control unit 54 of the control unit 5. Specifically, the switching control unit 54 applies a gate voltage V _GS equal to or higher than the gate threshold voltage to the switching element 83.

<Step S13>
In step S13, the control unit 5 adjusts the third voltage V3 output from the third power source 73 to the initial set value V3 _0. Here, when the temperature detected by the temperature detection unit 53 of the control unit 5 is a warning temperature, the third voltage V3 output from the third power supply control unit 52 is initialized in step S1551 (see FIG. 7) described later. It is adjusted to be lower than the value V3 _0. Therefore, when the recovery from the abnormality of the field effect transistor 81, the third voltage V3 output from the third power supply control unit 52 may be lower than the initial set value V3 _0. Therefore, by executing the processing in step S13, it is possible to a third voltage V3 at the start of driving of the rush current prevention circuit 8 always default value V3 _0. As a result, it is possible to prevent a situation in which the third voltage V3 is too low at the start of driving of the inrush current prevention circuit 8 due to recovery from the abnormality of the field effect transistor 81.

<Step S14>
In step S14, the control unit 5 determines whether or not a predetermined time has elapsed since the process of step S14 was started. Note that the starting point of whether or not the predetermined time in step S14 has elapsed may be the start time or end time of the temperature monitoring process in step S15 described later, or the start time or end time of the voltage monitoring process in step S16. Good.

  Here, if the control part 5 judges that predetermined time has passed since the process of step S14 was started (step S14: Yes), it will transfer a process to step S15. On the other hand, when determining that the predetermined time has not elapsed since the start of the process of step S14 (step S14: No), the control unit 5 determines that the predetermined time has elapsed since the start of the process of step S14. Until (step S14: Yes), the determination in step S14 is repeated.

<Step S15>
In step S15, the control unit 5 executes a temperature monitoring process. Here, the process of step S <b> 15 is executed by the temperature detection unit 53 and the abnormality determination unit 56 of the control unit 5. Details of the temperature monitoring process will be described later.

<Step S16>
In step S16, the control unit 5 performs a voltage monitoring process. Here, the process of step S <b> 16 is executed by the gate voltage detection unit 55 and the abnormality determination unit 56 of the control unit 5. The details of the voltage monitoring process will be described later. Further, the voltage monitoring process may be executed prior to the temperature monitoring process in step S15.

<Step S17>
In step S17, the control unit 5 determines whether or not the input of the first voltage V1 to the inrush current prevention circuit 8 is stopped. That is, the control unit 5 determines whether or not the driving of the inrush current prevention circuit 8 is stopped.

  The inrush current prevention circuit 8 is stopped when the main power source (not shown) of the image forming apparatus 10 is turned off or when an abnormality occurs in the inrush current prevention circuit 8 (step 1562 in FIG. 8). To be done.

  Here, if the control part 5 judges that the input of the 1st voltage V1 to the inrush current prevention circuit 8 is stopped (step S17: Yes), it will complete | finish FET monitoring processing. On the other hand, if the control part 5 judges that the input of the 1st voltage V1 to the inrush current prevention circuit 8 is not stopped (step S17: No), it will transfer a process to step S14, and predetermined time will pass. Under the condition (step S14: Yes), the temperature monitoring process of step S15 and the voltage monitoring process of step S16 are continuously executed.

[Temperature monitoring]
Next, details of the temperature monitoring process executed in step S15 of the FET monitoring process shown in FIG. 4 will be described with reference to FIGS.

<Step S151>
First, in step S151 shown in FIG. 5, the temperature detection unit 53 of the control unit 5 detects the temperature T of the field effect transistor 81 based on the voltage output from the thermistor. The detection of the temperature T of the field effect transistor 81 is repeatedly performed at predetermined intervals during the execution of the FET monitoring process.

<Step S152>
In step S152, the abnormality determination unit 56 of the control unit 5 determines whether or not the temperature detected by the temperature detection unit 53 is equal to or higher than the first threshold temperature Tth1. That is, the abnormality determination unit 56 determines whether the temperature T of the field effect transistor 81 is a normal temperature or higher than a warning temperature.

  Here, if the control part 5 judges that the temperature detected by the temperature detection part 53 is more than 1st threshold temperature Tth1 (step S152: Yes), it will transfer a process to step S154. On the other hand, if the control part 5 judges that the temperature detected by the temperature detection part 53 is less than 1st threshold temperature Tth1 (step S152: No), it will transfer a process to step S153.

<Step S153>
If the temperature detected by the temperature detection unit 53 is not equal to or higher than the first threshold temperature Tth1 (No at Step S152), the control unit 5 can determine that the temperature T of the field effect transistor 81 is normal. Therefore, in step S153, the control unit 5 executes a normal temperature process. Details of the normal temperature process will be described later.

<Step S154>
In step S154, the abnormality determination unit 56 of the control unit 5 determines whether or not the temperature detected by the temperature detection unit 53 is equal to or higher than the second threshold temperature Tth2. That is, the abnormality determination unit 56 determines whether the temperature T of the field effect transistor 81 is an abnormal overheat temperature or a warning temperature.

  Here, when it is determined that the temperature detected by the temperature detection unit 53 is equal to or higher than the second threshold temperature Tth2 (step S154: Yes), the control unit 5 shifts the process to step S156. On the other hand, if the control part 5 judges that the temperature detected in the temperature detection part 53 is less than 2nd threshold temperature Tth2 (step S154: No), it will transfer a process to step S155.

<Step S155>
When the temperature detected by the temperature detection unit 53 is equal to or higher than the first threshold temperature Tth1 (step S152: Yes) and not higher than the second threshold temperature Tth2 (step S154: No), the control unit 5 determines the temperature of the field effect transistor 81. It can be determined that T is the alert temperature. Therefore, in step S155, the control unit 5 executes a warning process. Details of the warning process will be described later.

<Step S156>
When the temperature detected by the temperature detector 53 is equal to or higher than the second threshold temperature Tth2 (step S154: Yes), the controller 5 determines that the temperature T of the field effect transistor 81 is an abnormal overheat temperature. it can. Therefore, in step S156, the control unit 5 executes an image processing stop process. The details of the image processing stop process will be described later.

(Processing at normal temperature)
Next, the details of the normal temperature processing executed in step 153 of FIG. 5 will be described with reference to FIG.

<Step S1530>
First, in step S1530 shown in FIG. 6, the abnormality determination unit 56 of the control unit 5 determines whether or not a predetermined time has elapsed since the first count value was reset last time. That is, the abnormality determination unit 56 determines whether or not the specific period for counting the number of times determined to be the alert temperature has elapsed.

  Here, if the control unit 5 determines that a predetermined time has elapsed since the first count value was reset last time (step S1530: Yes), the process proceeds to step S1531. On the other hand, when determining that the predetermined time has not elapsed since the first count value was reset last time (step S1530: No), the control unit 5 shifts the process to step S1532.

<Step S1531>
In step S1531, the abnormality determination unit 56 of the control unit 5 resets the first count value N1. The first count value N1 is determined by the abnormality determination unit 56 during a specific period from when the temperature T of the field effect transistor 81 is determined to be the normal temperature last time until it is determined to be the alert temperature this time. This corresponds to the number of times that the temperature T is determined to be the alert temperature. The first count value N1 is added in step 1553 of the warning process described later (see FIG. 7).

<Step S1532>
In step S1532, the control unit 5, the third voltage V3 to determine whether the initial set value V3 _0. This determination is performed the third voltage V3 which is calculated by subtracting the gate voltage V _GS detected in the gate voltage detection unit 55 from the first voltage V1 by the control unit 5 by comparing the initial set value V3 ₀ The

Here, the control unit 5, when the third voltage V3 is determined to be the initial set value V3 ₀ (Step S1532: Yes), then the process proceeds to step S1534. On the other hand, the control unit 5, when the third voltage V3 is determined not initial set value V3 ₀ (Step S1532: No), then the process proceeds to step S1533.

<Step S1533>
In step S1533, the control unit 5 adjusts the third voltage V3 to the initial set value V3 _0. The adjustment of the third voltage V3 in step S1533 is executed in the same procedure as in step S13 (see FIG. 4) described above.

<Step S1534>
In step S1534, the abnormality determination unit 56 of the control unit 5 determines whether or not a warning is being issued. Specifically, the abnormality determination unit 56 determines whether or not the warning is being performed based on whether or not a warning flag is set in step S1556 (see FIG. 7) or step S1666 (see FIG. 11) described later. .

  Here, if the control part 5 judges that it is during warning (step S1534: Yes), it will transfer a process to step S1535. On the other hand, if the control part 5 judges that it is not during warning (step S1534: No), it will complete | finish a normal temperature process and will transfer a process to step S16 (refer FIG. 4).

<Steps S1535 and S1536>
In steps S1535 and S1536, the abnormality determination unit 56 of the control unit 5 instructs the cancellation of the warning and clears the warning flag. When the process of step S1536 is completed, the control unit 5 ends the normal temperature process and shifts the process to step S16 (see FIG. 4).

(Warning process)
Next, details of the warning process executed in step 155 of FIG. 5 will be described with reference to FIG.

<Step S1551>
First, in step S1551 shown in FIG. 7, the third power supply control unit 52 of the control unit 5 adjusts the third voltage V3. Specifically, first, the third power supply control unit 52 determines a control amount according to a difference value between the temperature detected by the temperature detection unit 53 and a reference value such as the first threshold temperature Tth1. Next, the third power supply control unit 52 generates a voltage designation signal corresponding to the control amount based on the difference value. Then, the third power supply controller 52 adjusts the third voltage V <b> 3 output from the third power supply 73 by transmitting the voltage designation signal to the third power supply 73. The third voltage V3 is adjusted within a range between 0V and the initial set value V3 _0, is smaller as the difference value is larger. That is, when the temperature T of the field effect transistor 81 is a warning temperature, the third voltage V3 is adjusted to a voltage value that decreases the channel resistance of the field effect transistor 81 as the temperature T increases.

<Step S1552>
In step S1552, the abnormality determination unit 56 of the control unit 5 determines whether a warning is being issued. This determination is performed according to the same procedure as in step S1534 (see FIG. 6) of the normal temperature process.

  If the control unit 5 determines that the warning is being performed (step S1552: Yes), the warning process is terminated, and the process proceeds to step S16 (see FIG. 4). On the other hand, if the control part 5 judges that it is not during warning (step S1552: No), it will transfer a process to step S1553.

<Step S1553>
In step S1553, the abnormality determination unit 56 of the control unit 5 adds 1 to the first count value N1. That is, in step S1553, the abnormality determination unit 56 determines that the temperature is a warning temperature during a specific period from the time when the temperature T of the field effect transistor 81 is determined to be the previous normal temperature to the time when the current temperature is determined to be the warning temperature. Count the number of times.

<Step S1554>
In step S1554, the abnormality determination unit 56 determines whether or not the first count value N1 is a predetermined reference number N1α. That is, the abnormality determination unit 56 determines whether the temperature T of the field effect transistor 81 is a warning temperature is temporary or continuous.

  Here, when the control unit 5 determines that the first count value N1 is the reference number N1α (step S1554: Yes), the process proceeds to step S1555. On the other hand, when determining that the first count value N1 is not the reference number N1α (step S1554: No), the control unit 5 ends the warning process and shifts the process to step S16 (see FIG. 4).

<Step S1555>
In step S1555, the notification control unit 57 of the control unit 5 causes the notification unit such as the operation display unit 6 and a speaker (not shown) to give a warning that the temperature T of the field effect transistor 81 is the warning temperature. Thereby, it is possible to make the user recognize that it is in a warning state, and to take measures to prevent the temperature T of the field effect transistor 81 from becoming higher than the warning temperature.

<Step S1556>
In step S1556, the abnormality determination unit 56 sets a warning flag indicating that a warning is in progress. With this warning flag, the abnormality determination unit 56 can recognize that the warning is being performed. The warning flag is set in a register (not shown) of the control unit 5.

(Image processing stop processing)
Next, details of the image processing stop processing executed in step 156 of FIG. 5 will be described with reference to FIG.

<Step S1561>
First, in step S <b> 1561 shown in FIG. 8, the switching control unit 54 of the control unit 5 stops applying the third voltage V <b> 3 to the gate of the field effect transistor 81. That is, the switching control unit 54 stops the application of the third voltage V <b> 3 to the gate of the field effect transistor 81 by stopping the application of the voltage to the gate of the switching element 83. Thereby, the gate voltage V _GS of the field effect transistor 81 becomes smaller than the gate threshold voltage, and the driving of the field effect transistor 81 is stopped. As a result, the temperature rise of the field effect transistor 81 is suppressed.

<Step S1562>
In step S 1562, the selection processing unit 51 of the control unit 5 stops the input of the first voltage V 1 to the inrush current prevention circuit 8. That is, the switching control unit 54 stops driving the power supply unit 7 by turning off the interlock switch 74 and stops the input of the first voltage V1 to the inrush current prevention circuit 8. This also stops the driving of the inrush current prevention circuit 8. As a result, the driving of the field effect transistor 81 can be stopped more reliably, and the temperature rise of the field effect transistor 81 is more reliably suppressed.

<Step S1563>
In step S 1563, the notification control unit 57 of the control unit 5 instructs the notification unit such as the display unit of the operation display unit 6 to display a message for notifying that image processing cannot be performed. On the other hand, the notification unit such as the display unit of the operation display unit 6 that has received the instruction displays the message. Thereby, the image forming apparatus 10 notifies the user that the image processing cannot be performed. Further, the user who has confirmed the message can understand that image processing cannot be performed, and can take measures such as performing maintenance of the image forming apparatus 10. In addition to displaying the message on the display unit of the operation display unit 6, the control unit 5 displays a message indicating that the image forming apparatus 10 should be restarted and / or the image forming apparatus 10 should be maintained. May be.

[Voltage monitoring processing]
Next, details of the voltage monitoring process executed in step 16 of FIG. 4 will be described with reference to FIGS. 9 to 11.

<Step S161>
First, in step S <b> 161 shown in FIG. 9, the control unit 5 determines whether or not the first voltage V <b> 1 is input to the inrush current prevention circuit 8. Specifically, the control unit 5 determines whether or not the interlock switch 74 is in an on state by the switching control unit 54.

  Here, if the control part 5 judges that the 1st voltage V1 is input into the inrush current prevention circuit 8 (step S161: Yes), it will transfer a process to step S162. On the other hand, when the control unit 5 determines that the first voltage V1 is not input to the inrush current prevention circuit 8 (step S161: No), the voltage monitoring process is terminated, and the process proceeds to step S17 (see FIG. 4). Let That is, since the control unit 5 can determine that the driving of the inrush current prevention circuit 8 is stopped, the voltage monitoring process ends.

<Step S162>
In step S162, the gate voltage detection unit 55 of the control unit 5 detects the gate voltage V _GS. Specifically, the gate voltage detector 55 detects the gate voltage V _GS as the difference between the first voltage V1 and the third voltage V3 as described above. The detection of the gate voltage V _GS of the field effect transistor 81 is repeatedly performed every predetermined time during the execution of the FET monitoring process.

<Step S163>
In step S163, the abnormality determination unit 56 of the control unit 5 determines whether or not the gate voltage V _GS detected by the gate voltage detection unit 55 is equal to or lower than the first threshold voltage Vth1. That is, the abnormality determination unit 56 determines whether the gate voltage V _GS is a normal voltage or higher than a warning voltage.

Here, when the control unit 5 determines that the gate voltage V _GS is equal to or lower than the first threshold voltage Vth1 (step S163: Yes), the process proceeds to step S165. On the other hand, when determining that the gate voltage V _GS is not equal to or lower than the first threshold voltage Vth1 (step S163: No), the control unit 5 shifts the process to step S164.

<Step S164>
When the gate voltage V _GS is not equal to or lower than the first threshold voltage Vth1 (step S163: Yes), the control unit can determine that the gate voltage V _GS is normal. Therefore, in step S164, the control unit 5 executes a normal voltage process. Details of the normal voltage processing will be described later.

<Step S165>
In step S165, the abnormality determination unit 56 determines whether or not the gate voltage V _GS is equal to or lower than the second threshold voltage Vth2. That is, the gate voltage detection unit 55 determines whether the gate voltage V _GS is an abnormally low voltage or a warning voltage.

Here, when the control unit 5 determines that the gate voltage V _GS is equal to or lower than the second threshold voltage Vth2 (step S165: Yes), the process proceeds to step S167. On the other hand, when determining that the gate voltage V _GS is not equal to or lower than the second threshold voltage Vth2 (step S165: No), the control unit 5 shifts the process to step S166.

<Step S166>
Gate voltage V _GS is equal to or less than the first threshold voltage Vth1 (step S163: Yes), if not below the second threshold voltage Vth2 (step S165: No), the control unit 5 is the gate voltage V _GS of the FET 81 vigilance It can be determined that the voltage. Therefore, in step S166, the control unit 5 executes a warning process. Details of the warning process will be described later.

<Step S167>
When the gate voltage V _GS is equal to or lower than the second threshold voltage Vth2 (step S165: Yes), the control unit 5 can determine that the gate voltage V _GS of the field effect transistor 81 is an abnormally low voltage. Therefore, in step S167, the control unit 5 executes an image processing stop process. Note that the image processing stop processing in step S167 is the same as the image processing stop processing (see FIG. 8) of the temperature monitoring processing described above, and thus description thereof is omitted.

(Processing when the gate voltage is normal)
Next, details of the normal gate voltage process executed in step 164 of FIG. 9 will be described with reference to FIG.

<Step S1640>
First, in step S1640 shown in FIG. 10, the third power supply control unit 52 of the control unit 5 adjusts the third voltage V3 to the initial set value V3 _0. Step S1641 is executed according to the same procedure as step S13 (see FIG. 4) of the FET monitoring process.

<Step S1641>
In step S1641, the abnormality determination unit 56 of the control unit 5 determines whether or not a predetermined time has elapsed since the last reset of the second count value. That is, the abnormality determination unit 56 determines whether or not the specific period for counting the number of times determined to be the warning voltage has elapsed.

  Here, when the control unit 5 determines that a predetermined time has elapsed since the last reset of the second count value (step S1641: Yes), the control unit 5 shifts the processing to step S1642. On the other hand, when the control unit 5 determines that the predetermined time has not elapsed since the first count value was reset last time (step S1641: No), the process proceeds to step S1643.

<Step S1642>
In step S1642, the abnormality determination unit 56 of the control unit 5 resets the second count value N2. Second count value N2 is a certain period until the gate voltage V _GS is determined to be a time alert voltage from a decision of the previous normal voltage, the gate voltage V _GS is in alarm voltage by the abnormality determination unit 56 This corresponds to the number of times determined to be.

<Step S1643>
In step S1643, the abnormality determination unit 56 of the control unit 5 determines whether a warning is being issued. This determination is performed according to the same procedure as step S1534 (see FIG. 6) of the above-described normal temperature process.

  Here, if the control part 5 judges that it is during warning (step S1643: Yes), it will transfer a process to step S1644. On the other hand, when determining that the warning is not in progress (step S1643: No), the control unit 5 ends the normal gate voltage process and shifts the process to step S17 (see FIG. 4).

<Steps S1644 and S1645>
In steps S1644 and S1645, the abnormality determination unit 56 of the control unit 5 instructs the cancellation of the warning and clears the warning flag. When the process of step S1645 ends, the control unit 5 ends the normal gate voltage process and shifts the process to step S17 (see FIG. 4).

(Warning process)
Next, details of the warning process executed in step 166 of FIG. 9 will be described with reference to FIG.

<Step S1661>
First, in step S1661 shown in FIG. 11, the third power control unit 52 of the control unit 5 adjusts the third voltage V3. Specifically, first, the third power supply control unit 52 determines the control amount according to the difference value between the gate voltage V _GS detected by the gate voltage detection unit 55 and a reference value such as the first threshold voltage Vth1. . Next, the third power supply control unit 52 generates a voltage designation signal corresponding to the control amount based on the difference value. Then, the third power supply controller 52 adjusts the third voltage V <b> 3 output from the third power supply 73 by transmitting the voltage designation signal to the third power supply 73. The third voltage V3 is adjusted within a range between 0V and the initial set value V3 _0, is smaller as the absolute value of the difference value is large. That is, when the gate voltage V _GS of the field effect transistor 81 is a warning voltage, the voltage value of the third voltage V3 is adjusted so that the channel resistance of the field effect transistor 81 decreases as the gate voltage V _GS decreases. The

<Step S1662>
In step S1662, the abnormality determination unit 56 of the control unit 5 determines whether a warning is being issued. This determination is performed according to the same procedure as in step S1534 (see FIG. 6).

  If the control unit 5 determines that the warning is being performed (step S1662: YES), the control unit 5 ends the warning process and shifts the process to step S17 (see FIG. 4). On the other hand, if the control part 5 judges that it is not during warning (step S1662: No), it will transfer a process to step S1663.

<Step S1663>
In step S1663, the abnormality determination unit 56 of the control unit 5 adds 1 to the second count value N2. That is, in step S1663, the number of times that the gate voltage V _GS is determined to be the warning voltage during a specific period from the time when the gate voltage V _GS is determined to be the normal voltage to the time when the gate voltage V _GS is determined to be the current warning voltage is counted.

<Step S1664>
In step S1664, abnormality determination unit 56 determines whether or not second count value N2 is a predetermined reference number N2α. That is, in step S1664, it is determined whether the gate voltage V _GS is a warning voltage is temporary or continuous.

  Here, when the control unit 5 determines that the second count value N2 is the reference number N2α (step S1664: Yes), the control unit 5 shifts the processing to step S1665. On the other hand, when determining that the second count value N2 is not the reference number N2α (step S1664: No), the control unit 5 ends the warning process and shifts the process to step S17 (see FIG. 4).

<Step S1665>
In step S1665, the notification control unit 57 of the control unit 5 gives a warning that the gate voltage V _GS of the field effect transistor 81 is a warning voltage to the display unit of the operation display unit 6, a notification unit such as a speaker (not shown). Let it be done. Thereby, it is possible to make the user recognize that it is in a warning state, and to make the user take measures so that the gate voltage V _GS does not become lower than the warning voltage.

<Step S1666>
In step S1666, the abnormality determination unit 56 sets a warning flag indicating that a warning is in progress. With this warning flag, the abnormality determination unit 56 can recognize that the warning is being performed. The warning flag is set in a register (not shown) of the control unit 5.

As described above, in the image forming apparatus 10, the temperature T and the gate voltage V _GS of the field effect transistor 81 of the inrush current prevention circuit 8 are detected by the gate voltage detection unit 55 and the temperature detection unit 53 of the control unit 5 during execution of the FET monitoring process. Are repeatedly detected every predetermined time. Thereby, the state of the field effect transistor 81 can be monitored in real time. For the field effect transistor 81, the abnormality determination unit 56 of the control unit 5 determines whether the temperature T and the gate voltage V _GS of the field effect transistor 81 are abnormal under real-time monitoring. As a result, the abnormality in the temperature T or the gate voltage V _GS of the field effect transistor 81 in the inrush current prevention circuit 8 can be immediately detected from the time of occurrence of the abnormality.

In the inrush current prevention circuit 8, the switching element 83 is turned off by the switching control unit 54 of the control unit 5 when the field effect transistor 81 becomes an abnormal overheat temperature or an abnormal low voltage. On the other hand, when the switching element 83 is turned off, the field effect transistor 81 becomes in a stopped state because the gate voltage V _GS becomes less than the gate threshold voltage. As a result, the temperature rise of the field effect transistor 81 is suppressed, and problems such as open defects and burnout are suppressed in the field effect transistor 81 and its surrounding mounting components.

  In addition, in the inrush current prevention circuit 8, the interlock switch 74 is turned off by the selection processing unit 51 of the control unit 5 when the field effect transistor 81 becomes an abnormal overheat temperature or an abnormal low voltage. As a result, the input of the first voltage V1 to the inrush current prevention circuit 8 is stopped, and the driving of the inrush current prevention circuit 8 is stopped. Therefore, in the inrush current prevention circuit 8, the energization between the source and drain of the field effect transistor 81 is surely cut off, and the occurrence of problems in the field effect transistor 81 and its surrounding mounting parts is more reliably suppressed. The

In the image forming apparatus 10, the state T of the field effect transistor 81 in the inrush current prevention circuit 8 is monitored in real time, and the temperature T or the gate voltage V _GS of the field effect transistor 81 is warned by the abnormality determination unit 56 of the control unit 5. It is determined whether it is a voltage or a warning temperature. As a result, the field effect transistor 81 can be prevented from becoming an abnormal overheat temperature and an abnormal low voltage.

On the other hand, in the power supply device 7, a voltage is applied to the gate of the field effect transistor 81 in the inrush current prevention circuit 8 by a third power supply 73 that is a variable voltage power supply. Therefore, the gate voltage V _GS of the field effect transistor 81 can be adjusted by the output of the third power source 73. In the power supply device 7, the voltage applied to the gate of the field effect transistor 81 is reduced when the field effect transistor 81 is at the warning voltage or the warning temperature. Thereby, since the channel resistance of the field effect transistor 81 can be reduced, the field effect transistor 81 is prevented from becoming an abnormally low voltage and an abnormal overheating temperature.

[Second Embodiment]
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. 12 and 13. However, in the following description, a configuration common to the first embodiment in the second embodiment is denoted by the same reference numeral as the configuration of the first embodiment, and the detailed description thereof is omitted.

  As shown in FIG. 12, the image forming apparatus according to the second embodiment includes an inrush current prevention circuit 8A and a control unit 5A.

  The inrush current prevention circuit 8A includes a field effect transistor 81, a thermistor 82, a switching element 84A, and a comparator 85A.

  Field effect transistor 81 is a P-channel MOSFET. The field effect transistor 81 has a gate connected to the ground via the switching element 84 </ b> A, a source connected to the output line 711 of the first power supply 71, and a drain connected to the output line 721 of the second power supply 72.

  The thermistor 82 is disposed in the vicinity of the field effect transistor 81 and measures the temperature T of the field effect transistor 81. The thermistor 82 is connected to the output line 711 of the first power supply 71 and the ground. Therefore, the first voltage V1 is applied to the thermistor 82. The thermistor 82 is connected to the temperature detection unit 53 of the control unit 5A.

  The switching element 84A switches between an on state and an off state, thereby selecting a state where the first voltage V1 is applied to the gate of the field effect transistor 81 and a state where it is not applied. In the present embodiment, the switching element 84A is turned on when the temperature T of the field effect transistor 81 is normal, and is turned off when the temperature T of the field effect transistor 81 is an abnormal overheat temperature. Here, the switching element 84A is an N-channel MOSFET. The switching element 84A has a gate connected to the output side of the comparator 85A, a source connected to the ground, and a drain connected to the gate of the field effect transistor 81. The switching element 84A is switched between an on state and an off state by a control signal from a comparator 85A described later.

  The switching element 84A is an example of a drive stop unit according to the present invention. Other examples of the drive stop unit of the present invention include other types of transistors generally used as switching elements, such as P-channel MOSFETs, PNP transistors, and NPN transistors.

The comparator 85A outputs a HIGH level or LOW level control signal based on the comparison result between the voltage output from the thermistor 82 and the reference voltage. The comparator 85A outputs a HIGH level control signal when the voltage from the thermistor 82A is higher than the reference voltage, and outputs a LOW level control signal when the voltage from the thermistor 82A is lower than the reference voltage. . That is, the comparator 85A outputs a LOW level control signal when the temperature T of the field effect transistor 81 measured by the thermistor 82 is normal, and turns on the switching element 84A. On the other hand, when the temperature T of the field effect transistor 81 detected by the thermistor 82 is an abnormal overheat temperature, the comparator 85A outputs a HIGH level control signal to turn off the switching element 84A. In the field effect transistor 81, when the switching element 84A is turned off, the voltage applied to the gate and the source becomes V1. As a result, the gate voltage V _GS becomes 0 V, which is lower than the gate threshold voltage, so that the source and the drain are disconnected.

  The comparator 85A is an example of the switching unit of the present invention. Another example of the switching unit of the present invention is an operational amplifier.

  The control unit 5A includes a selection processing unit 51, a temperature detection unit 53, an abnormality determination unit 56A, and a notification control unit 57.

  The selection processing unit 51 controls switching of the interlock switch 74 between an on state and an off state. Then, the selection processing unit 51 turns on the interlock switch 74 when the temperature T of the field effect transistor 81 is normal. On the other hand, when the temperature T of the field effect transistor 81 is an abnormal overheat temperature, the selection processing unit 51 turns off the interlock switch 74 and stops the input of the first voltage V1 to the inrush current prevention circuit 8.

  The temperature detection unit 53 monitors the temperature T of the field effect transistor 81 based on the voltage output from the thermistor 82.

The abnormality determination unit 56A compares the temperature detected by the temperature detection unit 53 with the first threshold temperature Tth1 or the second threshold temperature Tth2, and determines the temperature abnormality of the field effect transistor 81. However, the abnormality determination unit 56A is different from the abnormality determination unit 56 of the first embodiment described above in that it does not determine the voltage abnormality of the gate voltage V _GS of the field effect transistor 81.

  Further, the abnormality determination unit 56A counts the number of times that the temperature T of the field effect transistor 81 is determined to be a warning temperature. Further, the abnormality determination unit 56A executes an image forming process because the instruction to warn the user that the temperature T of the field effect transistor 81 is a warning temperature and the temperature T of the field effect transistor 81 is an abnormal overheat temperature. An instruction for notifying that it cannot be performed is given to a notification unit such as the operation display unit 6 or a speaker (not shown).

  The notification control unit 57 causes the notification unit such as a display unit of the operation display unit 6 and a speaker (not shown) to issue a warning. For example, the notification control unit 57 causes the display unit of the operation display unit 6 to display a message indicating that the temperature T of the field effect transistor 81 is a warning temperature or that image processing cannot be performed. In addition, the notification control unit 57 may notify a speaker (not shown) that the temperature is the warning temperature and that image processing cannot be performed.

[FET monitoring process]
Hereinafter, an example of the procedure of the FET monitoring process executed by the control unit 5A will be described with reference to FIG. Here, the FET monitoring process is a process of monitoring only the temperature T of the field effect transistor 81 without executing the monitoring process of the gate voltage V _GS unlike the first embodiment. In the following, detailed description of the same steps as those in the FET monitoring process of the first embodiment described above will be omitted.

<Step S21>
First, in step S21 shown in FIG. 13, the control unit 5A determines whether or not the first voltage V1 is input to the inrush current prevention circuit 8A.

  Here, when the control unit 5A determines that the first voltage V1 has been input to the inrush current prevention circuit 8A (step S21: Yes), the process proceeds to step S22. On the other hand, when the control unit 5A determines that the first voltage V1 is not input to the inrush current prevention circuit 8 (step S21: No), the FET monitoring process is terminated.

<Step S22>
In step S22, the control unit 5A determines whether or not a predetermined time has elapsed since the process of step S22 was started. That is, a temperature monitoring process in step S23 described later is repeatedly performed every predetermined time.

  Here, when the control unit 5A determines that a predetermined time has elapsed since the start of the process of step S22 (step S22: Yes), the process proceeds to step S23. On the other hand, when it is determined that the predetermined time has not elapsed since the start of the process of step S22 (step S22: No), the control unit 5A determines that the predetermined time has elapsed since the start of the process of step S22. Until (step S22: Yes), the determination in step S22 is repeated.

<Step S23>
In step S23, the control unit 5A executes a temperature monitoring process. Here, the process of step S23 is performed by the temperature detection unit 53 and the abnormality determination unit 56A of the control unit 5 according to a procedure basically similar to the temperature monitoring process (see FIG. 5) of the first embodiment described above. . However, the process related to the third voltage V3 in the normal temperature process of step S153, the warning process of step S155, and the stop process of the image process of step S156 in the temperature monitoring process shown in FIG. 5 is not executed.

  Specifically, in the temperature monitoring process of step S23, steps S1531 and S1534 to S1536 are executed without executing steps S1532 and S1533 in the normal temperature process shown in FIG. 6 as the normal temperature process.

  Further, in the temperature monitoring process in step S23, as the warning process, steps S1552 to S1556 are executed without executing step S1551 in the warning process shown in FIG.

  Furthermore, in the temperature monitoring process in step S23, steps S1562 and S1563 are executed as the image processing stop process without executing step S1561 in the image processing stop process shown in FIG.

<Step S24>
In step S24, the control unit 5A determines whether or not the input of the first voltage V1 to the inrush current prevention circuit 8A is stopped. This determination is performed according to the same procedure as in step S17 of the FET monitoring process shown in FIG.

  If the control unit 5A determines that the input of the first voltage V1 to the inrush current prevention circuit 8A is stopped (step S24: Yes), the FET monitoring process is terminated. On the other hand, when the control unit 5A determines that the input of the first voltage V1 to the inrush current prevention circuit 8A has not been stopped (step S24: No), the control unit 5A shifts the process to step S22 and confirms that a predetermined time has elapsed. Under the condition (step S22: Yes), the temperature monitoring process of step S23 is continued.

  Thus, in the inrush current prevention circuit 8A, the voltage from the thermistor 82 is compared with the reference voltage in the comparator 85A. When the field effect transistor 81 is at an abnormal overheat temperature, the switching element 84A is turned off by the HIGH level control signal from the comparator 85A, and the driving of the field effect transistor 81 is stopped. Therefore, in the inrush current prevention circuit 8A, the temperature rise of the field effect transistor 81 is suppressed, and problems such as open defects and burnout are suppressed in the field effect transistor 81 and its peripheral mounting components.

  In addition, in the inrush current preventing circuit 8A, the interlock switch 74 is turned off by the selection processing unit 51 of the control unit 5A when the field effect transistor 81 reaches an abnormal overheat temperature. As a result, the input of the first voltage V1 to the inrush current prevention circuit 8A is stopped, so that the occurrence of a problem in the field effect transistor 81 and the like is more reliably suppressed.

[Third Embodiment]
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. 14 and 15. However, in the following description, a configuration common to the first embodiment in the third embodiment is denoted by the same reference numeral as that of the first embodiment, and the detailed description thereof is omitted.

  As shown in FIG. 14, the image forming apparatus according to the third embodiment includes an inrush current preventing circuit 8B and a control unit 5B.

  The inrush current prevention circuit 8B includes a field effect transistor 81, a thermal fuse 86B, and a fusing detector 87B.

The field effect transistor 81 is grounded via the temperature fuse 86 </ b> B, the source is connected to the output line 711 of the first power supply 71, and the drain is connected to the output line 721 of the second power supply 72. In this state, the gate voltage V _GS of the field effect transistor 81 is V1.

The thermal fuse 86B is disposed between the gate of the field effect transistor 81 and the ground. The thermal fuse 86B is blown when the inrush current prevention circuit 8B has an abnormal overheat temperature, and stops the driving of the field effect transistor 81. Specifically, when the thermal fuse 86B is blown, the first voltage V1 is applied to the gate of the field effect transistor 81. Therefore, the first voltage V <b> 1 is applied to the gate and source of the field effect transistor 81. As a result, the gate voltage V _GS of the field effect transistor 81 becomes 0 V, which is lower than the gate threshold voltage, and the driving of the field effect transistor 81 is stopped. The thermal fuse 86B is an example of a drive stop unit of the present invention.

  The fusing detector 87B detects that the thermal fuse 86B has blown. The fusing detector 87B has an NPN transistor 871B. The NPN transistor 871B has a collector grounded and an emitter connected to the output line 711 of the first voltage V1. The base of the NPN transistor 871B is grounded when the temperature fuse 86B is not blown, and is connected to the gate of the field effect transistor 81 when the temperature fuse 86B is blown.

  In the NPN transistor 871B, the emitter and the collector conduct when the temperature fuse 86B is not blown. On the other hand, in the NPN transistor 871B, the emitter and collector are disconnected when the temperature fuse 86B is blown. Therefore, the fusing detector 87B can detect the fusing of the thermal fuse 86B by cutting off the emitter and the collector due to the fusing of the thermal fuse 86B.

  Other examples of the fusing detector 87B include other types of transistors generally used as switching elements such as PNP transistors and MOSFETs.

  The control unit 5B includes a selection processing unit 51, a fusing determination processing unit 57B, and a notification control unit 57.

  The selection processing unit 51 turns on the interlock switch 74 when the temperature T of the field effect transistor 81 is normal. On the other hand, the selection processing unit 51 turns off the interlock switch 74 when it is determined by the blow determination processing unit 57B that the thermal fuse 86B is blown. As a result, the input of the first voltage V1 to the inrush current prevention circuit 8 is stopped.

  The fusing determination processing unit 57B is connected to the collector side of the NPN transistor 871B. The fusing determination processing unit 57B determines that the thermal fuse 86B has blown depending on whether or not a current flows between the emitter and collector of the fusing detection unit 87B. That is, the fusing determination processing unit 57B can detect that the temperature T of the field effect transistor 81 is an abnormal overheating temperature by determining fusing of the thermal fuse 86B.

  The notification control unit 57 causes the notification unit such as a display unit of the operation display unit 6 and a speaker (not shown) to issue a warning. For example, the notification control unit 57 displays a message indicating that maintenance of the inrush current prevention circuit 8B is necessary and that image processing cannot be performed. Further, the notification control unit 57 may notify a speaker (not shown) that maintenance of the inrush current prevention circuit 8B is necessary, that image processing cannot be performed, and the like.

[FET monitoring process]
Hereinafter, an example of the procedure of the FET monitoring process executed by the control unit 5B will be described with reference to FIG. Here, the FET monitoring process is a process of monitoring only the temperature T of the field effect transistor 81 without executing the voltage monitoring process of the gate voltage V _GS as in the second embodiment. However, the abnormality monitoring process of the third embodiment does not monitor that the temperature T of the field effect transistor 81 is a warning temperature, but only monitors that the temperature T is an abnormal overheating temperature. In the following, detailed description of the same steps as those in the FET monitoring process of the first embodiment and the second embodiment described above will be omitted.

<Step S31>
First, in step S31 shown in FIG. 15, the control unit 5B determines whether or not the first voltage V1 is input to the inrush current prevention circuit 8B.

  Here, when the control unit 5B determines that the first voltage V1 is input to the inrush current prevention circuit 8B (step S31: Yes), the process proceeds to step S32. On the other hand, when the control unit 5B determines that the first voltage V1 is not input to the inrush current prevention circuit 8B (step S31: No), the FET monitoring process ends.

<Step S32>
In step S32, the blow determination processing unit 57B of the control unit 5B determines whether or not the thermal fuse 86B is blown. Specifically, the fusing determination processing unit 57B detects whether or not the thermal fuse 86B is blown by detecting whether or not a current flows between the emitter and collector of the NPN transistor 871B. judge.

  Here, if the control part 5B judges that the thermal fuse 86B was blown (step S32: Yes), it will transfer a process to step S33. On the other hand, if the control part 5B judges that the thermal fuse 86B is not blown (step S32: No), it will transfer a process to step S35.

<Step S33>
When the temperature fuse 86B is blown (step S32: Yes), the control unit 5B can determine that the field effect transistor 81 has an abnormal overheat temperature. Therefore, in step S33, the selection processing unit 51 of the control unit 5B stops the input of the first voltage V1 to the inrush current prevention circuit 8B. This process is executed according to the same procedure as the process of step S1562 shown in FIG.

<Step S34>
In step S34, the notification control unit 57 of the control unit 5B instructs the display unit of the operation display unit 6 to display a message that notifies that image processing cannot be performed. This process is executed according to the same procedure as the process of step S1563 shown in FIG. Further, in the inrush current prevention circuit 8B, when the thermal fuse 86B is blown, the thermal fuse 86B needs to be replaced. Therefore, the notification control unit 57 may display a message prompting maintenance of the inrush current prevention circuit 8B on the display unit of the operation display unit 6.

<Step S35>
In step S35, the control unit 5B determines whether or not the input of the first voltage V1 to the inrush current prevention circuit 8B is stopped by turning off, restarting, forcibly ending the main power supply, or the like. The determination in step S35 is executed according to the same procedure as in step S17 of the FET monitoring process shown in FIG.

  Here, when the control unit 5B determines that the input of the first voltage V1 to the inrush current prevention circuit 8B has been stopped (step S35: Yes), the FET monitoring process ends. On the other hand, when determining that the input of the first voltage V1 to the inrush current prevention circuit 8B is not stopped (step S35: No), the control unit 5B shifts the process to step S32.

  Thus, in the inrush current prevention circuit 8B, the temperature fuse 86B is blown when the field effect transistor 81 is at an abnormal overheat temperature. Thereby, the driving of the field effect transistor 81 is stopped. Therefore, in the inrush current prevention circuit 8B, the temperature rise of the field effect transistor 81 is suppressed, and problems such as open defects and burnout are suppressed from occurring in the field effect transistor 81 and its surrounding mounting parts.

  In addition, in the inrush current prevention circuit 8B, when the fusing judgment processing unit 57B determines that the thermal fuse 86B is fusing, the interlock switch 74 (see FIG. 3) is turned off. As a result, the input of the first voltage V1 to the inrush current prevention circuit 8B is stopped, so that the occurrence of a problem in the field effect transistor 81 and the like is more reliably suppressed.

  Although the case where the field effect transistor 81 is used as an inrush current preventing element has been described in the present embodiment, the present invention can also be applied to the case where the field effect transistor 81 is used as a switching element.

DESCRIPTION OF SYMBOLS 10 Image forming apparatus 5,5A, 5B Control part 51 Selection process part 52 3rd power supply control part 53 Temperature detection part 54 Switching control part 55 Gate voltage detection part 56,56A Abnormality determination part 57 Notification control part 58B Fusing determination process part 6 Operation display unit 7 Power supply device 74 Interlock switch 8, 8A, 8B Inrush current prevention circuit 81 Field effect transistor 82 Thermistor 83 Switching element 84A Switching element 85A Comparator 86B Thermal fuse 87B Fusing detection part

Claims (9)

An image processing apparatus comprising a power supply device having an inrush current prevention circuit,
The inrush current prevention circuit is connected to a field effect transistor and a gate of the field effect transistor, and stops driving when the temperature of the field effect transistor is a predetermined abnormal overheat temperature. An image processing apparatus. The drive stop unit is a switching element that selects a drive state and a drive stop state of the field effect transistor by switching between an on state and an off state,
The inrush current prevention circuit includes: a temperature sensor that performs output according to a temperature of the field effect transistor; and a switching unit that switches between an on state and an off state of the switching element based on an output from the temperature sensor. Item 8. The image processing apparatus according to Item 1.   The switching unit outputs a control signal according to a result of comparing an output from the temperature sensor and a predetermined reference value to the switching element, and the switching element is turned on and off based on the control signal. The image processing apparatus according to claim 2, wherein The power supply device includes a circuit drive selection unit that selects a drive state and a drive stop state of the inrush current prevention circuit,
Based on the output from the temperature sensor, an abnormality determination unit that determines whether or not the temperature of the field effect transistor is the abnormal overheat temperature, and the temperature of the field effect transistor is set to the abnormal overheat temperature by the abnormality determination unit. 4. The image processing apparatus according to claim 2, further comprising: a control processing unit that causes the circuit drive selection unit to select a driving stop state of the inrush current prevention circuit when it is determined that . Based on the output from the temperature sensor, whether the temperature of the field effect transistor is the abnormal overheat temperature, a predetermined normal temperature, or a warning temperature between the normal temperature and the abnormal overheat temperature A control unit having an abnormality determination unit for performing the determination;
A notification unit for notifying that the temperature of the field effect transistor is the warning temperature;
When the abnormality determining unit determines that the temperature of the field effect transistor is the warning temperature, the control unit notifies the notification unit that the temperature of the field effect transistor is the warning temperature. The image processing apparatus according to claim 2, further comprising a notification control unit that causes the information to be transmitted.   The notification control unit counts the number of times that the temperature of the field effect transistor is determined to be the alert temperature, and the number of times that the temperature of the field effect transistor is determined to be the alert temperature within a predetermined period. The image processing apparatus according to claim 5, wherein when the number exceeds a predetermined number of times, the notification unit performs notification that the temperature of the field effect transistor is the warning temperature. The drive stop unit is a thermal fuse that stops driving the field effect transistor by fusing,
A notification unit for notifying that image processing cannot be performed;
A fusing determination processing unit that determines whether or not the thermal fuse is blown, and a notification that the image processing cannot be performed when the fusing determination processing unit determines that the thermal fuse is blown. The image processing apparatus according to claim 1, further comprising: a control unit having a notification control unit to be performed by the notification unit. The power supply device includes a circuit drive selection unit that selects a drive state and a drive stop state of the inrush current prevention circuit,
The control part which has a selection processing part which makes the circuit drive selection part select the drive stop state of the inrush current prevention circuit, when it judges with the thermal fuse having blown by the fusing judgment processing part. An image processing apparatus according to 1. A power supply device including an inrush current prevention circuit,
The inrush current prevention circuit is
A field effect transistor;
And a drive stop unit that is connected to a gate of the field effect transistor and stops driving the field effect transistor when the temperature of the field effect transistor is a predetermined abnormal overheating temperature.

Images