JP2018072860A - Analog output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable detecting abnormality of a voltage/current conversion resistance in an analog output circuit which outputs a current signal to a control target device after converting a voltage signal into the current signal by a voltage/current conversion circuit.SOLUTION: An analog output device includes: a digital/analog converter which converts a digital control instruction value into an analog voltage signal; a voltage/current conversion circuit which includes two or more resistance circuits connected in series, generates a control current signal by converting a control voltage value based on the voltage signal into a current value, and outputs the control current signal to a control target device; and a detection circuit which accepts, as an input, a partial pressure voltage signal indicating a partial voltage value divided by the resistor circuit connected in series in the voltage/current conversion circuit and changes its output as the voltage value of the partial pressure voltage signal changes.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an analog output device that outputs an analog control signal to a device to be controlled.

  An analog output device is used to output an analog control signal to a control target device such as a plant device (see Patent Document 1). For example, the analog output device receives a control instruction from the host controller, converts a signal included in the control instruction into an analog current signal by the voltage / current conversion circuit, and outputs the analog current signal to the control target device.

  This type of analog output device is required to be reliable, and the analog signal output device may be provided with a diagnostic function in order to detect an internal failure.

JP 2005-173848 A

  According to the technique described in Patent Document 1, a signal fed back from an analog output signal in an analog output device that converts a controlled voltage signal into a current signal by a voltage / current conversion resistor and outputs the current signal to a controlled device. Is controlled so as to match the voltage value of the analog signal based on the control instruction.

  Since the voltage value of the fed back signal is controlled to match the voltage value of the analog signal based on the control instruction, the fed back signal does not show an abnormal voltage value even if the voltage / current conversion resistor fails. There is a case. For this reason, a failure of the voltage / current conversion resistor may not be detected.

  An object of the present invention is to provide a technique that makes it possible to detect an abnormality in a voltage / current conversion resistor in an analog output circuit that converts a voltage signal into a current signal by a voltage / current conversion circuit and outputs the current signal to a control target device. That is.

  An analog output device according to an aspect of the present invention includes a digital / analog converter that converts a digital control instruction value into an analog voltage signal, and two or more resistor circuits connected in series, and controls based on the voltage signal A voltage / current conversion circuit that generates a control current signal obtained by converting a voltage value into a current value and outputs the control current signal to a control target device, and a divided voltage divided by the resistor circuit connected in series in the voltage / current conversion circuit And a detection circuit that receives a divided voltage signal indicating a value and changes its output when the voltage value of the divided voltage signal changes.

  According to the present invention, a voltage / current conversion resistor in an analog output circuit that converts a voltage signal into a current signal by a voltage / current conversion circuit and outputs the current signal to a controlled device is a series circuit of two or more resistance circuits, Since the voltage signal is monitored, the abnormality of the voltage / current conversion resistor can be detected.

1 is a circuit configuration diagram of an analog output device according to Embodiment 1. FIG. 4 is a graph showing input / output characteristics of a D / A converter 5 and an A / D converter 10. It is a flowchart which shows the process which the high-order control apparatus 2 performs. It is a table | surface which shows the relationship between the voltage value Vr of a divided voltage signal, a failure location, and a failure mode. 6 is a circuit configuration diagram of an analog output device according to Embodiment 2. FIG. 6 is a circuit configuration diagram of an analog output device according to Embodiment 3. FIG.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit configuration diagram of an analog output device according to a first embodiment. The analog output device 1 includes a control circuit 4, a digital / analog (D / A) converter 5, a voltage / current conversion circuit 6, a power supply circuit 7, and an analog / digital (A / D) converter 10. .

  The control circuit 4 is connected to the host controller 2 via the communication line 3. The control circuit 4 receives the control instruction signal from the host control device 2 via the communication line 3, analyzes the control instruction signal, and transmits the control instruction value obtained thereby through the signal line 11 to the D / A converter 5. Send to. Further, when the resistance circuit 9 fails, the voltage value Vr changes from the normal value, and the changed voltage value Vr is converted into a digital signal loaded with readback data by the A / D converter 10 and input to the control circuit 4. The control circuit 4 transmits read back data to the host control device 2 via the communication line 3. In this embodiment, as an example, the resistance values of the resistors Ra, Rb, Rc, and Rd are all equal, so that the normal voltage value Vr = Vf / 2.

  The D / A converter 5 converts the control instruction value into an analog voltage signal indicated by the voltage value Vi, and inputs the analog voltage signal to the voltage / current conversion circuit 6 through the signal line 12.

  The voltage / current conversion circuit 6 includes a resistance circuit 9, converts the voltage signal indicating the voltage value Vi into an analog current signal indicating the voltage value Vi = Vf by the resistance circuit 9, and controls the signal signal 14. It outputs to the plant equipment 8, which is the target equipment. At this time, the voltage / current conversion circuit 6 inputs the voltage value Vi and the voltage value Vf of the feedback signal to the operational amplifier, and operates so as to make the voltage value Vf coincide with the voltage value Vi.

  The output signal of the operational amplifier is input to the base of the transistor. The collector of the transistor is connected to the signal line 14 connected to the plant equipment 8, the emitter is connected to the resistor circuit 9, and the feedback signal of the voltage value Vf is fed back to the operational amplifier.

  The resistor circuit 9 has a configuration in which two resistor circuits are connected in series. One end is connected to the emitter of the transistor and the other end is grounded. A divided signal indicating a voltage value Vr obtained by dividing the voltage value Vf is input to the A / D converter 10 through the signal line 15 from the connection point of the two resistance circuits.

  The power supply circuit 7 provides a power supply for outputting the output signal from the analog output device 1 to the plant equipment 8.

  The A / D converter 10 converts the voltage value Vr of the analog signal on the signal line 15 into a digital value and sends it to the control circuit 4 through the signal line 16 as a detection signal indicating the presence or absence of abnormality.

  As described above, the analog output device 1 according to the present embodiment includes the D / A converter 5 that converts a digital control instruction value into an analog voltage signal, and two or more resistor circuits connected in series. A voltage / current conversion circuit 6 that generates a control current signal obtained by converting a control voltage value based on the voltage signal into a current value and outputs the control current signal to the plant equipment 8 and a resistor circuit 9 connected in series in the voltage / current conversion circuit 6 The A / D converter 10 is a detection circuit that receives a divided voltage signal indicating the divided divided voltage value as input and changes its output when the voltage value of the divided voltage signal changes. A voltage circuit is converted into a current signal by the voltage / current conversion circuit 6 and output to the plant equipment 8 to be controlled. The resistor circuit 9 serving as a voltage / current conversion resistor in the analog output circuit 1 is a series circuit of two or more resistance circuits. Since the divided voltage signal is monitored by the detection circuit (A / D converter 10), the abnormality of the resistance circuit 9 can be detected.

  The resistance circuit 9 of the voltage / current conversion circuit 6 includes four resistors Ra, Rb, Rc, and Rd. In the resistor circuit 9, a resistor circuit in which a resistor Ra and a resistor Rb are connected in parallel and a resistor circuit in which a resistor Rc and a resistor Rd are connected in parallel are connected in series. As an example, the resistors Ra, Rb, Rc, and Rd are all resistive elements having the same resistance value. The other end of the resistor circuit composed of resistors Ra and Rb is connected to the emitter of the transistor. The other end of the resistor circuit composed of the resistor Rc and the resistor Rd is grounded. The divided voltage Vr is input to the A / D converter 10 through the signal line 15 from the connection point of these two resistance circuits.

  The divided voltage Vr of the readback signal obtained by dividing the voltage value Vf by the resistor circuit 9 is Vr = Vf × (Ra + Rb) × Rc × Rd / ((Ra + Rb) × Rc × Rd + Ra × Rb × (Rc + Rd)). Become.

  When the resistance values of the resistors Ra, Rb, Rc, and Rd are all equal as in this embodiment, Vr = Vf / 2. The readback signal having the voltage value Vr is input to the A / D converter 10, and the A / D converter 10 converts the readback signal into a digital signal on which readback data indicating the voltage value Vr is mounted. The digital signal is transmitted from the A / D converter 10 to the control circuit 4. The control circuit 4 transmits readback data to the host controller 2 via the communication line 3, and the host controller 2 performs a readback diagnosis.

  As described above, the voltage / current conversion circuit 6 includes a resistor circuit in which a plurality of circuits in which a plurality of resistors are connected in parallel are connected in series. Therefore, even if any of the resistors Ra, Rb, Rc, and Rd becomes an abnormality of short circuit or open, the divided voltage value Vr changes from the normal value, and the abnormality can be detected.

  The voltage / current conversion circuit 6 includes, as an example, the resistor circuit in which two circuits in which two resistors having the same resistance value are connected in parallel are connected in series. Even if the abnormality occurs, the divided voltage value Vr changes, so that the detection failure of the abnormality can be reduced.

  In the voltage / current conversion circuit 6, the resistance values of all four resistors Ra, Rb, Rc, and Rd are equal. Therefore, when any one of the resistors becomes abnormal, the divided voltage becomes 2/3 times or 4/3 times normal, and when it becomes short-circuited, the divided voltage becomes twice normal or Since it becomes 0 V, it is easy to determine the change in the divided voltage, and an abnormality can be easily detected. It is also possible to estimate which resistance is abnormal.

  FIG. 2 is a graph showing input / output characteristics of the D / A converter 5 and the A / D converter 10.

  Here, as an example, the D / A converter 5 has a scale in which the maximum value of the voltage value Vf of the feedback signal that is an analog signal corresponds to digital data having a value of 4000 digits. The A / D converter 10 also has a scale corresponding to the maximum value of the voltage value Vf and digital data having a value of 4000 digits.

  As described above, since the resistor circuit 9 has a configuration in which two resistor circuits having the same resistance value are connected in series, the voltage value Vr of the readback signal is in the range of 0 to Vf / 2 [V] if there is no abnormality in the resistor circuit 9. It becomes the value in. However, when the resistance circuit 9 becomes abnormal, the voltage value Vr of the readback signal may be double that in the normal state. Therefore, the data of the A / D converter 10 is set to be within ½ of the full scale when the input is normal, and the data of the A / D converter 10 is not saturated when there is an abnormality.

  As described above, in this embodiment, the detection circuit is the A / D converter 10 that converts the divided voltage signal into digital divided voltage information indicating the divided voltage value. Since the divided voltage signal is converted into digital divided voltage information, an abnormality of the divided voltage can be easily detected from the divided voltage information.

  The voltage / current conversion circuit 6 includes a resistance circuit in which two resistance circuits having the same resistance value are connected in series. The A / D converter 10 has no abnormality in the resistance circuit 9 of the voltage / current conversion circuit 6. It is possible to convert the voltage up to twice the maximum input voltage. When the resistance of the voltage / current conversion circuit 6 becomes abnormal, the divided voltage rises up to twice, but at that time, it can be converted into a digital value without being saturated.

  In the present embodiment, the control circuit 4 receives the control instruction value from the host controller 2 and inputs it to the D / A converter 5, and reads the readback data based on the readback signal of the divided voltage value Vr. It transmits to the control apparatus 2. Specifically, the readback signal having the voltage value Vr is converted by the A / D converter 10 into a digital signal on which readback data indicating the voltage value Vr is mounted. The digital signal is transmitted from the A / D converter 10 to the control circuit 4. The control circuit 4 transmits readback data to the host controller 2 via the communication line 3, and the host controller 2 performs a readback diagnosis. It is possible to control the plant equipment 8 to be controlled in cooperation with the host controller 2 and to easily detect an abnormality in the resistance of the voltage / current conversion circuit 6 with the host controller 2. .

  FIG. 3 is a flowchart showing processing executed by the host control device 2. The host controller 2 sets the voltage value of the analog signal output from the analog output device 1 to the plant equipment 8 in the analog output device 1, and the voltage of the analog output device 1 based on the readback data from the analog output device 1. The abnormality of the resistance circuit 9 in the current conversion circuit 6 is monitored.

  Referring to FIG. 3, the host controller 2 sets output data indicating the voltage value of the analog signal to be output to the plant equipment 8 to the analog output device 1 in step 101. Subsequently, in step 102, the host controller 2 calculates an upper limit determination value and a lower limit determination value for verifying the normality of the readback data from the analog output device 1.

At that time, the host control device 2 first calculates theoretical data Dr1, which is the value of the theoretical readback data at normal time, from the output data Dao using the equation (1).
Dr1 = Dao × (Ra + Rb) × Rc × Rd / ((Ra + Rb) × Rc × Rd + Ra × Rb × (Rc + Rd)) (1)

Next, the host controller 2 calculates the upper limit determination value Dr1A from the theoretical data Dr1 using the equation (2).
Dr1A = Dr1 + α (2)

Similarly, the host controller 2 calculates the lower limit determination value Dr1B from the theoretical data Dr1 using the equation (3).
Dr1B = Dr1-α (3)

  Α in the equations (2) and (3) is an allowable error of the readback data. Here, the same tolerance value is used in Equation (2) and Equation (3), but different tolerance values may be used.

  When the upper limit determination value Dr1A and the lower limit determination value Dr1B are calculated as described above, the host control device 2 next acquires actual measurement data Dr2 of actual readback data in step 103.

  Next, in step 104, the host controller 2 determines whether or not the actual measurement data Dr2 is equal to or lower than the upper limit determination value Dr1A. If Dr2 is not equal to or less than Dr1A, the host controller 2 performs an abnormality process in step 106. For example, the abnormality process may be a pop-up display of a window informing the occurrence of an abnormality on the display screen or a warning sound informing the occurrence of an abnormality.

  If Dr2 is not more than Dr1A in step 104, the host controller 2 determines in step 105 whether or not the actual measurement data Dr2 is not less than the lower limit determination value Dr1B. If Dr2 is not equal to or greater than Dr1B, the host controller 2 performs an abnormality process in step 106. If Dr2 is greater than or equal to Dr1B in step 105, the host control device 2 ends the process.

  FIG. 4 is a table showing the relationship between the voltage value Vr of the divided voltage signal, the failure part, and the failure mode.

  The voltage of the readback signal when one of the resistors Ra, Rb, Rc, Rd of the voltage / current conversion circuit 6 fails and becomes abnormal in the readback diagnosis is shown. When one of the resistor Ra and the resistor Rb is opened, the voltage value Vr becomes 2/3 times normal. When one of the resistor Ra and the resistor Rb is short-circuited, the voltage value Vr becomes twice that in a normal state. When one of the resistor Rc and the resistor Rd is opened, the voltage value Vr becomes 4/3 times that in the normal state. When either the resistor Rc or the resistor Rd is short-circuited, the voltage value Vr becomes 0 [V]. Thus, the voltage Vr of the readback signal differs depending on the failure part and the failure mode. Therefore, at the time of failure, the failure part and failure mode can be estimated from the readback data.

  In the first embodiment, an example in which a readback diagnosis is performed using the A / D converter 10 and an abnormality of the resistance circuit 9 is detected is shown. However, in the second embodiment, a read operation is performed using two comparators 20 and 21. Back diagnosis is performed, and an abnormality of the resistance circuit 9 is detected.

  FIG. 5 is a circuit configuration diagram of an analog output device according to the second embodiment. The analog output device 1 in FIG. 5 is different from the analog output device 1 according to the first embodiment shown in FIG. 1 in that a comparator 20 and a comparator 21 are provided instead of the A / D converter 10.

The comparator 20 receives the signal line 12 and the signal line 15. The comparator 20 generates an upper limit determination value Vr1A to be compared with the divided voltage Vr from the voltage value Vi given from the signal line 12 using Expression (4). Further, the comparator 20 compares the actual divided voltage Vr given from the signal line 15 with the upper limit determination value Vr1A, and outputs an upper limit comparison result signal indicating whether the divided voltage Vr is equal to or lower than the upper limit determination value Vr1A. Output to the signal line 22.
Vr1A = Vi × (Ra + Rb) × Rc × Rd / ((Ra + Rb) × Rc × Rd + Ra × Rb × (Rc + Rd)) + α (4)

The signal line 12 and the signal line 15 are also input to the comparator 21. The comparator 21 generates a lower limit determination value Vr1B to be compared with the divided voltage Vr from the voltage value Vi given from the signal line 12 using Expression (5). Further, the comparator 21 compares the actual divided voltage Vr given from the signal line 15 with the lower limit determination value Vr1B, and outputs a lower limit comparison result signal indicating whether the divided voltage Vr is equal to or higher than the lower limit determination value Vr1B. Output to the signal line 23.
Vr1B = Vi × (Ra + Rb) × Rc × Rd / ((Ra + Rb) × Rc × Rd + Ra × Rb × (Rc + Rd)) − α (5)
Α in the equations (4) and (5) is an allowable error of the divided voltage Vr. Here, the same value of tolerance is used in Equation (4) and Equation (5), but different values of tolerance may be used.

  The control circuit 4 determines whether or not an abnormality has occurred in the resistance circuit 9 based on information included in the upper limit comparison result signal from the comparator 20 and information included in the lower limit comparison result signal from the comparator 21. Then, the determination result information is transmitted to the host control device 2. The divided voltage Vr is in the normal range if it is not less than the lower limit determination value Vr1B and not more than the upper limit determination value Vr1A. When the divided voltage Vr is smaller than the lower limit determination value Vr1B or larger than the upper limit determination value Vr1A, the control circuit 4 notifies the resistance circuit 9 that an abnormality has occurred.

  In the present embodiment, the detection circuit includes a comparator 20 and a comparator 21. The comparator 20 compares the divided voltage signal with a predetermined upper limit value, and the comparator 21 compares the divided voltage signal with a predetermined lower limit value. Compare. Since the divided voltage signal is compared with the upper limit value and the lower limit value, it can be easily detected that the divided voltage value Vr is out of the predetermined range.

  In the first and second embodiments, the resistance circuit 9 of the voltage / current conversion circuit 6 includes four resistance elements. In the third embodiment, the resistance circuit 9 includes two resistors connected in series.

  FIG. 6 is a circuit configuration diagram of an analog output device according to the third embodiment. The analog output device 1 of the third embodiment is different from that of the first embodiment shown in FIG. 1 in that the resistor circuit 9 has a configuration in which two resistors Re and Rf are connected in series.

  The analog output device 1 includes a resistor circuit 9 in which a plurality of resistors Re and Rf are connected in series. Therefore, the divided voltage value Vr changes from the normal value regardless of whether the resistance Re or the resistance Rf is short-circuited or open, and the abnormality can be detected.

DESCRIPTION OF SYMBOLS 1 ... Analog output device, 2 ... Host control device, 3 ... Communication line, 4 ... Control circuit, 5 ... D / A converter, 6 ... Voltage / current conversion circuit, 7 ... Power supply circuit, 8 ... Plant equipment, 9 ... Resistor circuit, 10 ... A / D converter, 11, 12, 13, 14, 15, 16 ... signal line, 20, 21 ... comparator, 22, 23 ... signal line

Claims (7)

A digital / analog converter for converting a digital control instruction value into an analog voltage signal;
A voltage / current conversion circuit that includes two or more resistor circuits connected in series, generates a control current signal obtained by converting a control voltage value based on the voltage signal into a current value, and outputs the control current signal to a control target device;
A detection circuit that receives a divided voltage signal indicating a divided voltage value divided by the resistor circuit connected in series in the voltage / current conversion circuit, and whose output changes when the voltage value of the divided voltage signal changes. When,
An analog output device.   The analog output device according to claim 1, wherein the voltage / current conversion circuit includes the resistor circuit in which a plurality of circuits in which a plurality of resistors are connected in parallel are connected in series.   The analog output circuit according to claim 2, wherein the voltage / current conversion circuit includes the resistor circuit in which two circuits in which two resistors having the same resistance value are connected in parallel are connected in series.   The analog output device according to claim 3, wherein the voltage / current conversion circuit has resistance values of all four resistors being equal.   The analog output device according to claim 1, wherein the detection circuit is an analog / digital converter that converts the divided voltage signal into digital divided voltage information indicating a divided voltage value. The voltage / current conversion circuit includes a resistance circuit in which two resistance circuits having the same resistance value are connected in series,
6. The analog output device according to claim 5, wherein the analog / digital converter is capable of converting up to a voltage twice or more of a maximum input voltage when there is no abnormality in the resistance circuit of the voltage / current conversion circuit.   The detection circuit includes a first comparator that compares the divided voltage signal with a predetermined upper limit value, and a second comparator that compares the divided voltage signal with a predetermined lower limit value. Analog output device.

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