JP2018067878A - Frequency multiplier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency multiplier that is able to output a balanced differential signal.SOLUTION: A pair of differentials D1/D2 differentiate and output a signal of a frequency including a multiplied frequency 2nf0 obtained by inputting a differential signal, distorting the differential signal, and multiplying it by the frequency f0 of the differential signal. A pair of phase shifter PC1/PC2 perform positive-phase-/orthogonal-output such that their respective phases are orthogonal to each other at the frequency f0 of the differential signal. A pair of cascodes Ca1 input respective positive outputs of the phase shifter PC1 and combine them at a differential output node N1a, and a pair of cascodes Ca2 input respective orthogonal outputs of the phase shifter PC2 and combine them at a differential output node N2a. Consequently, a signal with a multiplied frequency 2nf0 of the differential signal can be output from the pair of differential output nodes N1a, N2a.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a frequency multiplier.

  In recent years, various driving support technologies such as collision prevention and automatic driving have been proposed, and a technique for measuring the distance from the own device to a target using radar technology has attracted attention. For example, the applicant has proposed a millimeter wave band radar apparatus for automobiles as an apparatus for measuring the distance from the apparatus to the target. Various electronic parts are incorporated in the radar apparatus, and a frequency multiplier is used in the electronic parts.

  Conventionally, as this type of frequency multiplier, a push-push type having a relatively simple configuration has been used (for example, see Patent Document 1). According to the technique described in Patent Document 1, the multiplier core outputs a signal including a frequency component having an even multiple of the input signal in a single phase, and the differential amplifier differentially amplifies the single-phase output. Output.

  However, in the configuration of Patent Document 1, the gate terminal of one of the pair of input MOS transistors constituting the differential amplifier is grounded in an alternating manner, and as a result, even if a differential signal is output. In effect, it becomes a single-ended output.

  The inventors consider that a transformer may be used on the output side in order to obtain a differential output from this single-ended output. However, when a transformer is used, the balance often shifts and a high frequency band (for example, It is difficult to produce a balanced transformer in the millimeter wave band because parasitic capacitance is generated between components.

JP 2006-196963 A

  An object of the present invention is to provide a frequency multiplier capable of outputting a balanced differential signal.

  According to the first aspect of the present invention, the pair of differential pairs inputs a differential signal, distorts the differential signal, and differentially outputs a signal having a frequency including the multiplied frequency. Can be included in the differential output by the pair of differential pairs. In addition, the phase shifter outputs the differential output of the differential pair in the normal phase / orthogonal output so that the phases are orthogonal to each other at the frequency of the differential signal. A pair of differential output nodes are combined through the pair. For this reason, the basic frequency components of the differential signals can be substantially canceled out, and signals of the multiplied frequency can be synthesized and superimposed and output at the pair of differential output nodes. As a result, a balanced differential signal can be output. Moreover, since the cascode pair is provided, high isolation characteristics can be obtained between the input and output terminals.

Electrical configuration diagram of frequency multiplier in the first embodiment Electrical configuration diagram showing a specific example of a phase shifter in the first embodiment Explanatory drawing of the simulation result of the frequency multiplier in 1st Embodiment Electrical configuration diagram of frequency multiplier in the second embodiment Electrical configuration diagram of frequency multiplier in the third embodiment Electrical block diagram which shows the specific example of the phase shifter in 4th Embodiment (the 1) Electrical block diagram which shows the specific example of the phase shifter in 4th Embodiment (the 2) Gain-frequency characteristic diagram of phase shifter in the fourth embodiment Phase-frequency characteristic diagram of phase shifter in fourth embodiment Explanatory drawing of the simulation result of the frequency multiplier in 4th Embodiment Electrical configuration diagram of frequency multiplier in the fifth embodiment Explanatory drawing of the simulation result of the frequency multiplier in 5th Embodiment In 6th Embodiment, the electrical block diagram of LC parallel resonance circuit comprised between a pair of differential output nodes

  Hereinafter, some embodiments of the frequency multiplier will be described with reference to the drawings. In each embodiment described below, configurations that perform the same or similar operations are denoted by the same or similar reference numerals, and description thereof is omitted as necessary. In the following embodiments, the same or similar components are described by assigning the same reference numerals to the alphabet of the first letter of the code and the tens and first places appended thereto.

(First embodiment)
1 to 3 show explanatory views of the first embodiment. FIG. 1 shows a configuration example of the frequency multiplier 1. As shown in FIG. 1, the frequency multiplier 1 includes a pair of differential pairs D1 / D2, a pair of phase shifters PC1 / PC2, a pair of current sources Id1 / Id2, and a pair of cascode pairs Ca1 / Ca2. A grounding capacitor C1 / C2, a transmission line TL1, and a matching circuit MC.

  One differential pair D1 includes transistors M1 and M2, and the other differential pair D2 includes transistors M5 and M6. The differential pair D1, D2 is configured as a pair corresponding to the pair of cascode pairs Ca1 / Ca2 and the pair of phase shifters PC1 / PC2. One cascode pair Ca1 includes transistors M3 and M4, and the other cascode pair Ca2 includes transistors M7 and M8.

  The transistors M1 to M8 are composed of the same type of transistors, and are composed of, for example, an n-channel type MOS transistor, but may be composed of bipolar transistors. In the following, a configuration in which the transistors M1 to M8 are configured by n-channel MOS transistors is shown, and the connection is described by describing them as nMOS transistors M1 to M8, respectively.

  The gates of the nMOS transistors M1 and M5 are commonly connected to each other, and the gates of the nMOS transistors M2 and M6 are also commonly connected to each other. A bias circuit (not shown) is provided so that the gates and sources of the nMOS transistors M1, M2, M5, and M6 are biased in advance near the threshold voltage, or the drain current is relatively low. Biased. In other words, the nMOS transistors M1, M2, M5, and M6 are biased to operate, for example, class A, class AB, class B, or class C. The nMOS transistors M1, M2, M5, and M6 may be biased in any way as long as the differential output of each drain voltage can be distorted nonlinearly.

  The positive phase voltage VINP of the differential signal is applied to the gates of the nMOS transistors M1 and M5 from the positive phase input terminal INP. On the other hand, the negative phase input voltage VINN of the differential signal is supplied from the negative phase input terminal INN to the gates of the nMOS transistors M2 and M6. The differential signal based on the positive phase input voltage VINP and the negative phase input voltage VINN has an input frequency set to several tens [GHz] (for example, 40 [GHz]).

  The sources of the nMOS transistors M1 and M2 are commonly connected at a node N1, and a grounded capacitor C1 and a current source Id1 are connected in parallel between the common connection node N1 and the ground. The grounding capacitor C1 is provided to ground the common connection source of the nMOS transistors M1 and M2 in an alternating manner. The current source Id1 is provided so as to adjust the current bias of the nMOS transistors M1 and M2.

  On the other hand, the sources of the nMOS transistors M5 and M6 are also commonly connected at the node N2, and a grounded capacitor C2 and a current source Id2 are connected in parallel between the common connection node N2 and the ground. The grounding capacitor C2 is provided to ground the common connection source of the nMOS transistors M5 and M6 in an alternating manner. The current source Id1 is provided so as to adjust the current bias of the nMOS transistors M1 and M2.

  The drains of the nMOS transistors M1 and M2 are connected to the first phase shifter PC1. This 1st phase shifter PC1 is comprised along a pair of electricity supply path | route R1a, R1b, for example, is comprised using the transmission line which mutually shifts the same phase. On the other hand, the drains of the nMOS transistors M5 and M6 are connected to the second phase shifter PC2. This 2nd phase shifter PC2 is comprised using the transmission line which is comprised along a pair of electricity supply path | route R2a and R2b, for example, mutually makes the same phase shift.

  When the designer designs the frequency multiplier 1, the size of each nMOS transistor (for example, M1 to M8) is set to about 1 [μm] to about several tens [μm], and several hundred [μm] to several The transmission line is designed with a plane dimension of about [mm] (for example, 900 [μm]). For this reason, it is desirable to use a folded and bent line pattern from the viewpoint of reducing the circuit configuration when configuring this type of transmission line.

  Therefore, when the first and second phase shifters PC1 and PC2 are configured using transmission lines, a microstrip line, a coplanar line (CoPlanar Waveguide: CPW), a grounded coplanar line (Grand CoPlanar Waveguide: GCPW) and other line patterns should be folded. Moreover, you may comprise using a slow wave transmission line (Slow-wave transmission line: SWTL).

  This slow wave transmission line has a configuration in which, for example, a floating strip line perpendicular to a signal line and a ground line is provided and used as a dummy ground, and the signal line is brought close to the dummy ground. As a result, the effective inductance component can be increased, and if the length and volume are the same, the phase delay can be increased compared to a normal transmission line (for example, a coplanar line) not provided with a floating strip line. .

  When the transmission line is configured in the semiconductor chip, if the transmission line is configured using the slow wave transmission line, the physical line length can be shortened and the required circuit area can be further reduced. As will be described later, the first and second phase shifters PC1 and PC2 may be configured by using LC circuits including low-pass filters LPF1a and LPF1b, high-pass filters HPF2a and HPF2b, respectively.

  The first phase shifter PC1 is configured by a circuit that outputs a positive phase in a state where a predetermined phase difference θ / 2 (where θ ≧ 0 ° or θ> 0 °) is delayed at a frequency f0 of the differential signal, for example. For example, in the case where the first phase shifter PC1 is constituted by a transmission line (TL2P, TL2N, TL3P, TL3N, etc., which will be described later) in which the phase-frequency characteristics change linearly, the desired frequency f0 is doubled This is a circuit that delays a predetermined phase difference θ at a multiplication frequency of 2 · f0.

  The second phase shifter PC2 is configured by a circuit that outputs a quadrature signal by delaying a predetermined phase difference (θ + λ / 2) / 2 at, for example, the frequency f0 of the differential signal. For example, the second phase shifter PC2 In the case of a transmission line whose phase-frequency characteristics change linearly (TL2P, TL2N, TL3P, TL3N, etc., which will be described later), a predetermined phase difference is obtained by multiplying the frequency f0 by 2 and the frequency 2f0. The circuit is delayed by the opposite phase of θ (θ + λ / 2). For this reason, the first phase shifter PC1 and the second phase shifter PC2 are configured to output the positive / quadrature outputs so that the phases are orthogonal to each other at the frequency f0 of the differential signal.

  The nMOS transistors M3 and M4 form a cascode pair Ca1. A common DC bias voltage VG is applied to the gates of the nMOS transistors M3 and M4. The drains of the nMOS transistors M3 and M4 serving as the cascode output terminals of the cascode pair Ca1 are commonly connected at the node N1a. The common connection node N1a is connected to an output terminal (hereinafter referred to as a positive phase output terminal as necessary) OUTP of the positive phase output voltage VOUTP.

  The nMOS transistors M3 and M4 are cascode-connected from the nMOS transistors M1 and M2 via one phase shifter PC1, and the transistors M1 and M3 and M2 and M4 constitute a cascode circuit. Since the cascode pair Ca1 is provided, the positive phase input terminal INP side and the positive phase output terminal OUTP side can be kept in a high isolation state.

  On the other hand, the nMOS transistors M7 and M8 constitute a cascode pair Ca2. A common DC bias voltage VG is applied to the gates of these nMOS transistors M7 and M8. The drains of the nMOS transistors M7 and M8 serving as the cascode output terminals of the cascode pair Ca2 are commonly connected at a node N2a. The common connection node N2a is an output terminal of a negative-phase output voltage VOUTN (hereinafter referred to as a negative-phase output terminal if necessary). This is connected to OUTN.

  The nMOS transistors M7 and M8 are cascode-connected from the nMOS transistors M5 and M6 via the other phase shifter PC2, whereby the transistors M5 and M7 and M6 and M8 constitute a cascode circuit. Since the cascode pair Ca2 is provided, the opposite phase input terminal INN and the opposite phase output terminal OUTN can be kept in a high isolation state.

  A phase shifter SS1 is connected between the positive phase output terminal OUTP and the negative phase output terminal OUTN. The phase shifter SS1 includes a transmission line TL1 that is λ / 2 at a multiplied frequency (2 × n × f0). A matching circuit MC is connected between the power supply terminal T to which the power supply voltage VDD is applied and the positive phase output terminal OUTP and the negative phase output terminal OUTN. This matching circuit MC is a circuit for impedance matching with a subsequent circuit connected to the subsequent stage.

  The matching circuit MC is preferably configured while applying a bias based on the power supply voltage VDD to the differential output nodes N1a and N2a, and between the power supply terminal T and the differential output nodes N1a and N2a at the frequency of the differential signal. It is preferable that the impedance is maintained at a high impedance. For this reason, it is preferable to connect an inductor (not shown) or a transmission line functioning as an inductor between the power supply terminal T and the differential output nodes N1a and N2a. Thereby, a differential signal can be output between the positive phase output terminal OUTP and the negative phase output terminal OUTN.

  The operation of the frequency multiplier 1 will be described for the above configuration. The frequency multiplier 1 is a multiplier that outputs a signal including frequency components mainly having a frequency 2n (n ≧ 1) times the differential input signal (2 · n · f0: mainly a double wave). ing. For example, when the frequency multiplier 1 outputs a differential signal having a doubled frequency, for example, the following principle is used.

  As described above, the differential pair D1, D2 is biased by a bias circuit (not shown) so that the gates and sources of the nMOS transistors M1, M2, M5, M6 are close to the threshold voltage, or The drain current is biased in advance so that the drain current becomes lower. For this reason, when a sine wave differential signal is input to the gates of the nMOS transistors M1 and M2, the drain terminals of the nMOS transistors M1 and M2 are distorted including harmonics at which the signal has a frequency multiplied by the differential signal. It will be output in the state.

  This signal is output to the node N1a through the first phase shifter PC1 and the cascode pair Ca1. At the differential output node N1a that is the drain common connection node of the nMOS transistors M3 and M4, the odd-order components such as the fundamental wave components appear so as to be out of phase with each other. For this reason, the odd-order component is canceled by being synthesized at the differential output node N1a. On the mathematical formula, it can be shown as the formula (1).

他方、偶数次成分は、ノードＮ１ａにおいて互いに同相で現れることになるため互いに加算されることになり、正相出力端子ＯＵＴＰから正相出力電圧ＶＯＵＴＰを取り出すことができる。数式上では、下記の（２）式のように示すことができる。

On the other hand, since the even-order components appear in phase with each other at the node N1a, they are added together, and the positive-phase output voltage VOUTP can be taken out from the positive-phase output terminal OUTP. On the mathematical formula, it can be shown as the following formula (2).

他方、同様に、正弦波による差動信号がｎＭＯＳトランジスタＭ５、Ｍ６のゲートにそれぞれ差動入力されると、当該ｎＭＯＳトランジスタＭ５及びＭ６のドレイン端子には信号が差動信号の逓倍周波数となる高調波を含んで歪んだ状態で出力されることになる。

On the other hand, similarly, when a differential signal based on a sine wave is differentially input to the gates of the nMOS transistors M5 and M6, the harmonics at which the signal becomes the multiplied frequency of the differential signal are supplied to the drain terminals of the nMOS transistors M5 and M6. It is output in a distorted state including waves.

  This signal is output to the node N2a through the second phase shifter PC2 and the cascode pair Ca2. In the node N2a, the odd-order components such as the fundamental wave components are out of phase with each other, but these odd-order components are canceled by being synthesized. On the other hand, even-order components appear in phase with each other at the node N2a, and are added to each other. For this reason, at the node N2a, the addition component of the even-order components can be combined and acquired, and this combined signal component can be acquired from the output terminal OUTN as the negative phase output voltage VOUTN.

  The first phase shifter PC1 and the second phase shifter PC2 output anti-phase components to each other at a desired 2 · n multiplied frequency 2 · n · f0 (where n ≧ 1) of the even order, and the phase shifter SS1 The differential output terminals OUTP and OUTN are connected. With this configuration, the positive phase output voltage VOUTP and the negative phase output voltage VOUTN become opposite phase components at a desired 2 · n multiplication frequency, and the differential output terminals OUTP and OUTN receive even-numbered differential signals. Ingredients can be obtained stably.

  FIG. 2 shows a configuration example of the first and second phase shifters PC101 and PC102, and FIG. 3 shows a simulation result when the circuit is applied. As illustrated in FIG. 2, the frequency multiplier 101 includes a first phase shifter PC101 and a second phase shifter PC102.

  In the configuration example shown in FIG. 2, the first phase shifter PC shifts the predetermined phase 0 ° of the n-multiplied frequency, that is, the nMOS transistors M1 and M3 and the nMOS transistors M2 and M4 are directly connected with a length of 0 °. Has been. Further, the second phase shifter PC2 is configured to shift the predetermined phase 0 ° + 180 ° of the n-multiplied frequency. In the configuration example illustrated in FIG. 2, an example is illustrated in which the second phase shifter PC2 is configured by transmission lines TL2P and TL2N that are shifted in phase by a predetermined phase 0 ° + 180 °.

  In the circuit configuration example shown in FIG. 2, the constant current sources Id1 and Id2 and the ground capacitors C1 and C2 are not provided on the ground side of the node N1b corresponding to the node N1, and the common connection source of the pair of nMOS transistors M1 / M2 is provided. Although the configuration is such that the ground is connected and the common connection source of the pair of nMOS transistors M5 / M6 is grounded, this configuration may be used. In particular, it is desirable to use this circuit configuration when it is desired to obtain a large output amplitude.

  Even in such a case, as shown in the principle described above, signals having opposite phases can be output to the pair of differential output terminals OUTP / OUTN. FIG. 3A shows time waveforms of the positive phase input voltage VINP and the negative phase input voltage VINN. FIG. 3A shows the above-described positive-phase input voltage VINP by dividing the gate input voltage of the nMOS transistor M1 as VINP1 and the gate input voltage of the nMOS transistor M5 as VINP2. Regarding the above-described negative phase input voltage VINN, the gate input voltage of the nMOS transistor M2 is shown as VINN1, and the gate input voltage of the nMOS transistor M6 is shown as VINN2.

  FIG. 3B shows voltage waveforms of the interstage voltages VISP1, VISN1, VISP2, and VISN2 between the pair of phase shifters PC101 / PC102 and the pair of cascode pairs Ca1 / Ca2, and FIG. The time change waveforms of the dynamic output voltages VOUTP and VOUTN are shown.

  Since the pair of phase shifters PC101 / PC102 outputs the positive / quadrature outputs so that the phases are orthogonal to each other at the frequency f0, the positive phase interstage voltages VISP1 and VISP2 are about 90 ° relative to each other at the frequency f0. Has a phase difference. Further, the inter-stage voltages VISN1 and VISN2 have a phase difference of 90 ° from each other at the frequency f0 of the differential signal. In addition, the interstage voltages VISP1 and VISN1 have a relationship in which the phases are opposite to each other at the frequency f0, and the time-varying waveform is generally distorted in the same manner. Further, the interstage voltages VISP2 and VISN2 have a phase relationship opposite to each other at the frequency f0, and the time-varying waveform is distorted in the same manner.

  At this time, even if the interstage voltages VISP1, VISN1, VISP2, and VISN2 are distorted as shown in FIG. 3B, the odd-order components are as shown in the equations (1) and (2). The differential output nodes N1a and N2a cancel each other, and the even-order components are combined and superimposed at the differential output nodes N1a and N2a. The differential outputs are output through the differential output nodes N1a and N2a. Even-order components having opposite phases can be obtained from the terminals OUTP and OUTN.

  The simulation results shown in FIGS. 3A to 3C are obtained by adopting the circuit configuration of FIG. 2, and as shown in FIG. 3B, the interstage voltages VISP1, VISN1 are obtained. , VISP2 and VISN2 have a quadrature phase relationship.

  The even-order component appearing in the output voltages VOUTP and VOUTN is a frequency component 2n (where n ≧ 1) times the differential signals VINP1, VINN1, VINP2, and VINN2, but the level of the secondary frequency component is the largest. Therefore, the fourth, sixth,... Components are negligible compared to the secondary components. For this reason, in the time axis waveform, the waveform of the secondary component is the largest. It is also possible to filter by providing a filter circuit in the subsequent stage to extract 2n (where n ≧ 2) order components such as a 4th order component and a 6th order component.

  The features of the present embodiment are conceptually summarized. According to this embodiment, the pair of differential pairs D1 / D2 inputs a differential signal, distorts the differential signal, and differentially outputs a signal having a frequency including the multiplied frequency 2 · n · f0. Therefore, the signal component of the multiplication frequency 2 · n · f0 can be included in the differential output. Further, the phase shifters PC1, PC2 or PC101, PC102 output the differential outputs of the differential pairs D1, D2 so that the phases are orthogonal to each other at the frequency f0. The orthogonal outputs are respectively combined at the pair of differential output nodes N1a / N2a through the pair of cascode pairs Ca1 / Ca2. For this reason, the component of the frequency f0 of each differential signal can be canceled. Further, since the cascode pairs Ca1 and Ca2 are provided, high isolation characteristics can be obtained between the input and output terminals.

  The pair of differential pairs D1 / D2 outputs differential signals each having a frequency including the multiplied frequency 2 · n · f0. These differential outputs are paired through the pair of cascode pairs Ca1 / Ca2, respectively. When the signals are combined at the differential output nodes N1a and N2a, signals with a multiplication frequency of 2 · n · f0 are combined and superimposed. As a result, the signals having the multiplication frequency of 2 · n · f0 can be outputted from the pair of differential output nodes N1a and N2a in the normal phase / reverse phase, and the differential signal of the multiplication frequency of 2 · n · f0 can be outputted. As a result, it is possible to output a differential signal having a multiplication frequency of 2 · n · f0 with a small component of the frequency f0 of the differential signal at a high gain.

  In the circuit configuration shown in FIG. 1, the current source Id1 draws a constant current from the pair of nMOS transistors M1 / M2 of the differential pair D1 to the ground terminal, and the ground capacitor C1 is connected in parallel with the current source Id1. On the other hand, the current source Id2 draws a constant current from the pair of nMOS transistors M5 / M6 of the differential pair D2 to the ground terminal, and the ground capacitor C2 is connected in parallel with the current source Id2. Since the drain currents of the nMOS transistors M1 / M2 and M5 / M6 can be adjusted by the current sources Id1 and Id2, design margins such as bias conditions can be increased. As shown in FIG. 2, the output amplitude can be increased by omitting the current sources Id1 and Id2 and the grounded capacitors C1 and C2.

  Further, since the transmission line TL1 having a phase difference characteristic of 180 ° at the multiplication frequency 2 · n · f0 is formed between the pair of differential output nodes N1a and N2a, both the differential output nodes N1a and N2a Can be generated by reinforcing signals that are out of phase with each other, whereby the amplitude of the differential signal can be stably output between the differential output terminals OUTP and OUTN.

  As shown in FIG. 2, the pair of phase shifters PC101 / PC102 are configured to shift the phase by 0 ° and 90 ° respectively at the frequency f0 of the differential signal. The phase shift is 0 ° and 180 ° at 2 · n · f0, respectively. For this reason, it is possible to stably output a signal of 2 · n multiplication frequency 2 · n · f0 from the differential output nodes N1a and N2a.

Since the differential pair D1 / D2 is composed of nMOS transistors M1 / M2 and M5 / M6, integration is facilitated.
For example, when a control circuit (not shown) controls the oscillation frequency by an FMCW (Frequency-Modulated Continuous-Wave) modulation method in which the frequency is linearly changed by using the frequency multiplier 1, the output differential of the frequency multiplier 1 is used. The resonance frequency of the signal is finely controlled. For example, even if fine control is performed in a high frequency band where parasitic capacitance cannot be ignored in a high frequency band such as the millimeter wave band, the linearity of the FMCW frequency modulation can be maintained as high as possible by performing the fine control using the frequency multiplier 1. Become. Low phase noise performance can be realized.

(Second Embodiment)
FIG. 4 shows an additional explanatory diagram of the second embodiment. The second embodiment shows another specific example of the first and second phase shifters PC1 and PC2 in FIG. 1 of the first embodiment. As shown in FIG. 4, the frequency multiplier 201 includes a first phase shifter PC201 and a second phase shifter PC202.

  The first phase shifter PC201 includes a pair of transmission lines TL3P / TL3N. It is desirable that the pair of transmission lines TL3P / TL3N have characteristics having the same predetermined phase θ at the multiplication frequency 2 · n · f0.

  On the other hand, the second phase shifter PC202 is configured by a pair of transmission lines TL2P / TL2N. It is desirable that the pair of transmission lines TL2P / TL2N have the characteristics of having the same predetermined phase θ + 180 ° at the multiplication frequency 2 · n · f0. As a result, signals having phases opposite to each other at the multiplication frequency 2 · n · f0 can be output from the differential output terminals OUTP and OUTN.

  According to this embodiment, both of the pair of phase shifters PC201 / PC202 are configured by the transmission lines TL3P / TL3N and TL2P / TL2N. For this reason, for example, by setting the predetermined phase θ to an appropriate value, between the differential pair D1 and the cascode pair Ca1 or between the differential pair D2 and the cascode pair Ca2, it is about several hundred μm to several mm. Transmission lines TL3P / TL3N and TL2P / TL2N can be configured using a practical line pattern. Thereby, it can comprise more practically.

(Third embodiment)
FIG. 5 shows an additional explanatory diagram of the third embodiment. The third embodiment shows a configuration example of the matching circuit MC. As described in the first embodiment, the matching circuit MC is preferably connected with an inductor between the power supply terminal T and the differential output nodes N1a and N2a. Therefore, transmission lines TL4 and TL5 may be connected between the power supply terminal T and the differential output nodes N1a and N2a, respectively, as shown in FIG. Another inductor (not shown) for energizing the DC power supply voltage VDD may be additionally connected between the power supply terminal T and the differential output nodes N1a and N2a.

  As shown in FIG. 5, capacitors C3 and C4 are connected between the differential output nodes N1a and N2a and the differential output terminals OUTP and OUTN. Thereby, the differential output nodes N1a and N2a can be configured to be separated from the subsequent circuit (not shown) in a DC manner. And it is good to aim at impedance matching with a back | latter stage circuit by LC circuit by transmission line TL4, TL5 and capacitor C3, C4. As a result, the constant of the matching circuit MC can be adjusted according to the input impedance of the subsequent circuit, and can be adapted to various subsequent circuits.

(Fourth embodiment)
6 to 10 show additional explanatory views of the fourth embodiment. The fourth embodiment shows a specific example of the first and second phase shifters. As shown in FIG. 6, the first phase shifter PC301 includes a pair of passive CLC type low-pass filters LPF1a and LPF1b as LC circuits so as to communicate with the pair of energization paths R1a and R1b, respectively.

  The low-pass filter LPF1a is configured by including an inductor L1a and capacitors C5a and C6a in a π type, and each constant of the inductor L1a and the capacitors C5a and C6a so as to exhibit a lagging characteristic in which the phase is delayed by 45 ° at the frequency f0 of the differential signal. Is set.

  Similarly, the low-pass filter LPF1b is configured by including an inductor L1b and capacitors C5b and C6b in a π type, and the inductor L1b and the capacitor C5b, so that the phase is delayed by 45 ° at the frequency f0 of the differential signal. Each constant of C6b is set.

  On the other hand, as shown in FIG. 7, the second phase shifter PC302 includes passive LCL type π-type high-pass filters HPF2a and HPF2b as LC circuits so as to respectively pass through the pair of energization paths R2a and R2b.

  The high-pass filter HPF2a includes inductors L2a and L3a and a capacitor C7a in a π type, and each constant of the inductors L2a and L3a and the capacitor C7a so as to exhibit a phase advance characteristic in which the phase advances by 45 ° at the frequency f0 of the differential signal. Is set.

  Similarly, the high-pass filter HPF2b includes inductors L2b and L3b and a capacitor C7b in a π type, and the inductors L2b and L3b and the capacitor C7b so as to exhibit a phase advance characteristic in which the phase advances by 45 ° at the frequency f0 of the differential signal. Each constant is set.

  Hereinafter, simulation conditions and results will be described. FIG. 8 shows amplitude-frequency characteristics of the low-pass filters LPF1a and LPF1b, high-pass filters HPF2a and HPF2b. FIG. 9 shows phase-frequency characteristics of the low-pass filters LPF1a and LPF1b, high-pass filters HPF2a and HPF2b. Yes. The low-pass filters LPF1a and LPF1b have the same characteristics, and the high-pass filters HPF2a and HPF2b have the same characteristics. Here, the simulation is performed by setting the frequency f0 of the differential signal to 40 GHz. See the marker portion in FIGS.

  Note that a high-pass filter HPF2a and HPF2b shown in FIG. Therefore, as shown in the amplitude frequency characteristics of the high-pass filters HPF2a and HPF2b in FIG. 8, the high-pass filters HPF2a and HPF2b pass signals in a relatively low frequency band (DC to several GHz) on the DC side.

  FIG. 10A to FIG. 10D show signal waveforms at each node. The signal voltages VIBP1, VIBN1, VIBP2, and VIBN2 in FIG. 10B indicate the signal waveforms of the previous nodes of the filters LPF1a, LPF1b, HPF2a, and HPF2b, as shown in FIGS. Voltages VISP1, VISN1, VISP2, and VISN2 in (C) show signal waveforms at nodes after the filters LPF1a, LPF1b, HPF2a, and HPF2b, as shown in FIGS. The inter-voltages VISP1, VISN1, VISP2, and VISN2 will be described.

  10 (A) to 10 (D), the post-filter positive-phase voltages VISP1 and VISP2 shown in FIG. 10 (C) have a phase difference of approximately 90 ° from each other at the frequency f0. Yes. Further, the orthogonal interstage voltages VISN1 and VISN2 have a phase difference of approximately 90 ° from each other at the frequency f0. In addition, the interstage voltages VISP1 and VISN1 have a reverse phase relationship with each other at the frequency f0 and are distorted in the same manner. Further, the interstage voltages VISP2 and VISN2 have a phase relationship opposite to each other at the frequency f0 and are distorted in the same manner.

  At this time, even if the interstage voltages VISP1, VISN1, VISP2, and VISN2 are distorted as shown in FIG. 10C, the odd-order components are respectively expressed as shown in the equations (1) and (2). The differential output nodes N1a and N2a cancel each other, and even-order components are synthesized and superimposed at the individual differential output nodes N1a and N2a. Even order components can be acquired.

For this reason, the same operational effects as those of the above-described embodiment can be obtained, and signals having opposite phases at the multiplied frequency can be output from the differential output terminals OUTP and OUTN.
(Fifth embodiment)
11 and 12 show additional explanatory views of the fifth embodiment. The fifth embodiment shows another configuration example of the differential pair. The differential pair D1 and D2 shown in the above embodiment is configured as a pair corresponding to the pair of cascode pairs Ca1 / Ca2 and the pair of phase shifters PC1 / PC2, but the differential pair D401 of the present embodiment is Only one differential pair D401 (Only one differential pair) is provided corresponding to the pair of cascode pairs Ca1 / Ca2 and the pair of phase shifters PC1 / PC2.

  The drain of the nMOS transistor M401 of the differential pair D401 is connected to the source of the nMOS transistor M3 through the first phase shifter PC101 and to the source of the nMOS transistor M7 through the transmission line TL2P of the second phase shifter PC102. . The drain of the nMOS transistor M402 of the differential pair D401 is connected to the source of the nMOS transistor M4 through the first phase shifter PC101 and to the source of the nMOS transistor M8 through the second phase shifter PC102.

  In this case, since the nMOS transistors M1 and M2 in FIG. 1 correspond to the nMOS transistors M401 and M402 in FIG. 11, in this embodiment, the nMOS transistors M5 and M6 in FIG. Reduction effect is obtained.

  FIG. 12 shows the signal voltage at each node. As shown in FIGS. 12A to 12C, the relationship among the input voltages VINP and VINN, the output voltages VOUTP and VOUTN, and the interstage voltages VISP1, VISN1, VISP2, and VISN2 are as described above. 3 described in the first embodiment and the relationship shown in FIG. 10 described in the fourth embodiment are the same as those in the first embodiment or the fourth embodiment. The same effect is obtained.

  In addition, by using the same current source that draws the constant current value as in the previous embodiment, it becomes possible to distribute the current to the pair of energization paths R1a and R1b and R2a and R2b of the first phase shifters PC101 and PC102. As a result, current consumption during operation can be reduced as compared with the above-described embodiment.

(Sixth embodiment)
FIG. 13 shows an additional explanatory diagram of the sixth embodiment. The sixth embodiment is characterized in that instead of the transmission line TL1, an LC parallel resonance circuit having a resonance frequency of the multiplied frequency 2 · n · f0 is provided between a pair of differential output nodes. Yes.

  As shown in FIG. 13, the phase shifter SS501 includes an LC parallel resonant circuit LC501. The LC parallel resonant circuit LC501 is configured to be interposed between the differential output nodes N1a and N2a, and is configured by connecting an inductor L4 and a capacitor C8 in parallel. The LC parallel resonance circuit LC501 includes impedances of the inductor L4 and the capacitor C8 such that the frequency within a predetermined range centered on the frequency 2 · n · f0 or the frequency 2 · n · f0 is the parallel resonance frequency. Is stipulated. Therefore, the LC parallel resonant circuit LC501 maintains a high impedance between the differential output nodes N1a and N2a at the multiplied frequency 2 · n · f0 and the vicinity thereof. For this reason, it becomes possible to stably generate and output a signal having a multiplication frequency of 2 · n · f0 from the differential output terminals OUTP and OUTN, thereby maintaining the amplitude balance between the differential output terminals OUTP and OUTN.

(Other embodiments)
The present invention is not limited to the above-described embodiments, can be implemented with various modifications, and can be applied to various embodiments without departing from the gist thereof. For example, the following modifications or expansions are possible.

  The example of the multiplication by 2 has been mainly described, but the differential output nodes N1a and N2a are similarly applied to the even-order multiplication frequency 2 · n · f0 of 2 · n (n ≧ 2: 4, 8,...) Or more. The differential signal can be obtained from the differential output terminals OUTP and OUTN.

  In the above-described embodiment, the differential pair D1 is configured by the pair of transistors M1 and M2 and the differential pair D2 is configured by the pair of transistors M5 and M6. However, the differential pair D1 is configured by using pMOS transistors. Alternatively, a bipolar transistor may be used. By using a bipolar transistor, high frequency characteristics can be improved and output power can be easily increased.

  In the above-described fourth embodiment, the configuration in which the matching circuit MC is configured by the transmission lines TL4 and TL5 and the capacitors C3 and C4 has been described, but a capacitor (between the power supply terminal T and the differential output nodes N1a and N2a). (Not shown) may be connected, and an inductor (not shown) may be connected between the differential output nodes N1a and N2a and the differential output terminals OUTP and OUTN.

  In the fourth embodiment, the lag characteristics of the π-type low-pass filters LPF1a and LPF1b and the phase-advance characteristics of the π-type high-pass filters HPF2a and HPF2b are used to cancel the odd-order frequency of the frequency f0 of the differential signal. However, the present invention is not limited to this, and can be configured using various LC circuits such as an LC filter.

  You may comprise combining several embodiment mentioned above. Further, the reference numerals in parentheses described in the claims indicate the correspondence with the specific means described in the embodiment described above as one aspect of the present invention, and the technical scope of the present invention is It is not limited. An aspect in which a part of the above-described embodiment is omitted as long as the problem can be solved can be regarded as the embodiment. In addition, any conceivable aspect can be regarded as an embodiment as long as it does not depart from the essence of the invention specified by the words described in the claims.

  Although the present disclosure has been described based on the above-described embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including one element, more or less, are within the scope and spirit of the present disclosure.

  In the drawing, 1, 101, 201, 301, 401 are frequency multipliers, D1, D2 are differential pairs, PC1, PC101, PC201 are phase shifters (one pair of phase shifters), PC2, PC102, PC202 are Phase shifters (a pair of other phase shifters), PC1 / PC2, PC101 / PC102, PC201 / PC202, PC301 / PC302 are a pair of phase shifters, Ca1 is a cascode pair (one pair of cascode pairs), and Ca2 is Cascode pair (a pair of other cascode pairs), R1a, R1b, R2a, R2b are energization paths (R1a / R2a, R1b / R2b are a pair of energization paths), N1a is a differential output node (a pair of differential outputs) Node), N2a is a differential output node (a pair of other differential output nodes), C1 and C2 are ground capacitances, Id1 and Id2 are current sources, and TL1 is a transmission line. LC501 is an LC parallel resonant circuit, R1a, R2a, R1b, and R2b are energization paths, R1a / R1b are a pair of energization paths, L1a, L1b, L2a, L2b, L3a, and L3b are inductors, C5a, C5b, C6a, C6b, and C7a , C7b is a capacitor, LPF1a and LPF1b are low-pass filters (LC circuits), HPF2a and HPF2b are high-pass filters (LC circuits), TL2P / TL2N; TL2P / TL2N and TL3P / TL3N are transmission lines.

Claims (13)

A frequency comprising a pair of transistors (M1 / M2, M5 / M6; M401 / M402) including a multiplied frequency obtained by inputting a differential signal, distorting the differential signal, and multiplying the frequency of the differential signal A differential pair (D1 / D2; D401) that differentially outputs the signal of
A phase shifter (PC1, PC2; PC101, PC102; PC201, which includes a pair of energization paths (R1a / R1b, R2a / R2b) and shifts the differential output of the differential pair through the pair of energization paths. A pair of phase shifters (PC1 / PC2; PC101 / PC102; PC201) that output a positive phase / a quadrature so that phases are orthogonal to each other at the frequency of the differential signal. / PC202; PC301 / PC302),
A pair of cascode pairs (Ca1 / Ca2) respectively configured between the pair of phase shifters and a pair of differential output nodes (N1a / N2a) as a pair of cascode output ends;
With
The pair of cascode pairs (Ca1) is configured to receive the positive phase output of the pair of one phase shifter (PC1) and synthesize it at the pair of one differential output node (N1a), The pair of other cascode pairs (Ca2) are configured to input orthogonal outputs of the pair of other phase shifters (PC2) and synthesize them at the pair of other differential output nodes (N2a),
A frequency multiplier that outputs a signal having a frequency multiplied by the differential signal from the pair of differential output nodes. The frequency multiplier according to claim 1, wherein
A current source (Id1, Id2) that draws a constant current from a pair of transistors of the differential pair to a ground terminal;
Grounded capacitors (C1, C2) connected in parallel with the current source;
A frequency multiplier comprising: The frequency multiplier according to claim 1 or 2,
A frequency multiplier further comprising a transmission line (TL1) configured between the pair of differential output nodes and having a phase difference characteristic of 180 ° at the multiplied frequency. The frequency multiplier according to claim 1 or 2,
A frequency multiplier further comprising an LC parallel resonant circuit (LC501) configured between the pair of differential output nodes and having a frequency corresponding to the multiplied frequency as a resonant frequency. A frequency multiplier according to any one of claims 1 to 4,
One or both of the pair of phase shifters (PC301 / PC302) includes inductors (L1a, L1b, L2a, L2b, L3a, L3b) and capacitors (C5a, C5b, C6a, C6b, C7a, C7b). A frequency multiplier configured using the slow phase characteristics or the leading phase characteristics of the combined LC circuit (LPF1a, LPF1b, HPF2a, HPF2b). A frequency multiplier according to any one of claims 1 to 5,
One or both of the pair of phase shifters (PC101 / PC102; PC201 / PC202) are frequency multipliers configured by transmission lines (TL2P / TL2N; TL3P / TL3N, TL2P / TL2N). A frequency multiplier according to any one of claims 1 to 6,
The differential pair (D401) is a frequency multiplier configured by one differential pair. A frequency multiplier according to any one of claims 1 to 6,
The differential pair (D1 / D2) is a frequency multiplier configured as a pair corresponding to the pair of phase shifters. A frequency multiplier according to any one of claims 1 to 8,
The pair of phase shifters (PC101 / PC102) are frequency multipliers configured to shift phases by 0 ° and 90 °, respectively, at the frequency of the differential signal. A frequency multiplier according to any one of claims 1 to 8,
The pair of phase shifters (PC201 / PC202) are configured to shift the phase by a predetermined phase θ and the predetermined phase θ + 180 °, where θ> 0 °, respectively, at the frequency of the differential signal. . A frequency multiplier according to any one of claims 1 to 10,
A frequency multiplier further comprising a matching circuit (MC) for impedance matching from the pair of differential output nodes to a subsequent circuit. A frequency multiplier according to any one of claims 1 to 11,
The pair of transistors constituting the differential pair is a frequency multiplier constituted by MOS transistors (M1 / M2, M5 / M6; M401 / M402). A frequency multiplier according to any one of claims 1 to 12,
A frequency multiplier that outputs a signal of 2 · n multiplied frequency of the differential signal, where n ≧ 1, from the pair of differential output nodes.

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