JP2018064188A - Successive approximation type ad conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a successive approximation type AD conversion device that has a relatively simple circuit configuration, can perform AD conversion at high speed and with low power consumption, is suitable for mounting on a low power microcomputer, and enables the conversion error thereof to be suppressed.SOLUTION: The successive approximation type AD conversion device includes a switch S1 that includes m board capacitors, each of which has one end connected to a board voltage Vof a MOS transistor, the m board capacitors having capacitance C, C/2, ..., C/2. In a sampling mode, the switch S1 is turned ON to input a reference voltage Vto a common terminal Cn, connect the board voltage Vwith the common terminal Cn, and input an input voltage Vto the other end of each board capacitor. In an electric charge redistribution mode, the switch S1 is turned OFF to release connection between the board voltage Vand the common terminal Cn and input, to the other end of each board capacitor, the same voltage as a voltage input to one end of a corresponding capacitor of n conversion capacitors for successive approximation, each of which has the other end connected to the common terminal Cn.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a successive approximation AD converter.

  As an analog-digital converter (ADC), there are various types of devices such as a flash type, a delta-sigma (ΔΣ) type, a pipeline type, and a successive approximation type (SAR). Among them, the successive approximation type AD converter is inferior in speed to the flash type and inferior in accuracy to the delta sigma type, but has a good balance between speed and accuracy, low power consumption and multiple inputs (multichannel). It is used in many fields such as microcomputers, home appliances, and automobiles.

For example, as shown in FIG. 13, a conventional successive approximation AD converter has one end connected to a common terminal Cn and the other end connected to an input voltage _VIN , a positive reference voltage _VH, and a negative reference voltage _VL. preparative provided to be selectively inputted, the capacitance respectively ^{_{C S, C S / 2 1}} , ···, the _{^{C S / 2 n-1,}} C S / 2 a plurality of capacitors (n ^(n-1) ON and an integer of 2 or more), a comparator CMP which compares the potential _{V Cn} and the reference voltage _{V REF} of the common terminal Cn, in front of the comparison unit CMP, the input of the reference voltage _{V REF} to the common terminal Cn / The switch SW1 is provided so that it can be turned off.

When AD conversion is performed by the successive approximation AD converter shown in FIG. 13, first, as a sample mode, with the switch SW1 turned on, the other end of each capacitor is connected to the input voltage _VIN , and each capacitor is connected. The input voltage _VIN is charged (sampled). Thereby, the charge amount Q = 2C _S (V _REF −V _IN ) is stored in the common terminal Cn. Next, a charge redistribution mode for redistributing the charge amount is performed. In the charge redistribution mode, the switch SW1 is maintained in the OFF state.

As a first conversion step charge redistribution mode, by connecting a capacitor of capacitance C _S of the top-level positive side reference voltage V _H, to connect it from the lower the capacitor to the negative side reference voltage V _L. At this time, since the charge amount Q of the common terminal Cn is not changed,
_{Q = 2C S (V REF -V} IN) = C S (V Cn -V H) + C S (V Cn -V L)
And
V _Cn = (V _H + V _L ) / 2 + V _REF −V _IN
It becomes.

The comparison unit CMP compares the potential V _Cn of the common terminal Cn with the reference voltage V _REF, and when V _REF > V _Cn , V _IN > (V _H + V _L ) / 2, and the output cout = 1, and a capacitor of the capacitance C _S of the top-level positive side reference voltage V _H. Further, when V _REF <V _Cn , V _IN <(V _H + V _L ) / 2 is established, cout = 0, and the capacitor having the uppermost capacitor C _S is connected to the negative reference voltage V _L. The capacitor of the capacitance C _S of the uppermost, every conversion step after the charge redistribution mode continues directly connected to the higher reference voltage V _H or negative reference voltage V _L.

Next, as a second conversion step in the charge redistribution mode, the capacitor of the second capacitor C _S / 2 ¹ is connected to the positive reference voltage V _H , and each lower capacitor is set to the negative reference voltage V _L. Connecting. Similar to the first conversion step, the comparison unit CMP compares the potential V _Cn of the common terminal Cn with the reference voltage V _REF, and when V _REF > V _Cn , cout = 1 and the second capacitor C _S / connecting two ^first capacitor to the positive side reference voltage _{V H. Further,} when the V REF _{<V Cn,} and cout = 0, connecting the second capacitor _C S / ^{2 1} capacitors to the negative reference voltage _{V L.} Note that the capacitor having the second capacity C _S / 2 ¹ continues to be connected to the positive reference voltage V _H or the negative reference voltage V _{L as} it is in all the conversion steps in the subsequent charge redistribution mode.

Similarly, the third conversion step to the nth (final) conversion step are performed, and each capacitor is connected to the positive reference voltage V _H or the negative reference voltage V _L. In this way, an AD converted digital signal can be obtained based on the value of cout (1 or 0) corresponding to each capacitor.

FIG. 14A shows a range of values that the potential V _Cn of the common terminal Cn can take with respect to the reference voltage V _REF in the first conversion step to the n-th conversion step in the sample mode and the charge redistribution mode. In general, the positive reference voltage V _H = VDD (power supply potential), the negative reference voltage V _L = 0V, and V _REF = VDD / 2 are often used. Therefore, the reference voltage V _{REF at} that time is often used. FIG. 14B shows a range of values that the potential V _Cn of the common terminal Cn can take. As shown in FIGS. 14A and 14B, each time the conversion step is advanced, it can be confirmed that the potential V _Cn of the common terminal Cn converges to the reference voltage V _REF and AD conversion proceeds.

However, in such a conventional successive approximation AD converter, when the sample mode is switched to the first conversion step in the charge redistribution mode, the potential V _Cn of the common terminal _Cn is set to the maximum potential [in FIG. V _REF + (V _H −V _L ) / 2, in FIG. 14B, overshoot exceeding VDD], or the potential V _{Cn of the} common terminal is the minimum potential [in FIG. 14A, V _REF − (V _H− V _L ) / 2, and in FIG. 14B, an undershoot lower than 0V] may occur. Overshoot and undershoot occur due to charge loss from the common terminal Cn in the switch SW1 and charge injection to the common terminal Cn, causing AD conversion errors.

  Therefore, in order to reduce an AD conversion error due to overshoot or undershoot, the uppermost capacitor is divided into two and the comparison operation in the first conversion mode is performed twice, so that cout of the uppermost capacitor is obtained. (For example, see Patent Document 1) or the first conversion mode is not performed, and cout of the uppermost capacitor is set to 0 when the input voltage is near the negative reference voltage, and the input voltage is near the positive reference voltage. What is sometimes referred to as 1 (for example, see Patent Document 2) has been proposed.

Japanese Patent Laid-Open No. 11-17543 JP 2007-259224 A

  However, the successive approximation AD converter described in Patent Document 1 has a problem that the conversion time becomes long because the comparison operation in the first conversion mode is performed twice. In the successive approximation AD converter described in Patent Literature 2, it is determined whether or not the input voltage is near the negative reference voltage and whether or not the input voltage is near the positive reference voltage. Since an input voltage determination circuit is necessary, there is a problem that the circuit configuration becomes complicated and power consumption increases. Note that the successive approximation AD converters described in Patent Documents 1 and 2 prevent overshoot and undershoot, but there are no countermeasures that allow overshoot and undershoot.

Further, in the conventional successive approximation AD converter, the positive reference voltage V _H = VDD, the negative reference voltage V _L = 0V, and V _REF = VDD / 2 are often set, and the reference voltage V _REF is accurately set. Therefore, V _REF = (V _H + V _L ) / 2 is set to VDD / 2. However, if V _REF is not exactly VDD / 2, when the amplitude swings to the maximum in the first conversion step, charge loss or injection occurs even if no overshoot or undershoot occurs. Further, if V _REF fluctuates due to noise or the like during the conversion, the accuracy deteriorates. Therefore, it is necessary to generate a stable V _REF, and for this purpose, a high gain amplifier having a low output impedance must be used, which causes a problem of high power. In addition, although it is possible to use a low-power amplifier, there is a problem that it is slow to perform AD conversion with high accuracy because it is susceptible to fluctuations such as noise.

  The present invention has been made paying attention to such problems, and can perform AD conversion at a high speed and with low power consumption with a relatively simple circuit configuration, and is suitable for mounting on a low power microcomputer, and has an overshoot. Another object of the present invention is to provide a successive approximation AD converter capable of suppressing a conversion error due to undershoot. In addition, it is not necessary to generate a reference voltage internally or supply it from the outside, and using a stable reference voltage, it is possible to perform AD conversion with low power, high speed and high accuracy at a low power consumption. It is also an object to provide an apparatus.

In order to achieve the above object, a successive approximation AD converter according to the present invention has one end connected to a common terminal and the other end connected to an input voltage (V _IN ), a positive reference voltage (V _H ), and a negative side, respectively. a reference voltage _{(V L)} is selectively enterable in provided, capacity respectively ^{_{C S, C S / 2 1}} , ···, C S / 2 n-1 of n conversion capacitors (n Is an integer greater than or equal to 2), a comparison unit that compares the potential (V _Cn ) of the common terminal and a reference voltage (V _REF ), and an input of the reference voltage to the common terminal at a stage preceding the comparison unit Is a successive approximation AD converter having a switch that can be turned ON / OFF, the switch being connected to a MOS transistor and one end of which is connected to the substrate voltage (V _PS ) of the MOS transistor, and to the other end. each of said input voltage _{(V IN)} and before Positive reference voltage _{(V H)} and the negative side reference voltage _{(V L)} and a is selectively enterable in provided, capacitance _C P ^{_{respectively, C P / 2 1, ···}} , C P / 2 ^m-1 m board capacitors (m is an integer not smaller than 2 and not larger than n), and when the input voltage is sampled, the reference voltage is input to the common terminal by turning on, and Connecting the substrate voltage and the common terminal, and inputting the input voltage to the other ends of the m capacitors for the substrate of C _P , C _P / 2 ¹ ,..., C _P / 2 ^m−1 , When the successive approximation is performed by the comparison unit, the comparison unit is turned OFF and the connection between the substrate voltage and the common terminal is released, and C _P , C _P / 2 ¹ ,..., C _P / 2 ^m−1 The voltages input to the other ends of the m board capacitors are respectively corresponding C _S , C The connection of the other end of the substrate capacitor is switched so that the voltage is the same as the voltage input to the other ends of the m conversion capacitors of _S / 2 ¹ ,..., C _S / 2 ^m−1. It is configured to be possible.

In the successive approximation type AD converter according to the present invention, in the sample mode for sampling the input voltage and the charge redistribution mode in which the comparison is performed by the comparator, by connecting the same voltage as the other end of the converting capacitor, from sample mode to the m conversion step charge redistribution mode, it can be varied similarly to the variation in potential V _Cn of the common terminal of the substrate voltage V _PS . Thus, the substrate voltage V _PS is, since the overshoot or undershoot at the same timing as the potential V _Cn of the common terminal, not generated injection or extraction of electric charge, to suppress the conversion error due to overshoot or undershoot Can do. As described above, the successive approximation AD converter according to the present invention takes measures against the occurrence of overshoot and undershoot, and has a special circuit configuration as described in Patent Document 1 and Patent Document 2. The AD conversion can be performed at a high speed and with low power consumption with a relatively simple circuit configuration.

In the successive approximation AD converter according to the present invention, the reference voltage is preferably the negative reference voltage. In this case, since a circuit for generating the reference voltage is unnecessary, it is not necessary to generate the reference voltage _VREF internally or supply it from the outside, and a simpler circuit configuration can be achieved. Further, since there is no variation in the reference voltage, it is possible to perform AD conversion with low power, high speed and high accuracy using a stable reference voltage _VREF . In the successive approximation AD converter according to the present invention, the negative reference voltage may be set to 0 V in order to further simplify the circuit configuration.

In the successive approximation AD converter according to the present invention, the number m of the substrate capacitors is such that the amplitude (V _H −V _L ) / 2 ^m−1 of the fluctuation of the potential V _Cn of the common terminal is the forward bias of the MOS transistor. It is preferable that the conversion error is negligible and the conversion error is negligible. For example, m is preferably 3 or more.

In the successive approximation AD converter according to the present invention, the switch operates at a predetermined power supply potential, outputs the power supply potential when the power supply potential is input, and a voltage equal to or lower than the reference voltage when the ground potential is input. A first level shift circuit provided so as to output the first level shift circuit, a gate connected to the output of the first level shift circuit, a drain connected to the substrate voltage, and a source connected to the reference voltage A second MOS transistor having a transistor, a gate connected to the output of the first level shift circuit, a drain connected to the common terminal, and a source connected to the reference voltage; and sampling the input voltage When the input of the first level shift circuit is the power supply potential, the drain and source of the first MOS transistor are connected, When the drain and source of the second MOS transistor are connected and the comparison unit performs successive comparisons, the input of the first level shift circuit is set to the ground potential, and the drain and source of the first MOS transistor are connected to each other. And the connection between the drain and the source of the second MOS transistor may be released. In this case, AD conversion can be performed with a particularly simple circuit configuration at high speed and with low power consumption. In the second MOS transistor, the junction capacitance between the substrate voltage _VPS and the common terminal potential V _Cn is substantially eliminated, so that the parasitic capacitance of the common terminal is reduced and the conversion accuracy can be improved.

  In the case of including the first level shift circuit, the first level shift circuit operates with a low power supply potential lower than the power supply potential, and outputs a ground potential when the power supply potential is input, and outputs the ground potential when the ground potential is input. An inverter unit provided to output a low power supply potential, and when the power supply potential is input to the inverter unit, a ground potential is output, and when the ground potential is input to the inverter unit, the substrate voltage and the ground potential are low. A voltage conversion circuit for outputting one of the potentials, and an output of the inverter unit as an input, connected to the output of the voltage conversion circuit, and outputting the output of the voltage conversion circuit when the ground potential is input, and the low power supply A first shift unit provided to output the low power supply potential when a potential is input, and an output of the first shift unit as an input, to the output of the voltage conversion circuit; And a second shift unit provided to output the power supply potential when the output of the voltage conversion circuit is input and to output the output of the voltage conversion circuit when the low power supply potential is input. It may be. As a result, an element having a low allowable voltage can be used as an element such as a MOS transistor used in the first level shift circuit, and the cost and power consumption can be reduced.

  The voltage conversion circuit has a drain as an output, a gate connected to a ground potential, a source connected to the substrate voltage, a gate connected to the substrate voltage, and a drain connected to the first voltage. And a third MOS transistor having a drain connected to a ground potential and a source connected to a ground potential, and the bulk of the third MOS transistor and the fourth MOS transistor may be floating. . As a result, the bulk potentials of the third MOS transistor and the fourth MOS transistor automatically change to the lower one of the substrate voltage or the ground potential. When the substrate voltage is higher than the ground potential, the ground potential can be output.

  In the case of having the first level shift circuit, it has a fifth MOS transistor in which the input of the first level shift circuit is connected to the gate, the reference voltage is connected to the drain, and the substrate voltage is connected to the source. When sampling the input voltage, the substrate voltage is connected to the reference voltage, and when the successive comparison is performed by the comparison unit, the substrate voltage is connected to the reference voltage in synchronization with the first MOS transistor. And a sixth MOS transistor having a gate connected to the input of the first level shift circuit, a drain connected to the reference voltage, and a source connected to the common terminal When the input voltage is sampled, the common terminal is connected to the reference voltage, and the comparison unit performs a sequential comparison, In synchronization with the second MOS transistor, and a second switching circuit provided so as to release the connection of the common terminal to the reference voltage may have. Thereby, since the first switch circuit performs the same operation as the first MOS transistor, the connection operation and the connection release operation between the reference voltage and the substrate voltage can be performed more reliably. Further, since the second switch circuit performs the same operation as the second MOS transistor, the connection operation and the connection release operation between the reference voltage and the common terminal can be performed more reliably.

  Further, the power supply potential, the low power supply potential, and the ground potential can be selectively connected to the gate, the fifth MOS transistor having the drain connected to the reference voltage and the source connected to the substrate voltage is provided. When the input voltage is sampled, a ground potential is connected to the gate, the substrate voltage is connected to the reference voltage, and the low power supply potential is applied to the gate before proceeding to successive comparison by the comparison unit. A first switch circuit provided to connect the power supply potential to the gate and to release the connection of the substrate voltage to the reference voltage in synchronization with the first MOS transistor; A sixth MOS in which the power supply potential, the low power supply potential, and the ground potential can be selectively connected, the reference voltage is connected to the drain, and the common terminal is connected to the source When the input voltage is sampled, a ground potential is connected to the gate, the common terminal is connected to the reference voltage, and the low voltage is applied to the gate before proceeding to successive comparison by the comparison unit. A second switch circuit provided to connect a power supply potential, further connect the power supply potential to the gate, and release the connection of the common terminal to the reference voltage in synchronization with the second MOS transistor; May be included. As a result, when the fifth MOS transistor and the sixth MOS transistor are switched from ON to OFF, the respective gate voltages can be changed from the ground potential → the low power supply potential → the power supply potential, and the substrate voltage and the common terminal receive. Noise can be suppressed.

  The first switch circuit includes a seventh MOS transistor connected in series with the fifth MOS transistor between the source of the fifth MOS transistor and the substrate voltage. The switch circuit may include an eighth MOS transistor connected in series with the sixth MOS transistor between the source of the sixth MOS transistor and the common terminal. Thereby, since a large voltage is not applied to the elements such as the fifth to eighth MOS transistors, it is possible to use elements having a lower allowable voltage as these elements.

In the case of having the first level shift circuit, when sampling the input voltage, the source of the first MOS transistor and the source of the second MOS transistor are connected to the reference voltage, and the comparison unit sequentially performs comparison. In some cases, a third switch circuit may be provided so as to disconnect the source of the first MOS transistor and the source of the second MOS transistor from the reference voltage. Further, when switching from the sampling state of the input voltage to the state of successive comparison by the comparator, the third switch circuit is switched after the input of the first level shift circuit is switched from the power supply potential to the ground potential. It may be configured. Without the third switch circuit, when the substrate voltage V _PS is higher than the reference voltage V _REF , the source side of the first MOS transistor and the second MOS transistor is forward biased with respect to the bulk, and thus the substrate voltage V _PS Decreases to the reference voltage _VREF . Therefore, by providing the third switch circuit, the substrate voltage V _PS can be higher than the reference voltage V _{REF in} the charge redistribution mode, and the same operation as the common terminal potential V _Cn is possible. Conversion errors can be suppressed.

In the successive approximation type AD converter according to the present invention may be varied similarly to the variation in potential V _Cn of the common terminal of the substrate voltage V _PS, with variations and delay difference and the like characteristics of the elements, the substrate voltage V _PS is The potential may be higher than the potential V _{Cn of the} common terminal. Therefore, in order to lower the substrate voltage V _PS by V _FP during the fluctuation, the switch is configured such that the substrate voltage becomes lower by V _FP [where V _FP > 0] when performing the successive comparison by the comparison unit. May be. This prevents the substrate voltage V _PS is greater than the potential V _Cn of the common terminal, it is possible to suppress the conversion error to prevent the occurrence of implantation or extraction of charge. In this case, it can also be a substrate voltage _{V PS} negatively. For this purpose, for example, by using the Deep-Nwell, be set by setting the potential of the Pwell of N-channel type MOS transistor to the negative Can do.

When the first level shift circuit is included, the switch operates at a predetermined power supply potential, outputs the power supply potential when the power supply potential is input, and outputs a voltage equal to or lower than the reference voltage when the ground potential is input. A second level shift circuit provided to output, a ninth MOS transistor having the gate connected to the output of the second level shift circuit, the drain connected to the substrate voltage, and one end of the ninth MOS transistor When sampling the input voltage with the power storage unit connected to the source of the transistor, the positive reference voltage is connected to the other end of the power storage unit, and when the comparison unit performs successive comparisons, And a fourth switch circuit provided to connect the negative reference voltage to an end, and the second MOS transistor has a gate instead of the first level shift circuit. To the output is connected to the second level shift circuit, when performing the successive approximation by the comparing unit, _[wherein, V _{FP> 0]} The substrate voltage V _FP so as may be configured lower . In this case, it is possible to the substrate voltage V _PS in the variation is prevented from increasing than the potential V _Cn of the common terminal, to suppress the conversion error to prevent the occurrence of implantation or extraction of charge. Further, the first level shift circuit and the second level shift circuit can be moved at different timings.

  When the power storage unit is included, the second level shift circuit may have the same configuration as the first level shift circuit. The second level shift circuit is provided so as to operate with a low power supply potential lower than the power supply potential, to output a ground potential when the power supply potential is input, and to output the low power supply potential when the ground potential is input. And a voltage converter that outputs a ground potential when the power supply potential is input to the inverter unit, and outputs a lower potential of the substrate voltage and the ground potential when the ground potential is input to the inverter unit. And an output of the inverter unit as an input, connected to the output of the voltage conversion circuit, outputs the output of the voltage conversion circuit when the ground potential is input, and outputs the low power supply when the low power supply potential is input A first shift unit provided to output a potential; and an output of the first shift unit is connected to an output of the voltage conversion circuit, and an output of the voltage conversion circuit When input, the power supply potential is output while the fourth switch circuit connects the positive reference voltage to the other end of the power storage unit, and the fourth switch circuit is connected to the other end of the power storage unit. A second shift unit provided to output the low power supply potential while the negative reference voltage is connected and to output the output of the voltage conversion circuit when the low power supply potential is input; You may do it. As a result, an element having a low allowable voltage can be used as an element such as a MOS transistor used in the second level shift circuit, and the cost and power consumption can be reduced. Note that the second level shift circuit may be omitted, and the output of the first level shift circuit may be used as the output of the second level shift circuit.

  The voltage conversion circuit of the second level shift circuit has a drain as an output, a gate connected to a ground potential, a source connected to the substrate voltage, and a gate connected to the substrate voltage. And an eleventh MOS transistor having a drain connected to the drain of the tenth MOS transistor and a source connected to a ground potential, and the bulk of the tenth MOS transistor and the eleventh MOS transistor is It may be floating. As a result, the bulk potentials of the tenth MOS transistor and the eleventh MOS transistor are automatically changed to the lower one of the substrate voltage or the ground potential. When the substrate voltage is higher than the ground potential, the ground potential can be output.

In the case of having a power storage unit, if the capacity of the power storage unit is C _X [where C _X > 0],
C _X = 2 × C _P × (V _FP −V _REF ) / (V _H −V _L + V _REF −V _FP )
It is preferable that Thus, the capacity of the power storage unit can be adjusted to set V _FP to a desired value.

Further, when the power storage unit is included, when the input voltage is sampled, the source of the first MOS transistor and the source of the second MOS transistor are connected to the reference voltage, and the comparison unit sequentially performs comparison. A third switch circuit may be provided to disconnect the source of the first MOS transistor and the source of the second MOS transistor from the reference voltage. As a result, the potential V _Cn of the common terminal varies with reference to the reference voltage V _REF , whereas the substrate voltage V _PS can be varied with reference to V _REF −V _FP . Without the third switch circuit, when the substrate voltage V _PS is larger than the reference voltage V _REF , the source side of the first MOS transistor and the second MOS transistor is forward biased with respect to the bulk. V _PS falls to the reference voltage V _REF . Therefore, by providing the third switch circuit, the substrate voltage V _PS can be higher than the reference voltage V _{REF in} the charge redistribution mode, and the same operation as the common terminal potential V _Cn is possible. Conversion errors can be suppressed.

The first MOS transistor can be connected to a ground potential instead of the reference voltage at a source, and when sampling the input voltage, the source of the first MOS transistor is connected to the ground potential, When the source of the second MOS transistor is connected to the reference voltage and the successive comparison is performed by the comparison unit, the connection of the source of the first MOS transistor to the ground potential is canceled and the second MOS transistor You may have the 3rd switch circuit provided so that the connection to the said reference voltage of the source | sauce of a transistor might be cancelled | released. As a result, the potential V _Cn of the common terminal varies with reference to the reference voltage V _REF , whereas the substrate voltage V _PS can be varied with reference to −V _FP . Without the third switch circuit, when the substrate voltage _VPS is larger than the ground potential, the source side of the first MOS transistor is forward biased with respect to the bulk, so that the substrate voltage _VPS decreases to the ground potential. End up. Further, when the substrate voltage V _PS is higher than the reference voltage V _REF , the source side of the second MOS transistor is forward biased with respect to the bulk, so that the potential V _{Cn of the} common terminal is fixed to the reference voltage V _REF. . Therefore, by providing the third switch circuit, the substrate voltage V _PS can be higher than the reference voltage V _{REF in} the charge redistribution mode, and the common terminal potential V _Cn is fixed to the reference voltage V _REF . is the the can be prevented, because the substrate voltage V _PS is enabled the same operation as the electric potential V _Cn of the common terminal, it is possible to suppress the conversion error.

When switching from the sampling state of the input voltage to the successive approximation state by the comparison unit, the input of the first level shift circuit is switched from the power supply potential to the ground potential, the fourth switch circuit is switched, and the fourth switch circuit is switched. The input of the two-level shift circuit may be switched from the power supply potential to the ground potential, and the third switch circuit may be switched. As a result, the potential V _Cn and the substrate voltage V _PS of the common terminal can be reliably separated from the reference voltage V _REF and the ground potential 0 V, and then can be shifted to the charge redistribution mode. Further, when the input of the second level shift circuit is switched from the power supply potential to the ground potential, the connection between the common terminal by the second MOS transistor and the reference voltage, and the substrate voltage by the ninth MOS transistor. And the connection with the power storage unit may be released at different timings. As a result, it is possible to prevent the noise generated by the release of the connection between the substrate voltage and the power storage unit by the ninth MOS transistor from affecting the potential V _{Cn of the} common terminal.

The successive approximation type AD converter according to the present invention includes m−1 pieces corresponding to m−1 pieces of the substrate capacitors of C _P / 2 ¹ ,..., C _P / 2 ^m−1. Each additional capacitor has a size proportional to the capacity of the corresponding substrate capacitor, one end is grounded, and the other end is connected to the other end of the corresponding substrate capacitor. Also good. In this case, the respective additional capacitor, the size and residence time undershoot of the substrate voltage V _PS, can be larger than the size and residence time undershoot of potential V _Cn of the common terminal, the occurrence of withdrawal of charge It can be surely prevented.

In the successive approximation AD converter according to the present invention, the substrate voltage wiring may be arranged so as to surround the wiring of the common terminal. In this case, the parasitic capacitance in the wiring of the common terminal is almost only the capacitance between the wiring of the substrate voltage, but the potential V _{Cn of the} common terminal and the substrate voltage V _PS fluctuate at substantially the same potential. The capacity becomes very small. Thereby, the conversion error can be reduced and the conversion accuracy can be increased.

  According to the present invention, it is possible to provide a successive approximation AD converter capable of performing AD conversion at a high speed and low power consumption with a relatively simple circuit configuration and capable of suppressing a conversion error due to overshoot or undershoot. Can do. In addition, it is not necessary to generate a reference voltage internally or supply it from the outside, and using a stable reference voltage, it is possible to perform AD conversion with low power, high speed and high accuracy at a low power consumption. An apparatus can also be provided. In addition, it can be used as a low-voltage power supply if a circuit that uses a low-voltage power supply such as logic is mounted on the same chip. It is also possible to provide a successive approximation AD converter that is suitable for realizing a simple SOC.

1A is an overall circuit diagram showing a successive approximation AD converter according to a first embodiment of the present invention, and FIG. 2B is a circuit diagram of a switch S1. 2 is a circuit diagram of a first level shift circuit LS1 of the successive approximation AD converter shown in FIG. FIG. 2 is a sequence diagram showing an operation of a switch S1 of the successive approximation AD converter shown in FIG. 3 is a graph showing fluctuations of a common terminal potential V _Cn , a substrate voltage V _PS and an output voltage V _SX from an output terminal of a first level shift circuit LS1 in the successive approximation AD converter shown in FIG. 1. FIG. 3 is a circuit diagram of (a) a first modified example and (b) a second modified example of the second switch circuit of the successive approximation AD converter shown in FIG. 1. FIG. 6 is a sequence diagram showing an operation of the switch S1 of (a) a first modification of the second switch circuit shown in FIG. 5 and (b) a second modification. It is a circuit diagram of switch S1 which shows the successive approximation type AD converter of the 2nd Embodiment of this invention. FIG. 8 is a circuit diagram of a second level shift circuit LS2 of the successive approximation AD converter shown in FIG. (A) Sequence diagram showing the operation of the switch S1 of the successive approximation AD converter shown in FIG. 7, (b) Switch S1 as a modification of the third switch circuit SW1 of the successive approximation AD converter shown in FIG. It is a sequence diagram which shows the operation | movement of. 8 is a graph showing fluctuations of a common terminal potential V _Cn , a substrate voltage V _PS and an output voltage V _SX from an output terminal of the first level shift circuit LS1 in the successive approximation AD converter shown in FIG. 7. (A) a circuit diagram showing a modification having an additional capacitor of the successive approximation AD converter according to the first and second embodiments of the present invention; (b) a potential V _Cn of a common terminal of the modification, a substrate; voltage _{V PS} and a graph showing the variation of the output voltage _{V SX} from the output terminal of the first level shift circuit LS1. Successive approximation type AD converter of the first and second embodiments of the present invention, so as to surround the wiring of the common terminals Cn, is a circuit diagram showing a modification example in which the wiring of the substrate voltage V _PS. It is a circuit diagram which shows the conventional successive approximation type AD converter. In the conventional successive approximation AD converter shown in FIG. 13, (a) the potential V _Cn of the common terminal Cn with respect to the reference voltage V _REF in the first conversion step to the n-th conversion step in the sample mode and the charge redistribution mode is A graph showing a range of possible values, (b) A graph when the positive reference voltage V _H = VDD (power supply potential), the negative reference voltage V _L = 0V, and V _REF = VDD / 2 in (a). It is.

[Successive Approximation Type AD Converter 10 of First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 to 6 show a successive approximation AD converter according to a first embodiment of the present invention.
As shown in FIG. 1, the successive approximation AD converter 10 according to the first embodiment of the present invention is a single-ended input AD converter having a reference voltage V _REF, and has capacitances C _S and C _S / 2 ¹ ,..., C _S / 2 ⁿ⁻¹ , C _S / 2 ⁿ⁻¹ n + 1 conversion capacitors (n is an integer of 2 or more), and provided for each conversion capacitor , S [0], Sd, a comparison unit CMP, and a switch S1.

Each of the conversion capacitors has one end connected to the common terminal Cn and the other end connected to the corresponding conversion changeover switch. Each of the conversion switches S [n-1], S [n-2],..., S [0] connects the other end of the corresponding conversion capacitor to the input voltage _VIN and the positive reference voltage _VH. And a negative reference voltage _VL are selectively connectable. The conversion switch Sd is provided so that the other end of the corresponding conversion capacitor can be selectively connected to the input voltage _VIN and the negative reference voltage _VL .

The comparison unit CMP includes a comparator, and is provided to compare the potential V _Cn of the common terminal _Cn with the reference voltage V _REF . Switch S1 is in front of the comparison unit CMP, the common terminal Cn and are connected to a reference voltage _{V REF,} is provided to the input of the reference voltage _{V REF} ON / OFF can with respect to the common terminal Cn.
In the following description, the reference voltage V _REF is set to the negative reference voltage _VL .

[Configuration of Switch S1]
As shown in FIG. 1B, the switch S1 includes m + 1 substrates having capacitances C _P , C _P / 2 ¹ ,..., C _P / 2 ^m−1 , C _P / 2 ^m−1 , respectively. Capacitors (m is an integer from 2 to n) and m + 1 substrate switches S [n-1], S [n-2],... Provided corresponding to each substrate capacitor. S [nm], Sd, a first level shift circuit LS1, a first MOS transistor NS0, a second MOS transistor NS1, a first switch circuit 11, a second switch circuit 12, and a third switch circuit SW1. ing.

Each substrate capacitor has one end connected to the substrate voltage V _PS substrate node PS of each MOS transistor, the other end is connected to a corresponding selector switch board. Each board changeover switch S [n-1], S [n-2],..., S [nm] is connected to the other end of the corresponding board capacitor with the input voltage _VIN and the positive reference voltage _VH. And a negative reference voltage _VL are selectively connectable. The board changeover switch Sd is provided so that the other end of the corresponding board capacitor can be selectively connected to the input voltage _VIN and the negative reference voltage _VL .

^{_{Also, C P, C P / 2}} 1, ···, C P / 2 m-1 the substrates capacitor ^{_{of, C S, C S / 2}} 1, ···, of C S ^{/ 2 m-1} Corresponding to each conversion capacitor, each substrate switch S [n-1], S [n-2],..., S [nm], Sd is each conversion switch S [n-1]. , S [n-2],..., S [nm], Sd. The switch S1 is configured to be switched in synchronism with the movement of each conversion switch corresponding to each substrate switch. Accordingly, the switch S1 is configured such that the voltage input to the other end of each substrate capacitor is the same as the voltage input to the other end of each corresponding conversion capacitor.

  As shown in FIG. 2, the first level shift circuit LS1 includes an inverter unit IV1, a voltage conversion circuit 21, a first shift unit 22, and a second shift unit 23. The inverter unit IV1 can selectively input the power supply potential VDD and the ground potential 0V by the switch SW0a. The inverter unit IV1 is operated by a low power supply potential VDDL lower than the power supply potential VDD, and outputs a ground potential 0V when the power supply potential VDD is input, and outputs a low power supply potential VDDL when the ground potential 0V is input. Yes.

The voltage conversion circuit 21 includes a third MOS transistor N20, a fourth MOS transistor N21, a pMOS transistor P20, and two nMOS transistors N22 and N23. The third MOS transistor N20 is composed of an nMOS transistor and has a drain as an output, a gate connected to the ground potential 0V, and a source connected to the substrate voltage _VPS . Fourth MOS transistor N21 has a gate substrate voltage _{V PS} is connected to the drain of the third MOS transistor N20 (output) is connected to the drain is connected to the ground potential 0V to the source. In addition, the third MOS transistor N20 and the fourth MOS transistor N21 have the bulk PS3 floating, so that the potential of the bulk PS3 is automatically reduced to the lower one of the substrate voltage _VPS or the ground potential 0V. It has been changed to.

  P20, N22 and N23 are connected in series in this order. In P20, the inversion of the output of the inverter unit IV1 is connected to the gate, the low power supply potential VDDL is connected to the source, and the drain of N22 is connected to the drain. N22 has a gate connected to the output of inverter IV1, and a source connected to the source of N23 and the drain (output) of third MOS transistor N20. N23 has a drain connected to the ground potential 0V, a gate connected to the drain of P20 and a drain of N22, and a bulk connected to the source of N22.

Thus, when the power supply potential VDD is input to the inverter unit IV1, the voltage conversion circuit 21 is configured such that N23 is turned ON and the ground potential 0V is output. When the ground potential 0V is input to the inverter unit IV1, the voltage conversion circuit 21 causes the substrate voltage _{VPS to} be grounded because the bulk PS3 of the third MOS transistor N20 and the fourth MOS transistor N21 is floating. potential (in fact, the threshold voltage _{V TN)} when: outputs a substrate voltage _{V PS} N20 is turned oN, the substrate voltage _{V PS} is the ground potential (in fact, the threshold voltage _{V TN)} When it is larger, N21 is turned ON and the ground potential 0V is output.

  The first shift unit 22 includes two pMOS transistors P12 and P13, two nMOS transistors N12 and N13, and an inverter. In P12, the inversion of the output of the inverter unit IV1 is connected to the gate, and the low power supply potential VDDL is connected to the source. P13 has a gate connected to the output of the inverter IV1 via the inverter IV3, and a source connected to the low power supply potential VDDL. N12 has a gate connected to the drain of P13, a source connected to the output of the voltage conversion circuit 21, and a drain connected to the drain of P12. N13 has a gate connected to the drain of P12, a source connected to the output of the voltage conversion circuit 21, and a drain connected to the drain of P13. In the first shift unit 22, the drain of P13 is an output.

When the power supply potential VDD is input to the inverter unit IV1, the first shift unit 22 receives the ground potential 0V from the inverter unit IV1 and outputs the output voltage V _PS2 of the voltage conversion circuit 21. Further, when the ground potential 0V is input to the inverter unit IV1, the low power supply potential VDDL is input from the inverter unit IV1, and the low power supply potential VDDL is output. The first shift unit 22 outputs the output voltage V _PS2 of the voltage conversion circuit 21 from the source of N12 and the source of N13.

The second shift unit 23 includes an inverter IV4 connected to the switch SW0a, two pMOS transistors P14 and P15 connected in series with each other, and an nMOS transistor N14. P15 has a gate connected to the output of the inverter IV4 and a source connected to the power supply potential VDD. P14 has a gate connected to the ground potential 0V and a source connected to the drain of P15. The output of the first shift unit 22 is connected to the gate of N14, the source of N12 and the source of N13, that is, the output of the voltage conversion circuit 21, is connected to the source, and the drain of P14 is connected to the drain. The second shift unit 23 has an output terminal SX connected to the drains of P14 and N14. Second shift portion 23, the power supply potential VDD when input the output voltage _{V PS2} of the voltage conversion circuit 21 from the first shift section 22 outputs the output voltage _{V PS2} of the voltage converter circuit 21 when entering the low power supply potential VDDL Is output.

From the above, the first level shift circuit LS1 outputs the power supply potential VDD from the output terminal SX when the power supply potential VDD is input by the switch SW0a, and converts the voltage from the output terminal SX when the ground potential 0V is input by the switch SW0a. When the output voltage V _PS2 of the circuit 21, that is, the substrate voltage V _PS is equal to or lower than the ground potential 0V, the substrate voltage V _PS is output, and when the substrate voltage V _PS is higher than the ground potential 0V, the ground potential 0V is output. .

As shown in FIG. 1B, the first MOS transistor NS0 has the gate connected to the output terminal SX of the first level shift circuit LS1, the drain connected to the substrate voltage _VPS , and the source connected to the third switch circuit. A reference voltage V _REF (= V _L ) is connected via SW1. The second MOS transistor NS1 has a gate connected to the output terminal SX of the first level shift circuit LS1, a drain connected to the common terminal Cn, and a source connected to the reference voltage V _REF (via the third switch circuit SW1). = V _L ) is connected.

Thereby, when the power supply potential VDD is input to the first level shift circuit LS1 and the power supply potential VDD is output, the first MOS transistor NS0 and the second MOS transistor NS1 have their drains and sources connected to each other. The reference voltage V _REF (= V _L ) is input to the common terminal Cn, and the substrate voltage V _PS and the common terminal Cn are connected. In addition, when the ground potential 0V is input to the first level shift circuit LS1 and the output voltage V _PS2 of the voltage conversion circuit 21, that is, the voltage equal to or lower than the reference voltage 0V, is output, the connection between each drain and source is released. The connection between the common terminal Cn and the reference voltage V _REF (= V _L ) is released, and the connection between the substrate voltage V _PS and the common terminal Cn is also released.

As shown in FIG. 1B, the first switch circuit 11 includes an inverter IV5, a fifth MOS transistor PS0, and a seventh MOS transistor PS0a. The fifth MOS transistor PS0 is composed of a pMOS, and has a gate connected to a switch SW0a (input of the first level shift circuit LS1) via an inverter IV5 and a drain connected to a reference voltage V _REF (= V _L ). Yes. MOS transistor PS0a seventh consists pMOS, the ground potential 0V is connected to the gate, drain substrate voltage _{V PS} is connected to the source of the fifth MOS transistor PS0 is connected to the source.

The first switch circuit 11 connects the substrate voltage V _PS to the reference voltage V _REF (= V _L ) when the power supply potential VDD is input by the switch SW0a, and when the ground potential 0V is input by the switch SW0a, The substrate voltage V _PS is disconnected from the reference voltage V _REF (= V _L ) in synchronization with the one MOS transistor NS0.

The second switch circuit 12 includes an inverter IV6, a sixth MOS transistor PS1, and an eighth MOS transistor PS1a. The sixth MOS transistor PS1 is made of pMOS, and has a gate connected to a switch SW0a (input of the first level shift circuit LS1) via an inverter IV6 and a drain connected to a reference voltage V _REF (= V _L ). Yes. The eighth MOS transistor PS1a is made of pMOS, has a gate connected to the ground potential 0V, a drain connected to the common terminal Cn, and a source connected to the source of the sixth MOS transistor PS1.

The second switch circuit 12 connects the common terminal Cn to the reference voltage V _REF (= V _L ) when the power supply potential VDD is input by the switch SW0a, and the second switch circuit 12 receives the second potential when the ground potential 0V is input by the switch SW0a. The connection of the common terminal Cn to the reference voltage V _REF (= V _L ) is released in synchronization with the MOS transistor NS1.

As shown in FIG. 1B, the third switch circuit SW1 includes a reference voltage V _REF (= V _L ), a source of the first MOS transistor NS0, a source of the second MOS transistor NS1, and a fifth MOS. The connection between the drain of the transistor PS0 and the drain of the sixth MOS transistor PS1 is provided so as to be ON / OFF.

[Operation of switch S1]
As shown in FIG. 3, when the switch S1 is in the sample mode for sampling the input voltage _VIN (when the switch S1 is in the ON state), the switch SW0a is set to H (High), and the third switch circuit SW1 is set to H. Keep it. At this time, since the output terminal SX of the first level shift circuit LS1 outputs the power supply potential VDD, it is shared by the first MOS transistor NS0, the second MOS transistor NS1, the first switch circuit 11 and the second switch circuit 12. The reference voltage V _REF (= V _L ) is input to the terminal Cn, and the substrate voltage V _PS and the common terminal Cn are connected. At this time, the input voltage _VIN is input to the other ends of the capacitors for substrates C _P , C _P / 2 ¹ ,..., C _P / 2 ^m−1 , C _P / 2 ^m−1. .

Next, when switching from the sample mode to the charge redistribution mode in which successive comparison is performed by the comparison unit CMP, the switch S1 first switches the switch SW0a from H to L (Low) (circle numeral 1 in FIG. 3). At this time, the output terminal SX of the first level shift circuit LS1 outputs the output V _PS2 of the voltage conversion circuit 21, that is, the lower one of the substrate voltage V _PS and the ground potential 0V. Therefore, the input of the reference voltage V _REF (= V _L ) to the common terminal Cn is released by the first MOS transistor NS0, the second MOS transistor NS1, the first switch circuit 11, and the second switch circuit 12. with, connected to the substrate voltage V _PS and the common terminal Cn is also released.

Next, the switch S1 sets the third switch circuit SW1 to L (circle numeral 3 in FIG. 3). As a result, the connection between the reference voltage V _REF (= V _L ) and the first MOS transistor NS0 and the second MOS transistor NS1 is released, so that the substrate voltage V _PS becomes higher than the reference voltage V _REF (= V _L ). A large potential can be obtained. This also makes it possible to reliably switch to the charge redistribution mode.

During the charge redistribution mode, the voltages input to the other ends of the capacitors for substrates of C _P , C _P / 2 ¹ ,..., C _P / 2 ^m−1 correspond respectively to C _S and C _S. / 2 ^1, ..., so that the C S / 2 the same voltage as the voltage input to the other end of each conversion capacitor ^_m-1, the substrate for the changeover switch S [n-1], S [n -2],..., S [nm], Sd are synchronized with the movements of the corresponding conversion switches S [n-1], S [n-2], ..., S [nm], Sd. To switch. At this time, the output terminal SX of the first level shift circuit LS1 outputs the lower potential of the output V _PS2 of the voltage conversion circuit 21, that is, the substrate voltage V _PS and the ground potential 0 V (in the case of FIG. 2). In addition, the state where the input of the reference voltage V _REF (= V _L ) to the common terminal Cn is maintained, and the state where the connection between the substrate voltage V _PS and the common terminal Cn is also released is maintained.

Variations in the potential V _Cn of the common terminal _Cn , the substrate voltage V _PS , and the output voltage V _SX from the output terminal SX of the first level shift circuit LS1 in the sample mode and the charge redistribution mode due to the operation of the switch S1 described above. An example is shown in FIG.

[Operational effect of successive approximation AD converter 10]
In the successive approximation type AD converter 10, in the sample mode for sampling the input voltage and the charge redistribution mode in which the comparison unit CMP performs successive comparison, the other end of each corresponding conversion capacitor is connected to the other end of each corresponding substrate capacitor. for connecting the same voltage as, as shown in FIG. 4, from sample mode to the m conversion step charge redistribution mode, varying the substrate voltage V _PS like the variation of the potential V _Cn of the common terminal Cn it can. Thus, the substrate voltage V _PS is, since the overshoot or undershoot at the same timing as the potential V _Cn of the common terminal Cn, not generated injection or extraction of electric charge and suppresses conversion error due to overshoot or undershoot be able to. In this way, the successive approximation AD converter 10 is to take measures against the occurrence of overshoot and undershoot, and add a special circuit configuration as described in Patent Document 1 or Patent Document 2. Therefore, AD conversion can be performed at a high speed and with low power consumption with a relatively simple circuit configuration.

Since the successive approximation AD converter 10 uses the reference voltage V _REF = V _L , a circuit for generating the reference voltage V _REF is not necessary. Therefore, it is not necessary to generate the reference voltage V _REF internally or supply it from the outside, and a simpler circuit configuration can be achieved. Further, since the variation in the reference voltage V _REF is eliminated, by using a stable reference voltage V _REF, at low power, it is possible to perform AD conversion at a high speed and with high accuracy.

Successive approximation type AD converter 10, the second MOS transistor NS1, since the junction capacitance between the substrate voltage _{V PS} and the potential _{V Cn} of the common terminal Cn is substantially eliminated, small parasitic capacitance of the common terminal Cn Thus, the conversion accuracy can be increased. Further, in the successive approximation type AD converter 10, if the third switch circuit SW1 is not provided, the first MOS transistor NS0 and the second MOS transistor when the substrate voltage V _PS is higher than the reference voltage V _REF (= V _L ). Since the NS1 source side is forward-biased with respect to the bulk, the substrate voltage V _PS drops to the reference voltage V _REF (= V _L ). Therefore, by providing the third switch circuit SW1, the substrate voltage V _PS can be higher than the reference voltage V _REF (= V _L ) in the charge redistribution mode, and the potential V _{Cn of the} common terminal Cn Since the same operation is possible, conversion errors can be suppressed.

In the successive approximation AD converter 10, since the first level shift circuit LS1 uses the low power supply potential VDDL, an allowable voltage is used as an element such as a MOS transistor used in the first level shift circuit LS1. A low one can be used, and a low price and low power consumption can be achieved. For example, the maximum voltage applied to P12, P13, N12, and N13 of the first shift unit 22 is VDDL− [V _REF − (V _H −V _L ) / 2] + V _UN (undershoot potential), and V _REF When = V _L = 0V, VDDL + V _H / 2 + V _UN is obtained. Here, when VDDL = 1V and _VH = VDD = 3V, the maximum voltage is 2.5V + _VUN , and a MOS transistor having a withstand voltage of 3V can be used. In the sample mode, when the input from the switch SW0a is VDD (period before the circled number 1 in FIG. 3), the output from the output terminal SX of the second shift unit 23 is VDD, and the substrate voltage _VPS is the ground potential. Since it is 0V, the maximum voltage applied to P14, P15, and N14 of the second shift unit 23 is VDD. For this reason, when VDD = 3V, a MOS transistor having a withstand voltage of 3V can be used.

In addition, due to the configuration of the first switch circuit 11 and the second switch circuit 12, the elements such as the fifth MOS transistor PS0, the sixth MOS transistor PS1, the seventh MOS transistor PS0a, and the eighth MOS transistor PS1a are greatly increased. Since no voltage is applied, it is possible to use a device having a lower allowable voltage as these elements, and to reduce the cost and power consumption. For example, even when the potential V _Cn <0 and the substrate voltage V _PS <0 in the common terminal Cn in the charge redistribution mode (period after the circled numeral 3 in FIG. 3), the seventh MOS transistor PS0a and the eighth the potential of the source of the MOS transistor PS1a is maintained at approximately the threshold voltage _{V TP} is also low. Therefore, the maximum voltage applied to the fifth MOS transistor PS0 and the sixth MOS transistor PS1 is VDD, and the maximum voltage applied to the seventh MOS transistor PS0a and the eighth MOS transistor PS1a is V _TP − [V _REF − ( _VH− V _L ) / 2] + V _UN , and when V _REF = V _L = 0V, V _TP + V _H / 2 + V _UN . Therefore, for example, when V _H = VDD = 3 V, the maximum voltages are 3 V and about 2.2 V + V _FP , respectively, and a MOS transistor having a withstand voltage of 3 V can be used.

In the successive approximation AD converter 10, the number m + 1 of capacitors for each substrate is such that the amplitude (V _H −V _L ) / 2 ^m−1 of the fluctuation of the potential V _Cn of the common terminal Cn is based on the forward bias of the MOS transistor. Is preferably such that the conversion error is negligible. For example, m is preferably 3 or more.

[Modification of First Switch Circuit 11 and Second Switch Circuit 12]
As shown in FIG. 5A, the first switch circuit 11 and the second switch circuit 12 do not have an inverter, and are connected in series to each other, a pMOS transistor P17 and an nMOS transistor N15, a pMOS transistor P18, and a NAND circuit. NA1 may be included. Although only the second switch circuit 12 is shown in FIG. 5, the first switch circuit 11 has the same configuration.

  In P17, the switch SW0b is connected to the gate, and the power supply potential VDD is connected to the source. N15 has a gate connected to the switch SW0a, a source connected to the drain of P17, and a drain connected to the ground potential 0V. P18 has a gate connected to the output of NAND circuit NA1, a source connected to low power supply potential VDDL, a drain connected to P17 and the fifth MOS transistor PS0 (in the case of first switch circuit 11) or a sixth MOS. The gate of the transistor PS1 (in the case of the second switch circuit 12) is connected. The NAND circuit NA1 is connected with an inverted signal of the switch SW0a and the switch SW0b as inputs.

As shown in FIG. 6A, the first switch circuit 11 and the second switch circuit 12 are in the sample mode while the switch SW0a is connected to the power supply potential VDD (from the circled number 1 in FIG. 6A). In the previous period), the ground potential 0V is connected to the gates of the fifth MOS transistor PS0 and the sixth MOS transistor PS1, the substrate voltage V _PS is connected to the reference voltage V _REF (= V _L ), and the reference The common terminal Cn is connected to the voltage V _REF (= V _L ). In addition, while the switch SW0a is connected to the ground potential 0V and the switch SW0b is H (period 1 to 2 in FIG. 6A), the gates of the fifth MOS transistor PS0 and the sixth MOS transistor PS1 are used. Are connected to a low power supply potential VDDL. Further, while the switch SW0b is L (period after the circled number 2 in FIG. 6A), the power supply potential VDD is connected to the gates of the fifth MOS transistor PS0 and the sixth MOS transistor PS1, and the reference voltage is set. with disconnect the substrate voltage _{V PS} to _{V REF} (= V _L), is configured to disconnect the common terminal Cn to the reference voltage _V REF (= _{V L).}

Thus, when the first switch circuit 11 and the second switch circuit 12 switch the fifth MOS transistor PS0 and the sixth MOS transistor PS1 from ON to OFF, the respective gate voltages are changed from 0V → VDDL → VDD. And the noise received by the substrate voltage _VPS and the common terminal Cn can be suppressed. Even in the case shown in FIG. 5 (a), like the first switch circuit 11 and the second switch circuit 12 shown in FIG. 1, it is possible to use a MOS transistor having a low allowable voltage, which is low in price and low in power consumption. Can be.

As shown in FIG. 5B, the first switch circuit 11 and the second switch circuit 12 are connected to the inverter IV5 (first switch circuit 11) at the gates of the fifth MOS transistor PS0 and the sixth MOS transistor PS1, respectively. ) Or the inverter SW6 (in the case of the second switch circuit 12), the switch SW0b may be connected. In this case, as shown in FIG. 6B, while the switch SW0b is H (period before the circled number 2 in FIG. 6B), the fifth MOS transistor PS0 and the sixth MOS transistor PS1 A ground potential of 0 V can be connected to the gate. In addition, while the switch SW0b is L (period after the circled number 2 in FIG. 6B), the fifth MOS transistor PS0 and the sixth MOS are the same as in FIGS. 5A and 6A. The power supply potential VDD is connected to the gate of the transistor PS1, so that the connection of the substrate voltage V _PS to the reference voltage V _REF (= V _L ) is released and the common terminal Cn to the reference voltage V _REF (= V _L ) The connection can be released.

[Successive Approximation Type AD Converter 30 of Second Embodiment]
7 to 10 show the successive approximation AD converter 30 according to the second embodiment of the present invention.
Similar to the successive approximation AD converter 10 of the first embodiment of the present invention, the successive approximation AD converter 30 of the second embodiment of the present invention has a single-ended input having a reference voltage V _REF. a of the AD converter, capacity respectively ^{_{C S, C S / 2 1}} , ···, C S / 2 n-1, C S / 2 n-1 of the n + 1 of the converting capacitor (n is 2 or more And (n + 1) conversion switches S [n-1], S [n-2],..., S [0], Sd provided corresponding to each conversion capacitor. It has a part CMP and a switch S1. In the following description, the same components as those of the successive approximation AD converter 10 according to the first embodiment of the present invention are denoted by the same reference numerals, and redundant description is omitted.

[Configuration of Switch S1]
As shown in FIG. 7, the switch S <b> ¹ includes m + 1 board capacitors of C _P , C _P / 2 ¹ ,..., C _P / 2 ^m−1 , C _P / 2 ^m−1 and each board. , S [n-2],..., S [nm], Sd, and the first level shift circuit LS1 and The two-level shift circuit LS2, the first MOS transistor NS0, the second MOS transistor NS1, the first switch circuit 11, the second switch circuit 12, the third switch circuit SW1, the ninth MOS transistor NS2, and the capacitance C _X Power storage unit and a fourth switch circuit SW2. Further, the switch S1, using the Deep-Nwell, by setting the potential of the Pwell negatively, and setting the substrate voltage _{V PS} of built-MOS transistors (nMOS and pMOS) negative. Specifically, the substrate voltage V _{PS is set} to −V _FP [where V _FP > 0].

  As shown in FIG. 8, the second level shift circuit LS2 has the same configuration as the first level shift circuit LS1 shown in FIG. 2 except for the following points. That is, the voltage conversion circuit 21 has an inverter part IV2. The output of the inverter part IV2 is connected to the gate of P20, and the output of the inverter part IV2 is connected to the gate of N22. The inverter part IV2 has the same configuration as the inverter part IV1 except that it is switched by the switch SW0b.

In the second shift unit 23, the inverter IV4 is connected to the switch SW0b, and includes a pMOS transistor P16 and a NAND circuit NA2. In P16, the output of the NAND circuit NA2 is connected to the gate, the low power supply potential VDDL is connected to the source, and the drain of P14 is connected to the drain. The NAND circuit NA2 is connected with the inverted signal of the switch SW0b and the switch SW0c as inputs. Second shift unit 23, when receiving the output voltage _{V PS2} of the voltage conversion circuit 21 from the first shift portion 22, SW0b outputs the power source potential VDD by H, and outputs the low power supply potential VDDL SW0b is at L, when you enter the low power supply potential VDDL from the first shift portion 22, and outputs the output voltage V _PS2 of the voltage conversion circuit 21.

From the above, when the power supply potential VDD is input by the switch SW0c, the second level shift circuit LS2 outputs the power supply potential VDD when SW0b is H and the low power supply potential VDDL when SW0b is L and output from the output terminal SX1. It has become. Also, when inputting the ground potential 0V by the switch SW0c, the output voltage _{V PS2,} i.e. substrate voltage _{V PS} of the voltage conversion circuit 21 from the output terminal SX1 outputs a substrate voltage _{V PS} when: the ground potential 0V, the substrate voltage V _{When PS} is larger than the ground potential 0V, the ground potential 0V is output.

As shown in FIG. 7, the ground potential 0V is connected to the source of the first MOS transistor NS0 via the third switch circuit SW1 instead of the reference voltage _VREF . The second MOS transistor NS1 has a gate connected to the output terminal SX1 of the second level shift circuit LS2 instead of the first level shift circuit LS1. The second switch circuit 12 has a configuration shown in FIG.

The third switch circuit SW1 includes a switch sh2 provided so that the connection between the reference voltage V _REF (= V _L ) and the source of the second MOS transistor NS1 and the drain of the sixth MOS transistor PS1 can be turned on / off. The switch sh3 is provided so that the connection between the ground potential 0V and the source of the first MOS transistor NS0 and the drain of the fifth MOS transistor PS0 can be turned on / off. The switch sh2 and the switch sh3 perform the same operation.

As shown in FIG. 7, MOS transistor NS2 The ninth output terminal SX1 of the second level shift circuit LS2 is connected to the gate, the substrate voltage _{V PS} is connected to the drain. One end of the power storage unit of the capacitor _CX is connected to the source of the ninth MOS transistor NS2. The power storage unit sets the capacity C _X to C _X = 2 × C _P × (V _FP −V _REF ) / (V _H −V _L + V _REF −V _FP ) = 2C _P (V _FP −V _L ) / (V _H− V _FP ). The fourth switch circuit SW2 operates in the same manner as the switch SW0b, and is provided so that the positive reference voltage _VH and the negative reference voltage _VL can be selectively connected to the other end of the power storage unit.

[Operation of switch S1]
As shown in FIG. 9A, when the switch S1 is in the sample mode for sampling the input voltage _VIN (when the switch S1 is in the ON state), the switches SW0a, SW0b, and SW0c are set to H, and the third switch circuit SW1 (sh2 and sh3) and the fourth switch circuit SW2 are set to H. At this time, since the output terminal SX of the first level shift circuit LS1 and the output terminal SX1 of the second level shift circuit LS2 output the power supply potential VDD, the first MOS transistor NS0 and the first switch circuit 11 cause the substrate voltage V _{While PS} becomes the ground potential 0V, the reference voltage V _REF (= V _L ) is input to the common terminal Cn by the second MOS transistor NS1 and the second switch circuit 12. At this time, the input voltage _VIN is input to the other ends of the capacitors for substrates C _P , C _P / 2 ¹ ,..., C _P / 2 ^m−1 , C _P / 2 ^m−1. At the same time, the positive reference voltage _VH is connected to the other end of the power storage unit of the capacitor _CX by the fourth switch circuit SW2.

Next, when switching from the sample mode to the charge redistribution mode in which successive comparison is performed by the comparison unit CMP, the switch S1 first switches the switch SW0a from H to L (circled number 1 in FIG. 9A). At this time, since the output terminal SX of the first level shift circuit LS1 outputs the ground potential 0V, the substrate voltage _VPS is released from the ground potential 0V by the first MOS transistor NS0 and the first switch circuit 11.

Next, the switch S1 switches the fourth switch circuit SW2 and the switch SW0b from H to L (circle numeral 2 in FIG. 9A). At this time, the negative reference voltage V _L is connected to the other end of the power storage unit of the capacitor C _X. Before and after the switching, since the total charge Q _P at the substrate node PS is stored,
_{Q P = -2C P V IN -C} X V H = 2C P (V PS -V IN) + C X (V PS -V L)
And the substrate voltage V _PS is
V _PS = −C _X (V _H −V _L ) / (2C _P + C _X )
It becomes. Here, substituting C _X = 2C _P (V _FP −V _L ) / (V _H −V _FP ),
V _PS = −V _FP
It becomes.

At this time, the output terminal SX of the first level shift circuit LS1 outputs the substrate voltage V _PS (= −V _FP ), and the output terminal SX1 of the second level shift circuit LS2 outputs the low power supply potential VDDL. .

Next, the switch S1 switches the switch SW0c from H to L (circle numeral 3 in FIG. 9A). At this time, since the output terminal SX1 of the second level shift circuit LS2 outputs the substrate voltage V _PS (= −V _FP ), the reference to the common terminal Cn is set by the second MOS transistor NS1 and the second switch circuit 12. The connection of the voltage V _REF (= V _L ) is released. Similarly, the power storage unit having the capacitor _CX is separated from the substrate node PS by the ninth MOS transistor NS2. Thus, in the subsequent charge redistribution mode, the substrate voltage _{V PS} is ^{_{C P, C P / 2 1}} , ···, to become as determined by C P ^{/ 2 m-1} the substrates for capacitors, accurate The substrate voltage _VPS can be obtained.

Next, the switch S1 sets the third switch circuit SW1 to L (circle numeral 4 in FIG. 9A). As a result, the connection between the reference voltage V _REF (= V _L ) and the second MOS transistor NS1 and the connection between the ground potential 0V and the first MOS transistor NS0 are released, so that the substrate voltage V _PS is grounded. The potential V _Cn is prevented from being fixed to the potential 0 V, and the potential V Cn of the common terminal Cn is prevented from being fixed to the reference voltage V _REF (= V _L ). This also allows switching to the charge redistribution mode.

During the charge redistribution mode, the voltages input to the other ends of the capacitors for substrates of C _P , C _P / 2 ¹ ,..., C _P / 2 ^m−1 correspond respectively to C _S and C _S. / 2 ^1, ..., so that the C S / 2 the same voltage as the voltage input to the other end of each conversion capacitor ^_m-1, the substrate for the changeover switch S [n-1], S [n -2],..., S [nm], Sd are synchronized with the movements of the corresponding conversion switches S [n-1], S [n-2], ..., S [nm], Sd. To switch.

Variations in the potential V _Cn of the common terminal _Cn , the substrate voltage V _PS , and the output voltage V _SX from the output terminal SX of the first level shift circuit LS1 in the sample mode and the charge redistribution mode due to the operation of the switch S1 described above. An example is shown in FIG.

[Operational effect of successive approximation AD converter 30]
The successive approximation AD converter 30 can reduce the substrate voltage V _PS by V _FP when performing the successive approximation by the comparison unit CMP (actually, after the circled number 2 in FIG. 9A). as shown in FIG. 10, from the sample mode to the m conversion step charge redistribution mode, the substrate voltage V _PS in lower position by V _FP than the potential V _Cn of the common terminal, a change in the potential V _Cn of the common terminal It can be varied as well. Accordingly, reliably than the successive approximation type AD converter 10 of the first embodiment, it can prevent the substrate voltage V _PS is greater than the potential V _Cn of the common terminal, the charge injection and extraction of the generator Conversion error can be suppressed.

  The successive approximation AD converter 30 has a configuration in which the second level shift circuit LS2 uses the low power supply potential VDDL, like the first level shift circuit LS1 shown in FIG. 2 and the circuit shown in FIG. Therefore, an element having a low allowable voltage can be used as an element such as a MOS transistor used in the second level shift circuit LS2, so that the price and power consumption can be reduced.

[Modification of Second Level Shift Circuit LS2]
The second level shift circuit LS2 may have the same configuration as the first level shift circuit LS1. In this case, similarly to the switch S1 shown in FIG. 1B, the first level shift circuit LS1 and the second level shift circuit LS2 are formed of one circuit, and the output of the circuit is sent to the first level shift circuit. You may use as an output of LS1 and 2nd level shift circuit LS2. Further, the first level shift circuit LS1 and the second level shift circuit LS2 may be composed of separate circuits, and the first level shift circuit LS1 and the second level shift circuit LS2 may be moved at different timings.

The second level shift circuit LS2 may be configured to turn off the second MOS transistor NS1 and the ninth MOS transistor NS2 at different timings. In particular, it is preferable to turn off the ninth MOS transistor NS2 before the second MOS transistor NS1. In this case, for example, the second level shift circuit LS2 is composed of two, which are respectively connected to the second MOS transistor NS1 and the ninth MOS transistor NS2 and are turned off at different timings. In addition, a delay circuit may be provided between the output terminal SX1 of the two-level shift circuit LS2 and the second MOS transistor NS1 or the ninth MOS transistor NS2. When the second MOS transistor NS1 and the ninth MOS transistor NS2 are turned off simultaneously, the noise at the substrate node PS generated by turning off the ninth MOS transistor NS2 affects the potential V _Cn of the common terminal Cn, resulting in an error. It becomes the cause of. Therefore, by turning OFF the second MOS transistor NS1 and ninth MOS transistors NS2 at different timings, the noise of the substrate node PS can be prevented from affecting the electric potential _{V Cn} of the common terminal Cn.

[Modification of Third Switch Circuit SW1]
Similarly to the switch S1 shown in FIG. 1B, the third switch circuit SW1 includes the reference voltage V _REF (= V _L ), the source of the first MOS transistor NS0, the source of the second MOS transistor NS1, The connection between the drain of the fifth MOS transistor PS0 and the drain of the sixth MOS transistor PS1 may be provided so as to be ON / OFF. Thereby, the potential V _Cn of the common terminal fluctuates with reference to the reference voltage V _REF (= V _L ), whereas the substrate voltage V _PS is changed with reference to V _REF −V _FP (= V _L −V _FP ). Can be varied.

In this case, as shown in FIG. 9 (b), when switching the switch SW0b from H to L (circled number 2 in FIG. 9 (b)), the substrate voltage _{V PS is} a V L _{-V FP.} For this reason, when the switch SW0b is switched from H to L (circle numeral 2 in FIG. 9B), the output terminal SX of the first level shift circuit LS1 is V _L −V _FP <0 [actually , −V _TN (threshold voltage)], V _L −V _FP is output, and when V _L −V _FP ≧ 0 [actually −V _TN (threshold voltage)], 0 V is output. Can be output. Further, when the switch SW0c is switched from H to L (circle numeral 3 in FIG. 9B), the output terminal SX1 of the second level shift circuit LS2 becomes V _L −V _FP <0 [actually, When -V _TN (threshold voltage)], V _L -V _FP is output, and when V _L -V _FP ≧ 0 [actually -V _TN (threshold voltage)], 0 V is output. can do.

  Note that the successive approximation AD converter 10 uses the third switch circuit SW1 shown in FIG. 7 as the third switch circuit SW1, and the third MOS circuit NS0 is connected to the third switch circuit SW1 as in FIG. The ground potential 0V may be connected via the switch circuit SW1.

[Modifications of the successive approximation AD converter 10 and the successive approximation AD converter 30]
As shown in FIG. 11 (a), the switch S1 corresponds to m substrate capacitors of C _P / 2 ¹ ,..., C _P / 2 ^m−1 , C _P / 2 ^m−1. additional capacitance of m-1 pieces provided ^{_{C PP / 2 1, ···,}} C PP / 2 m-1, has a C PP ^{/ 2 m-1,} each additional capacitor is the corresponding capacitor substrate The other end of the substrate capacitor may be connected to the other end of the corresponding substrate capacitor.

An example of fluctuations in the potential V _Cn of the common terminal Cn, the substrate voltage V _PS , and the output voltage V _SX from the output terminal SX of the first level shift circuit LS1 in the sample mode and the charge redistribution mode in this case is shown in FIG. 11 (b). As shown in FIG. 11 (b), each additional capacitor, the size and residence time undershoot of the substrate voltage V _PS, be larger than the size and residence time undershoot of potential V _Cn of the common terminal Cn (See the portion surrounded by a circle in FIG. 11B), and it is possible to more reliably prevent the occurrence of charge extraction. In particular, it is effective when used in the successive approximation AD converter 10 of the first embodiment.

Further, as shown in FIG. 12, successive approximation type AD converter 10 and the successive approximation type AD converter 30, so as to surround the wiring of the common terminals Cn, it may be disposed wiring substrate voltage V _PS is. In this case, the wiring of the substrate voltage V _PS, it is preferable to cover as much as possible vertical and lateral wires of the common terminal Cn. At this time, the parasitic capacitance C _gamma in the wiring of the common terminals Cn, but is only the capacitance between the almost substrate voltage V _PS wiring, the potential V _Cn and the substrate voltage V _PS common terminal at approximately the same potential to change the parasitic capacitance C _gamma becomes very small. Thereby, the conversion error can be reduced and the conversion accuracy can be increased.

DESCRIPTION OF SYMBOLS 10 Successive approximation type AD converter 11 1st switch circuit 12 2nd switch circuit 21 Voltage conversion circuit 22 1st shift part 23 2nd shift part

30 successive approximation AD converter

LS1 first level shift circuit LS2 second level shift circuit NS0 first MOS transistor NS1 second MOS transistor N20 third MOS transistor N21 fourth MOS transistor PS0 fifth MOS transistor PS1 sixth MOS transistor PS0a second MOS transistor PS0a 7 MOS transistor PS1a 8th MOS transistor NS2 9th MOS transistor

S [n-1], S [n-2], ..., S [0], Sd conversion selector switch S [n-1], S [n-2], ..., S [nm] , Sd substrate changeover switch CMP comparator S1, SW0a, SW0b, SW0c, sh2, sh3 switch SW1 third switch circuit SW2 fourth switch circuit P12 to P18, P20 pMOS transistors N12 to N15, N22, N23 nMOS transistors IV1, IV2 Inverter part IV3, IV4, IV5, IV6 Inverter NA1, NA2 NAND circuit

Claims (23)

One end is connected to a common terminal, and the other end is provided with a capacitor capable of selectively inputting an input voltage (V _IN ), a positive reference voltage (V _H ), and a negative reference voltage (V _L ), respectively. C _S , C _S / 2 ¹ ,..., C _S / 2 ⁿ⁻¹ n conversion capacitors (n is an integer of 2 or more), the potential (V _Cn ) of the common terminal, and a reference voltage A successive approximation AD converter having a comparison unit that compares (V _REF ) and a switch that is provided in a preceding stage of the comparison unit so that the input of the reference voltage can be turned on / off with respect to the common terminal. There,
The switch is
The MOS transistor has one end connected to the substrate voltage (V _PS ) of the MOS transistor and the other end connected to the input voltage (V _IN ), the positive reference voltage (V _H ), and the negative reference voltage (V _{L), respectively.} ), And M capacitors for substrates having capacitances C _P , C _P / 2 ¹ ,..., C _P / 2 ^m−1 (m is 2 to n) Integer), and
When sampling the input voltage, the reference voltage is turned on to input the reference voltage to the common terminal, and the substrate voltage and the common terminal are connected to each other, and C _P , C _P / 2 ¹ ,. _The input voltage is input to the other end of the m number of capacitors for the substrate of _P / 2 ^m−1 .
When the successive approximation is performed by the comparison unit, the comparison unit is turned OFF and the connection between the substrate voltage and the common terminal is released, and C _P , C _P / 2 ¹ ,..., C _P / 2 ^m−1 In addition to the m conversion capacitors of C _S , C _S / 2 ¹ ,..., C _S / 2 ^m−1 , the voltages input to the other ends of the m capacitors for the substrate are respectively corresponding. A successive approximation AD converter characterized in that the connection of the other end of the substrate capacitor can be switched so as to be the same voltage as the voltage inputted to the end.   2. The successive approximation AD converter according to claim 1, wherein the reference voltage is the negative reference voltage.   3. The successive approximation AD converter according to claim 1, wherein the negative reference voltage is 0V. The switch is
A first level shift circuit provided to operate at a predetermined power supply potential, to output the power supply potential when the power supply potential is input, and to output a voltage equal to or lower than the reference voltage when the ground potential is input;
A first MOS transistor having a gate connected to the output of the first level shift circuit, a drain connected to the substrate voltage, and a source connected to the reference voltage;
A second MOS transistor having a gate connected to the output of the first level shift circuit, a drain connected to the common terminal, and a source connected to the reference voltage;
When sampling the input voltage, the input of the first level shift circuit is set to the power supply potential, the drain and source of the first MOS transistor are connected, and the drain and source of the second MOS transistor are connected. connection,
When performing the successive comparison by the comparator, the input of the first level shift circuit is set to the ground potential, the connection between the drain and the source of the first MOS transistor is released, and the drain of the second MOS transistor The successive approximation AD converter according to any one of claims 1 to 3, wherein the connection between the source and the source is released. The first level shift circuit includes:
An inverter unit provided to operate with a low power supply potential lower than the power supply potential, to output a ground potential when the power supply potential is input, and to output the low power supply potential when a ground potential is input;
A voltage conversion circuit that outputs a ground potential when the power supply potential is input to the inverter unit, and outputs a lower potential of the substrate voltage and the ground potential when a ground potential is input to the inverter unit;
The output of the inverter unit is input, connected to the output of the voltage conversion circuit, the output of the voltage conversion circuit is output when the ground potential is input, and the low power supply potential is output when the low power supply potential is input A first shift unit provided to
The output of the first shift unit is input, connected to the output of the voltage conversion circuit, the power supply potential is output when the output of the voltage conversion circuit is input, and the voltage conversion circuit is input when the low power supply potential is input A second shift unit provided to output the output of
5. The successive approximation AD converter according to claim 4, further comprising: The voltage conversion circuit includes:
A third MOS transistor having a drain as an output, a gate connected to a ground potential, and a source connected to the substrate voltage;
A fourth MOS transistor having a gate connected to the substrate voltage, a drain connected to the drain of the third MOS transistor, and a source connected to a ground potential;
6. The successive approximation AD converter according to claim 5, wherein bulks of the third MOS transistor and the fourth MOS transistor are floating. A fifth MOS transistor having a gate connected to an input of the first level shift circuit, a drain connected to the reference voltage, and a source connected to the substrate voltage; When the substrate voltage is connected to a reference voltage, and the successive comparison is performed by the comparison unit, the connection of the substrate voltage to the reference voltage is released in synchronization with the first MOS transistor. 1 switch circuit,
A sixth MOS transistor having a gate connected to the input of the first level shift circuit, a drain connected to the reference voltage, and a source connected to the common terminal; A second terminal provided to disconnect the connection of the common terminal to the reference voltage in synchronization with the second MOS transistor when the common terminal is connected to a reference voltage and the comparison unit performs successive comparisons; Switch circuit,
The successive approximation AD converter according to claim 4, wherein the successive approximation AD converter is provided. The power supply potential, the low power supply potential, and the ground potential can be selectively connected to the gate, the reference voltage is connected to the drain, and the substrate voltage is connected to the source. When sampling the input voltage, a ground potential is connected to the gate, the substrate voltage is connected to the reference voltage, and the low power supply potential is connected to the gate before proceeding to successive comparison by the comparison unit. A first switching circuit provided to connect the power supply potential to the gate and to release the connection of the substrate voltage to the reference voltage in synchronization with the first MOS transistor;
The power supply potential, the low power supply potential, and the ground potential can be selectively connected to the gate, the reference voltage is connected to the drain, and the sixth MOS transistor is connected to the common terminal. When sampling the input voltage, the ground potential is connected to the gate, the common terminal is connected to the reference voltage, and the low power supply potential is connected to the gate before shifting to the successive approximation by the comparison unit. A second switch circuit provided to connect the power supply potential to the gate and to release the connection of the common terminal to the reference voltage in synchronization with the second MOS transistor;
The successive approximation AD converter according to claim 4, wherein the successive approximation AD converter is provided. The first switch circuit includes a seventh MOS transistor connected in series with the fifth MOS transistor between the source of the fifth MOS transistor and the substrate voltage.
The second switch circuit includes an eighth MOS transistor connected in series with the sixth MOS transistor between the source of the sixth MOS transistor and the common terminal. The successive approximation AD converter according to claim 7 or 8.   When sampling the input voltage, the source of the first MOS transistor and the source of the second MOS transistor are connected to the reference voltage, and when the comparison unit performs successive comparisons, The sequential switch according to any one of claims 4 to 9, further comprising a third switch circuit provided to disconnect the source and the source of the second MOS transistor from the reference voltage. Comparative AD converter.   When switching from the sampling state of the input voltage to the successive approximation state by the comparator, the third switch circuit is switched after the input of the first level shift circuit is switched from the power supply potential to the ground potential. The successive approximation AD converter according to claim 10, wherein 12. The switch according to claim 1, wherein the substrate voltage is configured to be lower by V _FP [where V _FP > 0] when the comparison unit performs successive comparisons. The successive approximation AD converter according to the item. The switch is
A second level shift circuit provided to operate at a predetermined power supply potential, to output the power supply potential when the power supply potential is input, and to output a voltage equal to or lower than the reference voltage when the ground potential is input;
A ninth MOS transistor having a gate connected to the output of the second level shift circuit and a drain connected to the substrate voltage;
A power storage unit having one end connected to the source of the ninth MOS transistor;
When sampling the input voltage, connect the positive reference voltage to the other end of the power storage unit, and connect the negative reference voltage to the other end of the power storage unit when performing sequential comparison by the comparison unit. A fourth switch circuit provided,
The second MOS transistor has a gate connected to the output of the second level shift circuit instead of the first level shift circuit,
10. The device according to claim 4, wherein the substrate voltage is configured to be lower than V _FP [where V _FP > 0] when the comparison unit performs successive comparisons. Successive comparison AD converter.   14. The successive approximation AD converter according to claim 13, wherein the second level shift circuit has the same configuration as the first level shift circuit. The second level shift circuit includes:
An inverter unit provided to operate with a low power supply potential lower than the power supply potential, to output a ground potential when the power supply potential is input, and to output the low power supply potential when a ground potential is input;
A voltage conversion circuit that outputs a ground potential when the power supply potential is input to the inverter unit, and outputs a lower potential of the substrate voltage and the ground potential when a ground potential is input to the inverter unit;
The output of the inverter unit is input, connected to the output of the voltage conversion circuit, the output of the voltage conversion circuit is output when the ground potential is input, and the low power supply potential is output when the low power supply potential is input A first shift unit provided to
When the output of the first shift unit is an input, is connected to the output of the voltage conversion circuit, and receives the output of the voltage conversion circuit, the fourth switch circuit is connected to the positive reference voltage at the other end of the power storage unit. Is output, while the fourth switch circuit is connected to the negative reference voltage to the other end of the power storage unit, the low power supply potential is output, A second shift unit provided to output the output of the voltage conversion circuit when a low power supply potential is input;
14. The successive approximation AD converter according to claim 13, further comprising: The voltage conversion circuit includes:
A tenth MOS transistor having a drain as an output, a gate connected to a ground potential, and a source connected to the substrate voltage;
An eleventh MOS transistor having a gate connected to the substrate voltage, a drain connected to the drain of the tenth MOS transistor, and a source connected to a ground potential;
The successive approximation AD converter according to claim 15, wherein the bulks of the tenth MOS transistor and the eleventh MOS transistor are floating. When the capacity of the power storage unit is C _X [where C _X > 0],
C _X = 2 × C _P × (V _FP −V _REF ) / (V _H −V _L + V _REF −V _FP )
The successive approximation AD converter according to any one of claims 13 to 16, wherein   When sampling the input voltage, the source of the first MOS transistor and the source of the second MOS transistor are connected to the reference voltage, and when the comparison unit performs successive comparisons, 18. The sequential circuit according to claim 13, further comprising: a third switch circuit provided to disconnect the source and the source of the second MOS transistor from the reference voltage. Comparative AD converter. In the first MOS transistor, a ground potential can be connected to a source instead of the reference voltage,
When sampling the input voltage, the source of the first MOS transistor is connected to the ground potential, the source of the second MOS transistor is connected to the reference voltage, and the comparison unit performs a sequential comparison, A third switch circuit provided to release the connection of the source of the first MOS transistor to the ground potential and to release the connection of the source of the second MOS transistor to the reference voltage; The successive approximation AD converter according to any one of claims 13 to 17.   When switching from the sampling state of the input voltage to the successive approximation state by the comparator, the input of the first level shift circuit is switched from the power supply potential to the ground potential, the fourth switch circuit is switched, and the second level is switched. 20. The successive approximation AD converter according to claim 18, wherein the input of the shift circuit is switched from the power supply potential to the ground potential and the third switch circuit is switched.   When switching the input of the second level shift circuit from the power supply potential to the ground potential, the connection between the common terminal by the second MOS transistor and the reference voltage, the substrate voltage by the ninth MOS transistor, and the 21. The successive approximation AD converter according to claim 13, wherein the connection with the power storage unit is released at different timing. .., C _P / 2 ¹ ,..., C _P / 2 ^m−1 having m−1 additional capacitors provided corresponding to the m−1 board capacitors.
Each of the additional capacitors has a size proportional to the capacitance of the corresponding substrate capacitor, one end is grounded, and the other end is connected to the other end of the corresponding substrate capacitor. The successive approximation AD converter according to any one of 1 to 21. 23. The successive approximation AD converter according to claim 1, wherein the substrate voltage wiring is arranged so as to surround the common terminal wiring.

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