JP2018060858A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device without lowering the productivity, which enables the achievement of a small contact electric resistance without reducing an on-current, and which is easy to shape in a desired form.SOLUTION: A semiconductor device of the present invention comprises: a source electrode; a drain electrode; a gate electrode; a channel layer; and an oxide thin film including ZnO of 50-95% in mole percentage on an oxide basis between each or one of the source and drain electrodes, and the channel layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor element and a method for manufacturing a semiconductor element.

  2. Description of the Related Art In recent years, semiconductor elements such as thin film transistors that are formed by forming electrodes such as a source, a drain, and a gate, a gate insulating layer, a channel layer, and the like on an insulating substrate have attracted attention. Such a semiconductor element can be applied to various electronic devices such as an electro-optical device.

  In general, an n-type channel layer has a low electron density, and when a metal used as a source / drain electrode is brought into direct contact, the contact electric resistance increases, so that there is a gap between the channel layer and the source / drain electrode. A layer having a high electron density called a contact layer is often provided. Similarly, since the p-type channel layer has a low hole density, a layer having a high hole density is provided as a contact layer. In order to form these contact layers, it is necessary to use expensive equipment such as an ion implantation method. The contact layer does not reduce the current caused by electrons induced in the channel layer under a positive gate bias (hereinafter referred to as on-current), but is caused by holes induced in the channel layer under a negative gate bias. Current (hereinafter referred to as off-state current) is required to be reduced.

Currently, hydrogenated amorphous silicon TFT, which is used as a back plane of a liquid crystal display: In (a-Si H-TFT) , as a contact layer, n ⁺ with enhanced doped electron density group V element such as phosphorus - a-Si: H is used.

  Further, Patent Document 1 proposes a semiconductor element using an amorphous oxide electride thin film containing calcium atoms and aluminum atoms as a contact layer in order to reduce the contact electric resistance.

  Non-Patent Documents 1 and 2 indicate that in a semiconductor element using a silicon-based thin film as a channel layer, the off-current is reduced by using an electride thin film as a contact layer.

International Publication No. 2014/192701

Proceedings of the 62nd JSAP Spring Meeting, 12a-A29-6 Proceedings of the 62nd JSAP Spring Meeting, 12a-A29-7

  In order to manufacture a semiconductor element, it is necessary to form a predetermined film and then pattern it into a desired shape by a photolithography process and an etching process. Etching is roughly classified into two types, one is dry etching that uses the reaction between the gas and the film to be patterned, and the other is wet etching that uses the reaction between the liquid and the film to be patterned. Considering productivity, wet etching is preferable.

However, when n ⁺ -a-Si: H is used as the contact layer, since n ⁺ -a-Si: H is a hardly soluble material, nitric acid and hydrofluoric acid are included for wet etching. Etching solution is required. Such an etching solution has a problem that members other than n ⁺ -a-Si: H such as a glass substrate also dissolve.

  In addition, when an electride thin film is used as the contact layer, the electride thin film has low acid resistance, and thus may be etched more than desired in wet etching.

  The present invention provides a semiconductor element that can reduce the contact electrical resistance, reduce the on-current without reducing the on-current, and has high acid resistance, and a method for manufacturing the same.

The semiconductor element of the present invention is a semiconductor element having a source electrode, a drain electrode, a gate electrode, and a channel layer,
Between the one or both of the source electrode and the drain electrode and the channel layer, an oxide thin film containing 50 to 95% ZnO in terms of oxide-based molar percentage is provided.

A method for manufacturing a semiconductor element of the present invention is a method for manufacturing a semiconductor element having a source electrode, a drain electrode, a gate electrode, and a channel layer,
Forming an oxide thin film containing 50 to 95% ZnO in terms of oxide-based mole percentage between one or both of the source electrode and the drain electrode and the channel layer (a)
It is characterized by having.

  The present invention realizes a semiconductor element that can reduce the contact electric resistance, reduce the on-current without reducing the on-current, and has high acid resistance. In addition, a method for manufacturing such a semiconductor device has been realized.

1 is a cross-sectional view schematically showing a configuration of a semiconductor element according to an embodiment of the present invention. The flowchart at the time of manufacturing the semiconductor element which concerns on one Embodiment of this invention. Sectional drawing which showed roughly the laminated body for evaluating an oxide thin film. The evaluation result of the IV characteristic of the laminated body of Example 1 and Example 2. FIG. The evaluation result of the IV characteristic of the laminated body of Example 3 and Example 4. FIG.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Hereinafter, in the present specification, “˜” indicating a numerical range is used in the sense of including the numerical values described before and after the numerical value as a lower limit value and an upper limit value.

  First, a semiconductor element according to an embodiment of the present invention will be described.

  FIG. 1 is a cross-sectional view showing a semiconductor device 100 according to an embodiment of the present invention.

  As shown in FIG. 1, the semiconductor element 100 includes a substrate 110, a channel layer 105, a source electrode 120, a drain electrode 122, a gate electrode 124, and a gate insulating layer 130.

  The gate electrode 124 is disposed on the substrate 110. A channel layer 105 is disposed on the gate electrode 124 with a gate insulating layer 130 interposed therebetween. The source electrode 120 and the drain electrode 122 are disposed on the channel layer 105.

  An oxide thin film 150 is disposed between one or both of the source electrode 120 and the drain electrode 122 and the channel layer 105. A first oxide thin film 150 a is disposed between the source electrode 120 and the channel layer 105, and a second oxide thin film 150 b is disposed between the drain electrode 122 and the channel layer 105. One of the first oxide thin film 150a and the second oxide thin film 150b may be omitted.

  The semiconductor device 100 shown in FIG. 1 has a so-called bottom gate structure-top contact method. In this example, the gate electrode 124 is disposed below the channel layer 105 (bottom gate structure), and the source electrode 120 and the drain electrode 122 are disposed above the channel layer 105 (top contact method). However, the arrangement structure of each member constituting the semiconductor element is not limited to this. The top gate structure-bottom contact method may be used, the bottom gate structure-top contact method may be used, or the bottom gate structure-bottom contact method may be used.

  Here, each member which comprises the semiconductor element 100 is demonstrated.

  In the present embodiment, the material of the substrate 110 is a glass substrate. However, it is not limited to this. It may be an insulating substrate such as a ceramic substrate, a plastic substrate, and a resin substrate.

The gate electrode 124 has a two-layer structure of Al metal and Mo metal. However, it is not particularly limited as long as it has conductivity. By forming the Mo metal after forming the Al metal, the Al metal is hardly deteriorated and the durability of the gate electrode 124 is good. Moreover, it has better conductivity than a single layer structure made of only Mo metal. The gate electrode 124 may be, for example, an element selected from Al, Ag, Au, Cr, Cu, Ta, Ti, Mo, and W, or a metal or alloy containing these elements as a component. The gate electrode 124 is made of, for example, ITO, antimony oxide (Sb ₂ O ₃ ), zirconium oxide (ZrO ₂ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), IZO (Indium Zinc Oxide), or AZO. (ZnO—Al ₂ O ₃ : zinc oxide doped with aluminum), GZO (ZnO—Ga ₂ O ₃ : zinc oxide doped with gallium), Nb-doped TiO ₂ , Ta-doped TiO ₂ , and IWZO ( In ₂ O ₃ —WO ₃ —ZnO: indium oxide doped with tungsten trioxide and zinc oxide) may be used. Alternatively, the gate electrode 124 may be a transparent electrode using a metal thin enough to transmit visible light. The gate electrode 124 may be a single layer, or may be composed of two or more layers made of a plurality of metals, alloys, metal oxide materials, or the like.

  The gate insulating layer 130 is silicon oxide. However, it is not limited to this. It may be made of an inorganic insulating material such as silicon nitride, silicon oxide containing nitrogen and silicon nitride containing oxygen, or an organic insulating material such as acrylic or polyimide.

  Alternatively, the gate insulating layer 130 has a skeleton structure formed of a bond of silicon and oxygen, and has an organic group (for example, an alkyl group or an aryl group) containing at least hydrogen as a substituent and a fluoro group, a so-called siloxane-based material. It may be constituted by. The gate insulating layer 130 may be a single layer or may be composed of two or more layers.

  The channel layer 105 is silicon-based semiconductor amorphous silicon (a-Si: H). However, it is not limited to this. For example, you may be comprised with common semiconductor materials, such as IV group semiconductors, such as silicon and germanium, and an organic semiconductor. Further, the semiconductor is not limited to a crystalline semiconductor, and may be an amorphous semiconductor (amorphous semiconductor) or a state containing amorphous and crystalline.

  Examples of the silicon-based semiconductor include amorphous silicon (a-Si: H), low-temperature polysilicon (LTPS), and the like.

  Examples of organic semiconductors include polycyclic aromatic compounds, conjugated double bond compounds, macrocyclic compounds, metal phthalocyanine complexes, charge transfer complexes, condensed ring tetracarboxylic acid diimides, oligothiophenes, fullerenes, carbon nanotubes, etc. Is mentioned. For example, polypyrrole, polythiophene, poly (3-alkylthiophene), polythienylene vinylene, poly (p-phenylene vinylene), polyaniline, polydiacetylene, polyazulene, polypyrene, polycarbazole, polyselenophene, polyfuran, poly (p-phenylene) , Polyindole, polybilidazine, naphthacene, tetracene, pentacene, hexacene, heptacene, pyrene, chrysene, perylene, coronene, terylene, ovalene, quaterylene, triphenodioxazine, triphenodiliadine, hexacene-6,15-quinone, polyvinylcarbazole, polyphenylene Sulfide, polyvinylene sulfide, polyvinyl pyridine, naphthalene tetracarboxylic acid diimide, anthracene tetracarboxylic acid diimide, C6 , C70, C76, C78, C84, and can be used derivatives thereof. Specific examples thereof include pentacene, tetracene, α-sexithiophene (6T), copper phthalocyanine, bis (1,2,5-thiadiazolo) -p-quinobis (1), which are generally P-type semiconductors. , 3-dithiol), rubrene, poly (2,5-thienylenevinylene) (abbreviation: PTV), poly (3-hexylthiophene-2,5-diyl) (abbreviation: P3HT), (poly [(9,9 -Dioctylfluorenyl-2,7-diyl) -co-bithiophene]) (abbreviation: F8T2). In addition, 7,7,8,8, -tetracyanoquinodimethane (abbreviation: TCNQ) perylene-3,4,9,10-tetracarboxylic dianhydride (abbreviation: PTCDA), which is generally an N-type semiconductor, 1,4,5,8-naphthalenetetracarboxylic dianhydride (abbreviation: NTCDA), N, N′-dioctyl-3,4,9,10-perylenetetracarboxylic acid diimide (abbreviation: PTCDI-C8H), copper (II) 1,2,3,4,8,9,10,11,15,16,17,18,22,23,24,25-Foxadecafluoro-29H, 31H-phthalocyanine (abbreviation: F16CuPc) 3 ′, 4′-dibutyl-5,5 ″ -bis (dicyanomethylene) -5,5 ″ -dihydro-2,2 ′: 5 ′, 2 ″ -terthiophene) (abbreviation: DCMT), etc. There is. Note that the P-type and N-type characteristics of an organic semiconductor are not unique to the substance, but depend on the relationship with the electrode into which carriers are injected and the strength of the electric field at the time of injection.

  The channel layer 105 may have a work function of 3.5 eV or more, or 4.0 eV or more. The work function may be 7.0 eV or less, or 5.0 eV or less.

The channel layer 105 may have an electron density of 10 ⁹ cm ⁻³ or more, or 10 ¹⁵ cm ⁻³ or more. Further, the electron density may be 10 ¹⁹ cm ⁻³ or less, or 10 ¹⁸ cm ⁻³ or less.

  The source electrode 120 and the drain electrode 122 have a two-layer structure of Mo metal and Al metal. However, it is not particularly limited as long as it has conductivity. By depositing the Al metal after depositing the Mo metal, the oxide thin film 105 and the Mo metal, which will be described later, are in contact with each other. Smaller than the single layer structure. The source electrode 120 and the drain electrode 122 are, for example, an element selected from Al, Ag, Cr, Cu, Nb, Nd, Ta, Ti, Mo, and W, or a metal or an alloy containing these elements as components. May be. Moreover, it is preferable that patterning can be performed by wet etching.

  The semiconductor device 100 according to an embodiment of the present invention contains 50% to 95% ZnO in terms of oxide-based mole percentage between one or both of the source electrode 120 and the drain electrode 122 and the channel layer 105. The oxide thin film 150 is provided. By having an oxide thin film containing 50% to 95% of ZnO in terms of oxide-based mole percentage, the contact electrical resistance can be reduced, and the off-current is reduced without reducing the on-current. In addition, since the oxide thin film 150 has appropriate acid resistance, the oxide thin film 150 is less likely to be etched than the desired shape when performing wet etching. In the example of FIG. 1, the contact oxide resistance at the interface between the source electrode 120 and the channel layer 105 can be reduced by disposing the first oxide thin film 150 a between the source electrode 120 and the channel layer 105. it can. Similarly, when the second oxide thin film 150b is disposed between the drain electrode 122 and the channel layer 105, the contact electrical resistance at the interface between the drain electrode 122 and the channel layer 105 can be reduced. One of the causes of the off-current is considered to be a current derived from holes induced in the channel layer under a negative gate bias. When the channel layer 105 is made of silicon, the upper end of the valence band is about 5 eV from the vacuum level, and when the channel layer 105 is made of germanium, the upper end of the valence band is about 5 eV from the vacuum level. It is about 4.5 eV. On the other hand, the upper end of the valence band of the oxide thin film 150 is 6 to 9 eV from the vacuum level. Therefore, an energy barrier of 1 to 4 eV is generated at the upper end of the valence band at the interface between the oxide thin film 150 and the channel layer 105. Since holes propagate in the upper end of the valence band or in the vicinity thereof, the transport of holes from the channel layer 105 to the oxide thin film 150 is suppressed, so that off-current can be reduced. This is called the hole blocking effect.

  In the semiconductor device 100 according to an embodiment of the present invention, the content of ZnO in the oxide thin film 150 is 50% to 95% in terms of a molar percentage based on the oxide. If it is 50% or more, the electron density becomes high, and the contact electric resistance with the channel layer can be lowered. The content of ZnO is more preferably 70% or more, and further preferably 75% or more in terms of mole percentage based on oxide. If the ZnO content is 95% or less, the acid resistance of the oxide thin film 150 is improved, the etching rate of wet etching is easily controlled, and the oxide thin film 150 is easily formed into a desired shape. The content of ZnO is more preferably 90% or less, and even more preferably 85% or less in terms of mole percentage based on oxide.

The oxide thin film 150 preferably contains 5 to 50% of SnO ₂ in terms of a molar percentage based on the oxide. If the content of SnO ₂ is 5% or more, the electron density of the oxide thin film 150 is increased, and the contact electric resistance with the channel layer can be decreased. The content of SnO ₂ is more preferably 10% or more, and further preferably 15% or more. If the content of SnO ₂ is 50% or less, the etching rate of wet etching can be easily controlled, and the oxide thin film 150 can be easily formed into a desired shape. The content of SnO ₂ is more preferably 33% or less, and further preferably 25% or less.

In addition, the oxide thin film 150 preferably has a total content of ZnO and SnO ₂ of 55 to 100% in terms of oxide-based molar percentage. If the total content of ZnO and SnO ₂ is 55% or more, the on-state current of the semiconductor element is unlikely to decrease. The total content of ZnO and SnO ₂ is more preferably 70% or more, and still more preferably 80% or more. If the total content of ZnO and SnO ₂ is 95% or less, it becomes amorphous easily and there is no leakage current due to grain boundaries, so that the hole blocking effect can be increased and the off-current is reduced. The The total content of ZnO and SnO ₂ is more preferably 90% or less, and still more preferably 85% or less.

In addition, the oxide thin film 150 preferably has a ZnO / SnO ₂ value of 0.01 to 0.19, which is obtained by dividing the ZnO content by the SnO ₂ content in terms of an oxide-based molar percentage. If ZnO / SnO ₂ is 0.01 or more, the acid resistance does not become too strong, and the oxide thin film 150 can be formed into a desired shape by wet etching. ZnO / SnO ₂ is more preferably 0.015 or more, and further preferably 0.023 or more. If ZnO / SnO ₂ is 0.19 or less, the acid resistance does not become too weak, and the oxide thin film 150 does not melt too much by wet etching, so that the oxide thin film 150 is less likely to be etched than the desired shape. ZnO / SnO ₂ is more preferably 0.09 or less, and even more preferably 0.057 or less.

The oxide film 150 preferably contains _Ga 2 _{O 3 5~50%} in mole percentage on an oxide basis. If the content of Ga ₂ O ₃ is 5% or more, the electron density of the oxide thin film 150 is increased, and the contact electric resistance with the channel layer can be decreased. The content of Ga ₂ O ₃ is more preferably 10% or more, and further preferably 15% or more. If the content of Ga ₂ O ₃ is 50% or less, the oxide thin film is easily wet-etched. The content of Ga ₂ O ₃ is more preferably 33% or less, and further preferably 25% or less.

The oxide film 150 preferably contains 5-50% of SiO2 and GeO ₂ in a total amount in mole percent on an oxide basis. If the total amount of SiO ₂ and GeO ₂ is 5% or more, the oxide thin film 150 is likely to be amorphous, and there is no leakage current due to crystal grain boundaries, so that the hole blocking effect can be increased, and the off-current can be reduced. Reduced. The total amount of SiO ₂ and GeO ₂ is more preferably 10% or more, and further preferably 15% or more. If the total amount of SiO ₂ and GeO ₂ is 50% or less, a film having a high electron density can be obtained. The total amount of SiO ₂ and GeO ₂ is more preferably 30% or less, and further preferably 20% or less.

The electrical resistivity of the oxide thin film 150 is preferably 1 × 10 ⁻¹ Ωcm to ¹ × 10 ⁵ Ωcm. When the electrical resistivity of the oxide thin film 150 is 1 × 10 ⁻¹ Ωcm or more, the flow of holes under a negative gate bias is suppressed, and the off-current can be suppressed to a small value. The electrical resistivity is more preferably 1 Ωcm or more, and further preferably 10 Ωcm or more. If the electrical resistivity is 10 ⁵ Ωcm or less, a sufficient current can flow under a positive gate bias. The electrical resistivity is more preferably 10 ⁴ Ωcm or less, and further preferably 10 ³ Ωcm or less.

  The thickness of the oxide thin film 150 is preferably 1 nm to 500 nm. If the thickness of the oxide thin film 150 is 1 nm or more, the oxide thin film 150 has few pinholes. The thickness of the oxide thin film 150 is more preferably 10 nm or more, and further preferably 100 nm or more. If the thickness of the oxide thin film 150 is 500 nm or less, it can be patterned with high accuracy by, for example, photolithography. The thickness of the oxide thin film 150 is more preferably 400 nm or less, and further preferably 300 nm or less.

The oxide thin film 150 may include one or more of Nb ₂ O ₅ , TiO ₂ , Al ₂ O ₃ , Bi ₂ O ₃ , Ta ₂ O ₅ , ZrO ₂ , and HfO ₂ . By including these components, chemical durability is improved.

The electron density of the oxide thin film 150 is preferably 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . When the electron density is 1 × 10 ¹⁴ cm ⁻³ or more, the contact resistance between the oxide thin film 150 and the channel layer 105 is small. The electron density is more preferably 1 × 10 ¹⁴ cm ⁻³ or more, and further preferably 1 × 10 ¹⁶ cm ⁻³ or more. When the electron density is 1 × 10 ²⁰ cm ⁻³ or less, the oxide thin film 150 forms a heterojunction with the channel layer 105 and can suppress off-state current. The electron density is more preferably 1 × 10 ¹⁹ cm ⁻³ or less, and further preferably 1 × 10 ¹⁸ cm ⁻³ or less.

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. Here, the film is formed using a vapor deposition method.

  Here, the “vapor deposition method” means a film deposition method for depositing vaporized raw materials on a substrate, including a physical vapor deposition (PVD) method and a chemical vapor deposition (CVD) method. . The PVD method includes a vacuum deposition method, a molecular beam epitaxy method, a sputtering method, an ion plating method, and a laser deposition (ablation) method. The CVD method includes a thermal CVD method, a photo CVD method, a plasma CVD method, an atmospheric pressure CVD (AP-CVD), a low pressure CVD (LP-CVD), and a metal organic chemical vapor deposition method (MO-CVD).

FIG. 2 is a flowchart for manufacturing the semiconductor device 100 according to the embodiment of the present invention. The method for manufacturing the semiconductor device 100 according to the embodiment shown in FIG.
Forming a gate electrode (step S510);
Forming a channel layer (step S520);
Forming an oxide thin film containing 50-95% ZnO in oxide-based mole percentage display (step S530);
Forming a source electrode and a drain electrode (step S540);
Have

  Hereinafter, each step will be described in detail. In the following description, the reference numerals shown in FIG. 1 are used for the respective members for the sake of clarity.

(Step S510)
First, the gate electrode 124 is formed on the substrate 110. Various methods conventionally used can be used to form the gate electrode 124. For example, the gate electrode 124 may be formed by a sputtering method, an evaporation method, or the like. After the conductive layer for forming the gate electrode 124 is formed, the gate electrode 124 can be formed by performing photolithography treatment, etching treatment, or the like on the film.

(Step S520)
Next, a gate insulating film 130 is formed so as to cover the gate electrode 124.

The gate insulating film 130 may be formed by a coating method such as a dipping method, a spin coating method, a droplet discharge method, a casting method, a spinner method, a printing method, a CVD method, a sputtering method, or the like.

  Thereafter, the channel layer 105 is formed on the gate insulating film 130.

  The method for forming the channel layer 105 is not particularly limited, and the channel layer 105 may be formed on the gate insulating film 130 by a conventionally implemented method. When the channel layer 105 is an amorphous semiconductor such as amorphous silicon, it is formed on the gate insulating film 130 by CVD or the like.

  The formed channel layer 105 can be formed into a desired shape by performing, for example, a photolithography process and an etching process.

(Step S530)
Next, an oxide thin film 150 containing 50 to 95% ZnO in terms of oxide-based mole percentage is formed on the channel layer 105. This thin film will later become the first thin film 150a and / or the second thin film 150b.

The formation of the oxide thin film 150 is
Preparing a target containing Zn (S531);
A step of forming a film on the channel layer by a vapor phase growth method using the target (S532);
Is done.

(Step S531)
First, a deposition target used in the subsequent step S132 is prepared.

  The target preferably contains 45 to 98% of Zn. Zn may be a metal or an oxide. The relative density is preferably 95% or more. The shape may be flat or cylindrical.

  The obtained target is used as a raw material source when the oxide thin film 150 is formed in the next step.

(Step S532)
Next, film formation is performed on the channel layer by a vapor deposition method using the target manufactured in the above-described step S531.

  Of the vapor phase growth methods, the sputtering method is particularly preferable. In the sputtering method, a thin film can be formed relatively uniformly in a large area.

  Here, a DC (direct current) sputtering method is applied. However, the method is not limited to this, and a known sputtering method can be applied. Any of a high-frequency sputtering method, a helicon wave sputtering method, an ion beam sputtering method, and a magnetron sputtering method may be used.

  The temperature of the deposition target substrate when forming the oxide thin film is not particularly limited, and any temperature in the range from room temperature to 700 ° C. may be employed. However, there may be a case where the temperature of the deposition target substrate rises “incidentally” due to the radiant heat of the vapor deposition source. For example, the temperature of the deposition target substrate may be 200 ° C. or higher, or 300 ° C. or higher. When the temperature of the deposition substrate is 200 ° C. or higher, the electron density of the oxide thin film 150 can be increased. If the temperature of the deposition substrate is 300 ° C. or higher, the electron density can be further increased. Further, the temperature of the deposition target substrate may be 500 ° C. or lower, 400 ° C. or lower, or 200 ° C. or lower. When the temperature of the deposition target substrate is 500 ° C. or lower, a chemical reaction hardly occurs between the oxide thin film 150 and the channel layer 105.

  When the film formation substrate is not “positively” heated, it is possible to use a material whose heat resistance is lowered on the high temperature side exceeding 700 ° C., such as glass or plastic, for example.

Ar (argon) and O ₂ (oxygen) were used as the sputtering gas. However, the present invention is not limited to this, and it is sufficient if a trace amount oxygen source is added to a rare gas. Examples of the rare gas include He (helium), Ne (neon), Ar (argon), Kr (krypton), and Xe (xenon). Examples of the oxygen source include O ₂ (oxygen) and CO ₂ (carbon dioxide). At this time, it is more preferable to use O ₂ as the oxygen source in the sputtering gas when the target is an oxide, and the concentration of O ₂ is preferably 0.01% to 0.5%. When the target is a metal, it is more preferable to use CO ₂ as the oxygen source in the sputtering gas, and the concentration of CO ₂ is preferably 10% to 60%.

  The pressure of the sputtering gas (pressure in the chamber of the sputtering apparatus) is preferably in the range of 0.05 Pa to 10 Pa, more preferably 0.1 Pa to 5 Pa, and further preferably 0.2 Pa to 3 Pa. If it is this range, since the pressure of sputtering gas will not be too low, plasma will become stable. Further, since the pressure of the sputtering gas is not too high, an increase in the temperature of the substrate due to an increase in ion bombardment can be suppressed.

  Heretofore, the method for forming the oxide thin film has been briefly described by taking the DC sputtering method as an example. However, the method for forming the oxide thin film is not limited to this, and it is obvious that the above-described two steps (steps S131 and S132) may be appropriately changed or various steps may be added. is there.

  In this way, the oxide thin film 150 is formed on the patterned channel layer 105. Further, a conductive layer to be the source electrode 120 and the drain electrode 122 is continuously formed.

(Step S540)
Next, the source electrode 120 and the drain electrode 122 are formed on the oxide thin film 150. The source electrode 120 and the drain electrode 122 can be formed by performing a photolithography process, an etching process, or the like on the film after forming a conductive layer for forming the source electrode 120 and the drain electrode 122. However, the present invention is not limited to this, and various methods conventionally used can be used to form the source electrode 120 and the drain electrode 122.

  Here, the source electrode 120, the drain electrode 122, and the oxide thin film 150 may be patterned with the same resist pattern. In the etching process, the source electrode 120, the drain electrode 122, and the oxide thin film 150 may be etched at a time by wet etching, or the etchant is changed separately for each of the source electrode 120, the drain electrode 122, and the oxide thin film 150. Etching may be performed. For example, the source electrode 120 and the drain electrode 122 may be wet etched with a mixed acid of phosphoric acid, nitric acid, and acetic acid, and the oxide thin film 150 may be wet etched with hydrochloric acid or hydrofluoric acid. Alternatively, the source electrode 120 and the drain electrode 122 may be dry-etched and the oxide thin film 150 may be wet-etched. In this case, since the oxide thin film 150 functions as an etch stopper layer that prevents etching by dry etching, the channel layer 105 is hardly etched when the source electrode 120 and the drain electrode 122 are dry etched.

  Compared with dry etching, wet etching does not use a vacuum apparatus or the like, and thus the manufacturing process is simple. Further, since the channel layer 105 is not etched and the channel layer 105 is not etched by selecting an etchant that can etch the oxide thin film 150 into a desired shape, the channel layer 105 may be thinner than the conventional one. In particular, the on-current of the semiconductor element 100 can be increased. As such an etching solution, for example, a PAN (Phosphoric-Acetic-Nitric-acid) etching solution in which phosphoric acid, acetic acid, and nitric acid are mixed may be used. Further, since the oxide thin film 150 is an oxide and has a hole blocking effect, the off-state current of the semiconductor element 100 can be reduced.

  The semiconductor element 100 is preferably heat-treated after patterning. The heat treatment temperature is preferably 100 ° C. or higher, and more preferably 200 ° C. or higher. The temperature is lower than the temperature at which the coating film and the deposition target substrate can withstand, and is preferably 700 ° C. or lower. When the channel layer 105 is a-Si: H, the heat treatment temperature is preferably 350 ° C. or lower in order to prevent dehydrogenation of a-Si: H. The holding time at the predetermined temperature may be 1 minute to 2 hours, or 10 minutes to 1 hour. The atmosphere may be any of air, nitrogen, rare gas, and hydrogen, or a mixed gas thereof. When the channel layer 105 or the oxide thin film 150 is damaged during patterning or the like, the damage is recovered by heat treatment.

  The semiconductor element 100 can be manufactured through the above steps.

  In the above description, an example of a method for manufacturing a semiconductor device according to the present invention has been described using the semiconductor device 100 shown in FIG. 1 as an example.

  However, the order of each step is not limited to this. That is, the semiconductor element may be manufactured by changing the order of the steps shown in FIG.

  Moreover, a transparent semiconductor element can be manufactured by making all the board | substrates, electrodes, and channel layers used for the semiconductor element of this invention into a transparent material.

  Hereinafter, the present invention will be specifically described with reference to examples, but the present invention is not limited to these examples.

  FIG. 3 is a cross-sectional view schematically showing a stacked body 300 for evaluating an oxide thin film.

  A stacked body 300 including an oxide thin film 330 containing 50 to 90% of ZnO in terms of an oxide-based mole percentage was manufactured, and current-voltage characteristics (IV characteristics) were evaluated.

First, a semiconductor thin film 320 was formed by PECVD on a low resistance (4 × 10 ⁻³ Ωcm) P-type silicon substrate 310 to a thickness of 50 nm. Next, a thin film 330 was formed to a thickness of 30 nm, and 2 mm square of Mo was sputtered as an electrode 340 using a metal mask. Finally, Al was deposited as the back electrode 350. The semiconductor thin film 320 and the thin film 330 are shown in Table 1, and four types of laminated bodies 300 of Examples 1 to 4 were produced.

例１、例３は実施例であり、例２、例４は比較例である。

Examples 1 and 3 are examples, and examples 2 and 4 are comparative examples.

P-type a-Si: H was formed by PECVD under conditions of 280 ° C. and 133 Pa using SiH ₄ , H ₂ and B ₂ H ₆ as reaction gases. In addition, I-type a-Si: H was formed by PECVD using SiH ₄ as a reaction gas under the conditions of 280 ° C. and 40 Pa. N-type a-Si: H was formed by PECVD under the conditions of 280 ° C. and 133 Pa using SiH ₄ , H ₂ , and PH ₃ as reaction gases. 85mol% ZnO / 15mol% SnO ₂ thin film is 85% of ZnO in a molar percentage display, the sputtering target containing SnO ₂ 15%, was formed by sputtering.

  The produced laminate 300 was heat-treated in the atmosphere at 250 ° C. for 60 minutes, and the IV characteristics were measured.

4 and 5 are measurement results of IV characteristics. The current value of Example 3 was about the same as Example 4, and the current value of Example 1 was about an order of magnitude smaller than Example 2. Examples 3 and 4 in which the semiconductor thin film 320 is I-type a-Si: H simulate the case where a positive gate voltage is applied to the semiconductor element 100 of the present invention. The fact that the current values of Example 3 and Example 4 are almost equal means that the on-current of a semiconductor element in which an 85 mol% ZnO / 15 mol% SnO ₂ thin film is arranged as a contact layer is n ⁺ -a-Si: H. If the on-state current of the semiconductor element arranged as is the same as the thickness of the channel layer 105, it means that they are equivalent. Here, when n ⁺ -a-Si: H is used as the contact layer, as described above, n ⁺ -a-Si: H is a hardly soluble material. Therefore, nitric acid or hydrofluoric acid is used for wet etching. The solution which mixed these etc. is required and there exists a problem that members other than n ^<+> -a-Si: H, such as a glass substrate, will also melt | dissolve. Semiconductor elements arranged 85mol% ZnO / 15mol% SnO ₂ thin film as a contact layer, rather than 85mol% ZnO / 15mol% SnO ₂ thin film hardly soluble material, it is possible to wet etching without dissolving the member such as a glass substrate , N ⁺ -a-Si: H can be made thinner than the case where n ⁺ -a-Si: H is used as a contact layer, and n ⁺ -a-Si: H is contacted from the results of IV characteristics of Examples 3 and 4. It can be seen that the on-state current is larger than that when used as a layer.

Examples 1 and 2 in which the semiconductor thin film 320 is P-type a-Si: H simulate the case where a negative gate voltage is applied to the semiconductor element 100 of the present invention. Since the current of Example 1 is smaller than that of Example 2, it is considered that the off-current can be reduced when the 85 mol% ZnO / 15 mol% SnO ₂ thin film is disposed in the semiconductor element 100 of the present invention.

  Next, in order to show that the semiconductor element 100 of the present invention has high acid resistance, the thin film shown in Table 2 was formed on an alkali-free glass substrate, and the etching rate of the thin film was measured.

  Example 5 is an example and Example 6 is a comparative example.

まず、スパッタ成膜装置（アルバック社製ＥＣ−２）の成膜室に、表２に示す薄膜を成膜するためのスパッタリングターゲットと、および無アルカリガラス基板を、スパッタリングターゲットと無アルカリガラス基板との距離が６．７ｃｍとなるように設置した。次に、成膜室内の圧力が１×１０^−４Ｐａ未満となるようにターボポンプで排気した後、アルゴン９９．２５ｖｏｌ％／酸素０．７５ｖｏｌ％の混合ガスを成膜室の圧力が２Ｐａとなるように導入した。スパッタリングターゲットに直流電圧を印加し、プラズマを発生させ、無アルカリガラス基板上に薄膜の厚さが１００ｎｍとなるようにスパッタ成膜を行った。次に、成膜された薄膜の一部分にフォトレジストを塗布し、１００℃で３分間加熱してレジストを硬化させた。そして、混酸エッチャント（関東化学社製、成分：リン酸８０％未満、硝酸５％未満、酢酸１０％未満、水５％以上）に浸漬し、フォトレジストの塗布されていない部分をエッチングした。さらに、フォトレジストを剥離液で除去し、ＩＰＡにより洗浄した。このようにして得られた酸化物薄膜の段差を接触式段差計で測定し、エッチングレートを求め、表２に示した。

First, a sputtering target for forming a thin film shown in Table 2 and a non-alkali glass substrate in a film forming chamber of a sputtering film forming apparatus (EC-2 manufactured by ULVAC, Inc.), a sputtering target and a non-alkali glass substrate, The distance was set to 6.7 cm. Next, after evacuating with a turbo pump so that the pressure in the film formation chamber is less than 1 × 10 ⁻⁴ Pa, a mixed gas of 99.25 vol% argon / 0.75 vol% oxygen is set to 2 Pa in the film formation chamber. Introduced to be. A direct current voltage was applied to the sputtering target to generate plasma, and sputtering film formation was performed on the non-alkali glass substrate so that the thickness of the thin film became 100 nm. Next, a photoresist was applied to a part of the formed thin film, and the resist was cured by heating at 100 ° C. for 3 minutes. Then, it was immersed in a mixed acid etchant (manufactured by Kanto Chemical Co., Inc., components: phosphoric acid less than 80%, nitric acid less than 5%, acetic acid less than 10%, water 5% or more), and the portion where the photoresist was not applied was etched. Further, the photoresist was removed with a stripping solution and washed with IPA. The steps of the oxide thin film thus obtained were measured with a contact-type step meter, and the etching rate was determined.

The 85 mol% ZnO / 15 mol% SnO ₂ thin film of Example 5 has a slower etching rate and higher acid resistance than the amorphous C12A7 electride thin film of Example 6.

  Since the amorphous electride thin film of Example 6 has a high etching rate and low acid resistance, it may be etched more than desired in wet etching.

  The present invention can be applied to, for example, semiconductor elements used in various electronic devices such as electro-optical elements. For example, it can be used for electronic devices such as displays such as televisions, electrical appliances such as washing machines and refrigerators, and information processing devices such as mobile phones and computers. In addition, the semiconductor element of the present invention can be used for electronic devices included in automobiles and various industrial equipment.

DESCRIPTION OF SYMBOLS 100 Semiconductor element 105 Channel layer 110 Substrate 120 Source electrode 122 Drain electrode 124 Gate electrode 130 Gate insulating layer 150a, 150b Oxide thin film containing ZnO

Claims (10)

A semiconductor element having a source electrode, a drain electrode, a gate electrode, and a channel layer,
A semiconductor element comprising an oxide thin film containing 50 to 95% ZnO in terms of oxide-based mole percentage, between one or both of the source electrode and the drain electrode and the channel layer. The semiconductor element according to claim 1, wherein the oxide thin film further includes SnO ₂ and includes 5 to 50% of SnO ₂ in terms of an oxide-based molar percentage. 3. The semiconductor element according to claim 2, wherein the oxide thin film contains 55 to 100% of ZnO and SnO ₂ in total in terms of oxide-based mole percentage. The value of ZnO / SnO ₂ obtained by dividing the content of ZnO by the content of SnO ₂ in terms of the oxide-based molar percentage is 0.01 to 0.19. 2. The semiconductor element according to item 1. 5. The semiconductor element according to claim 1, wherein the oxide thin film contains 5 to 50% of Ga ₂ O ₃ in terms of an oxide-based molar percentage. The semiconductor device according to claim 1 wherein the oxide thin film containing 5-50% SiO ₂ and GeO ₂ in a total amount in mole percentage based on oxides.   The thickness of the said oxide thin film is 1 nm-500 nm, The semiconductor element of any one of Claims 1-6.   The semiconductor element according to claim 1, wherein the channel layer is amorphous silicon. A method of manufacturing a semiconductor device having a source electrode, a drain electrode, a gate electrode, and a channel layer, and having the channel layer between the source electrode and the drain electrode,
Forming an oxide thin film containing 50 to 95% ZnO in terms of oxide-based mole percentage between one or both of the source electrode and the drain electrode and the channel layer (a)
A method for manufacturing a semiconductor device, comprising: further,
Forming the gate electrode (b);
Forming the channel layer (c);
Forming the source electrode and the drain electrode (d);
Have
The method for manufacturing a semiconductor device according to claim 9, wherein the step (a) is provided between the step (c) and the step (d).

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