JP2018060516A - Method of constructing equivalent circuit of capacitor, and simulation method and apparatus thereof - Google Patents

Method of constructing equivalent circuit of capacitor, and simulation method and apparatus thereof Download PDF

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JP2018060516A
JP2018060516A JP2017122149A JP2017122149A JP2018060516A JP 2018060516 A JP2018060516 A JP 2018060516A JP 2017122149 A JP2017122149 A JP 2017122149A JP 2017122149 A JP2017122149 A JP 2017122149A JP 2018060516 A JP2018060516 A JP 2018060516A
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voltage
circuit
equivalent circuit
capacitor
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JP7063552B2 (en
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慎 板倉
Shin ITAKURA
慎 板倉
宏嘉 小林
Hiroyoshi Kobayashi
宏嘉 小林
政行 清水
Masayuki Shimizu
政行 清水
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Taiyo Yuden Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To satisfactorily approximate characteristics to those obtained when a DC voltage is superposed, with a simple arrangement, and to improve practicability and operability.SOLUTION: An equivalent circuit obtained when a DC voltage is not applied is used as a reference for a capacitor equivalent circuit model obtained when a DC voltage is superposed on a signal. A portion indicating capacity is converted into a voltage control current source or a voltage source used to adjust a signal in response to a superposed DC current voltage. The voltage control current source or the voltage source is described by approximation expression of a current or a voltage indicating change of a signal corresponding to change in capacitor characteristics caused by application of the DC current voltage superposition. An element indicating capacity in the equivalent circuit by the superposition of the DC current voltage is operated as if it was a variable element. This approximation expression does not provide any calculation load to a simulator and prevents divergence.SELECTED DRAWING: Figure 1

Description

本発明は、コンデンサの等価回路の構築方法,シミュレーション方法及びその装置に関し、特に、直流電圧(直流バイアス電圧)が信号電圧に重畳印加される場合に好適なコンデンサの等価回路の構築方法,シミュレーション方法及びその装置に関するものである。   The present invention relates to a capacitor equivalent circuit construction method, simulation method, and apparatus therefor, and more particularly to a capacitor equivalent circuit construction method and simulation method suitable when a DC voltage (DC bias voltage) is superimposed on a signal voltage. And an apparatus for the same.

一般的にコンデンサは、その材料や構造に起因する周波数特性をもち、理想的な容量素子の特性からずれる。そのため、シミュレータなどでコンデンサの特性を精度良く計算する際には、実測したコンデンサの周波数特性に合わせこんだ等価回路モデルが必要とされ、各コンデンサベンダから提供されている。   Generally, a capacitor has frequency characteristics due to its material and structure, and deviates from the characteristics of an ideal capacitive element. For this reason, when calculating the capacitor characteristics with a simulator or the like, an equivalent circuit model that matches the actually measured frequency characteristics of the capacitor is required and provided by each capacitor vendor.

しかし近年、特に積層セラミックコンデンサにおいて、直流電圧重畳時の特性を表現するモデルが必要とされるようになり、直流電圧のない信号のみに対する周波数特性のみを実測に合わせこんだシミュレーションモデルでは対応できなくなってきている。   However, in recent years, especially in multilayer ceramic capacitors, a model that expresses the characteristics when DC voltage is superimposed has become necessary, and simulation models that only match frequency characteristics with only actual measurements for signals without DC voltage cannot be used. It is coming.

このような不具合を改善するものとして、例えば、下記特許文献1に開示されている「コンデンサの回路シミュレーションモデル及びその構築方法,回路シミュレーション方法及び回路シミュレータ」があり、電圧制御電流源を用い、直流電圧がコンデンサに印加されたときは、自動的に印加直流電圧に応じた特性に相当する電流を流す等価回路モデルを提示している。これにより、実測時における直流電圧重畳時の特性を高精度に再現できる。   For example, there is a “capacitor circuit simulation model and its construction method, circuit simulation method and circuit simulator” disclosed in Patent Document 1 below, which uses a voltage-controlled current source to When a voltage is applied to a capacitor, an equivalent circuit model that automatically flows a current corresponding to a characteristic corresponding to the applied DC voltage is presented. Thereby, the characteristic at the time of DC voltage superposition at the time of measurement can be reproduced with high accuracy.

特開2012-150579公報JP 2012-150579 A

しかしながら、上述した背景技術では、同公報図1にあるように、回路構成に微分演算を行うエレメントが含まれ、更にそれが同公報図6のように多数にわたって展開されているため、実際の計算の際には発散などの不具合が生ずる可能性がある。また、DC重畳特性の近似式が多項式近似であることも、発散の不具合を起こす原因となりうる。更に、複雑な計算式が多数存在するため、実際に使用する演算ソフトウェアなどへの計算負荷が大きくなり、結果的に演算に時間を要するようになる。   However, in the background art described above, as shown in FIG. 1 of the same publication, the circuit configuration includes an element for performing a differential operation, and further, as shown in FIG. In such cases, problems such as divergence may occur. Further, the fact that the approximation formula of the DC superimposition characteristic is a polynomial approximation can also cause a problem of divergence. In addition, since there are many complicated calculation formulas, the calculation load on the calculation software or the like actually used increases, and as a result, the calculation takes time.

加えて、等価回路モデルの構成が複雑であるため、1個のコンデンサのシミュレーションモデルを構築するために膨大な工数と時間がかかり、技術的に熟知していないとシミュレーションモデルを構築することができず、技術者の確保が困難といった不都合もある。   In addition, since the structure of the equivalent circuit model is complicated, it takes a lot of man-hours and time to build a simulation model of one capacitor, and it is possible to build a simulation model without technical knowledge. In addition, there is a disadvantage that it is difficult to secure engineers.

本発明は、以上のような点に着目したもので、等価回路モデルの複雑さに起因する様々な実用性の問題を解決し、簡素な構成でありながら、良好に直流電圧重畳特性を近似することができる、実用性,作業性に優れたコンデンサ等価回路の構築方法及びシミュレーション方法及びその装置を提供することを、その目的とする。   The present invention focuses on the above points, solves various practical problems caused by the complexity of the equivalent circuit model, and approximates the DC voltage superposition characteristics satisfactorily with a simple configuration. It is an object of the present invention to provide a capacitor equivalent circuit construction method, simulation method, and apparatus that are excellent in practicality and workability.

本発明のコンデンサの等価回路の構築方法は、信号に直流電圧が重畳して印加されることがあるコンデンサの等価回路の構築方法であって、直流電圧が無印加で、信号のみが印加されている状態において、前記等価回路に含まれる各回路素子の値を実測から求めて基準等価回路を得るステップと、前記基準等価回路に含まれている回路素子であって、直流電圧の重畳により値が変化する回路素子を、電圧制御電流源又は電圧制御電圧源で置換するステップと、置換した回路素子に信号のみが印加されている状態を表現する閉回路を付加するステップと、該閉回路によって回路素子に生ずる電流又は電圧を係数倍した値の電流又は電圧を、前記電圧制御電流源又は電圧制御電圧源から出力するステップと、を含むことを特徴とする。   The method for constructing an equivalent circuit for a capacitor according to the present invention is a method for constructing an equivalent circuit for a capacitor in which a DC voltage may be superimposed on a signal, and only a signal is applied with no DC voltage applied. In a state where a value of each circuit element included in the equivalent circuit is obtained by actual measurement to obtain a reference equivalent circuit, and a circuit element included in the reference equivalent circuit, the value being obtained by superimposing a DC voltage. Replacing a circuit element that changes with a voltage-controlled current source or a voltage-controlled voltage source; adding a closed circuit representing a state in which only a signal is applied to the replaced circuit element; And outputting from the voltage controlled current source or the voltage controlled voltage source a current or voltage having a value obtained by multiplying the current or voltage generated in the element by a coefficient.

主要な形態の一つは、前記信号に直流電圧を重畳印加した状態において実測した回路素子の周波数特性と、前記信号のみが印加されている状態において実測した回路素子の周波数特性とを比較し、直流電圧重畳による前記回路素子の値の変化を求めるステップと、前記ステップで求めた直流電圧重畳による前記回路素子の値の変化に基づいて、前記電圧制御電流源又は電圧制御電圧源における電圧又は電流の値の係数倍の出力を行うステップと、を含むことを特徴とする。   One of the main forms is to compare the frequency characteristic of the circuit element measured in a state where a DC voltage is superimposed on the signal and the frequency characteristic of the circuit element measured in a state where only the signal is applied, A step of obtaining a change in the value of the circuit element due to the DC voltage superimposition, and a voltage or current in the voltage controlled current source or the voltage controlled voltage source based on the change in the value of the circuit element due to the DC voltage superposition obtained in the step And a step of outputting a coefficient multiple of the value of.

他の形態の一つは、前記閉回路において、前記電圧制御電流源又は電圧制御電圧源で置換された回路素子と直列に、電圧源又は電流源が接続されており、これら電圧源又は電流源によって前記閉回路に印加される電圧又は電流に基づいて、前記電圧制御電流源又は電圧制御電圧源の出力を制御することを特徴とする。あるいは、前記基準等価回路に含まれている回路素子が複数あるときに、各回路素子を置換した電圧制御電流源又は電圧制御電圧源、あるいは閉回路を、複数の回路素子に対して共通にまとめたことを特徴とする。更には、前記コンデンサが、積層セラミックコンデンサであることを特徴とする。   In another embodiment, in the closed circuit, a voltage source or a current source is connected in series with the circuit element replaced with the voltage controlled current source or the voltage controlled voltage source. The output of the voltage controlled current source or the voltage controlled voltage source is controlled based on the voltage or current applied to the closed circuit. Alternatively, when there are a plurality of circuit elements included in the reference equivalent circuit, a voltage control current source or a voltage control voltage source in which each circuit element is replaced, or a closed circuit is integrated in common for the plurality of circuit elements. It is characterized by that. Furthermore, the capacitor is a multilayer ceramic capacitor.

本発明のシミュレーション方法は、前記いずれかの構築方法で構築したコンデンサの等価回路を利用して、該等価回路のコンデンサを含む電子回路の特性を得ることを特徴とする。   The simulation method of the present invention is characterized in that characteristics of an electronic circuit including a capacitor of the equivalent circuit are obtained by using an equivalent circuit of the capacitor constructed by any one of the construction methods.

本発明のシミュレーション装置は、前記いずれかの構築方法で構築したコンデンサの等価回路を、シミュレーション対象の回路に含まれるコンデンサの代わりに接続して、シミュレーション対象の回路の特性を演算することを特徴とする。本発明の前記及び他の目的,特徴,利点は、以下の詳細な説明及び添付図面から明瞭になろう。   The simulation apparatus of the present invention is characterized in that the equivalent circuit of the capacitor constructed by any one of the construction methods is connected instead of the capacitor included in the circuit to be simulated, and the characteristics of the circuit to be simulated are calculated. To do. The above and other objects, features and advantages of the present invention will become apparent from the following detailed description and the accompanying drawings.

本発明によれば、直流電圧無印加時の等価回路を基準とし、該等価回路に含まれる回路素子に対して、直流電圧重畳による特性変化を示す回路を付加することとしたので、シミュレーション時の計算負荷が軽減されるとともに、発散などによる計算上の不具合も低減される。また、直流電圧重畳時の受動部品の特性変化を比較的簡素で、かつ高精度に表現できる。   According to the present invention, the circuit showing the characteristic change due to the DC voltage superposition is added to the circuit elements included in the equivalent circuit with reference to the equivalent circuit when no DC voltage is applied. Calculation load is reduced, and calculation problems due to divergence and the like are also reduced. In addition, the characteristic change of the passive component when the DC voltage is superimposed can be expressed with relatively simple and high accuracy.

容量素子に対する実施例1の基本的な考え方を示す説明図である。It is explanatory drawing which shows the fundamental view of Example 1 with respect to a capacitive element. 抵抗素子に対する実施例1の基本的な考え方を示す説明図である。It is explanatory drawing which shows the fundamental view of Example 1 with respect to a resistive element. 容量素子に対する実施例1の他の考え方を示す説明図である。It is explanatory drawing which shows the other view of Example 1 with respect to a capacitive element. 直流電圧無印加時の等価回路の一例を示す回路図である。It is a circuit diagram which shows an example of the equivalent circuit at the time of DC voltage no application. 直流電圧無印加時と重畳時の周波数特性を示すグラフである。It is a graph which shows the frequency characteristic at the time of DC voltage no application and superimposition. 重畳する直流電圧を変化させたときの等価回路素子の下限容量値及び容量変化率の変化を示すグラフである。It is a graph which shows the change of the minimum capacity | capacitance value of an equivalent circuit element when changing the superimposed DC voltage, and a capacity | capacitance change rate. 前記図4の等価回路部に対して前記図1及び図2の等価回路を適用したときの回路構成を示す回路図である。FIG. 5 is a circuit diagram showing a circuit configuration when the equivalent circuit of FIGS. 1 and 2 is applied to the equivalent circuit section of FIG. 4. 前記図4の基準等価回路に対して前記図1及び図2の等価回路を適用したときの全体の回路構成を示す回路図である。FIG. 5 is a circuit diagram showing an overall circuit configuration when the equivalent circuit of FIGS. 1 and 2 is applied to the reference equivalent circuit of FIG. 4. 本発明の実施例2の基本的な考え方を示す説明図である。It is explanatory drawing which shows the fundamental view of Example 2 of this invention. 実施例2において等価回路に接続される複数の電圧制御電圧源をまとめる方法を示す説明図である。FIG. 10 is an explanatory diagram illustrating a method for grouping a plurality of voltage control voltage sources connected to an equivalent circuit in the second embodiment. 実施例2における直流電圧の重畳印加時の等価回路を示す回路図である。6 is a circuit diagram showing an equivalent circuit when a DC voltage is superimposed and applied in Embodiment 2. FIG. 本発明のシミュレーション装置の実施例を示すブロック図である。It is a block diagram which shows the Example of the simulation apparatus of this invention.

以下、本発明を実施するための最良の形態を、実施例に基づいて詳細に説明する。   Hereinafter, the best mode for carrying out the present invention will be described in detail based on examples.

最初に、図1を参照しながら、本発明の実施例1について説明する。図1(A)に示すように、容量Cの容量素子C10の端子間に信号電圧Vacが印加されると、数1式で示す信号電流Iacが流れる。

Figure 2018060516
First, Embodiment 1 of the present invention will be described with reference to FIG. As shown in FIG. 1A, when the signal voltage Vac is applied between the terminals of the capacitor C10 of the capacitor C, the signal current Iac expressed by Equation 1 flows.
Figure 2018060516

一方、同図(B)のように、同図(A)の容量素子C10を電圧制御電流源E10に置き換え、信号電圧Vacを電圧源E12にコピーする。電圧源E12に、容量素子C10と電流モニタ用のモニタ電圧源Vmを直列に接続し、閉回路を形成する。モニタ電圧源Vmは、この閉回路の電流特性に影響しないので、この閉回路は同図(A)に示した回路と等価であり、容量素子C10には数2式で示す信号電流Iacが流れる。

Figure 2018060516
On the other hand, as shown in FIG. 5B, the capacitive element C10 in FIG. 5A is replaced with a voltage-controlled current source E10, and the signal voltage Vac is copied to the voltage source E12. A capacitive element C10 and a monitor voltage source Vm for current monitoring are connected in series to the voltage source E12 to form a closed circuit. Since the monitor voltage source Vm does not affect the current characteristics of the closed circuit, the closed circuit is equivalent to the circuit shown in FIG. 5A, and the signal current Iac shown in the equation (2) flows through the capacitive element C10. .
Figure 2018060516

この信号電流Iacは、モニタ電圧源Vmによりモニタされて電圧制御電流源E10にフィードバックされ、電圧制御電流源E10は信号電流Iacに係数C*を乗じて出力する。以上のような操作を行うことで、端子間に流れる電流I(E10)は、数3式で示すようになる。この数3式から明らかなように、図1(B)の等価回路は、容量素子C10の容量CをC倍した容量素子を接続した回路と等価になる。このように、電圧制御電流源E10を利用することで、直流電圧重畳時の特性を表すことができる。

Figure 2018060516
This signal current Iac is monitored by the monitor voltage source Vm and fed back to the voltage control current source E10. The voltage control current source E10 multiplies the signal current Iac by the coefficient C * and outputs it. By performing the operation as described above, the current I (E10) flowing between the terminals is expressed by the equation (3). As is apparent from Equation (3), the equivalent circuit of FIG. 1B is equivalent to a circuit in which a capacitive element obtained by multiplying the capacitance C of the capacitive element C10 by C * is connected. In this way, by using the voltage controlled current source E10, the characteristics at the time of superimposing the DC voltage can be expressed.
Figure 2018060516

容量素子の場合と同様に、抵抗素子に対してもほぼ同じ手順で抵抗をR*倍した等価回路を得ることができる。すなわち、図2(A)に示すように、抵抗値Rの抵抗素子R10の端子間に信号電圧Vacが印加されると、数4式で示す信号電流Iacが流れる。

Figure 2018060516
As in the case of the capacitive element, an equivalent circuit obtained by multiplying the resistance by R * can be obtained for the resistive element by substantially the same procedure. That is, as shown in FIG. 2A, when the signal voltage Vac is applied between the terminals of the resistance element R10 having the resistance value R, the signal current Iac expressed by the equation (4) flows.
Figure 2018060516

一方、同図(B)のように、同図(A)の抵抗素子R10を電圧制御電流源E10に置き換え、信号電圧Vacを電圧源E12にコピーする。電圧源E12には、抵抗素子R10と電流モニタ用のモニタ電圧源Vmを直列に接続し、閉回路を形成する。モニタ電圧源Vmは、この閉回路の電流特性に影響しないので、この閉回路は同図(A)に示した回路と等価であり、抵抗素子R10には数5式で示す信号電流Iacが流れる。

Figure 2018060516
On the other hand, as shown in FIG. 5B, the resistance element R10 in FIG. 6A is replaced with a voltage-controlled current source E10, and the signal voltage Vac is copied to the voltage source E12. A resistor R10 and a monitor voltage source Vm for current monitoring are connected in series to the voltage source E12 to form a closed circuit. Since the monitor voltage source Vm does not affect the current characteristics of the closed circuit, the closed circuit is equivalent to the circuit shown in FIG. 5A, and the signal current Iac shown in the equation (5) flows through the resistance element R10. .
Figure 2018060516

この信号電流Iacは、モニタ電圧源Vmによりモニタされて電圧制御電流源E10にフィードバックされ、電圧制御電流源E10は信号電流Iacに係数R*を乗じて(「除して」)出力する。以上のような操作を行うことで、端子間に流れる電流I(E10)は、数6式で示すようになる。この数6式から明らかなように、図2(B)の等価回路は、抵抗素子R10の抵抗値RをR倍(電流は1/R倍)した抵抗素子を接続した回路と等価になる。

Figure 2018060516
This signal current Iac is monitored by the monitor voltage source Vm and fed back to the voltage control current source E10. The voltage control current source E10 multiplies the signal current Iac by a coefficient R * ("divides") and outputs the signal. By performing the operation as described above, the current I (E10) flowing between the terminals is expressed by Equation 6. As is apparent from Equation (6), the equivalent circuit of FIG. 2B is equivalent to a circuit in which a resistance element R * times the resistance value R of the resistance element R10 is connected (current is 1 / R * times). Become.
Figure 2018060516

更に、電圧制御電圧源で容量素子C10の容量をC*倍した等価回路を構成することも可能である。図3(A)に示すように、容量Cの容量素子C10の端子間の信号電圧Vacは、信号電流Iacに対して、数7式で示すようになる。

Figure 2018060516
Furthermore, it is possible to configure an equivalent circuit in which the capacitance of the capacitive element C10 is multiplied by C * with a voltage control voltage source. As shown in FIG. 3A, the signal voltage Vac between the terminals of the capacitor C10 of the capacitor C is expressed by the equation 7 with respect to the signal current Iac.
Figure 2018060516

一方、同図(B)に示すように、同図(A)の容量素子C10を電圧制御電圧源E20に置き換えるとともに、モニタ電源Vmを直列に接続する。このモニタ電源Vmでモニタした信号電流Iacを、電流源E22にコピーする。電流源E22には容量素子C10を直列に接続し、閉回路を形成する。この閉回路は、同図(A)に示した回路と等価であり、容量素子C10には数8式で示す信号電流Iacが流れる。

Figure 2018060516
On the other hand, as shown in FIG. 5B, the capacitive element C10 in FIG. 6A is replaced with a voltage control voltage source E20, and a monitor power source Vm is connected in series. The signal current Iac monitored by the monitor power source Vm is copied to the current source E22. A capacitive element C10 is connected in series to the current source E22 to form a closed circuit. This closed circuit is equivalent to the circuit shown in FIG. 5A, and the signal current Iac shown by the equation 8 flows through the capacitive element C10.
Figure 2018060516

そして、容量素子C10に印加される信号電圧Vacを電圧制御電圧源E20にフィードバックするとともに、電圧制御電圧源E20でフィードバックした電圧を1/C倍して出力すると、電流源E22の端子間電圧をV(3,4)としたとき、モニタ電圧源Vmは影響しないので、数9式で示す端子間電圧V(1,2)が得られ、結果的に容量素子C10の容量CをC*倍した等価回路が得られる。

Figure 2018060516
When the signal voltage Vac applied to the capacitive element C10 is fed back to the voltage control voltage source E20 and the voltage fed back by the voltage control voltage source E20 is multiplied by 1 / C * and output, the voltage across the terminals of the current source E22 is output. Since V (3,4) does not affect the monitor voltage source Vm, the inter-terminal voltage V (1, 2) shown in Equation 9 is obtained, and as a result, the capacitance C of the capacitive element C10 is represented by C *. A doubled equivalent circuit is obtained.
Figure 2018060516

抵抗素子の場合も同様の手順で、電圧制御電圧源の出力をR*倍すると、抵抗素子の抵抗値をR*倍した等価回路が得られる。 In the case of a resistor element, the equivalent procedure is obtained by multiplying the output of the voltage control voltage source by R * in the same procedure, and multiplying the resistance value of the resistor element by R * .

このような関係を利用して、直流電圧Vdc無印加時(無重畳時)の信号電圧Vacのみが印加される等価回路(以下「基準等価回路」という)の容量素子,抵抗素子の直流電圧Vdc重畳による容量変化率,抵抗変化率を予め実測により調べておき、各素子に対して、上述したように電圧制御電流源(図3では電圧制御電圧源)を直列接続することで、前記基準等価回路で表されるコンデンサの直流電圧重畳特性を表現できる。すなわち、
a,前記基準等価回路に含まれている容量素子や抵抗素子の回路定数を予め実測により求めておく。
b,次に、信号電圧Vacに直流電圧Vdcを重畳して印加した状態における前記容量素子や抵抗素子の値を実測により求める。
c,前記aの直流電圧Vdc=0のときの各素子の値と、前記bの直流電圧重畳印加時(Vac+Vdc)の各素子の値から、直流電圧重畳による容量変化率,抵抗変化率を求める。
d,求めた各変化率から、前記数3式,数6式により電流I(E10)を求める。
e,求めた電流I(E10)の電圧制御電流源E10(図3では電圧制御電圧源E20)を、前記基準等価回路における容量素子や抵抗素子の代わりに接続することで、直流電圧Vdcを信号電圧Vacに重畳して印加したときの等価回路を得ることができる。
By utilizing such a relationship, the DC voltage Vdc of the capacitive element and the resistive element of an equivalent circuit (hereinafter referred to as “reference equivalent circuit”) to which only the signal voltage Vac is applied when no DC voltage Vdc is applied (no superposition). The reference equivalent is obtained by previously measuring the capacitance change rate and resistance change rate due to superposition, and connecting a voltage controlled current source (voltage controlled voltage source in FIG. 3) in series to each element as described above. The DC voltage superposition characteristics of the capacitor represented by the circuit can be expressed. That is,
a. The circuit constants of the capacitive element and the resistive element included in the reference equivalent circuit are obtained in advance by actual measurement.
b, Next, the values of the capacitive element and the resistive element in a state in which the DC voltage Vdc is superimposed and applied to the signal voltage Vac are obtained by actual measurement.
c, Capacitance change rate and resistance change rate due to DC voltage superposition are obtained from the value of each element when DC voltage Vdc of a is 0 and the value of each element when DC voltage superimposition is applied (bac + Vdc). .
d, The current I (E 10 ) is obtained from the obtained change rates by the above formulas 3 and 6.
e. By connecting a voltage-controlled current source E10 (voltage-controlled voltage source E20 in FIG. 3) of the obtained current I (E 10 ) instead of the capacitive element and the resistive element in the reference equivalent circuit, the DC voltage Vdc is An equivalent circuit can be obtained when applied in a superimposed manner on the signal voltage Vac.

図4(A)には、直流電圧Vdcが印加されない基準等価回路の一例が示されている。この基準等価回路は、特開2013-228997号公報の図17として公知のものである。同図において、キャパシタンスCm,C1〜C3が直列に接続されており、キャパシタンスC1〜C3には、レジスタンスRC1〜RC3がそれぞれ並列に接続されている。また、これらの回路の全体に対して並列にキャパシタンスC0が並列に接続されている。以上の等価回路部QAが容量性の部分であり、これに含まれる各素子に、直流電圧重畳による変化率を反映した電圧制御電流源を直列に接続することで、直流電圧重畳特性の等価回路とすることができる。   FIG. 4A shows an example of a reference equivalent circuit to which the DC voltage Vdc is not applied. This reference equivalent circuit is known as FIG. 17 of JP 2013-228997 A. In the figure, capacitances Cm and C1 to C3 are connected in series, and resistances RC1 to RC3 are connected in parallel to the capacitances C1 to C3, respectively. Further, a capacitance C0 is connected in parallel to the entire circuit. The equivalent circuit portion QA described above is a capacitive portion, and by connecting a voltage control current source reflecting the rate of change due to DC voltage superimposition to each element included in this, an equivalent circuit of DC voltage superimposition characteristics. It can be.

等価回路部QAには、更にレジスタンスR0が並列に、インダクタンスL0が直列に接続されている。また、インダクタンスLmと、インダクタンスL1〜L3とレジスタンスRL1〜RL3をそれぞれ直列に接続した3つの直列回路が、更に並列に接続されており、これが、前記インダクタンスL0と直列に接続されている。また、レジスタンスRdcも直列に接続されている。そして、以上の回路に対して、キャパシタンスCtとレジスタンスRtの直列回路が、並列に接続されている。   The equivalent circuit portion QA is further connected with a resistance R0 in parallel and an inductance L0 in series. Further, an inductance Lm, and three series circuits in which the inductances L1 to L3 and the resistances RL1 to RL3 are connected in series are further connected in parallel, which are connected in series to the inductance L0. Resistance Rdc is also connected in series. A series circuit of a capacitance Ct and a resistance Rt is connected in parallel to the above circuit.

ここで、上述した等価回路部QAには、回路素子が8個存在し、各素子の直流電圧重畳時における容量変化率や抵抗変化率をすべて調べてもよいが、必ずしも作業効率がよいとはいえない。そこで、本実施例では、積層セラミックコンデンサのいくつかのサンプルにおける周波数特性を利用することとする。   Here, in the above-described equivalent circuit portion QA, there are eight circuit elements, and the capacitance change rate and the resistance change rate at the time of superimposing the DC voltage of each element may be examined, but the work efficiency is not necessarily good. I can't say that. Therefore, in this embodiment, frequency characteristics of several samples of the multilayer ceramic capacitor are used.

図5には、代表的な材料を使用した積層セラミックコンデンササンプルにおける小振幅信号印加時の周波数特性が示されている。例えば、出願人製の22μF積層セラミックコンデンサの数種類のサンプルを用いて、小振幅信号印加時の周波数特性を実測する。同図(A)は直流電圧無印加時の特性を示し、同図(B)は直流電圧重畳時の特性を示す。グラフの横軸は周波数(対数)を示し、縦軸は容量を示す。   FIG. 5 shows frequency characteristics when a small amplitude signal is applied to a multilayer ceramic capacitor sample using a typical material. For example, frequency characteristics when a small amplitude signal is applied are measured using several types of samples of 22 μF multilayer ceramic capacitors manufactured by the applicant. (A) shows the characteristics when no DC voltage is applied, and (B) shows the characteristics when DC voltage is superimposed. The horizontal axis of the graph indicates frequency (logarithm), and the vertical axis indicates capacity.

これらの実線のグラフGFa,GFbに示すように、コンデンサ容量は、周波数の対数に対して直線的に減少し、最終的にある容量値を下限値として、その値に収束することが分かった。鎖線のグラフGLa,GLbは、容量の減少を示す直線であり、下限値がGPa,GPbである。これらのグラフを比較すれば明らかなように、グラフGLa,GLbの傾き及び下限値GPa,GPbが、直流電圧Vdcの無印加時と重畳時とで変化することが分かる。このように、積層セラミックコンデンサの直流電圧重畳の有無による容量の周波数特性の変化は、グラフGLa,GLbの傾きで示される容量変化率ΔGLa,ΔGLbと下限容量値GPa,GPbの2つのパラメータの変化で特徴付けられる。   As shown in these solid line graphs GFa and GFb, it has been found that the capacitance of the capacitor linearly decreases with respect to the logarithm of the frequency and finally converges to a certain capacitance value as a lower limit value. The chain line graphs GLa and GLb are straight lines indicating a decrease in capacity, and the lower limit values are GPa and GPb. As is apparent from the comparison of these graphs, it can be seen that the slopes of the graphs GLa and GLb and the lower limit values GPa and GPb change between when the DC voltage Vdc is not applied and when it is superimposed. As described above, the change in the frequency characteristic of the capacitance due to the presence or absence of the DC voltage superposition of the multilayer ceramic capacitor is the change in the two parameters of the capacitance change rates ΔGLa and ΔGLb and the lower limit capacitance values GPa and GPb indicated by the slopes of the graphs GLa and GLb. It is characterized by.

してみると、直流電圧Vdcを重畳印加した等価回路についても、前記容量変化率ΔGLa,ΔGLbと下限容量値GPa,GPbに対応する素子構成部分があればよいことになり、図4(A)に示した等価回路部QAに含まれる8個の回路素子のそれぞれについて直流電圧重畳による容量ないし抵抗の変化率を調べなくてもよい。実際、直流電圧無印加時の積層セラミックコンデンサの容量周波数特性を基準等価回路で合わせ込み、そのときの回路定数を基準とし、次に、直流電圧重畳印加時に、図4(B)に示す等価回路部QA1,QA2において印加電圧に応じた共通の変化率を各素子の定数にそれぞれかけると、直流電圧重畳印加時の等価回路定数を定めることができる。   As a result, the equivalent circuit to which the DC voltage Vdc is applied in a superimposed manner also needs to have element components corresponding to the capacitance change rates ΔGLa and ΔGLb and the lower limit capacitance values GPa and GPb, as shown in FIG. For each of the eight circuit elements included in the equivalent circuit portion QA shown in FIG. 6, it is not necessary to examine the rate of change of the capacitance or resistance due to the DC voltage superposition. Actually, the capacitance frequency characteristics of the multilayer ceramic capacitor when no DC voltage is applied are matched with the reference equivalent circuit, and the circuit constant at that time is used as a reference. Next, the equivalent circuit shown in FIG. When the common rate of change corresponding to the applied voltage is applied to the constants of the respective elements in the parts QA1 and QA2, the equivalent circuit constant when the DC voltage superimposed application is applied can be determined.

図5(C)には、その様子が示されている。同図中、実線のグラフGFAは、出願人製の22μF積層セラミックコンデンサの直流電圧無印加時の実測した容量周波数特性を示し、実線のグラフGFBは、同コンデンサの直流電圧重畳時の実測した容量周波数特性を示す。重畳した直流電圧Vdcは1[V]である。これらのグラフに示すように、直流電圧Vdcの重畳によって、容量変化率と下限容量値が減少し、グラフGFAがグラフGFBになる。   FIG. 5C shows the state. In the figure, the solid line graph GFA shows the measured capacitance frequency characteristics of the 22 μF multilayer ceramic capacitor manufactured by the applicant when no DC voltage is applied, and the solid line graph GFB shows the measured capacitance when the DC voltage of the capacitor is superimposed. Shows frequency characteristics. The superimposed DC voltage Vdc is 1 [V]. As shown in these graphs, the capacity change rate and the lower limit capacity value are reduced by superimposing the DC voltage Vdc, and the graph GFA becomes the graph GFB.

一方、点線のグラフGSAは、前記直流電圧無印加時の実測した容量周波数特性を、図4に示した基準等価回路で合わせ込んだものである。各回路素子の具体的な数値例を示すと、以下のようになる。
Cm=1.5718uF
C1=1uF
C2=0.52638uF
C3=0.001uF
RC1=36.345Ω
RC2=7.9335Ω
RC3=6.5488Ω
On the other hand, the dotted line graph GSA is obtained by combining the measured capacitance frequency characteristics when no DC voltage is applied with the reference equivalent circuit shown in FIG. Specific numerical examples of each circuit element are as follows.
Cm = 1.5718uF
C1 = 1uF
C2 = 0.52638uF
C3 = 0.001uF
RC1 = 36.345Ω
RC2 = 7.9335Ω
RC3 = 6.5488Ω

このような直流電圧無印加時の回路定数に対して、前記等価回路部QA1のキャパシタンスC0の容量値を約0.698倍、等価回路部QA2のキャパシタンスCm,C1〜C3の容量値を約0.48倍、レジスタンスRC1〜RC3の抵抗値を約1/0.48倍としたときの等価回路から得られる容量周波数特性を示すと、点線のグラフGSBのようになる。これを実測値のグラフGFBと比較すると、非常によく一致していることが分かる。また、等価回路部QA1のキャパシタンスC0の容量値を変化させると、概ねグラフGSBの下限容量値(前記GPa,GPbに対応)が変化し、等価回路部QA2のキャパシタンスCm,C1〜C3の容量値や、レジスタンスRC1〜RC3の抵抗値を変化させると、概ねグラフGSBの容量変化率(前記グラフGLa,GLbの傾きに対応)が変化する。このように、図4の基準等価回路の等価回路部QA1の特性が下限容量値にほぼ相当し、等価回路部QA2の特性が容量変化率にほぼ相当する。   With respect to such a circuit constant when no DC voltage is applied, the capacitance value of the capacitance C0 of the equivalent circuit portion QA1 is about 0.698 times, and the capacitance values of the capacitances Cm and C1 to C3 of the equivalent circuit portion QA2 are about 0.48 times. The capacitance frequency characteristic obtained from the equivalent circuit when the resistance values of the resistances RC1 to RC3 are about 1 / 0.48 times is shown as a dotted line graph GSB. When this is compared with the graph GFB of actual measurement values, it can be seen that the values agree very well. Further, when the capacitance value of the capacitance C0 of the equivalent circuit portion QA1 is changed, the lower limit capacitance value of the graph GSB (corresponding to the GPa and GPb) changes, and the capacitance values of the capacitances Cm and C1 to C3 of the equivalent circuit portion QA2 change. If the resistance values of the resistances RC1 to RC3 are changed, the capacity change rate of the graph GSB (corresponding to the slopes of the graphs GLa and GLb) changes. As described above, the characteristic of the equivalent circuit portion QA1 of the reference equivalent circuit of FIG. 4 substantially corresponds to the lower limit capacitance value, and the characteristic of the equivalent circuit portion QA2 substantially corresponds to the capacitance change rate.

上述した図5は、重畳した直流電圧Vdcが1[V]の場合であるが、同じような処理を、直流電圧Vdcの値を変えて繰り返し行うと、直流電圧Vdcと、等価回路部QA1,QA2に含まれる各素子の各回路定数の変化率との関係を求めることができる。図6(A)には、直流電圧Vdcに対する下限容量値の実測値を合わせこんだ計算値が丸印で示されており、同図(B)には、直流電圧Vdcに対する容量変化率の実測値を合わせこんだ計算値が丸印で示されている。同図(A)は、等価回路部QA1のキャパシタンスC0の変化率(直流電圧無印加時の値に対する変化割合)に相当し、同図(B)は、等価回路部QA2のキャパシタンスCm,C1〜C3の容量値の変化率(直流電圧無印加時の値に対する変化割合)、ならびにレジスタンスRC1〜RC3の抵抗値の変化率の逆数に相当する。   FIG. 5 described above is a case where the superimposed DC voltage Vdc is 1 [V]. However, if the same processing is repeated while changing the value of the DC voltage Vdc, the DC voltage Vdc and the equivalent circuit unit QA1, The relationship with the change rate of each circuit constant of each element included in QA2 can be obtained. In FIG. 6 (A), the calculated value obtained by combining the measured value of the lower limit capacity value with respect to the DC voltage Vdc is indicated by a circle, and in FIG. 6 (B), the measured capacity change rate with respect to the DC voltage Vdc. The calculated value that combines the values is indicated by a circle. 4A corresponds to the rate of change of the capacitance C0 of the equivalent circuit portion QA1 (rate of change relative to the value when no DC voltage is applied), and FIG. 3B shows the capacitances Cm, C1 to C1 of the equivalent circuit portion QA2. This corresponds to the rate of change of the capacitance value of C3 (change rate with respect to the value when no DC voltage is applied) and the reciprocal of the rate of change of resistance values of the resistances RC1 to RC3.

図6の実測値のグラフを数式で示すと、次の数10式のようになる。式中、Vpk,ζk,αk,βkはフィッティング係数である。

Figure 2018060516
The measured value graph of FIG. 6 is expressed by the following mathematical formula 10. In the equation, Vpk, ζk, αk, βk are fitting coefficients.
Figure 2018060516

この数10式を見ると、関数は直流電圧Vdcに対して偶関数で逆電圧に対して対称であり、かつ、べき級数のような発散の心配がない。このため、シミュレータ上での計算結果の矛盾や、計算時の負荷が生じにくい。このように、直流電圧重畳印加による回路定数の変化率を前記数10式を使用して記述した電圧制御電流源を、等価回路部QA1,QA2の各素子に直列に接続することで、直流電圧Vdcの重畳によって生ずる容量変化率や抵抗変化率を表すことができる。   Looking at the equation (10), the function is an even function with respect to the DC voltage Vdc and symmetrical with respect to the reverse voltage, and there is no fear of divergence such as a power series. For this reason, contradiction of calculation results on the simulator and load during calculation are unlikely to occur. In this way, by connecting the voltage controlled current source in which the change rate of the circuit constant due to the DC voltage superimposition application is described using the above equation 10 to each element of the equivalent circuit portions QA1 and QA2, in series, The rate of change in capacitance and the rate of change in resistance caused by the superposition of Vdc can be expressed.

次に、上述した図4に示した等価回路部QAに対して図1及び図2に示した等価回路の適用例を説明する。例えば、図4(B)ないし図7(A)に示す等価回路部QA2に着目すると、キャパシタンスCm,C1〜C3の容量値をC*倍、レジスタンスRC1〜RC3の抵抗値を1/C*倍する図1(B),図2(B)の等価回路にそれぞれ置き換える。キャパシタンスC1とレジスタンスRC1の並列接続に対し、本来であれば、それぞれ変化率に対応する電圧制御電流源をそれぞれ接続すべきであるが、これをまとめるようにする。キャパシタンスC2とレジスタンスRC2の組,キャパシタンスC3とレジスタンスRC3の組についても同様にまとめ、更に等価回路部QA2の全体を電圧制御電流源E10に置き換えている。   Next, an application example of the equivalent circuit shown in FIGS. 1 and 2 will be described with respect to the equivalent circuit portion QA shown in FIG. 4 described above. For example, focusing on the equivalent circuit portion QA2 shown in FIGS. 4B to 7A, the capacitance values of the capacitances Cm and C1 to C3 are C * times, and the resistance values of the resistances RC1 to RC3 are 1 / C * times. Replace with the equivalent circuits of FIG. 1 (B) and FIG. 2 (B). For the parallel connection of the capacitance C1 and the resistance RC1, normally, the voltage controlled current sources corresponding to the respective rates of change should be connected to each other. The set of the capacitance C2 and the resistance RC2, the set of the capacitance C3 and the resistance RC3 are summarized in the same manner, and the entire equivalent circuit portion QA2 is replaced with the voltage controlled current source E10.

素子単体のときと同様にフィードバック電流をC*倍すると、キルヒホッフの法則により、以下の数11式が得られる。なお、同式において、Iciは、キャパシタンスCm,C1,C2,C3の電流Icm,Ic1,Ic2,Ic3であり、IRciは、レジスタンスRC1,RC2,RC3の電流IRc1,IRc2,IRc3である。各素子Cm,C1〜C3,RC1〜RC3にかかる電圧は変化しないので、結果的に、等価回路部QA2を構成する各素子に流れる電流をC*倍する効果が得られる。従って、図7(B)の等価回路は、同図(A)の等価回路部QA2のキャパシタンスCm,C1〜C3の容量値をC*倍、レジスタンスRC1〜RC3の抵抗値を1/C* 倍した等価回路となり、素子各々に電流源を用いた等価回路を構築することなく、個々の電流源をまとめた簡便な構成の等価回路を得ることができる。

Figure 2018060516
When the feedback current is multiplied by C * as in the case of a single element, the following equation (11) is obtained according to Kirchhoff's law. In the equation, Ici is the currents Icm, Ic1, Ic2, and Ic3 of the capacitances Cm, C1, C2, and C3, and IRci is the currents IRc1, IRc2, and IRc3 of the resistances RC1, RC2, and RC3. Since the voltage applied to each element Cm, C1 to C3, RC1 to RC3 does not change, as a result, the effect of multiplying the current flowing through each element constituting the equivalent circuit portion QA2 by C * is obtained. Therefore, the equivalent circuit of FIG. 7B has the capacitance values Cm and C1 to C3 of the equivalent circuit portion QA2 of FIG. 7A as C * times, and the resistance values of the resistances RC1 to RC3 as 1 / C * times. Thus, an equivalent circuit having a simple configuration in which the individual current sources are combined can be obtained without constructing an equivalent circuit using a current source for each element.
Figure 2018060516

同様に、等価回路部QA1についても、図1(B)の等価回路を適用すると、図4に示した等価回路は、図8に示すようになる。   Similarly, when the equivalent circuit of FIG. 1B is applied to the equivalent circuit portion QA1, the equivalent circuit shown in FIG. 4 becomes as shown in FIG.

次に、本実施例の全体動作について説明する。
a,図4の基準等価回路に含まれる回路素子の各回路定数を、シミュレーション対象のコンデンサに直流電圧Vdcが重畳されていない状態における周波数特性の実測値に基づいてそれぞれ決定する。
b,次に、直流電圧Vdcを重畳したときの周波数特性を実測し、図6に示したグラフを得る。
c,そして、それらのグラフから数10式の演算を行い、図8の電圧制御電流源EC0,ECmの係数C,Rを決定する。
d,次に、直流電圧Vdcの重畳時は、電圧制御電流源EC0,ECmによる電流I(E10)の出力によって、重畳直流電圧Vdcに見合う回路定数変化が生成される。
e,図8の等価回路は、例えば、代表的なスパイスシミュレータ(LTspice, PSpice)など)に適合するスパイスモデルフォーマットに記述し、スパイスモデルを用いてシミュレータ上でシミュレーションを行う。あるいは、等価回路の各素子の回路定数と容量性部分の素子の定数変化率の情報を、スタンドアローンないしWeb用のソフトウェアに記述した上で、上記実施例で示した計算手法をソフトウェア上で適用し、対象となる積層セラミックコンデンサの任意直流電圧における各周波数特性のグラフやデータの提示,任意直流電圧における指定の周波数特性を満たすコンデンサの検索,より簡単な等価回路に適用した場合の周波数特性の計算,などを行うようにしてもよい。
Next, the overall operation of this embodiment will be described.
a. Each circuit constant of the circuit element included in the reference equivalent circuit of FIG. 4 is determined based on an actual measurement value of the frequency characteristic in a state where the DC voltage Vdc is not superimposed on the capacitor to be simulated.
b, Next, the frequency characteristic when the DC voltage Vdc is superimposed is measured, and the graph shown in FIG. 6 is obtained.
c, and the calculation of Equation 10 is performed from these graphs to determine the coefficients C * and R * of the voltage controlled current sources EC0 and ECm of FIG.
d. Next, when the DC voltage Vdc is superimposed, a change in circuit constant corresponding to the superimposed DC voltage Vdc is generated by the output of the current I (E 10 ) from the voltage controlled current sources EC0 and ECm.
e, the equivalent circuit of FIG. 8 is described in a spice model format suitable for a typical spice simulator (LTspice, PSpice, etc.), for example, and simulation is performed on the simulator using the spice model. Alternatively, the circuit constant of each element of the equivalent circuit and the constant change rate information of the element of the capacitive part are described in the stand-alone or Web software, and the calculation method shown in the above embodiment is applied on the software. And presenting graphs and data of each frequency characteristic at an arbitrary DC voltage of the target multilayer ceramic capacitor, searching for a capacitor that satisfies a specified frequency characteristic at an arbitrary DC voltage, and frequency characteristics when applied to a simpler equivalent circuit Calculations may be performed.

以上のように、本実施例によれば、図4に示した直流電圧無印加時の等価回路を基準とし、その容量性を表現する部分QAに、重畳された直流電圧Vdcに応じて信号電流Iacを調節する電圧制御電流源EC0,ECmを並列に接続し、直流電圧重畳印加時におけるコンデンサの特性変化分に相当する印加信号電流変化を、電圧制御電流源EC0,ECmで表現することとした。これにより、基準等価回路中の容量性を表現する素子が、直流電圧重畳印加によって可変素子のように振舞う。その際の電圧制御電流源EC0,ECmの電流(数3式、数6式)に使用される係数(C*, R*)の近似式(数10式)は、シミュレーション時における計算負荷を低減し、使用電圧内において発散などによる計算上の不具合も生じない。これにより、任意の直流電圧重畳印加時の積層セラミックコンデンサの特性を、精度よく、かつ素早く等価回路上に表現できる。また、比較的簡素な等価回路の構成のため、等価回路作成における合わせ込みなどの作業も容易になり、等価回路作成の作業性や効率性が向上する。   As described above, according to the present embodiment, the signal current corresponding to the superimposed DC voltage Vdc is superimposed on the portion QA expressing the capacitance with reference to the equivalent circuit shown in FIG. 4 when no DC voltage is applied. Voltage controlled current sources EC0 and ECm for adjusting Iac are connected in parallel, and the applied signal current change corresponding to the change in characteristics of the capacitor when DC voltage is superimposed is expressed by the voltage controlled current sources EC0 and ECm. . As a result, the element expressing the capacitance in the reference equivalent circuit behaves like a variable element when the DC voltage is superimposed. The approximate expression (Equation 10) of the coefficients (C *, R *) used for the currents (Equation 3 and Equation 6) of the voltage controlled current sources EC0 and ECm at that time reduces the calculation load during simulation. However, there is no calculation problem due to divergence within the operating voltage. As a result, the characteristics of the multilayer ceramic capacitor when an arbitrary DC voltage is superimposed can be accurately and quickly expressed on the equivalent circuit. In addition, the relatively simple equivalent circuit configuration facilitates operations such as alignment in creating an equivalent circuit, and improves the workability and efficiency of creating an equivalent circuit.

次に、図9〜図11を参照しながら、本発明の実施例2について説明する。図9(A)に示すように、容量素子に対して電圧制御電圧源を直列に接続し、電圧制御電圧源によって以下の数12式で表される電圧Vsを印加したとすると、見かけ上Cの変化率分だけ、容量素子の容量値が変化するように見える。

Figure 2018060516
Next, Embodiment 2 of the present invention will be described with reference to FIGS. As shown in FIG. 9A, assuming that a voltage control voltage source is connected in series to the capacitive element and a voltage Vs expressed by the following equation (12) is applied by the voltage control voltage source, it is apparent that C It seems that the capacitance value of the capacitive element changes by the change rate of * .
Figure 2018060516

同様に、図9(B)に示すように、抵抗素子に対して電圧制御電圧源を直列に接続し、電圧制御電圧源によって以下の数13式で表される電圧Vsを印加したとすると、見かけ上Rの変化率分だけ、抵抗素子の抵抗値が変化するように見える。

Figure 2018060516
Similarly, as shown in FIG. 9B, when a voltage control voltage source is connected in series to a resistance element and a voltage Vs expressed by the following equation (13) is applied by the voltage control voltage source, Apparently, it seems that the resistance value of the resistance element changes by the change rate of R * .
Figure 2018060516

このような関係を利用して、直流電圧Vdc無印加時(無重畳時)の信号電圧Vacのみが印加される基準等価回路の容量素子,抵抗素子の直流電圧Vdc重畳による容量変化率,抵抗変化率を予め実測により調べておき、各素子に対して、上述したように電圧制御電圧源を直列接続することで、前記基準等価回路で表されるコンデンサの直流電圧重畳特性を表現できる。すなわち、
a,前記基準等価回路に含まれている容量素子や抵抗素子の回路定数を予め実測により求めておく。
b,次に、信号電圧Vacに直流電圧Vdcを重畳して印加した状態における前記容量素子や抵抗素子の値を実測により求める。
c,前記aの直流電圧Vdc=0のときの各素子の値と、前記bの直流電圧重畳印加時(Vac+Vdc)の各素子の値から、直流電圧重畳による容量変化率,抵抗変化率を求める。
d,求めた各変化率から、前記数12式,数13式により電圧Vsを求める。
e,求めた電圧Vsの直流制御電圧源を、前記基準等価回路における容量素子や抵抗素子に直列に接続することで、直流電圧Vdcを信号電圧Vacに重畳して印加したときの等価回路を得ることができる。
By utilizing such a relationship, the capacitance change rate and resistance change due to the superimposition of the DC voltage Vdc of the reference equivalent circuit to which only the signal voltage Vac is applied when no DC voltage Vdc is applied (no superimposition) and the DC voltage Vdc of the resistance element. By examining the rate in advance by actual measurement and connecting the voltage control voltage source in series to each element as described above, the DC voltage superposition characteristics of the capacitor represented by the reference equivalent circuit can be expressed. That is,
a. The circuit constants of the capacitive element and the resistive element included in the reference equivalent circuit are obtained in advance by actual measurement.
b, Next, the values of the capacitive element and the resistive element in a state in which the DC voltage Vdc is superimposed and applied to the signal voltage Vac are obtained by actual measurement.
c, Capacitance change rate and resistance change rate due to DC voltage superposition are obtained from the value of each element when DC voltage Vdc of a is 0 and the value of each element when DC voltage superimposition is applied (bac + Vdc). .
d, The voltage Vs is obtained from the obtained change rates according to the equations (12) and (13).
e. A DC control voltage source of the obtained voltage Vs is connected in series with the capacitive element and the resistive element in the reference equivalent circuit, thereby obtaining an equivalent circuit when the DC voltage Vdc is superimposed on the signal voltage Vac. be able to.

次に、図4の基準等価回路に対する電圧制御電圧源の接続について説明する。まず、等価回路部QA1については、キャパシタンスC0に、図6(A)のグラフで示す変化率を数12式に適用した電圧値を有する電圧制御電圧源DE1を接続する。次に、等価回路部QA2に着目すると、キャパシタンスC1〜C3とレジスタンスRC1〜RC3の並列接続の組が3つ存在する。等価回路部QA1の各素子の変化率は、キャパシタンスでは共通しており、レジスタンスではその逆数が変化率となる(数13式参照)。このため、並列接続の各素子に、前記数10式の変化率を記述した電圧制御電圧源を接続すると、以下の数14式のようなアドミッタンスYとなる。同式中、Cは並列接続されているキャパシタンスの値,Rは並列接続されているレジスタンスの値である。

Figure 2018060516
Next, connection of the voltage control voltage source to the reference equivalent circuit of FIG. 4 will be described. First, with respect to the equivalent circuit portion QA1, a voltage control voltage source DE1 having a voltage value obtained by applying the change rate shown in the graph of FIG. Next, paying attention to the equivalent circuit portion QA2, there are three sets of parallel connection of the capacitances C1 to C3 and the resistances RC1 to RC3. The change rate of each element of the equivalent circuit portion QA1 is common in capacitance, and the reciprocal of resistance is the change rate (see Equation 13). For this reason, when a voltage control voltage source describing the rate of change of the equation (10) is connected to each element connected in parallel, the admittance Y shown in the following equation (14) is obtained. In the equation, C is a value of capacitance connected in parallel, and R is a value of resistance connected in parallel.
Figure 2018060516

この数14式を参照すると、キャパシタンスとレジスタンスの並列接続の組にしたものの全体に、キャパシタンスの変化率を記述した電圧制御電圧源を接続した回路のアドミッタンスYと一致する。従って、各並列接続の組の電圧制御電圧源は、1つにまとめることができる。   Referring to Equation 14, the admittance Y of the circuit in which the voltage control voltage source describing the rate of change of the capacitance is connected to the whole of the combination of the capacitance and the resistance connected in parallel. Therefore, the voltage control voltage source of each parallel connection set can be combined into one.

図10(A)には、その様子が示されている。キャパシタンスC1とレジスタンスRC1の並列接続に対し、本来であれば、それぞれ変化率に対応する電圧制御電圧源DVC1,DVRC1をそれぞれ接続すべきであるが、これを電圧制御電圧源DV1にまとめている。キャパシタンスC2とレジスタンスRC2の組,キャパシタンスC3とレジスタンスRC3の組についても同様である。   FIG. 10A shows the state. For the parallel connection of the capacitance C1 and the resistance RC1, originally, the voltage control voltage sources DVC1 and DVRC1 corresponding to the rate of change should be connected to each other, but these are combined into the voltage control voltage source DV1. The same applies to the set of capacitance C2 and resistance RC2, and the set of capacitance C3 and resistance RC3.

そうすると、上述した等価回路部QA2の電圧制御電圧源は、同図(B)に示すDVm,DV1〜DV3のようになり、同じ容量変化率を持つインピーダンスを直列に4つ接続した回路となる。同じ変化率の電圧制御電圧源DVm,DV1〜DV3の直列接続によるインピーダンスは、以下の数15式のようになる。従って、同図に示すように、電圧制御電圧源以外の素子を全て接続してから直列に1つ電圧制御電圧源DE2を接続したものと等価になることが分かる。

Figure 2018060516
Then, the voltage control voltage source of the above-described equivalent circuit portion QA2 becomes DVm and DV1 to DV3 shown in FIG. 4B, and is a circuit in which four impedances having the same capacitance change rate are connected in series. The impedance due to the series connection of the voltage control voltage sources DVm, DV1 to DV3 having the same rate of change is expressed by the following equation (15). Therefore, as shown in the figure, it is understood that this is equivalent to one in which all the elements other than the voltage control voltage source are connected and then one voltage control voltage source DE2 is connected in series.
Figure 2018060516

次に、電圧制御電圧源DE1,DE2で信号電圧Vacを検知する際に、重畳されている余分な直流電圧Vdcを除去する必要がある。このため、基準等価回路の入力電圧(信号電圧Vac+重畳直流電圧Vdc)を、極めてカットオフ周波数が低いハイパスフィルタで直流成分を取り除いた後に、電圧制御電圧源DE1,DE2に検知信号として供給する。このようなフィルタ回路を、電圧制御電圧源DE1,DE2とともに図4の基準等価回路に加えることで、直流電圧Vdc重畳時の周波数特性を表現する等価回路を得ることができる。   Next, when the voltage control voltage sources DE1 and DE2 detect the signal voltage Vac, it is necessary to remove the superposed DC voltage Vdc. For this reason, the input voltage (signal voltage Vac + superimposed DC voltage Vdc) of the reference equivalent circuit is supplied as a detection signal to the voltage control voltage sources DE1 and DE2 after the DC component is removed by a high-pass filter having a very low cutoff frequency. By adding such a filter circuit to the reference equivalent circuit of FIG. 4 together with the voltage control voltage sources DE1 and DE2, an equivalent circuit expressing the frequency characteristics when the DC voltage Vdc is superimposed can be obtained.

図11には、その一例が示されている。等価回路部QA1においては電圧制御電圧源DE1が直列に接続されており、等価回路部QA2においては電圧制御電圧源DE2が直列に接続されている。また、フィルタ回路GBにおいては、直列キャパシタンスCP及び並列インダクタンスLPによってハイパスフィルタが構成されており、信号電圧Vacは負荷RPによって検知されるようになっている。更に、電圧制御電圧源DE3には、等価回路の入力側と出力側がそれぞれ接続されており、入力電圧Vin,出力電圧Voutが供給されている。電圧制御電圧源DE3は、それら入力電圧Vin,出力電圧Voutの差を出力する。そして、その差から前記ハイパスフィルタで余分な直流電圧Vdcが除去されるとともに、前記負荷RPで信号電圧Vacが検出されて、電圧制御電圧源DE1,DE2にそれぞれ供給されるようになっている。   An example is shown in FIG. In the equivalent circuit section QA1, the voltage control voltage source DE1 is connected in series, and in the equivalent circuit section QA2, the voltage control voltage source DE2 is connected in series. In the filter circuit GB, a high-pass filter is configured by the series capacitance CP and the parallel inductance LP, and the signal voltage Vac is detected by the load RP. Further, the input side and the output side of the equivalent circuit are connected to the voltage control voltage source DE3, and the input voltage Vin and the output voltage Vout are supplied. The voltage control voltage source DE3 outputs the difference between the input voltage Vin and the output voltage Vout. Then, the excess DC voltage Vdc is removed by the high-pass filter from the difference, and the signal voltage Vac is detected by the load RP and supplied to the voltage control voltage sources DE1 and DE2, respectively.

次に、本実施例の全体動作について説明する。
a,図4の基準等価回路に含まれる回路素子の各回路定数を、シミュレーション対象のコンデンサに直流電圧Vdcが重畳されていない状態における周波数特性の実測値に基づいてそれぞれ決定する。
b,次に、直流電圧Vdcを重畳したときの周波数特性を実測し、図6に示したグラフを得る。
c,そして、それらのグラフから数10式の演算を行い、図11の電圧制御電圧源DE1,DE2の係数Cを決定する。なお、本例では、電圧制御電圧源DE2は、数15式により係数をまとめることが保証されているが、係数を個別に決定する場合(C≠1/R)は、前記電圧制御電圧源DE2のように電圧源をまとめることができないので、個々の素子に電圧制御電圧源を直列に接続したままとする。
d,次に、直流電圧Vdcの重畳時は、図11のフィルタ回路QBによって信号電圧Vacを検知し、これにより電圧制御電圧源DE1,DE2による電圧Vsの出力によって、重畳直流電圧Vdcに見合う回路定数変化が生成される。
e,図11の等価回路は、例えば、代表的なスパイスシミュレータ(LTspice, PSpice)など)に適合するスパイスモデルフォーマットに記述し、スパイスモデルを用いてシミュレータ上でシミュレーションを行う。あるいは、等価回路の各素子の回路定数と容量性部分の素子の定数変化率の情報を、スタンドアローンないしWeb用のソフトウェアに記述した上で、上記実施例で示した計算手法をソフトウェア上で適用し、対象となる積層セラミックコンデンサの任意直流電圧における各周波数特性のグラフやデータの提示,任意直流電圧における指定の周波数特性を満たすコンデンサの検索,より簡単な等価回路に適用した場合の周波数特性の計算,などを行うようにしてもよい。
Next, the overall operation of this embodiment will be described.
a. Each circuit constant of the circuit element included in the reference equivalent circuit of FIG. 4 is determined based on an actual measurement value of the frequency characteristic in a state where the DC voltage Vdc is not superimposed on the capacitor to be simulated.
b, Next, the frequency characteristic when the DC voltage Vdc is superimposed is measured, and the graph shown in FIG. 6 is obtained.
c, and the calculation of Equation 10 is performed from these graphs to determine the coefficient C * of the voltage control voltage sources DE1 and DE2 in FIG. In this example, it is guaranteed that the voltage control voltage source DE2 summarizes the coefficients according to the equation (15). However, when the coefficients are determined individually (C * ≠ 1 / R * ), the voltage control voltage source DE2 Since the voltage sources cannot be combined like the source DE2, voltage control voltage sources remain connected in series to the individual elements.
d. Next, when the DC voltage Vdc is superimposed, the signal voltage Vac is detected by the filter circuit QB of FIG. 11, and thereby the circuit corresponding to the superimposed DC voltage Vdc by the output of the voltage Vs by the voltage control voltage sources DE1 and DE2. A constant change is generated.
e, the equivalent circuit of FIG. 11 is described in a spice model format suitable for a typical spice simulator (LTspice, PSpice, etc.), for example, and simulation is performed on the simulator using the spice model. Alternatively, the circuit constant of each element of the equivalent circuit and the constant change rate information of the element of the capacitive part are described in the stand-alone or Web software, and the calculation method shown in the above embodiment is applied on the software. And presenting graphs and data of each frequency characteristic at an arbitrary DC voltage of the target multilayer ceramic capacitor, searching for a capacitor that satisfies a specified frequency characteristic at an arbitrary DC voltage, and frequency characteristics when applied to a simpler equivalent circuit Calculations may be performed.

以上のように、本実施例によれば、図4に示した直流電圧無印加時の等価回路を基準とし、その容量性を表現する部分QAに、重畳された直流電圧Vdcに応じて信号電圧Vacを調節する電圧制御電圧源DE1,DE2を直列に接続し、直流電圧重畳印加時におけるコンデンサの特性変化分に相当する印加信号電圧変化を、電圧制御電圧源DE1,DE2で表現することとした。これにより、基準等価回路中の容量性を表現する素子が、直流電圧重畳印加によって可変素子のように振舞う。その際の電圧制御電圧源DE1,DE2の電圧(数12式、数13式)に使用される係数(C*, R*)の近似式(数10式)は、シミュレーション時における計算負荷を低減し、使用電圧内において発散などによる計算上の不具合も生じない。これにより、任意の直流電圧重畳印加時の積層セラミックコンデンサの特性を、精度よく、かつ素早く等価回路上に表現できる。また、比較的簡素な等価回路の構成のため、等価回路作成における合わせこみなどの作業も容易になり、等価回路作成の作業性や効率性が向上する。   As described above, according to the present embodiment, the signal voltage corresponding to the superimposed DC voltage Vdc is superimposed on the portion QA expressing the capacitance with reference to the equivalent circuit shown in FIG. 4 when no DC voltage is applied. Voltage control voltage sources DE1 and DE2 for adjusting Vac are connected in series, and the applied signal voltage change corresponding to the change in the characteristics of the capacitor when DC voltage is superimposed is expressed by voltage control voltage sources DE1 and DE2. . As a result, the element expressing the capacitance in the reference equivalent circuit behaves like a variable element when the DC voltage is superimposed. The approximate expression (Equation 10) of the coefficients (C *, R *) used for the voltages (Equation 12 and Equation 13) of the voltage control voltage sources DE1 and DE2 at that time reduces the calculation load during the simulation. However, there is no calculation problem due to divergence within the operating voltage. As a result, the characteristics of the multilayer ceramic capacitor when an arbitrary DC voltage is superimposed can be accurately and quickly expressed on the equivalent circuit. In addition, the relatively simple equivalent circuit configuration facilitates operations such as fitting in creating an equivalent circuit, and improves the workability and efficiency of creating an equivalent circuit.

次に、図12を参照しながら、シミュレーション装置の実施例について説明する。本実施例のシミュレーション装置100は、一般的なコンピュータシステムによって構成されており、CPUを中心に構成された演算処理部110に、キーボードなどの入力部122,液晶ディスプレイなどの出力部124,プログラムメモリ130,データメモリ140が接続された構成となっている。プログラムメモリ130には、シミュレーションプログラム132(例えばSPICEシミュレータ)が格納されている。データメモリ140には、コンデンサを含むシミュレーション対象回路142と、図8ないし図11に示したコンデンサ等価回路144が格納されている。   Next, an embodiment of the simulation apparatus will be described with reference to FIG. The simulation apparatus 100 according to the present embodiment is configured by a general computer system, and includes an arithmetic processing unit 110 mainly configured by a CPU, an input unit 122 such as a keyboard, an output unit 124 such as a liquid crystal display, and a program memory. 130 and the data memory 140 are connected. The program memory 130 stores a simulation program 132 (for example, a SPICE simulator). The data memory 140 stores a simulation target circuit 142 including a capacitor and a capacitor equivalent circuit 144 illustrated in FIGS. 8 to 11.

シミュレーション対象回路142としては、直流電圧Vdcが信号電圧Vacに重畳印加されるような回路,例えば、CPUのような演算処理用ICの電源ラインなどが該当する。コンデンサ等価回路144は、各コンデンサ毎にそれぞれ用意される。例えば、○○社製の型番○○○の等価回路144A,144B,・・・という具合である。なお、シミュレーションプログラム132がSPICEシミュレータのときは、コンデンサ等価回路144はSPICEファイルとして提供される。   The simulation target circuit 142 corresponds to a circuit in which the DC voltage Vdc is superimposed on the signal voltage Vac, for example, a power supply line of an arithmetic processing IC such as a CPU. The capacitor equivalent circuit 144 is prepared for each capacitor. For example, the equivalent circuit 144A, 144B,... When the simulation program 132 is a SPICE simulator, the capacitor equivalent circuit 144 is provided as a SPICE file.

シミュレーション対象回路142に含まれるコンデンサとして、いずれの会社のいずれの型番のコンデンサを使用するのかが指示されると、該当するコンデンサの等価回路144がデータメモリ140から読み出され、これがシミュレーション対象回路142のコンデンサの位置に接続される。そして、その回路に基づいて、プログラムメモリ130のシミュレーションプログラム132が演算処理部110で実行され、所望のシミュレーションが行われる。図8ないし図11に示した直流電圧重畳印加時の等価回路を用いることで、シミュレーションに要する時間を短縮して効率的に精度の高いシミュレーションを行うことができる。   When it is instructed which capacitor of which model of which company is used as the capacitor included in the simulation target circuit 142, the equivalent circuit 144 of the corresponding capacitor is read from the data memory 140, and this is the simulation target circuit 142. Connected to the capacitor position. Based on the circuit, the simulation program 132 in the program memory 130 is executed by the arithmetic processing unit 110 to perform a desired simulation. By using the equivalent circuit at the time of applying the DC voltage superimposed shown in FIGS. 8 to 11, the time required for the simulation can be shortened and an efficient simulation can be performed efficiently.

以上のように、本実施例によれば、次のような効果が得られる。
(1)電子部品メーカーやその代理商社は、自社が提供する各種コンデンサについて、その直流電圧重畳印加時の等価回路を顧客に提供し、もしくは会社のホームページに公開し、自社製品を採用する顧客に対して回路設計上の便宜を図ることができ、更には、製品販売機会の創出につなげることができる。
(2)電子機器メーカーや電子回路の設計会社は、前記公開された直流電圧重畳印加時の等価回路を使用することで、設計回路に最適な電子部品を効率よく選定して電子製品を精度よく設計でき、設計時間を大幅に短縮できる。
As described above, according to the present embodiment, the following effects can be obtained.
(1) Electronic component manufacturers and their trading companies provide customers with equivalent circuits for the various capacitors they provide when DC voltage is superimposed, or publish them on the company's website to customers who adopt their products. On the other hand, convenience in circuit design can be achieved, and further, product sales opportunities can be created.
(2) Electronic device manufacturers and electronic circuit design companies can use the published equivalent circuit when DC voltage is superimposed to efficiently select the optimal electronic components for the design circuit and accurately select electronic products. Design is possible and the design time can be greatly reduced.

なお、本発明は、上述した実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲内において種々変更を加えることができる。例えば、以下のものも含まれる。
(1)前記実施例で示した基準等価回路は一例であり、各種の構成の基準等価回路に本発明は適用可能である。
(2)前記実施例で示した回路定数の数値や比率なども一例であり、何ら限定されるものではない。
(3)前記説明では、図1及び図2に示した電圧制御電流源E10を用いた等価回路を基準等価回路に含まれる容量素子や抵抗素子に適用した場合を主として説明したが、代わりに、図3に示した電圧制御電圧源E20を用いた等価回路を用いてもよい。また、前記実施例では、基準等価回路に含まれている容量素子や抵抗素子の場合を説明したが、インダクタ素子の場合も同様である。
(4)本発明は、積層セラミックコンデンサが典型的な適用例であるが、各種のコンデンサの等価回路に適用可能である。
In addition, this invention is not limited to the Example mentioned above, A various change can be added in the range which does not deviate from the summary of this invention. For example, the following are also included.
(1) The reference equivalent circuit shown in the above embodiment is an example, and the present invention can be applied to reference equivalent circuits having various configurations.
(2) The numerical values and ratios of the circuit constants shown in the above embodiment are examples, and are not limited at all.
(3) In the above description, the case where the equivalent circuit using the voltage controlled current source E10 shown in FIGS. 1 and 2 is applied to the capacitive element and the resistive element included in the reference equivalent circuit has been mainly described. An equivalent circuit using the voltage control voltage source E20 shown in FIG. 3 may be used. In the above embodiment, the case of the capacitive element and the resistance element included in the reference equivalent circuit has been described, but the same applies to the case of the inductor element.
(4) The present invention is typically applied to a multilayer ceramic capacitor, but can be applied to equivalent circuits of various capacitors.

本発明によれば、直流電圧無印加時の等価回路を基準とし、信号に重畳印加される直流電圧による特性変化を示す回路を付加することとしたので、シミュレーション時の計算負荷が軽減されるとともに、発散などによる計算上の不具合も低減される。また、直流電圧重畳時の回路素子の特性変化を比較的簡素で、かつ高精度に表現できるので、積層セラミックコンデンサなどの特性解析に好適である。   According to the present invention, since a circuit showing a characteristic change due to a DC voltage superimposed on a signal is added on the basis of an equivalent circuit when no DC voltage is applied, a calculation load during simulation is reduced. In addition, calculation problems due to divergence and the like are reduced. In addition, since the characteristic change of the circuit element when the DC voltage is superimposed can be expressed relatively simply and with high accuracy, it is suitable for characteristic analysis of a multilayer ceramic capacitor or the like.

C0,C1〜C3,Cm,Ct,CP:キャパシタンス
C10:容量素子
E10:電圧制御電流源
E12:電圧源
E20:電圧制御電圧源
E22:電流源
L0,L1〜L3,Lm,LP:インダクタンス
R0,RC1〜RC3,RL1〜RL3,Rdc,Rt,RP:レジスタンス
R10:抵抗素子
DE1,DE2,DE3,DVC1,DVRC1,DVm,DV1〜DV3:電圧制御電圧源
QA,QA1,QA2:等価回路部
QB:フィルタ回路
Vac:信号電圧
Vdc:直流電圧
Vin:入力電圧
Vout:出力電圧
Vm:モニタ電圧源
100:シミュレーション装置
110:演算処理部
122:入力部
124:出力部
130:プログラムメモリ
132:シミュレーションプログラム
140:データメモリ
142:シミュレーション対象回路
144,144A,144B,・・:コンデンサの等価回路
C0, C1 to C3, Cm, Ct, CP: Capacitance C10: Capacitance element E10: Voltage controlled current source E12: Voltage source E20: Voltage controlled voltage source E22: Current source L0, L1 to L3, Lm, LP: Inductance R0, RC1 to RC3, RL1 to RL3, Rdc, Rt, RP: Resistance R10: Resistive elements DE1, DE2, DE3, DVC1, DVRC1, DVm, DV1 to DV3: Voltage control voltage sources QA, QA1, QA2: Equivalent circuit part QB: Filter circuit Vac: Signal voltage Vdc: DC voltage Vin: Input voltage Vout: Output voltage Vm: Monitor voltage source 100: Simulation device 110: Arithmetic processing unit 122: Input unit 124: Output unit 130: Program memory 132: Simulation program 140: Data memory 142: Simulation target circuit 144, 144A, 144B,...: Equivalent circuit of capacitor

図4(A)には、直流電圧Vdcが印加されない基準等価回路の一例が示されている。この基準等価回路は、特開2013-228997号公報の図17として公知のものである。同図において、キャパシタンスCm,C1〜C3が直列に接続されており、キャパシタンスC1〜C3には、レジスタンスRC1〜RC3がそれぞれ並列に接続されている。また、これらの回路の全体に対して並列にキャパシタンスC0が並列に接続されている。以上の等価回路部QAが容量性の部分であり、これに含まれる各素子、直流電圧重畳による変化率を反映した電圧制御電流源に置換することで、直流電圧重畳特性の等価回路とすることができる。 FIG. 4A shows an example of a reference equivalent circuit to which the DC voltage Vdc is not applied. This reference equivalent circuit is known as FIG. 17 of JP 2013-228997 A. In the figure, capacitances Cm and C1 to C3 are connected in series, and resistances RC1 to RC3 are connected in parallel to the capacitances C1 to C3, respectively. Further, a capacitance C0 is connected in parallel to the entire circuit. More equivalent circuit QA is a moiety of the capacitive, the elements contained therein, by replacing the voltage controlled current source that reflects the rate of change by a DC voltage superimposed to an equivalent circuit of the DC voltage bias characteristics be able to.

この数10式を見ると、関数は直流電圧Vdcに対して偶関数で逆電圧に対して対称であり、かつ、べき級数のような発散の心配がない。このため、シミュレータ上での計算結果の矛盾や、計算時の負荷が生じにくい。このように、等価回路部QA1,QA2を直流電圧重畳印加による回路定数の変化率を前記数10式を使用して記述した電圧制御電流源に置換することで、直流電圧Vdcの重畳によって生ずる容量変化率や抵抗変化率を表すことができる。 Looking at the equation (10), the function is an even function with respect to the DC voltage Vdc and symmetrical with respect to the reverse voltage, and there is no fear of divergence such as a power series. For this reason, contradiction of calculation results on the simulator and load during calculation are unlikely to occur. In this manner, by substituting the equivalent circuit QA1, QA2 rate of change in circuit constant by a DC voltage superimposed application of the voltage controlled current source described using the number 10 formula, produced by superposition of DC voltage Vdc Capacitance change rate and resistance change rate can be expressed.

素子単体のときと同様にフィードバック電流をC*倍すると、キルヒホッフの法則により、以下の数11式が得られる。なお、同式において、Iciは、キャパシタンスCm,C1,C2,C3の電流Icm,Ic1,Ic2,Ic3であり、IRciは、レジスタンスRC1,RC2,RC3の電流IRc1,IRc2,IRc3である。各素子Cm,C1〜C3,RC1〜RC3にかかる電圧は変化しないので、結果的に、等価回路部QA2を構成する各素子に流れる電流をC*倍する効果が得られる。従って、図7(B)の等価回路は、同図(A)の等価回路部QA2のキャパシタンスCm,C1〜C3の容量値をC*倍、レジスタンスRC1〜RC3の抵抗値を1/C* 倍した等価回路となり、素子各々に電流源を用いた等価回路を構築することなく、個々の電流源をまとめた簡便な構成の等価回路を得ることができる。

Figure 2018060516
When the feedback current is multiplied by C * as in the case of a single element, the following equation (11) is obtained according to Kirchhoff's law. In the equation, Ici is the currents Icm, Ic1, Ic2, and Ic3 of the capacitances Cm, C1, C2, and C3, and IRci is the currents IRc1, IRc2, and IRc3 of the resistances RC1, RC2, and RC3. Since the voltage applied to each element Cm, C1 to C3, RC1 to RC3 does not change, as a result, the effect of multiplying the current flowing through each element constituting the equivalent circuit portion QA2 by C * is obtained. Therefore, the equivalent circuit of FIG. 7B has the capacitance values Cm and C1 to C3 of the equivalent circuit portion QA2 of FIG. 7A as C * times, and the resistance values of the resistances RC1 to RC3 as 1 / C * times. Thus, an equivalent circuit having a simple configuration in which the individual current sources are combined can be obtained without constructing an equivalent circuit using a current source for each element.
Figure 2018060516

Claims (7)

信号に直流電圧が重畳して印加されることがあるコンデンサの等価回路の構築方法であって、
直流電圧が無印加で、信号のみが印加されている状態において、前記等価回路に含まれる各回路素子の値を実測から求めて基準等価回路を得るステップと、
前記基準等価回路に含まれている回路素子であって、直流電圧の重畳により値が変化する回路素子を、電圧制御電流源又は電圧制御電圧源で置換するステップと、
置換した回路素子に信号のみが印加されている状態を表現する閉回路を付加するステップと、
該閉回路によって回路素子に生ずる電流又は電圧を係数倍した値の電流又は電圧を、前記電圧制御電流源又は電圧制御電圧源から出力するステップと、
を含むことを特徴とするコンデンサの等価回路の構築方法。
A method for constructing an equivalent circuit of a capacitor in which a DC voltage may be applied in a superimposed manner on a signal,
In a state where no DC voltage is applied and only a signal is applied, obtaining a reference equivalent circuit by obtaining the value of each circuit element included in the equivalent circuit from actual measurement;
Replacing a circuit element included in the reference equivalent circuit, the value of which changes due to superposition of a DC voltage, with a voltage-controlled current source or a voltage-controlled voltage source;
Adding a closed circuit representing a state in which only the signal is applied to the replaced circuit element;
Outputting a current or voltage having a value obtained by multiplying a current or voltage generated in the circuit element by the closed circuit by a factor from the voltage controlled current source or the voltage controlled voltage source;
A method for constructing an equivalent circuit of a capacitor, comprising:
前記信号に直流電圧を重畳印加した状態において実測した回路素子の周波数特性と、前記信号のみが印加されている状態において実測した回路素子の周波数特性とを比較し、直流電圧重畳による前記回路素子の値の変化を求めるステップと、
前記ステップで求めた直流電圧重畳による前記回路素子の値の変化に基づいて、前記電圧制御電流源又は電圧制御電圧源における電流又は電圧の値の係数倍の出力を行うステップと、
を含むことを特徴とする請求項1記載のコンデンサの等価回路の構築方法。
The frequency characteristic of the circuit element measured in a state where a DC voltage is superimposed on the signal is compared with the frequency characteristic of the circuit element actually measured in a state where only the signal is applied, and Determining a change in value;
Based on the change in the value of the circuit element due to the DC voltage superposition obtained in the step, the step of outputting a coefficient multiple of the current or voltage value in the voltage controlled current source or voltage controlled voltage source;
The method for constructing an equivalent circuit for a capacitor according to claim 1, comprising:
前記閉回路において、前記電圧制御電流源又は電圧制御電圧源で置換された回路素子と直列に、電圧源又は電流源が接続されており、
これら電圧源又は電流源によって前記閉回路に印加される電圧又は電流に基づいて、前記電圧制御電流源又は電圧制御電圧源の出力を制御することを特徴とする請求項1又は2記載のコンデンサの等価回路の構築方法。
In the closed circuit, a voltage source or a current source is connected in series with the circuit element replaced with the voltage controlled current source or the voltage controlled voltage source,
3. The capacitor according to claim 1, wherein an output of the voltage controlled current source or the voltage controlled voltage source is controlled based on a voltage or current applied to the closed circuit by the voltage source or the current source. Equivalent circuit construction method.
前記基準等価回路に含まれている回路素子が複数あるときに、各回路素子を置換した電圧制御電流源又は電圧制御電圧源、あるいは閉回路を、複数の回路素子に対して共通にまとめたことを特徴とする請求項1〜3のいずれか一項に記載のコンデンサの等価回路の構築方法。   When there are a plurality of circuit elements included in the reference equivalent circuit, a voltage controlled current source or a voltage controlled voltage source in which each circuit element is replaced or a closed circuit is grouped together for a plurality of circuit elements. The method for constructing an equivalent circuit for a capacitor according to any one of claims 1 to 3. 前記コンデンサが、積層セラミックコンデンサであることを特徴とする請求項1〜4のいずれか一項に記載のコンデンサの等価回路の構築方法。   The said capacitor | condenser is a multilayer ceramic capacitor, The construction method of the equivalent circuit of the capacitor | condenser as described in any one of Claims 1-4 characterized by the above-mentioned. 請求項1〜5のいずれか一項に記載の構築方法で構築したコンデンサの等価回路を利用して、該等価回路のコンデンサを含む電子回路の特性を得ることを特徴とするコンデンサの等価回路のシミュレーション方法。   An equivalent circuit of a capacitor characterized in that, by using the equivalent circuit of the capacitor constructed by the construction method according to any one of claims 1 to 5, characteristics of an electronic circuit including the capacitor of the equivalent circuit are obtained. Simulation method. 請求項1〜6のいずれか一項に記載の構築方法で構築したコンデンサの等価回路を、シミュレーション対象の回路に含まれるコンデンサの代わりに接続して、シミュレーション対象の回路の特性を演算することを特徴とするコンデンサの等価回路のシミュレーション装置。   An equivalent circuit of the capacitor constructed by the construction method according to any one of claims 1 to 6 is connected instead of the capacitor included in the circuit to be simulated, and the characteristics of the circuit to be simulated are calculated. A device for simulating an equivalent circuit of a characteristic capacitor.
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