JP2018056985A - Circuit device, physical quantity measurement device, electronic apparatus, and movable body - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit device which can realize high-performance of time digital conversion while spontaneously generating a first signal, and the like.SOLUTION: A circuit device is input with a first clock signal CK1 having a first clock frequency f1 and a second clock signal CK2 having a second clock frequency f2 different from the first clock frequency f1, and includes a time digital conversion circuit converting a time difference TDF between transition timing of a first signal STA and transition timing of a second signal STP into a digital value DQ and a synchronization circuit synchronizing phases of the first and second clock signals CK1 and CK2. The time digital conversion circuit subjects a signal level of the first signal STA to transition based on the first clock signal CK1 and obtains the digital value DQ corresponding to the time difference TDF by performing phase comparison between the second signal STP of which a signal level is subjected to transition corresponding to the first signal STA and the second clock signal CK2 after phase synchronization timing TM of the first and second clock signals CK1 and CK2.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a circuit device, a physical quantity measuring device, an electronic device, a moving object, and the like.

  Conventionally, a time digital conversion circuit that converts time into a digital value is known. The time digital conversion circuit converts a time difference between transition timings of a first signal (for example, a start signal) and a second signal (for example, a stop signal) into a digital value. As a conventional example of a circuit device having such a time digital conversion circuit, for example, conventional techniques disclosed in Patent Documents 1 to 4 are known.

JP 2009-246484 A JP 2007-110370 A JP 2010-119077 A Japanese Patent Laid-Open No. 5-87954

  In the prior arts of Patent Documents 1 to 3, time digital conversion is realized using a so-called vernier delay circuit. In the vernier delay circuit, time digital conversion is realized using a delay element which is a semiconductor element.

  Patent Document 4 includes a first crystal oscillator that outputs a first clock pulse, a second crystal oscillator that outputs a second clock pulse, an edge coincidence detection circuit, a synchronization counter, a microcomputer, and a transmission time control unit. A minute time measuring device provided is disclosed. The edge coincidence detection circuit detects the synchronization point of the first and second clock pulses. The synchronization counter performs a count process in synchronization with the first and second clock pulses. The microcomputer calculates an unknown time from the start pulse to the stop pulse based on the value of the synchronization counter. The transmission time control unit outputs a start pulse according to the output of the edge coincidence detection circuit and the values of the synchronization counter and the microcomputer.

  However, in the prior arts disclosed in Patent Documents 1 to 3, when the time difference between the start signal and the stop signal is obtained, the start signal is input from the outside. Moreover, in the time digital conversion using a semiconductor element like patent documents 1-3, although the improvement of a resolution is easy, there exists a subject that the improvement of an accuracy is difficult.

  In the prior art of Patent Document 4, since the first crystal oscillator and the second crystal oscillator oscillate independently, the synchronization point is detected by the edge coincidence detection circuit and the time digital conversion is realized. There is a need to. For this reason, problems such as complicated circuit processing, a long conversion time, and reduced accuracy occur.

  According to some aspects of the present invention, it is possible to provide a circuit device, a physical quantity measuring device, an electronic device, a moving body, and the like that can realize high-performance time digital conversion while spontaneously generating the first signal.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or modes.

  According to one embodiment of the present invention, a first clock signal having a first clock frequency and a second clock signal having a second clock frequency different from the first clock frequency are input. A time digital conversion circuit that converts a time difference in transition timing of a second signal into a digital value; and a synchronization circuit that synchronizes the phases of the first clock signal and the second clock signal. The conversion circuit transitions the signal level of the first signal based on the first clock signal after the phase synchronization timing of the first clock signal and the second clock signal, and the first signal And a circuit device for obtaining the digital value corresponding to the time difference by performing a phase comparison between the second signal whose signal level transitions in response to the second clock signal and the second clock signal. .

  According to one aspect of the present invention, first and second clock signals having different clock frequencies are input, and time digital conversion processing for converting a time difference between transition timings of the first and second signals into a digital value is performed. . Further, the synchronization circuit performs phase synchronization of the first and second clock signals. In one embodiment of the present invention, for example, after the phase synchronization timing of the first and second clock signals by the synchronization circuit, the signal level of the first signal is changed. When the second signal level transitions in response to the first signal, the phase comparison between the second signal and the second clock signal is performed, and a digital value corresponding to the time difference is obtained. In this way, time digital conversion can be realized by spontaneously generating the first signal. The digital value can be obtained by comparing the phase of the second and second clock signals while synchronizing the phase of the first and second clock signals at the phase synchronization timing, realizing high-performance time-to-digital conversion. it can. Therefore, it is possible to provide a circuit device or the like that can realize high performance of time digital conversion while spontaneously generating the first signal.

  In the aspect of the invention, the time digital conversion circuit may transition the signal level of the first signal every clock cycle of the first clock signal after the phase synchronization timing.

  In this way, since the first signal level is shifted every clock cycle of the first clock signal and the digital value corresponding to the time difference can be obtained, high-performance time digital conversion can be realized.

  In the aspect of the invention, the time digital conversion circuit may perform phase comparison between the second signal whose signal level transitions in response to the first signal and the second clock signal. The digital value corresponding to the time difference may be obtained by performing every clock cycle of one clock signal.

  In this way, since the phase comparison between the second signal and the second clock signal can be performed every clock cycle of the first clock signal to obtain a digital value corresponding to the time difference, the time digital The conversion speed can be increased.

  In the aspect of the invention, the synchronization circuit may synchronize the phase of the first clock signal and the second clock signal at each phase synchronization timing.

  In this way, the first and second clock signals are phase-synchronized at each phase synchronization timing, and after the phase synchronization timing, the signal level of the first signal is transited to change the second signal and the second clock signal. It is possible to compare the phases of the clock signals. Therefore, time digital conversion can be executed using the phase synchronization timing as a reference timing, and the time digital conversion processing and circuit configuration can be simplified.

  In one embodiment of the present invention, the time-to-digital conversion circuit corresponds to the first signal after the phase synchronization timing, and the signal level of the first signal transits based on the first clock signal. Then, when the signal level of the second signal transitions, the digital value corresponding to the time difference is specified by specifying a timing at which the phase relationship between the second signal and the second clock signal is switched. You may ask for.

  In this way, after the phase synchronization timing, the time digital conversion can be realized by a simple process of specifying the timing at which the phase relationship between the second signal and the second clock signal is switched. Digital conversion processing and circuit configuration can be simplified.

  In the aspect of the invention, the time digital conversion circuit may perform time digital conversion with a resolution corresponding to a frequency difference between the first clock frequency and the second clock frequency.

  In this way, by reducing the frequency difference between the first and second clock frequencies, the resolution can be reduced and high resolution of time digital conversion can be realized.

  In the aspect of the invention, the time digital conversion circuit may calculate a time difference between transition timings of the first clock signal and the second clock signal in the i-th clock cycle after the phase synchronization timing. When the time difference TR = i × Δt, the time digital conversion may be performed with the resolution Δt.

  In this way, time digital conversion with resolution Δt can be realized using the time difference TR = i × Δt between the transition timings of the first and second clock signals after the phase synchronization timing. .

  In the aspect of the present invention, the time-to-digital conversion circuit may be configured such that the phase relationship between the second signal and the second clock signal is switched in the jth clock cycle after the phase synchronization timing. In addition, a digital value corresponding to the clock time difference TR = j × Δt may be obtained as the digital value corresponding to the time difference.

  In this way, the digital value corresponding to the time difference can be obtained by identifying the clock cycle in which the phase relationship between the second signal and the second clock signal is switched after the phase synchronization timing. become.

  In the aspect of the invention, the time-to-digital conversion circuit may be configured such that the first clock signal is a clock signal generated using a first oscillator, and the second clock signal is a second clock signal. It may be a clock signal generated using an oscillator.

  By performing time digital conversion using the first and second clock signals generated by the first and second oscillators as described above, more accurate time digital conversion can be realized.

  In the aspect of the invention, the time digital conversion circuit may include a signal output unit that outputs the first signal every clock cycle of the first clock signal based on the first clock signal. Good.

  If such a signal output unit is provided, the signal level of the first signal can be changed every clock cycle of the first clock signal.

  In the aspect of the invention, the time-to-digital conversion circuit may not update the count value when the phase comparison result signal between the second signal and the second clock signal is at the first voltage level. When the signal of the phase comparison result is at the second voltage level, the counter includes a counter that updates the count value, and the digital value corresponding to the time difference is calculated based on the count value of the counter. You may ask for it.

  In this way, the digital value corresponding to the time difference can be obtained by controlling the counter counting process using the phase comparison result between the second signal and the second clock signal.

  In one embodiment of the present invention, the time-digital conversion circuit samples the other signal based on one signal of the second signal and the second clock signal, so that the second signal and the second signal are sampled. A phase comparison with the two clock signals may be performed.

  In this way, the phase relationship between the second signal and the second clock signal can be determined using the voltage level obtained by sampling the other signal based on one signal.

  In one embodiment of the present invention, the synchronization circuit includes a first PLL circuit that performs phase synchronization between the first clock signal and a reference clock signal, and the second clock signal and the reference clock signal. And a second PLL circuit that performs phase synchronization.

  By performing phase synchronization using the first and second PLL circuits in this way, the frequency of phase synchronization is increased compared to the case where the phase synchronization of the first and second clock signals is performed by one PLL circuit. This makes it possible to realize high-performance time digital conversion processing using the first and second clock signals.

  In one embodiment of the present invention, J ≦ Δt, where J is the jitter amount per clock cycle of the first clock signal and the second clock signal, and Δt is the resolution of time digital conversion. May be.

  In this way, it is possible to suppress a situation in which the accuracy of time digital conversion deteriorates due to the jitter amount exceeding the resolution.

  In one embodiment of the present invention, the timing at which one of the first clock signal and the second clock signal is phase-synchronized with the other clock signal or the reference clock signal is synchronized with the next timing. J ≧ Δt / K, where K is the number of clocks of the one clock signal in the period between

  In this way, it is possible to suppress a situation in which the accuracy of time digital conversion deteriorates due to the resolution.

In one embodiment of the present invention, one clock signal of the first clock signal and the second clock signal may be between a timing synchronized with the other clock signal or a reference clock signal and a timing synchronized with the next. (1/10) × (Δt / K ^1/2 ) ≦ J ≦ 10 × (Δt / K ^1/2 ) where K is the number of clocks of the one clock signal in the period Good.

  In this way, time digital conversion can be realized with a resolution that takes into account the effect of accumulated jitter, and high accuracy of time digital conversion can be achieved.

  According to another aspect of the present invention, there is provided the circuit device according to any one of the above, a first oscillator for generating the first clock signal, and a first oscillator for generating the second clock signal. And a physical quantity measuring device including two oscillators.

  By performing time digital conversion using the first and second oscillators in this way, it is possible to perform a physical quantity measurement process with higher accuracy.

  Another aspect of the invention relates to an electronic device including any one of the circuit devices described above.

  Moreover, the other aspect of this invention is related with the moving body containing the circuit apparatus in any one of said.

1 is a configuration example of a circuit device according to the present embodiment. Explanatory drawing of the time digital conversion technique using a clock frequency difference. The figure which shows the relationship between signal STA and STP. The figure which shows the example of the physical quantity measurement using signals STA and STP. 1 is a first configuration example of a time digital conversion circuit. The structural example of a phase detector. The signal waveform diagram explaining operation | movement of the time digital conversion circuit of a 1st structural example. Explanatory drawing of the time digital conversion method of this embodiment. Explanatory drawing of the time digital conversion method of this embodiment. 2 shows a second configuration example of a time digital conversion circuit. The signal waveform diagram explaining operation | movement of the time digital conversion circuit of a 2nd structural example. 1 shows a first configuration example of a synchronization circuit. The signal waveform diagram explaining operation | movement of a synchronizing circuit. 2 shows a second configuration example of a synchronization circuit. The signal waveform diagram explaining the update method of a clock cycle designation | designated value. The signal waveform diagram explaining the update method of a clock cycle designation | designated value. The signal waveform diagram explaining the update method of a clock cycle designation | designated value. The signal waveform diagram explaining a binary search method. The other structural example of the circuit apparatus of this embodiment. The signal waveform diagram explaining operation | movement of the other structural example of the circuit apparatus of this embodiment. The figure which shows an example of the setting of a frequency division ratio. Explanatory drawing of random walk and quantum walk. Explanatory drawing of accumulated jitter. Explanatory drawing about the relationship between resolution and jitter. Explanatory drawing about the relationship between resolution and jitter. The structural example of a physical quantity measuring apparatus. Configuration example of an electronic device. Configuration example of a moving body.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Circuit Device FIG. 1 shows a configuration example of a circuit device 10 according to this embodiment. The circuit device 10 includes a time digital conversion circuit 20 and a synchronization circuit 110. Further, the oscillation circuits 101 and 102 can be included. The circuit device is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of these components (for example, an oscillation circuit) and adding other components are possible.

  The time digital conversion circuit 20 converts the time difference between the signal STA (first signal, eg, start signal) and the signal STP (second signal, eg, stop signal) into a digital value DQ. Specifically, the time digital conversion circuit 20 includes a clock signal CK1 (first clock signal) having a clock frequency f1 (first clock frequency) and a clock signal CK2 (first clock frequency) having a clock frequency f2 (second clock frequency). 2 clock signal) is input. Then, using these clock signals CK1 and CK2, the time difference between the transition timings of the signal STA and the signal STP is converted into a digital value DQ and output. Here, the clock frequency f2 is a frequency different from the clock frequency f1, and is, for example, a frequency lower than the clock frequency f1. The time difference between the transition timings of the signal STA and the signal STP is a time difference between the edges of the signal STA and the signal STP (for example, between rising edges or falling edges). The time digital conversion circuit 20 may perform a filtering process (digital filtering process, low-pass filtering process) on the digital value DQ, and output the digital value DQ after the filtering process. The time digital conversion circuit 20 may perform time digital conversion using three or more clock signals having different clock frequencies. For example, the first, second, and third clock signals may be input, and the time difference between the transition timings of the signal STA and the signal STP may be converted into a digital value DQ.

  The synchronization circuit 110 performs phase synchronization between the clock signal CK1 and the clock signal CK2. For example, the synchronization circuit 110 synchronizes the phase of the clock signal CK1 and the clock signal CK2 at every phase synchronization timing (for every given timing). Specifically, phase synchronization is performed to make the transition timings of the clock signals CK1 and CK2 coincide with each other for each phase synchronization timing. A specific configuration example of the synchronization circuit 110 will be described later.

  The time digital conversion circuit 20 changes the signal level of the signal STA based on the clock signal CK1 after the phase synchronization timing of the clock signals CK1 and CK2. For example, phase synchronization of the clock signals CK1 and CK2 is performed by the synchronization circuit 110, and after the timing of the phase synchronization, the time digital conversion circuit 20 changes the signal level of the signal STA using the clock signal CK1. For example, the signal level of the signal STA is changed from a first voltage level (for example, L level) to a second voltage level (for example, H level). Specifically, the time digital conversion circuit 20 spontaneously generates a pulse signal STA.

  Then, the time digital conversion circuit 20 obtains a digital value DQ corresponding to the time difference by performing phase comparison between the signal STP whose signal level transitions in response to the signal STA and the clock signal CK2. For example, the digital value DQ is obtained by determining the timing at which the phase relationship between the signal STP and the clock signal CK2 is switched by phase comparison. The timing at which the phase relationship of the phases is switched is such that one of the signals STP and the clock signal CK2 is delayed in phase from the other signal, so that one of the signals is more advanced than the other signal. It is the timing when the state is switched to.

  As described above, in the present embodiment, the synchronization circuit 110 performs phase synchronization of the clock signals CK1 and CK2, and after this phase synchronization timing, the signal STA is spontaneously generated based on the clock signal CK1. Then, the phase comparison between the signal STP whose signal level transitions in response to the signal STA generated in this manner and the clock signal CK2 is performed, and it corresponds to the time difference between the transition timings of the signal STA and the signal STP. A digital value DQ to be obtained is obtained. In this way, high-performance (high accuracy, high resolution) time digital conversion can be realized while spontaneously generating the first signal used for time digital conversion.

  For example, in this embodiment, as described later with reference to FIG. 2, the time difference between the transition timings of the signal STA and the signal STP is converted into a digital value by using the frequency difference (| f1-f2 |) between the clock signals CK1 and CK2. doing. By doing in this way, the precision of time digital conversion can be improved compared with the conventional method which implement | achieves time digital conversion using the delay element which is a semiconductor element like the above-mentioned patent documents 1-3. In particular, if clock signals CK1 and CK2 generated by the oscillators XTAL1 and XTAL2 are used, a significant improvement in accuracy can be expected as compared with the conventional method.

  On the other hand, in the conventional methods of Patent Documents 1 to 3, the start signal and the stop signal are input from the outside. In this conventional method, time digital conversion is realized by a so-called vernier delay circuit. The vernier delay circuit includes, for example, a first delay circuit that receives an external start signal and delays the signal, a second delay circuit that receives an external stop signal and delays the signal, A logic circuit for obtaining a digital value based on the signal of the second delay circuit is included. For example, the time digital conversion is realized by making the delay amount of the delay element constituting the first delay circuit larger than the delay amount constituting the second delay circuit.

  However, when using the clock signals CK1 and CK2 generated by the oscillators XTAL1 and XTAL2, etc., the above conventional method that assumes that the signals STA and STP are input from outside realizes time digital conversion. Can not. For example, when the oscillation operation of the oscillator XTAL1 by the oscillation circuit 101 is started with the input of the signal STA from the outside as a trigger, it takes time until the oscillation is started, and thus the time measurement is not in time.

  Therefore, in the present embodiment, a method is employed in which the signal STA is not input from the outside but is generated spontaneously based on the clock signal CK1. For example, the clock signals CK1 and CK2 are generated by the free-run oscillation operation of the oscillation circuits 101 and 102. Then, the signal level of the signal STA is changed using the clock signal CK1 generated by the free-run oscillation operation, and the pulse signal STA is spontaneously generated. Then, as shown in FIGS. 3 and 4 to be described later, the time difference between the signals STA and STP is obtained by comparing the phase of the signal STP whose signal level transitions in response to the signal STA and the clock signal CK2 generated by the oscillation operation. Time digital conversion for obtaining a digital value DQ corresponding to is realized.

  In this case, if the timing used as a reference for time measurement is not specified, problems such as complicated circuit processing, long conversion time, and reduced accuracy as in the conventional method of Patent Document 4 described above. Will occur.

  Therefore, in this embodiment, the synchronization circuit 110 is further provided, and the clock signals CK1 and CK2 generated by the oscillation operation are phase-synchronized by the synchronization circuit 110. For example, the clock signals CK1 and CK2 are phase-synchronized at each phase synchronization timing. In this way, time digital conversion using the clock signals CK1 and CK2 can be realized using the phase synchronization timing as a reference timing, so that problems such as complicated circuit processing can be solved. Further, by synchronizing the phase of the clock signals CK1 and CK2 at the phase synchronization timing, the conversion time can be shortened and the accuracy can be improved, and the performance of time digital conversion can be improved.

  More specifically, the time digital conversion circuit 20 changes the signal level of the signal STA every clock cycle of the clock signal CK1 after the phase synchronization timing. For example, the signal level of the clock signal CK1 transitions (for example, rising transition or falling transition) every clock cycle, but the signal level of the signal STA is shifted so as to be synchronized with the transition of the signal level of the clock signal CK1.

  By doing so, the pulse signal of the signal STA used for the time digital conversion can be generated with a short period corresponding to the clock frequency f1 of the clock signal CK1, so that the time digital conversion can be speeded up. For example, the conventional method of Patent Document 4 described above has a problem that the conversion time of time digital conversion becomes very long because only one start signal is generated by one time measurement. On the other hand, according to the technique in which the signal level of the signal STA is transitioned every clock cycle of the clock signal CK1 after the phase synchronization timing, such a problem is solved and the time digital conversion is speeded up. Can be realized.

  More specifically, the time digital conversion circuit 20 performs phase comparison between the signal STP whose signal level transitions in response to the signal STA and the clock signal CK2 every clock cycle of the clock signal CK1, thereby obtaining a time difference. Find the corresponding digital value DQ. That is, the signal STA is generated based on the clock signal CK1 every clock cycle, and the phase comparison between the signal STP and the clock signal CK2 is performed every clock cycle.

  In this way, it becomes possible to obtain the result of phase comparison between the signal STP and the clock signal CK2 every clock cycle, and based on the obtained result of phase comparison, the digital value DQ corresponding to the time difference is obtained. It becomes possible to ask. Therefore, the time digital conversion can be greatly speeded up.

  Further, as will be described later in detail, the synchronization circuit 110 synchronizes the clock signals CK1 and CK2 at each phase synchronization timing. Then, the time digital conversion circuit 20 changes the signal level of the signal STA based on the clock signal CK1 for each clock cycle in the measurement period between the first phase synchronization timing and the second phase synchronization timing of the clock signals CK1 and CK2. The phase comparison between the signal STP and the clock signal CK2 is performed every clock cycle.

  In this way, in the measurement period between the first and second phase synchronization timings, the signal STP and the clock signal CK2 are compared several times using the signal STA based on the clock signal CK1, and the time is Measurement processing for digital conversion can be executed. Therefore, compared with the conventional method of Patent Document 4 in which only one time measurement can be performed in one measurement period, time digital conversion can be significantly speeded up.

  The phase comparison between the signal STP and the clock signal CK2 is a process for determining whether the phase of the signal STP is delayed or advanced with respect to the clock signal CK2, for example. This phase comparison can be realized, for example, by sampling the other signal based on one of the signal STP and the clock signal CK2.

  The oscillation circuits 101 and 102 are circuits that oscillate the oscillators XTAL1 and XTAL2. For example, the oscillator circuit 101 (first oscillator circuit) oscillates the oscillator XTAL1 (first oscillator) to generate the clock signal CK1 having the clock frequency f1. The oscillator circuit 102 (second oscillator circuit) oscillates the oscillator XTAL2 (second oscillator) to generate the clock signal CK2 having the clock frequency f2. For example, the clock frequency has a relationship of f1> f2.

  Each of the oscillation circuits 101 and 102 can include an oscillation buffer circuit (inverter circuit) provided between one end and the other end of the oscillator (XTAL1, XTAL2). The buffer circuit can be composed of one or a plurality of (odd number) inverter circuits. The buffer circuit may be a circuit capable of controlling oscillation enable / disable and controlling the flowing current. Each of the oscillation circuits 101 and 102 includes a feedback resistor provided between one end and the other end of the oscillator, a first capacitor or a first variable capacitance circuit connected to one end of the oscillator, A second capacitor or a second variable capacitance circuit connected to the other end can be included. By providing a variable capacitance circuit, the oscillation frequency can be finely adjusted. Note that a capacitor or a variable capacitance circuit may be provided only on one end and the other end of the oscillator.

  The oscillators XTAL1 and XTAL2 are, for example, piezoelectric vibrators. Specifically, the oscillators XTAL1 and XTAL2 are, for example, crystal resonators. For example, a thickness shear vibration type crystal resonator such as an AT cut type or an SC cut type. For example, the oscillators XTAL1 and XTAL2 may be a simple package type (SPXO) vibrator, an oven type type (OCXO) having a thermostat, or a temperature compensated type (TCXO) having no thermostat. It may be a child. Further, as the resonators XTAL1 and XTAL2, a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) resonator as a silicon resonator, or the like may be employed.

  As described above, in FIG. 1, the clock signal CK1 is a clock signal generated using the oscillator XTAL1, and the clock signal CK2 is a clock signal generated using the oscillator XTAL2. By using the clock signal generated by the oscillator in this way, it is possible to improve the accuracy of time digital conversion compared to a method not using the oscillator. However, the present embodiment is not limited to this, and the clock signals CK1 and CK2 may be clock signals generated by a clock signal generation circuit such as a ring oscillator circuit as long as at least the clock frequencies are different. . Further, a clock signal from an oscillator in which an oscillation circuit and an oscillator are housed in a package may be used.

  FIG. 2 is an explanatory diagram of a time digital conversion method using a clock frequency difference. At t0, the transition timings (phases) of the clock signals CK1 and CK2 match. Thereafter, at t1, t2, t3,..., The clock time difference TR (phase difference), which is the time difference between the transition timings of the clock signals CK1, CK2, becomes longer as Δt, 2Δt, and 3Δt. In FIG. 2, the time difference between clocks is represented by a pulse signal having a width of TR.

  Here, when the clock frequencies of the clock signals CK1 and CK2 are f1 and f2, the resolution of time digital conversion (time resolution) is Δt = | 1 / f1-1 / f2 | = | f1-f2 | / (f1 Xf2). In the time digital conversion method of this embodiment, for example, a plurality of oscillators are used, and the time is converted into a digital value using the clock frequency difference. Taking FIG. 2 as an example, time is converted to a digital value using the frequency difference Δf = | f1−f2 | between the clock signals CK1 and CK2. In other words, the time is converted into a digital value with a resolution Δt corresponding to the frequency difference Δf = | f1−f2 | between the clock signals CK1 and CK2. For example, time is converted into a digital value using the caliper principle. The resolution Δt only needs to be at least | f1−f2 | / (f1 × f2), and the substantial resolution may be smaller than | f1−f2 | / (f1 × f2).

  FIG. 3 is a diagram illustrating the relationship between the signal STA (first signal, start signal) and the signal STP (second signal, stop signal). The time digital conversion circuit 20 of the present embodiment converts the time difference TDF between the transition timings of the signal STA and the signal STP into a digital value. In FIG. 3, TDF is the time difference between the rising transition timings of the signal STA and the signal STP (between rising edges), but between the falling transition timings of the signal STA and the signal STP (between falling edges). The time difference may be.

  FIG. 4 is a diagram illustrating an example of physical quantity measurement using the signals STA and STP. For example, the physical quantity measuring device including the circuit device 10 of the present embodiment emits irradiation light (for example, laser light) to an object (for example, an object around the car) using the signal STA. A signal STP is generated by receiving reflected light from the object. For example, the physical quantity measuring device generates a signal STP by shaping the light reception signal. In this way, by converting the time difference TDF between the transition timings of the signal STA and the signal STP into a digital value, the distance to the object can be measured as a physical quantity by, for example, a time-of-flight (TOF) method. It can be used for automatic driving.

  Alternatively, the physical quantity measuring device transmits a transmission sound wave (for example, an ultrasonic wave) to an object (for example, a living body) using the signal STA. A signal STP is generated by receiving the received sound wave from the object. For example, the physical quantity measuring device generates the signal STP by shaping the waveform of the received sound wave. In this way, by converting the time difference TDF between the transition timings of the signal STA and the signal STP into a digital value, the distance to the object can be measured, and biological information can be measured using ultrasonic waves.

  3 and 4, the transmission data is transmitted by the signal STA, and the signal STP by the reception of the reception data may be used to measure the time from transmission data transmission to reception data reception. . In addition, the physical quantity measured by the physical quantity measuring apparatus of the present embodiment is not limited to time and distance, and various physical quantities such as a flow rate, a flow velocity, a frequency, a velocity, an acceleration, an angular velocity, or an angular acceleration can be considered.

2. Time Digital Conversion Circuit FIG. 5 shows a first configuration example of the time digital conversion circuit 20. The time digital conversion circuit 20 includes phase detectors 21 and 22, a counter 44, a processing unit 30, and a signal output unit 32. The time-digital conversion circuit 20 is not limited to the configuration shown in FIG. 5, and various modifications such as omitting some of these components or adding other components are possible.

  The phase detector 21 (phase comparator) receives the clock signals CK 1 and CK 2 and outputs a reset signal RST to the counter 44. For example, a reset signal RST of a pulse signal that becomes active at the phase synchronization timing is output.

  The phase detector 22 (phase comparator) receives the signal STP and the clock signal CK2, and outputs a signal PQ2 that is a phase comparison result. The phase detector 22 compares the phase of the signal STP and the clock signal CK2, for example, by sampling one of the signal STP and the clock signal CK2 with the other signal.

  The counter 44 resets the count value TCNT based on the reset signal RST from the phase detector 22. Based on the phase comparison result signal PQ2 from the phase detector 22, the count value TCNT is counted. For example, the count process is performed based on the clock signal CK2. Specifically, when the signal PQ2 of the phase comparison result between the signal STP and the clock signal CK2 is at the first voltage level (for example, L level), the counter 44 does not update the count value TCNT, and the phase comparison result When the signal PQ2 is at the second voltage level (for example, H level), the count value TCNT is updated. Then, the time digital conversion circuit 20 obtains a digital value DQ corresponding to the time difference based on the count value TCNT of the counter 44.

  In this way, the digital value DQ can be obtained by a simple circuit process in which the counter 44 performs the count process of the count value TCNT, and the circuit process is more complicated than the above-described conventional technique that complicates the circuit process. Can be simplified.

  The processing unit 30 performs arithmetic processing for obtaining a digital value DQ corresponding to the time difference between the signal STA and the signal STP. Specifically, the processing unit 30 performs a calculation process for obtaining the digital value DQ based on the count value TCNT. The processing unit 30 can be realized by, for example, an ASIC logic circuit or a processor such as a CPU.

  The signal output unit 32 outputs a signal STA based on the clock signal CK1. For example, the signal output unit 32 outputs the signal STA for each clock cycle of the clock signal CK1 based on the clock signal CK1. In FIG. 5, the signal output unit 32 includes a buffer circuit BF1, and outputs a signal obtained by buffering the clock signal CK1 as a signal STA. In this way, the signal STA whose signal level transitions every clock cycle of the clock signal CK1 can be spontaneously generated and output.

  FIG. 6 shows a configuration example of the phase detector 22. The phase detector 22 is configured by, for example, a flip-flop circuit DFB. The signal STP is input to the data terminal of the flip-flop circuit DFB, and the clock signal CK2 is input to the clock terminal. Thereby, the phase comparison by sampling the signal STP with the clock signal CK2 can be realized. Note that the clock signal CK2 may be input to the data terminal of the flip-flop circuit DFB, and the signal STP may be input to the clock terminal. Thereby, the phase comparison by sampling the clock signal CK2 with the signal STP can be realized.

  FIG. 7 is a signal waveform diagram for explaining the operation of the time digital conversion circuit 20 of the first configuration example of FIG. In FIG. 7, the phase synchronization of the clock signals CK1 and CK2 is performed at the phase synchronization timing TM. Specifically, phase synchronization is performed so that the transition timings (eg, rising transition timing, rising edge) of the clock signals CK1 and CK2 coincide with each other at the phase synchronization timing TM. This phase synchronization is performed by the synchronization circuit 110 of FIG. At the phase synchronization timing TM, the count value TCNT of the counter 44 is reset to 0, for example.

  When the phase synchronization timing TM is a known timing in the system of the circuit device 10, the phase synchronization timing TM is set by, for example, a timing control unit (not shown). In this case, the function of the phase detector 21 in FIG. 5 is realized by the timing control unit. That is, the timing control unit outputs a reset signal RST that becomes active at the phase synchronization timing TM to the counter 44.

  Then, the time digital conversion circuit 20 changes the signal level of the signal STA based on the clock signal CK1 after the phase synchronization timing TM of the clock signals CK1 and CK2. Specifically, after the phase synchronization timing TM, the signal level of the signal STA is changed every clock cycle of the clock signal CK1. For example, the signal level of the signal STA is changed from L level to H level. For example, the signal output unit 32 of FIG. 5 outputs a signal obtained by buffering the clock signal CK1 by the buffer circuit BF1 as the signal STA so that the signal level of the signal STA transitions every clock cycle of the clock signal CK1. Become.

  In FIG. 7, CCT is a clock cycle value. The clock cycle value CCT is updated every clock cycle of the clock signal CK1. Specifically, it is incremented every clock cycle. Here, for convenience of explanation, the clock cycle value of the first clock cycle is CCT = 0. Therefore, the clock cycle value of the next clock cycle is CCT = 1. In FIG. 7, CCT is the clock cycle value of the clock signal CK1, but the clock cycle value of the clock signal CK2 may be used.

  As described above, when the signal level of the signal STA transitions based on the clock signal CK1 after the phase synchronization timing TM, the signal level of the signal STP transitions corresponding to the signal STA as described with reference to FIGS. To do. Here, the time difference between the transition timings of the signals STA and STP is TDF.

  In this case, the time digital conversion circuit 20 performs a phase comparison between the signal STP and the clock signal CK2, as indicated by G1 to G6 in FIG. Based on the result of the phase comparison, a digital value DQ corresponding to the time difference TDF between the transition timings of the signals STA and STP is obtained. Specifically, the processing unit 30 in FIG. 5 performs a calculation process for obtaining the digital value DQ based on the signal PQ2 as a result of the phase comparison from the phase detector 22.

  For example, as described with reference to FIG. 2, after the phase synchronization timing TM, the clock time difference TR, which is the time difference between the transition timings of the clock signals CK1 and CK2, is, for example, Δt, 2Δt, 3Δt. It increases every clock cycle of CK1. In the present embodiment, after the phase synchronization timing TM, time digital conversion is realized by paying attention to the time difference TR between clocks that increases by Δt in this way.

  Specifically, the time digital conversion circuit 20 performs phase comparison between the signal STP and the clock signal CK2 every clock cycle as indicated by G1 to G6 in FIG. This phase comparison can be realized, for example, by sampling one of the signal STP and the clock signal CK2 with the other signal. For example, as described with reference to FIG. 6, the phase detector 22 samples the signal STP with the clock signal CK2, thereby realizing phase comparison. Note that the phase comparison may be realized by sampling the clock signal CK2 with the signal STP.

  In G1 to G3 in FIG. 7, the phase comparison result signal PQ2, which is a signal obtained by sampling the signal STP with the clock signal CK2, is at the L level. That is, in G1 to G3, since the signal STP is delayed in phase from the clock signal CK2, the signal PQ2 becomes L level. Note that when phase comparison is performed by sampling the clock signal CK2 with the signal STP, the signal PQ2 becomes H level in G1 to G3.

  As described above, in G1 to G3 in FIG. 7, it is determined that the phase of the signal STP is delayed from that of the clock signal CK2 based on the result of the phase comparison between the signal STP and the clock signal CK2. In other words, in G1, G2, and G3, TDF> TR = Δt, TDF> TR = 2Δt, and TDF> TR = 3Δt, respectively, and the time difference TDF between the transition timings of the signals STA and STP However, it is longer than the clock time difference TR between the clock signals CK1 and CK2.

  In G4 of FIG. 7, the phase relationship between the signal STP and the clock signal CK2 is switched. For example, the signal STP is switched from a state in which the phase is delayed with respect to the clock signal CK2 to a state in which the signal STP is advanced in phase with respect to the clock signal CK2.

  Thus, when the phase relationship of the phases is switched, as shown in G4 to G6, the phase comparison result signal PQ2, which is a signal obtained by sampling the signal STP with the clock signal CK2, becomes H level. That is, in G4 to G6, the signal STP has a higher phase than the clock signal CK2, and therefore the signal PQ2 becomes H level. When phase comparison is performed by sampling the clock signal CK2 with the signal STP, the signal PQ2 becomes L level in G4 to G6.

  As described above, in G4 to G6, it is determined that the phase of the signal STP is more advanced than that of the clock signal CK2 based on the result of the phase comparison between the signal STP and the clock signal CK2. In other words, in G4, G5, and G6, TDF <TR = 4Δt, TDF <TR = 5Δt, and TDF <TR = 6Δt, respectively, and the time difference TDF between the transition timings of the signals STA and STP However, it is shorter than the time difference TR between clocks of the clock signals CK1 and CK2.

  In G1 to G3 in FIG. 7, the signal PQ2 as a result of the phase comparison is at the L level, and it is determined that the phase of the signal STP is delayed with respect to the clock signal CK2. In this case, the count value TCNT of the counter 44 in FIG. 5 is not updated. For example, the count value TCNT does not increase from zero. On the other hand, in G4 to G6, the signal PQ2 of the phase comparison result is at the H level, and it is determined that the phase of the signal STP is ahead of that of the clock signal CK2. In this case, the count value TCNT of the counter 44 is updated. For example, the count value TCNT is incremented by 1 for each clock cycle, for example.

  The time digital conversion circuit 20 (processing unit 30) obtains a digital value DQ corresponding to the time difference TDF using the count value TCNT obtained in this way. For example, the code represented by the count value TCNT is converted to obtain and output an output code that is the final digital value DQ.

  In FIG. 7, the count value TCNT is not updated when the phase of the signal STP is delayed compared to the clock signal CK2, and the count value TCNT is updated when the phase is advanced. The reverse may be possible. For example, the count value TCNT is updated when the phase of the signal STP is delayed compared to the clock signal CK2 (G1 to G3), and the count value TCNT is not set when the phase is advanced (G4 to G6). It may be updated. That is, at least when the signal PQ2 of the phase comparison result is at the first voltage level, the count value TCNT is not updated, and when the signal PQ2 is at the second voltage level, the count value TCNT is updated. In this case, the first voltage level at which the count value TCNT is not updated is, for example, the H level (G4 to G6), and the second voltage level (G1 to G3) at which the count value TCNT is updated is For example, it becomes L level.

  FIG. 8 is an explanatory diagram of the time digital conversion method of this embodiment. At the phase synchronization timings TMA and TMB, the synchronization circuit 110 performs phase synchronization of the clock signals CK1 and CK2. Thereby, the transition timings of the clock signals CK1 and CK2 coincide with each other at the phase synchronization timings TMA and TMB. A period between the phase synchronization timings TMA and TMB is a measurement period TS. In the present embodiment, a digital value DQ corresponding to the time difference TDF is obtained in the measurement period TS.

  Specifically, as described in FIG. 7, after the phase synchronization timing TMA (TM), the signal level of the signal STA transitions based on the clock signal CK1, and the signal level of the signal STP transitions corresponding to the signal STA. To do. In this case, as indicated by G4 in FIG. 7 and FIG. 8, the time digital conversion circuit 20 specifies the timing at which the phase relationship between the signal STP and the clock signal CK2 is switched, and thereby the digital value DQ corresponding to the time difference TDF. Ask for. Specifically, the digital value DQ is obtained by specifying the clock cycle in which the phase relationship changes.

  For example, as indicated by G1 to G3 in FIG. 7, in the clock cycle where CCT = 1, 2, and 3, the phase of the signal STP is delayed from that of the clock signal CK2, and TDF> TR. On the other hand, as indicated by G4, the phase relationship between the signal STP and the clock signal CK2 is switched in the clock cycle where CCT = 4. That is, as shown in G4 to G6, in the clock cycle where CCT = 4, 5, and 6, the phase of the signal STP is more advanced than that of the clock signal CK2, and TDF <TR.

  As described above, in the present embodiment, the digital value DQ is obtained by performing the phase comparison between the signal STP and the clock signal CK2 and specifying (determining) the timing at which the phase relationship of these signals is switched. For example, by specifying the clock cycle in which CCT = 4 shown in G4, the digital value DQ corresponding to the time difference TDF is, for example, a digital value corresponding to TR = 4Δt (or a digital value corresponding to a value between 3Δt and 4Δt). ). Therefore, since the time difference TDF can be converted into the digital value DQ in one measurement period TS of FIG. 8, the time digital conversion can be speeded up.

  For example, in the conventional method described in Patent Document 4 described above, since only one start pulse is generated in one measurement period in which time measurement is performed, a very large number of measurement periods are repeated in order to obtain a final digital value. There is a need.

  On the other hand, according to the method of the present embodiment, as shown in FIGS. 7 and 8, the signal STA is generated a plurality of times in one measurement period TS, and the phase comparison is performed a plurality of times (for example, 1000 times or more). To obtain the digital value DQ. As a result, the final digital value DQ can be obtained within one measurement period TS, so that time digital conversion can be greatly speeded up as compared with the conventional method.

  In FIG. 8, the length of the measurement period TS corresponds to, for example, the number of clocks N (the number of clock cycles) of the clock signal CK1 in the measurement period TS. For example, the synchronization circuit 110 performs phase synchronization of the clock signals CK1 and CK2 every measurement period TS corresponding to the set number of clocks N. In this embodiment, in order to realize high-resolution time digital conversion, the number of clocks N in the measurement period TS is set to a very large number such as 1000 or more (or 5000 or more). For example, when the clock frequencies of the clock signals CK1 and CK2 are f1 and f2, the resolution of time digital conversion in this embodiment can be expressed as Δt = | f1−f2 | / (f1 × f2). Therefore, the smaller the frequency difference | f1−f2 | or the larger f1 × f2, the smaller the resolution Δt, thereby realizing a high-resolution time digital conversion. As the resolution Δt decreases, the number of clocks N in the measurement period TS also increases.

  The count value TCNT of the counter 44 described in FIGS. 5 and 7 corresponds to the length of the period TSB in FIG. Here, the first half period from the phase synchronization timing TMA to the G4 timing at which the phase relationship changes is TSF, and the second half period from the G4 timing to the phase synchronization timing TMB is TSB. For example, when the number of clocks (number of clock cycles) of the clock signal CK1 in the period TSF is NF, for example, N = NF + TCNT holds. For example, in FIG. 7, since NF = 4, a value corresponding to the final digital value DQ = 4 × Δt is a digital value corresponding to the clock number NF. Therefore, the time digital conversion circuit 20 (processing unit 30) obtains a digital value corresponding to NF = N−TCNT based on the count value TCNT. For example, when the digital value DQ is 8 bits, the digital value corresponding to the clock number N is, for example, 11111111. However, the counter 44 may perform a count process of the number of clocks NF to obtain the digital value DQ.

  Note that when the number of clocks N corresponding to the measurement period TS is increased, the time difference TDF that can be measured in FIG. 7 is shortened, so that the dynamic range is decreased. However, in this embodiment, the time digital conversion is completed in one measurement period TS while increasing the number of clocks N to increase the resolution. As a result, for example, high resolution can be realized while realizing high-speed conversion processing as in flash A / D conversion.

  In this case, in this embodiment, the signal STA is not always generated and the phase comparison is performed every clock cycle, but the signal STA may be generated and the phase comparison is performed only in a specific period. For example, after the search range of the digital value DQ is narrowed by a binary search method described later, a signal STA is generated for each clock cycle in a period corresponding to the search range, and the phase comparison is performed. May be requested. In this case, for example, in the measurement period TS in FIG. 8, only in the period corresponding to the narrowed search range, the time digital conversion for generating the signal STA every clock cycle and performing the phase comparison may be performed. For example, it is assumed that the digital value DQ is 10 bits and the measurement period TS is a period corresponding to Δt to 1024Δt. In this case, for example, when the search range is narrowed to Δt to 256Δt, digital conversion for generating a signal STA for each clock cycle and performing phase comparison only in the first half period corresponding to Δt to 256Δt is performed. Good.

  Further, after the timing (G4) at which the phase relationship is switched in FIGS. 7 and 8 is specified, the signal STA may not be generated to save power.

  As described above, according to the method of the present embodiment, there is no need to always generate the signal STA every clock cycle and perform the phase comparison, and the signal STA based on the clock signal CK1 is generated only in a specific period. Can be implemented.

  In the present embodiment, as described with reference to FIG. 2, the time digital conversion circuit 20 performs the time digital conversion with the resolution Δt corresponding to the frequency difference Δf = | f1−f2 | between the clock frequencies f1 and f2 of the clock signals CK1 and CK2. I do. For example, time digital conversion is performed with a resolution Δt = | f1−f2 | / (f1 × f2).

  In this way, by reducing the frequency difference Δf = | f1−f2 | between the clock frequencies f1 and f2, it becomes possible to reduce the resolution Δt = | f1−f2 | / (f1 × f2). High-resolution temporal digital conversion can be realized.

  More specifically, the time-to-digital conversion circuit 20 sets the time difference between the transition timings of the clock signals CK1 and CK2 in the i-th clock cycle after the phase synchronization timing as TR = i × Δt (i is an integer of 1 or more). In this case, time digital conversion is performed with a resolution Δt.

  For example, as shown in FIG. 9, after the phase synchronization timing TM of the clock signals CK1 and CK2, the clock time difference TR = i × Δt between the clock signals CK1 and CK2 increases as Δt, 2Δt, 3Δt,. Go. For example, TR = Δt in the first clock cycle (i = 1, CCT = 1) of the clock signal CK1, and TR = 2Δt in the second clock cycle (i = 2, CCT = 2). Similarly, in the third to sixth clock cycles (i = 3 to 6, CCT = 3 to 6), TR = 3Δt to 6Δt.

  In this embodiment, when the time difference between the transition timings of the clock signals CK1 and CK2 in the i-th clock cycle after the phase synchronization timing TM is set to TR = i × Δt as described above, the resolution is as shown in G7. Time digital conversion is performed at Δt. That is, by using the fact that the time difference between clocks TR = i × Δt sequentially increases by Δt after the phase synchronization timing TM, the magnitude relationship between the time difference between clocks TR and the time difference TDF is determined, thereby resolving the resolution. Time digital conversion at Δt is realized.

  In this way, the time difference TDF can be converted into the digital value DQ with a resolution Δt corresponding to the frequency difference between the clock frequencies f1 and f2 of the clock signals CK1 and CK2, and high-resolution time-digital conversion can be realized. become.

  Specifically, the time digital conversion circuit 20 corresponds to TR = j × Δt when the phase relationship between the signal STP and the clock signal CK2 is switched in the j-th clock cycle after the phase synchronization timing TM. The digital value is obtained as a digital value DQ corresponding to the time difference TDF.

  For example, in FIG. 9, the phase relationship between the signal STP and the clock signal CK2 is switched in the fourth clock cycle (j = 4, CCT = 4) after the phase synchronization timing TM. That is, in the third clock cycle (CCT = 3), the signal STP is delayed in phase from the clock signal CK2, but in the fourth clock cycle (CCT = 4), the signal STP is the clock signal. The phase is ahead of CK2. In this case, as indicated by G4, a digital value corresponding to 4Δt (j × Δt in a broad sense) is obtained as a digital value DQ corresponding to the time difference TDF, and is output as a final output code.

  In this way, the digital value DQ corresponding to the time difference TDF can be obtained by a simple process of determining the timing at which the phase relationship between the signal STP and the clock signal CK2 is switched. Therefore, time digital conversion can be realized with simple circuit processing compared to the conventional method, and the circuit configuration can be simplified and downsized.

  In this embodiment, as shown in FIG. 1, the clock signals CK1 and CK2 are clock signals generated using the oscillators XTAL1 and XTAL2, respectively. As described above, according to the technique using the clock signals CK1 and CK2 generated by the oscillators XTAL1 and XTAL2, the time (in comparison with the conventional technique that realizes the time digital conversion using a semiconductor element such as a vernier delay circuit). The accuracy of measurement of (physical quantity) can be greatly improved.

  For example, the conventional method using a semiconductor element has a problem that it is relatively easy to improve resolution, but difficult to improve accuracy. That is, the delay time of the delay element, which is a semiconductor element, varies greatly due to manufacturing variations and environmental changes. For this reason, there is a limit to increasing the accuracy of measurement due to this variation. For example, relative accuracy can be guaranteed to some extent, but it is difficult to guarantee absolute accuracy.

  On the other hand, the oscillation frequency of the oscillator is extremely small in variation due to manufacturing variations and environmental changes compared to the delay time of the delay element that is a semiconductor element. Therefore, according to the technique for performing time digital conversion using the clock signals CK1 and CK2 generated by the oscillators XTAL1 and XTAL2, the accuracy can be greatly improved as compared with the conventional technique using a semiconductor element. Further, the resolution can be increased by reducing the frequency difference between the clock signals CK1 and CK2.

  For example, if the frequency difference between the clock signals CK1 and CK2 is Δf = | f1−f2 | = 1 MHz and f1 and f2 are about 100 MHz, the time measurement resolution Δt = | f1−f2 | / (f1 × f2) It can be about 100 ps (picosecond). Similarly, if f1 and f2 are about 100 MHz and Δf = 100 kHz, 10 kHz, and 1 kHz, the resolution can be about Δt = 10 ps, 1 ps, and 0.1 ps, respectively. And the fluctuation | variation of the oscillation frequency of oscillator XTAL1 and XTAL2 is very small compared with the method using a semiconductor element. Therefore, it is possible to achieve both improvement in resolution and improvement in accuracy.

  Further, in the conventional method of Patent Document 4 described above, time digital conversion is realized using a crystal oscillator. However, in this conventional method, the time measurement start timing is sequentially delayed from the timing of the synchronization point at which the edges of the first and second clock pulses coincide. Each time measurement is performed from the timing of the synchronization point where the edges of the first and second clock pulses coincide with each other, and it is necessary to repeat this time measurement many times. For this reason, there is a problem that the conversion time of the time digital conversion becomes very long.

  On the other hand, in the present embodiment, the time digital conversion is realized by generating the signal STA a plurality of times and performing the phase comparison a plurality of times in the measurement period TS. Therefore, time digital conversion can be greatly speeded up as compared with the conventional method.

  FIG. 10 shows a second configuration example of the time digital conversion circuit 20, and FIG. 11 shows a signal waveform diagram for explaining the operation of the second configuration example. The difference between the first configuration example in FIG. 5 and the second configuration example in FIG. 10 is the circuit configuration of the signal output unit 32.

  In FIG. 10, the signal output unit 32 includes a flip-flop circuit DFC, an AND circuit AN, and a buffer circuit BF2. The AND circuit AN and the buffer circuit BF2 constitute a pulse signal generation circuit. The pulse signal generation circuit receives the clock signal CK2 and outputs a reset signal of the pulse signal that becomes active (H level) at the rising transition timing (rising edge) of the clock signal CK2 to the reset terminal of the flip-flop circuit DFC. . The power supply voltage VDD on the high potential side is input to the data terminal of the flip-flop circuit DFC, and the clock signal CK1 is input to the clock terminal.

  By using the signal output unit 32 having such a circuit configuration, as shown in FIG. 11, it becomes active (H level) at the rising transition timing of the clock signal CK1, and inactive (L) at the rising transition timing of the clock signal CK2. Level) can be generated. Thereby, based on the clock signal CK1, the signal output unit 32 that outputs the signal STA at every clock cycle of the clock signal CK1 can be realized. Then, after the phase synchronization timing, the signal level of the signal STA can be changed every clock cycle of the clock signal CK1.

  Then, as indicated by H1 to H6 in FIG. 11, the phase comparison between the signal STP whose signal level transitions in response to the signal STA generated in this way and the clock signal CK2 is performed. As described above, the digital value DQ corresponding to the time difference TDF can be obtained by specifying the timing (clock cycle) of H4 at which the phase relationship between the signal STP and the clock signal CK2 changes.

3. Synchronization Circuit Next, a specific configuration example of the synchronization circuit 110 will be described. The synchronization circuit 110 is not limited to the following configuration, and various modifications such as omitting some of the components or adding other components are possible.

  FIG. 12 shows a first configuration example of the synchronization circuit 110, and FIG. 13 shows a signal waveform diagram for explaining the operation of the synchronization circuit 110.

  The oscillation circuits 101 and 102 oscillate the oscillators XTAL1 and XTAL2, respectively, and generate clock signals CK1 and CK2 having clock frequencies f1 and f2. For example, the oscillation signals OS1 and OS2 from the oscillation circuits 101 and 102 are buffered by the buffer circuits BA3 and BA4 and output as the clock signals CK1 and CK2.

  The synchronization circuit 110 performs phase synchronization of the clock signals CK1 and CK2. For example, the clock signals CK1 and CK2 are phase-synchronized at every phase synchronization timing (every given timing). For example, phase synchronization is performed so that the transition timings of the clock signals CK1 and CK2 coincide with each other at each phase synchronization timing.

  Specifically, the synchronization circuit 110 in FIG. 12 performs phase synchronization of the oscillation signal OS1 (first oscillation signal) in the oscillation circuit 101 and the oscillation signal OS2 (second oscillation signal) in the oscillation circuit 102. For example, the synchronization circuit 110 synchronizes the oscillation signals OS1 and OS2 with each phase synchronization timing. For example, in FIG. 13, the oscillation signals OS1 and OS2 are phase-synchronized at the phase synchronization timing TMA, and the oscillation signals OS1 and OS2 are phase-synchronized at the next phase synchronization timing TMB. The same applies to the next phase synchronization timing. With this phase synchronization, the phases of the oscillation signals OS1 and OS2 are aligned at the phase synchronization timing.

  More specifically, the synchronization circuit 110 performs phase synchronization so that the transition timing of the clock signal CK1 and the transition timing of the clock signal CK2 coincide with each other at each phase synchronization timing. For example, the phase synchronization is performed by the synchronization circuit 110 at the phase synchronization timing TMA in FIG. 13, so that the transition timings (edges) of the clock signals CK1 and CK2 coincide. Further, the phase synchronization by the synchronization circuit 110 is performed at the phase synchronization timing TMB, so that the transition timings of the clock signals CK1 and CK2 coincide.

  Further, as shown in FIG. 12, the synchronization circuit 110 oscillates the oscillation loop LP1 (first oscillation loop) of the oscillation circuit 101 and the oscillation loop LP2 (second oscillation loop) of the oscillation circuit 102 for each phase synchronization timing. Connect electrically. For example, the synchronization circuit 110 includes an output node NA1 of the oscillation buffer circuit BA1 (first buffer circuit) included in the oscillation circuit 101 and an oscillation buffer circuit BA2 (second buffer circuit) included in the oscillation circuit 102. Connect the output node NA2.

  Specifically, the synchronization circuit 110 includes a counter 112 that performs a counting operation based on one of the clock signals CK1 and CK2. In FIG. 12, the counter 112 performs a counting operation based on the clock signal CK1, for example. The synchronization circuit 110 performs phase synchronization every time the count value of the counter 112 reaches a given set value. This set value is, for example, a value corresponding to the number of clocks of the clock signal CK1 (or clock signal CK2) between the phase synchronization timing TMA and the phase synchronization timing TMB in FIG.

  More specifically, the synchronization circuit 110 includes a switch circuit SWA that electrically connects the oscillation loop LP1 of the oscillation circuit 101 and the oscillation loop LP2 of the oscillation circuit 102. The switch circuit SWA is turned on based on the signal CTA from the counter 112, and electrically connects the oscillation loop LP1 and the oscillation loop LP2. For example, as shown in FIG. 13, the signal CTA is a pulse signal that becomes active (eg, H level) at each phase synchronization timing. When the signal CTA becomes active, the switch circuit SWA is turned on. Specifically, the counter 112 activates the signal CTA when the count value reaches the set value, thereby turning on the switch circuit SWA. Thereafter, the count value of the counter 112 is reset.

  In FIG. 12, if the phases of the oscillation signal OS1 and the oscillation signal OS2 are shifted by exactly 180 degrees when the switch circuit SWA is turned on, there is a possibility that the oscillation stops.

  Therefore, in the synchronization circuit 110, one of the oscillation circuits 101 and 102 is activated, and the other oscillation circuit is activated at the phase synchronization timing (for example, the first phase synchronization timing) after activation of one of the oscillation circuits. Is desirable. For example, in FIG. 12, the oscillation circuit 101 is activated, and the oscillation circuit 102 is activated at the phase synchronization timing after the oscillation circuit 101 is activated. The start-up of the oscillation circuit 101 can be realized by, for example, a seed circuit (not shown) provided in the oscillation circuit 101. When the switch circuit SWA is turned on at the phase synchronization timing after the oscillation circuit 101 is activated, the oscillation signal OS1 from the oscillation circuit 101 is transmitted to the oscillation loop LP2 of the oscillation circuit 102. Then, the transmitted oscillation signal OS1 becomes a seed signal, and oscillation of the oscillation circuit 102 is started. In this way, it is possible to prevent the occurrence of the problem that the oscillation is stopped as described above.

  As a modification of FIG. 12, a configuration may be adopted in which the oscillation signal of one of the oscillation circuits 101 and 102 is transmitted to the oscillation loop of the other oscillation circuit at each phase synchronization timing. That is, instead of connecting the oscillation loop LP1 and the oscillation loop LP2 by the switch circuit SWA (bidirectional connection), the oscillation signal of one oscillation circuit is transmitted to the other oscillation circuit, thereby realizing phase synchronization. May be.

  FIG. 14 shows a second configuration example of the synchronization circuit 110. In FIG. 14, a PLL circuit 120 is used as the synchronization circuit 110. That is, the circuit device 10 of FIG. 14 includes a time digital conversion circuit 20 and a PLL circuit 120. The time digital conversion circuit 20 receives the clock signal CK1 having the clock frequency f1 generated using the oscillator XTAL1 and the clock signal CK2 having the clock frequency f2 generated using the oscillator XTAL2, and receives the clock signal CK1, Time is converted to a digital value using CK2. The PLL circuit 120 performs phase synchronization between the clock signal CK1 and the clock signal CK2.

  Specifically, the PLL circuit 120 performs phase synchronization of the clock signals CK1 and CK2 so that the frequency difference between the clock frequency f1 and the clock frequency f2 becomes a frequency difference corresponding to the resolution of time digital conversion. For example, the resolution of the time digital conversion in this embodiment can be expressed as Δt = | 1 / f1-1 / f2 | = | f1-f2 | / (f1 × f2). The PLL circuit 120 generates a clock signal so that the frequency difference | f1−f2 | between the clock frequencies f1 and f2 becomes a frequency difference corresponding to the time digital conversion resolution Δt = | f1−f2 | / (f1 × f2). Phase synchronization of CK1 and CK2 is performed.

  Specifically, as shown in FIG. 14, the PLL circuit 120 includes frequency dividing circuits 122 and 124 (first and second frequency dividing circuits) and a phase detector 126 (phase comparator). The divider circuit 122 divides the clock signal CK1 and outputs a divided clock signal DCK1 (first divided clock signal). Specifically, the clock signal CK1 is divided so that the clock frequency f1 is 1 / N, and the divided clock signal DCK1 having the clock frequency f1 / N is output.

  The frequency dividing circuit 124 divides the clock signal CK2 and outputs a divided clock signal DCK2 (second divided clock signal). Specifically, the clock signal CK2 is divided so that the clock frequency f2 is 1 / M, and the divided clock signal DCK2 having the clock frequency f2 / M is output. For example, the circuit device 10 includes an oscillation circuit 102, which oscillates the oscillator XTAL 2, generates a clock signal CK 2, and outputs the clock signal CK 2 to the frequency divider circuit 124. Then, the phase detector 126 performs phase comparison between the divided clock signal DCK1 and the divided clock signal DCK2.

  The circuit device 10 includes an oscillation circuit 101, which is controlled based on the phase comparison result of the phase detector 126 of the PLL circuit 120 to oscillate the oscillator XTAL1. The oscillation circuit 101 is also a component of the PLL circuit 120, for example. Specifically, the oscillation circuit 101 is, for example, a voltage control type oscillation circuit (VCXO) whose oscillation frequency is controlled by voltage control. The PLL circuit 120 includes a charge pump circuit 128, and the phase detector 126 outputs a signal PQ that is a phase comparison result to the charge pump circuit 128. The signal PQ is, for example, an up / down signal, and the charge pump circuit 128 outputs a control voltage VC based on the signal PQ to the oscillation circuit 101. For example, the charge pump circuit 128 includes a loop filter, which converts an up / down signal, which is a signal PQ, into a control voltage VC. The oscillation circuit 101 performs the oscillation operation of the resonator XTAL1 whose oscillation frequency is controlled based on the control voltage VC, and generates the clock signal CK1. For example, the oscillation circuit 101 has a variable capacitance circuit, and the oscillation frequency is controlled by controlling the capacitance value of the variable capacitance circuit based on the control voltage VC.

  According to the second configuration example of FIG. 14, the phase synchronization of the clock signals CK <b> 1 and CK <b> 2 can be realized by effectively using the PLL circuit 120. That is, similarly to FIG. 13, phase synchronization can be realized in which the transition timings of the clock signals CK <b> 1 and CK <b> 2 coincide with each other at each phase synchronization timing.

  If the synchronization circuit 110 is provided in the circuit device 10 as described above, the transition timings of the clock signals CK1 and CK2 can be matched at each phase synchronization timing. Therefore, circuit processing can be started using the phase synchronization timing as a reference timing, so that circuit processing and circuit configuration can be simplified. In addition, time digital conversion processing can be started immediately from the phase synchronization timing by the synchronization circuit 110 without waiting for the transition timings of the clock signals CK1 and CK2 to coincide. Therefore, the time digital conversion can be speeded up. Further, by providing the synchronization circuit 110, an error caused by the time difference between the transition timings of the clock signals CK1 and CK2 at the phase synchronization timing can be minimized. Therefore, the error generated systematically due to this time difference can be sufficiently reduced to improve accuracy.

  For example, in the conventional method described in Patent Document 4 described above, the edge coincidence detection circuit detects the coincidence of the edges of the first and second clock pulses, and starts time measurement on the condition that the coincidence of the edges is detected. . However, in this conventional method, since time measurement cannot be started unless the coincidence of the edges of the first and second clock pulses is detected, the start of time measurement is delayed and the conversion time of time digital conversion becomes longer. There is a first problem. Further, when the relationship between the clock frequencies of the first and second clock pulses is such that the edges do not coincide at the synchronization point, the edges coincide only by chance, thereby realizing time digital conversion. There is a second problem that it becomes difficult. In addition, since the timing of the synchronization point of the first and second clock pulses cannot be determined systematically, there is a third problem that circuit processing and circuit configuration become complicated. Further, when there is an error in the coincidence detection of the edges of the first and second clock pulses, there is a fourth problem that the accuracy is lowered due to the error.

  On the other hand, in this embodiment, by providing the synchronization circuit 110, the transition timings of the clock signals CK1 and CK2 can be forcibly matched at each phase synchronization timing. Accordingly, since the time digital conversion process can be started immediately after the phase synchronization timing, the first problem of the conventional method can be solved. In addition, according to the present embodiment, even when the relationship between the clock frequencies of the clock signals CK1 and CK2 is such that the transition timings do not coincide with each other, the synchronization circuit 110 forcibly for each phase synchronization timing. The transition timings of the clock signals CK1 and CK2 coincide. Therefore, the second problem of the conventional method can be solved. Further, since the phase synchronization timing can be determined systematically by the phase synchronization of the synchronization circuit 110, the circuit processing and the circuit device can be simplified, and the third problem of the conventional method can be solved. Further, since the transition timings of the clock signals CK1 and CK2 coincide with each other at the phase synchronization timing, the conversion error caused by the shift of the transition timings of the clock signals CK1 and CK2 can be reduced, and the fourth problem of the conventional method can be solved. .

4). Update Method of Clock Cycle Designated Value The method of changing the signal level of the signal STA based on the clock signal CK1 and comparing the phase of the signal STP and the clock signal CK2 is not limited to the method described with reference to FIGS. Can be implemented. First, as a modified example, a method for realizing time digital conversion by updating a clock cycle designation value (clock cycle designation information in a broad sense) will be described.

  15 to 17 are signal waveform diagrams for explaining a clock cycle designation value updating method (hereinafter simply referred to as an updating method as appropriate). CIN is clock cycle designation information. In the following description, it is assumed that CIN is a clock cycle designation value represented by clock cycle designation information.

  TMA and TMB are phase synchronization timings. 15 to 17, the phase synchronization timings TMA and TMB are timings at which the transition timings (rising edges) of the clock signals CK1 and CK2 coincide. However, the update method of the present embodiment is not limited to this, and the phase synchronization timings TMA and TMB may be timings at which the phase relationship of the clock signals CK1 and CK2 is switched. The timing at which the phase relationship is switched is from the state where one clock signal is more advanced in phase than the other clock signal, to the state where one clock signal is more out of phase than the other clock signal. It is the timing to change.

  The update period TP is a period between the phase synchronization timings TMA and TMB. In the update method of the present embodiment, for example, one update of the clock cycle specified value is performed in the update period TP. 15 to 17 show a case where the number of clocks of the clock signal CK1 in the update period TP is 14 for the sake of simplicity of explanation. However, in practice, in order to set a high resolution, the number of clocks in the update period TP is set to a very large number such as 1000 or more (or 5000 or more).

  In the update period TP (first update period) in FIG. 15, the clock cycle designation value is CIN = 3. Therefore, the signal level of the signal STA is changed in the clock cycle (CCT = 3) designated by CIN = 3. As described above, in the update method of this embodiment, the signal level of the signal STA is changed in the clock cycle of the clock signal CK1 specified based on the clock cycle specification value CIN (clock cycle specification information). As described with reference to FIGS. 3 and 4, the signal level of the signal STP transitions in response to the signal STA, and the time difference between the transition timings of the signals STA and STP is TDF.

  On the other hand, in the clock cycle (CCT = 3) specified by CIN = 3, the time difference between clocks, which is the time difference between the transition timings of the clock signals CK1 and CK2, is TR = CIN × Δt = 3Δt as described in FIG. It has become.

  In this case, in the update method according to the present embodiment, the phase comparison between the signal STP and the clock signal CK2 is performed as indicated by A1 in FIG. This phase comparison can be realized, for example, by sampling one of the signal STP and the clock signal CK2 with the other signal.

  In A1 of FIG. 15, the phase comparison result that is the result of sampling the signal STP with the clock signal CK2 is at the L level. Based on the result of the phase comparison, it is determined that the signal STP is delayed in phase from the clock signal CK2. In other words, TDF> TR = 3Δt in A1 of FIG. 15, and the time difference TDF between the transition timings of the signals STA and STP is greater than the time difference between clocks TR = 3Δt of the clock signals CK1 and CK2. It is getting longer. In this case, an update for increasing the clock cycle designation value CIN is performed.

  In the update period TP (second update period) in FIG. 16, the clock cycle designation value is CIN = 9. For example, in the previous update period TP shown in FIG. 15, the clock cycle designation value is updated to CIN = 9 by updating the clock cycle designated value from CIN = 3 as described above. Therefore, the signal level of the signal STA is changed in the clock cycle (CCT = 9) designated by CIN = 9. The signal level of the signal STP transitions corresponding to the signal STA, and the time difference between the transition timings of the signals STA and STP is TDF.

  On the other hand, in the clock cycle (CCT = 9) designated by CIN = 9, the time difference between clocks of the clock signals CK1 and CK2 is TR = CIN × Δt = 9Δt.

  In the update method of the present embodiment, the phase comparison between the signal STP and the clock signal CK2 is performed as shown by A2 in FIG. In this case, since the phase comparison result obtained by sampling the signal STP with the clock signal CK2 is at the H level, it is determined that the phase of the signal STP is more advanced than that of the clock signal CK2. In other words, in A2 of FIG. 16, TDF <TR = 9Δt, and the time difference TDF is shorter than the clock time difference TR = 9Δt. In this case, an update for decreasing the clock cycle designation value CIN is performed.

  In the update period TP (third update period) in FIG. 17, the clock cycle designation value is CIN = 6. For example, in the previous update period TP shown in FIG. 16, the clock cycle designation value is updated to CIN = 6 by updating the clock cycle designated value from CIN = 9 as described above. Therefore, the signal level of the signal STA is changed in the clock cycle (CCT = 6) specified by CIN = 6. The signal level of the signal STP transitions corresponding to the signal STA, and the time difference between the transition timings of the signals STA and STP is TDF.

  On the other hand, in the clock cycle (CCT = 6) designated by CIN = 6, the clock time difference between the clock signals CK1 and CK2 is TR = CIN × Δt = 6Δt.

  In the update method according to the present embodiment, the phase comparison between the signal STP and the clock signal CK2 is performed as indicated by A3 in FIG. In this case, in A3 of FIG. 17, the transition timing (phase) of the signal STP and the clock signal CK2 coincides (substantially coincides). In other words, TDF = TR = 6Δt in A3 of FIG. Therefore, in this case, a digital value corresponding to DQ = TR = 6Δt is output as a final result as a digital value obtained by converting the time difference TDF between the signals STA and STP.

  In order to simplify the description in FIGS. 15 to 17, the increase / decrease value of the clock cycle designation value CIN in each update period is set to a value larger than 1, but in reality, a Δ sigma type A Like the / D conversion, the increase / decrease value of the clock cycle designation value CIN can be 1 or GK which is a small value of 1 or less. GK is a gain coefficient and is a value satisfying GK ≦ 1.

  For example, in FIG. 15 and FIG. 16, the clock cycle designation value CIN is increased from 3 to 9, but in practice, for example, for each update period, an update that increases the clock cycle designation value CIN by a given value GK is performed. Do. For example, when the gain coefficient satisfying GK ≦ 1 is GK, the clock cycle designation value CIN is updated to + GK. For example, when GK = 0.1, the clock cycle designation value CIN is incremented by 1, for example, when + GK is updated ten times.

  In FIGS. 16 and 17, the clock cycle designation value CIN is decreased from 9 to 6, but in practice, for example, for each update period, the clock cycle designation value CIN is decreased by a given value GK. Do. For example, the clock cycle designation value CIN is updated to -GK. For example, when GK = 0.1, the clock cycle designation value CIN is decremented by 1, for example, when -GK is updated 10 times.

  In A3 of FIG. 17, the clock cycle designation value CIN is updated after the transition timings of the signal STP and the clock signal CK2 substantially coincide with each other, for example, CIN is 6, 7, 6, 7,. Suppose that it has changed. In this case, the digital value DQ output as the final result can be a value between 6Δt and 7Δt (for example, 6.5 × Δt). As described above, according to the updating method of the present embodiment, the substantial resolution can be reduced as in the case of Δ sigma type A / D conversion.

  As described above, in the update method of the present embodiment, the signal STP whose signal level transitions in response to the signal STA is compared with the clock signal CK2, and the signal level of the signal STA is determined based on the result of the phase comparison. The clock cycle designation value CIN for transitioning is updated.

  Specifically, the signal level of the signal STA is changed in a clock cycle specified by the clock cycle specified value CIN. For example, in FIG. 15, the signal level of the signal STA is changed in a clock cycle designated by CIN = 3. In FIG. 16, the signal level of the signal STA is changed in the clock cycle specified by CIN = 9. The same applies to FIG.

  When the signal level of the signal STP transitions corresponding to the signal STA, the phase comparison between the signal STP and the clock signal CK2 is performed, and the clock cycle designation value CIN is updated based on the phase comparison result. For example, in FIG. 15, the phase comparison result indicates that the phase of the signal STA is delayed from that of the clock signal CK <b> 2, so CIN = 3 in FIG. 15 is updated to CIN = 9 in FIG. 16. In FIG. 16, since the phase comparison result indicates that the signal STA is ahead of the phase of the clock signal CK2, CIN = 9 in FIG. 16 is updated to CIN = 6 in FIG. The final value of the clock cycle designation value CIN updated in this way is output as the digital value DQ of the time difference TDF between the signals STA and STP.

  In the update method of this embodiment, the clock cycle designation value CIN is updated in each update period. The updated clock cycle designation value CIN is fed back. Therefore, even when the time or physical quantity to be measured changes dynamically, time digital conversion following the dynamic change can be realized. For example, as shown at A3 in FIG. 17, even when the time dynamically changes after approaching the clock cycle specified value CIN corresponding to the time to be measured (time difference TDF), the clock cycle specified value is accordingly changed. Such dynamic changes can be accommodated by sequentially updating CIN.

  Further, in the update method of the present embodiment, when the error component due to the mismatch of the transition timings of the clock signals CK1 and CK2 is reduced, the time digital conversion circuit 20 uses the clock cycle specified value and the update period of the clock cycle specified value. It is desirable to perform processing for converting the time difference into the digital value DQ based on the clock number information of the clock signal CK1 or the clock signal CK2. For example, the digital value DQ is obtained by updating the clock cycle designation value CIN based on the phase comparison result between the signal STP and the clock signal CK2 and the clock number information.

  That is, in the update method of the present embodiment, time digital conversion can be realized even when the transition timings of the clock signals CK1 and CK2 do not exactly match at the phase synchronization timing. For example, in the update method of the present embodiment, the phase synchronization timings TMA and TMB may be any timing at which the phase relationships of the clock signals CK1 and CK2 are switched, and the transition timings of the clock signals CK1 and CK2 do not completely match. Also good. That is, in the present embodiment, a modification in which the synchronization circuit 110 is not provided is possible.

  For example, in order to make the transition timings of the clock signals CK1 and CK2 exactly coincide with each other at the phase synchronization timing, it is necessary to satisfy the relationship of N / f1 = M / f2. Here, N and M are the clock numbers of the clock signals CK1 and CK2 in the update period, respectively, and are integers of 2 or more. However, it may actually be difficult to set the clock frequencies f1 and f2 by the oscillators XTAL1 and XTAL2 in FIG. 1 to a frequency that strictly satisfies the relationship of N / f1 = M / f2. If the synchronization circuit 110 is not provided when the relationship of N / f1 = M / f2 is not satisfied, the phase synchronization timings TMA and TMB cause a shift in the transition timings of the clock signals CK1 and CK2, and this shift is converted. There is a risk of errors.

  Therefore, in the update method of this embodiment, the number N of clocks in each update period is measured. Since the transition timings of the clock signals CK1 and CK2 are shifted in the phase synchronization timings TMA and TMB, the number of clocks N does not always have the same value and varies according to the update period. The time digital conversion circuit 20 updates the clock cycle designation value CIN based on the number of clocks N that fluctuate in this way, and the phase comparison result between the signal STP and the clock signal CK2. By doing so, it is possible to reduce a conversion error caused by a shift in transition timing of the clock signals CK1 and CK2 at the phase synchronization timings TMA and TMB.

5. Binary Search Method Next, a binary search method will be described as a second modified example of the method of making a phase comparison between the signal STP and the clock signal CK2 by changing the signal level of the signal STA based on the clock signal CK1.

  FIG. 18 is a signal waveform diagram illustrating the binary search method. In FIG. 18, a digital value corresponding to the time difference between the transition timings of the signal STA and the signal STP is obtained by a binary search with a resolution corresponding to the frequency difference between the clock frequencies f1 and f2. Specifically, the update of the clock cycle designation value CIN based on the phase comparison result between the signal STP and the clock signal CK2 is realized by a binary search.

  The binary search (binary search, bisection method) is a method of finding a final digital value while narrowing the search range by dividing the search range one after another (dividing into two). For example, a digital value DQ obtained by converting the time difference is 4-bit data, and each 4-bit bit is b4, b3, b2, b1. b4 is the MSB and b1 is the LSB. In FIG. 18, each bit b4, b3, b2, b1 of the digital value DQ is obtained by binary search. For example, each bit b4, b3, b2, b1 of the digital value DQ is sequentially obtained by the same method as the A / D conversion of successive approximation.

  For example, in FIG. 18, the clock frequencies of the clock signals CK1 and CK2 are, for example, f1 = 100 MHz (period = 10 ns), f2 = 94.12 MHz (period = 10.625 ns), and the resolution is Δt = 0.625 ns. It has become. E1 and E2 in FIG. 18 are phase synchronization timings, which are timings at which the transition timings of the clock signals CK1 and CK2 coincide, for example. The clock cycle designation value CIN is set to CIN = 8, which is an initial value, for example. This initial value CIN = 8 corresponds to, for example, a value in the vicinity of the middle in the first search range.

  When CIN = 8 is set in this way, in the first update period TP1 (first update period), as shown by E3 in FIG. 18, when the clock cycle value becomes CCT = 8, the signal STA The signal level of is shifted. When the signal level of the signal STP transitions in response to the signal STA, the phase comparison between the signal STP and the clock signal CK2 is performed. For example, a phase comparison is performed by sampling the clock signal CK2 with the signal STP, and the H level of the clock signal CK2 is sampled as indicated by E4, and this H level becomes the phase comparison result. As described above, when the phase comparison result is at the H level, it is determined that the logic level of the bit b4 that is the MSB of the digital value DQ is b4 = 1.

  Since b4 = 1 is obtained in this way, the search range of the binary search is narrowed, and the CIN corresponding to the final digital value DQ is determined to be within the search range of 8 to 15, for example. Then, the clock cycle designation value is updated to, for example, CIN = 12, so as to be set to a value within this search range (for example, a value near the center).

  When updated to CIN = 12 in this way, in the next update period TP2 (second update period), the signal level of the signal STA when the clock cycle value becomes CCT = 12, as indicated by E5. Transition. Then, the phase comparison between the signal STP and the clock signal CK2 is performed and, for example, the L level of the clock signal CK2 is sampled as indicated by E6, so that this L level becomes the phase comparison result. As described above, when the phase comparison result is at the L level, it is determined that the logical level of the bit b3 next to the digital value DQ is b3 = 0.

  Since b4 = 1 and b3 = 0 are obtained in this way, the search range of the binary search is narrowed, and the CIN corresponding to the final digital value DQ is determined to be within the search range of 8 to 11, for example. The Then, the clock cycle designation value is updated to CIN = 10, for example, so as to be set to a value within this search range (for example, a value near the center).

  When updated to CIN = 10 in this way, in the next update period TP3 (third update period), as shown in E7, when the clock cycle value becomes CCT = 10, the signal level of the signal STA Transition. Then, the phase comparison between the signal STP and the clock signal CK2 is performed. For example, as shown at E8, the H level of the clock signal CK2 is sampled, so this H level becomes the phase comparison result. Thus, when the phase comparison result is at the H level, it is determined that the logic level of the bit b2 next to the digital value DQ is b2 = 1.

  Finally, CIN = 11 is updated, and in the next update period TP4 (fourth update period), as shown in E9, when the clock cycle value becomes CCT = 11, the signal level of the signal STA is changed. Let Then, the phase comparison between the signal STP and the clock signal CK2 is performed. For example, as shown at E10, the H level of the clock signal CK2 is sampled, so this H level becomes the phase comparison result. Thus, when the phase comparison result is at the H level, the bit b1 which is the LSB of the digital value DQ is set to b1 = 1. Then, as indicated by E11, DQ = 1011 (binary number) is output as the output code that is the final digital value.

  By using such a binary search method, it is possible to obtain a digital value DQ corresponding to the time difference between the transition timings of the signals STA and STP at high speed. For example, in the conventional method of Patent Document 4 described above, in the case of FIG. 18, for example, a maximum of 15 time measurements are required to obtain the final digital value DQ. On the other hand, according to the method of the present embodiment, as shown in FIG. 18, the final digital value DQ can be obtained, for example, in four update periods, and the time digital conversion can be speeded up.

In particular, when the resolution Δt is reduced and the bit number L of the digital value DQ is increased, the conventional method requires time measurement of, for example, about 2 ^L , and the conversion time becomes very long. End up. On the other hand, according to the method of the present embodiment, the final digital value DQ can be obtained, for example, in L update periods, and time digital conversion can be significantly speeded up compared to the conventional method.

  In addition, after the upper bit side of the digital value DQ is obtained by the binary search method of FIG. 18, the lower bit side (for example, the lower bit including LSB or the lower bit of LSB) has been described with reference to FIGS. You may make it obtain | require by the update method. For example, in FIG. 18, the clock cycle designation value CIN is updated so as to be a value within the search range while the search range (successive comparison range) is narrowed sequentially as in the case of successive approximation type A / D conversion. On the other hand, in the update method shown in FIGS. 15 to 17, the CIN is increased / decreased by ± GK based on the phase comparison result as in the Δ sigma type A / D conversion. GK is a gain coefficient, and GK ≦ 1. Specifically, when the phase comparison result indicates that the signal STP is delayed in phase from the clock signal CK2, updating (digital calculation processing) is performed to increase CIN by + GK. On the other hand, when the phase comparison result indicates that the phase of the signal STP is more advanced than that of the clock signal CK2, updating (digital arithmetic processing) is performed to decrease CIN by -GK. By combining the two methods in this way, it is possible to realize both high speed and high accuracy of time digital conversion.

6). Other Configuration Examples FIG. 19 shows another configuration example of the circuit device 10 of the present embodiment. In the circuit device 10 of FIG. 19, a plurality of PLL circuits 120 and 130 are provided as the synchronization circuit 110 of FIG.

  The PLL circuit 120 (first PLL circuit) performs phase synchronization between the clock signal CK1 and the reference clock signal CKR. Specifically, the PLL circuit 120 receives the clock signal CK1 of the clock frequency f1 generated using the oscillator XTAL1 (first oscillator) and the reference clock signal CKR, and receives the clock signal CK1 and the reference clock signal. Phase synchronization with CKR is performed. For example, the PLL circuit 120 synchronizes the phase of the clock signal CK1 and the reference clock signal CKR every first phase synchronization timing (every first period) (matches the transition timing).

  The PLL circuit 130 (second PLL circuit) performs phase synchronization between the clock signal CK2 and the reference clock signal CKR. Specifically, the PLL circuit 130 receives the clock signal CK2 of the clock frequency f2 generated using the oscillator XTAL2 (second oscillator) and the reference clock signal CKR, and receives the clock signal CK2 and the reference clock signal. Phase synchronization with CKR is performed. For example, the PLL circuit 130 synchronizes the phase of the clock signal CK2 and the reference clock signal CKR every second phase synchronization timing (every second period) (matches the transition timing).

  The reference clock signal CKR is generated, for example, by causing the oscillation circuit 103 to oscillate the oscillator XTAL3 (third oscillator). The clock frequency fr of the reference clock signal CKR is a frequency different from the clock frequencies f1 and f2 of the clock signals CK1 and CK2, and is, for example, a frequency lower than the clock frequencies f1 and f2. As the oscillator XTAL3, an element similar to the oscillators XTAL1 and XTAL2 can be used, and for example, a crystal oscillator or the like can be used. By using a crystal unit, it is possible to generate a highly accurate reference clock signal CKR with small jitter and phase error, and as a result, jitter and phase error of the clock signals CK1 and CK2 can be reduced, and time digital conversion is highly accurate. Etc. can be planned.

  Thus, in the present embodiment, the clock signal CK1 and the reference clock signal CKR are phase-synchronized by the PLL circuit 120, and the clock signal CK2 and the reference clock signal CKR are phase-synchronized by the PLL circuit 130. As a result, the clock signal CK1 and the clock signal CK2 are phase-synchronized. It is also possible to perform a modification in which three or more PLL circuits (three or more oscillators) are provided to perform phase synchronization of the clock signals CK1 and CK2.

  Specifically, the PLL circuit 120 includes frequency dividing circuits 122 and 124 (first and second frequency dividing circuits) and a phase detector 126 (first phase comparator). The frequency dividing circuit 122 performs frequency division so that the clock frequency f1 of the clock signal CK1 is 1 / N1, and outputs a frequency-divided clock signal DCK1 having a clock frequency of f1 / N1. The frequency dividing circuit 124 performs frequency division so that the clock frequency fr of the reference clock signal CKR is 1 / M1, and outputs a frequency-divided clock signal DCK2 having a clock frequency fr / M1. Then, the phase detector 126 performs phase comparison between the divided clock signal DCK1 and the divided clock signal DCK2, and outputs a signal PQ1 that is an up / down signal to the charge pump circuit 128. The oscillation circuit 101 (VCXO) performs the oscillation operation of the oscillator XTAL1 whose oscillation frequency is controlled based on the control voltage VC1 from the charge pump circuit 128, and generates the clock signal CK1.

  The PLL circuit 130 includes frequency dividing circuits 132 and 134 (third and fourth frequency dividing circuits) and a phase detector 136 (second phase comparator). The frequency dividing circuit 132 performs frequency division so that the clock frequency f2 of the clock signal CK2 is 1 / N2, and outputs a frequency-divided clock signal DCK3 having the clock frequency f2 / N2. The frequency divider circuit 134 performs frequency division so that the clock frequency fr of the reference clock signal CKR is 1 / M2, and outputs a frequency-divided clock signal DCK4 having a clock frequency fr / M2. Then, the phase detector 136 performs a phase comparison between the divided clock signal DCK3 and the divided clock signal DCK4, and outputs a signal PQ2 that is an up / down signal to the charge pump circuit 138. The oscillation circuit 102 (VCXO) performs an oscillation operation of the oscillator XTAL2 whose oscillation frequency is controlled based on the control voltage VC2 from the charge pump circuit 138, and generates the clock signal CK2.

  FIG. 20 is a signal waveform diagram for explaining the operation of the circuit device 10 of FIG. Note that FIG. 20 shows an example in which N1 = 4, M1 = 3, N2 = 5, and M2 = 4 are set for the sake of simplification, but actually, in order to increase the resolution of time digital conversion. N1, M1, N2, and M2 are set to very large numbers.

  As shown in FIG. 20, the signal obtained by dividing the clock signal CK1 by N1 = 4 becomes the divided clock signal DCK1, and the signal obtained by dividing the reference clock signal CKR by M1 = 3 becomes the divided clock signal DCK2, and every period T12. Phase synchronization is performed. That is, the PLL circuit 120 performs phase synchronization of the clock signal CK1 and the reference clock signal CKR so that the relationship of T12 = N1 / f1 = M1 / fr is established.

  A signal obtained by dividing the clock signal CK2 by N2 = 5 becomes a divided clock signal DCK3, and a signal obtained by dividing the reference clock signal CKR by M2 = 4 becomes a divided clock signal DCK4, and phase synchronization is performed every period T34. Is called. That is, the PLL circuit 130 performs phase synchronization of the clock signal CK2 and the reference clock signal CKR so that the relationship of T34 = N2 / f2 = M2 / fr is established. As described above, the clock signal CK1 and the reference clock signal CKR are phase-synchronized every period T12, and the clock signal CK2 and the reference clock signal CKR are phase-synchronized every period T34, so that the clock signals CK1 and CK2 are synchronized every period TAB. Phase-synchronized with each other. Here, the relationship of TAB = T12 × M2 = T34 × M1 is established. For example, when M2 = 4 and M1 = 3, TAB = T12 × 4 = T34 × 3.

  The frequency dividing ratios N1, M1, N2, and M2 of the frequency dividing circuits 122, 124, 132, and 134 in FIG. 19 are actually set to very large numbers. FIG. 21 shows an example of setting the frequency division ratio. For example, when the clock frequency of the reference clock signal CKR is fr = 101 MHz, by setting the frequency dividing ratio of the frequency dividing circuits 122 and 124 to N1 = 101 and M1 = 100, the PLL circuit 120 sets f1 = 102.01 MHz. A clock signal CK1 is generated. Further, by setting the frequency dividing ratios of the frequency dividing circuits 132 and 134 to N2 = 102 and M2 = 101, the PLL circuit 130 generates the clock signal CK2 of f2 = 102 MHz. Thereby, the resolution (time resolution) of the time digital conversion described in FIG. 2 can be set to Δt = | 1 / f1-1 / f2 | = 0.96 ps (picosecond), and the time digital conversion with very high resolution can be performed. Can be realized.

  As shown in FIG. 21, N1 and M1 are two or more different integers, and N2 and M2 are also two or more different integers. Further, at least one of N1 and M1 and at least one of N2 and M2 are different integers. Preferably, N1 and N2 have a greatest common divisor of 1 and a least common multiple of N1 × N2, and M1 and M2 have a greatest common divisor of 1 and a least common multiple of M1 × M2. .

  In FIG. 21, a relationship of | N1 × M2−N2 × M1 | = 1 holds. That is, N1, M1, N2, and M2 are set so that the relationship | N1 × M2−N2 × M1 | = 1 holds. Taking FIG. 20 as an example where N1 = 4, M1 = 3, N2 = 5, and M2 = 4, | N1 × M2-N2 × M1 | = | 4 × 4-5 × 3 | = 1. . This means that the length of 16 clock signals CK1 is equal to the length of 15 clock signals CK2. In this way, the clock signal CK1 and the clock signal CK2 are shifted by one clock cycle (one clock period) every period TAB. Thereby, time digital conversion using the caliper (vernier) principle can be easily realized.

  19 and 20, the phase of the clock signal CK1 and the reference clock signal CKR is synchronized every period T12 shorter than the period TAB, and the phase of the clock signal CK2 and the reference clock signal CKR every period T34 shorter than the period TAB. Synchronization is done. Accordingly, the frequency of phase comparison is increased compared to the configuration example of FIG. 14 described above, and the jitter (cumulative jitter) and phase noise of the clock signals CK1 and CK2 can be reduced. In particular, when N1, M1, N2, and M2 are set to a large number in order to realize a high resolution Δt, the length of the synchronization period becomes very long in the configuration example of FIG. Accumulation increases jitter and phase error. On the other hand, in FIGS. 19 and 20, since phase comparison is performed every short period T12 and T34, there is an advantage that the integration error can be reduced and the jitter and phase error can be improved.

  Although the PLL circuits 120 and 130 in FIG. 19 have an analog circuit configuration, a digital (ADPLL) circuit configuration may be adopted. In this case, each PLL circuit (120, 130) can be realized by a phase detector having a counter and a TDC, a digital arithmetic unit, and the like. The counter generates digital data corresponding to the integer part of the result of dividing the clock frequency (fr) of the reference clock signal (CKR) by the clock frequency (f1, f2) of the clock signal (CK1, CK2). The TDC generates digital data corresponding to the decimal part of the division result. Digital data corresponding to the addition result of these integer part and decimal part is output to the digital operation part. The digital calculation unit detects the phase error with the set frequency data based on the set frequency data (FCW1, FCW2) and the digital data of the comparison result from the phase detector, and performs the phase error smoothing process. Frequency control data is generated and output to the oscillation circuits (101, 102). The oscillation circuit controls the oscillation frequency based on the frequency control data, and generates clock signals (CK1, CK2). Instead of using TDC, a digital PLL circuit may be realized with a configuration using a Bang-Bang type phase detector and PI control.

7). Jitter and resolution As described above, in this embodiment, high-resolution time-to-digital conversion is realized. However, there is a problem that accuracy corresponding to high resolution cannot be realized due to accumulation of jitter of a clock signal. . For example, if the jitter is simply white noise, the accumulated jitter is, for example, a random walk. That is, with respect to jitter (white noise) such as perfect noise without autocorrelation, the cumulative jitter as the cumulative sum is a random walk and has autocorrelation.

  For example, the random walk converges to a normal distribution (Gaussian distribution) as indicated by C1 in FIG. The quantum walk converges to a given probability density function with a finite platform (compact support), as shown at C2 and C3.

For example, in FIG. 8, the clock signals CK1 and CK2 are phase-synchronized every period TS. As shown by D1 in FIG. 23, the clock signals CK1 and CK2 have jitter for each clock cycle. The clock signals CK1 and CK2 are phase-synchronized every period TK, and D2 is the accumulated jitter in this period TK. Here, the jitter amount per clock cycle of the clock signals CK1 and CK2 is J, and the number of clocks in the period TK for one of the clock signals CK1 and CK2 (or the reference clock signal) is K. At this time, assuming a random walk, the cumulative jitter amount (jitter integration error) can be expressed as, for example, K ^1/2 × J. Assuming that it is a quantum walk, the cumulative jitter amount can be expressed as K × J, for example.

  Here, the jitter amount J represents a phase shift with respect to an ideal clock signal, is represented by an RMS value, and a unit is time. For example, the jitter amount J is a standard value (maximum standard value) determined by the performance of the resonator, for example, an RMS value representing an average phase shift per clock. The number of clocks K is one in a period TK between the timing when one of the clock signals CK1 and CK2 is phase-synchronized with the other clock signal or the reference clock signal (CKR) and the next phase-synchronizing timing. This is the number of clock signals. In the example of FIG. 8, the clock number K corresponds to the clock numbers N and M of the clock signals CK1 and CK2. The period TK corresponds to the period TS in FIG. When the frequency of one of the clock lock signals CK1 and CK2 is f (f1, f2) and the resolution of time digital conversion is Δt, it can be expressed as K = 1 / (f × Δt). On the other hand, in the example of FIG. 19, the clock number K corresponds to N1 and N2 of FIG. The period TK corresponds to the periods T12 and T34 in FIG.

  As shown in FIG. 23, the larger the number of clocks K in the period TK representing the phase synchronization interval, the larger the error due to accumulated jitter and the lower the accuracy. In that sense, in the configuration example of FIG. 19, since the number of clocks K in the period TK can be reduced, errors due to accumulated jitter can be reduced, and accuracy can be improved.

H1, H2, and H3 in FIG. 24 indicate the relationship between the resolution (sec) and the jitter (sec_rms) of the clock signal when assuming a random walk, for example. For example, the relationship between the resolution and the jitter when the cumulative jitter amount is expressed as K ^1/2 × J is shown. H1, H2, and H3 are the frequencies of the clock signals (CK1, CK2) of 100 MHz, 1 GHz, 10 MHz. This corresponds to the case. In FIG. 24, a region indicated by H4 is a region in which accuracy is deteriorated due to jitter as a main factor. The region indicated by H5 is a region that deteriorates accuracy mainly due to resolution.

For example H1 of Figure 24, the frequency of the clock signal is 100 MHz, shows a case clock number K of about 10 ^4. In example H1, when the resolution (Delta] t) is ^{1ps (10} -12 sec), jitter (J) has become a ^0.01ps (10 -14 ^sec_rms), When K = 10 ^4, Δt = K The relationship of ^1/2 × J is established. For example, when the frequency of the clock signal is increased to 1 GHz, the number of clocks K can be reduced. Therefore, the line representing the relationship Δt = K ^1/2 × J is indicated by H2, and the demand for jitter is moderated. On the other hand, when the frequency of the clock signal is lowered to 10 MHz, the number of clocks K increases, so the line representing the relationship Δt = K ^1/2 × J becomes H3, and the requirement for jitter becomes severe.

In the present embodiment, when the jitter amount per clock cycle of the clock signals CK1 and CK2 is J and the resolution of time digital conversion is Δt, at least the relationship of J ≦ Δt is established. For example, H6 in FIG. 25 indicates a line where the relationship of J = Δt is established, and this corresponds to a region where the accuracy is degraded due to jitter as shown in H4 in FIG. 24, and the jitter does not exceed the resolution at least. This shows the upper limit of jitter. For example, when the resolution (Δt) is 1 ps (10 ⁻¹² sec), the jitter amount J is required to be at least 1 ps (10 ⁻¹² sec_rms) or less, and the jitter amount J is more than 1 ps (RMS value). Do not allow it to grow. This is because when the jitter amount J is larger than 1 ps, it becomes meaningless to have a high resolution such as Δt = 1 ps.

  In the present embodiment, one clock signal of the clock signals CK1 and CK2 is in a period TK between the timing of phase synchronization with the other clock signal or the reference clock signal (CKR) and the next phase synchronization timing. When the number of clocks of one clock signal is K, the relationship of J ≧ Δt / K is established. For example, H7 in FIG. 25 indicates a line where the relationship of J = Δt / K is established, which corresponds to a region where the accuracy is degraded due to the resolution as shown in H5 in FIG. Is shown. For example, H7 corresponds to the quantum walk. As described above, when J ≧ Δt / K, it is possible to cope with the case where the behavior of the accumulated jitter is assumed to be a quantum walk, and it becomes unnecessary to select an oscillator having a jitter characteristic better than necessary. .

For example, when the frequency of the clock signals (CK1, CK2) is f (f1, f2) and the number of clocks in the period TK is K, K = 1 / (f × Δt) holds. In the example of FIG. 8, N = 1 / (f1 × Δt) and M = 1 / (f2 × Δt) are established. This means that the phase of one clock signal and the other clock signal (CK1, CK2) is shifted by one clock cycle every period TK (TS). Therefore, the relational expression of J ≧ Δt / K becomes a relational expression of J ≧ f × Δt ^{2 when} expressed by the frequency f of the clock signal.

In the present embodiment, for example, a relationship of (1/10) × (Δt / K ^1/2 ) ≦ J ≦ 10 × (Δt / K ^1/2 ) is established. For example, when the clock frequency is 100 MHz, H1 in FIG. 25 corresponds to a line of J = Δt / K ^1/2 , which corresponds to a random walk line. In this case, for example, within the range indicated by H8 in FIG. 25, the accuracy does not decrease due to jitter as shown in H4 in FIG. 24, or the accuracy does not decrease due to the resolution as shown in H5. (1/10) × (Δt / K ^1/2 ) ≦ J ≦ 10 × (Δt / K ^1/2 ) indicates that it is in the range indicated by H8 in FIG. 25, and the relationship between resolution and jitter. Is preferably in the range indicated by H8. The H8 range area is the boundary between the area where the accumulated jitter controls the accuracy and the area where the resolution controls the accuracy, so high-precision time-to-digital conversion can be performed without using an overspec oscillator. Can be realized.

For example, assuming a random walk, a relational expression in which the resolution and the cumulative jitter amount antagonize can be expressed as J = Δt / K ^1/2 . As described above, when K = 1 / (f × Δt) holds, J = Δt / K ^1/2 becomes a relational expression of J = (f × Δt ³ ) ^1/2 . Therefore, as shown in FIG. 25, when the frequency f of the clock signal is in the range of 10 MHz to 1 GHz, the relationship of (10 ⁷ × Δt ³ ) ^1/2 ≦ J ≦ (10 ⁹ × Δt ³ ) ^1/2 is established. Become. When the frequency f of the clock signal is in the range of 10 KHz to 10 GHz, the relationship of (10 ⁴ × Δt ³ ) ^1/2 ≦ J ≦ (10 ¹⁰ × Δt ³ ) ^1/2 is established.

8). Physical Quantity Measuring Device, Electronic Device, Mobile Object FIG. 26 shows a configuration example of the physical quantity measuring device 400 of this embodiment. The physical quantity measuring device 400 includes the circuit device 10 of the present embodiment, an oscillator XTAL1 (first oscillator, first vibrating element) for generating the clock signal CK1, and an oscillation for generating the clock signal CK2. A child XTAL2 (second oscillator, second vibrating piece) is included. The physical quantity measuring device 400 can include a package 410 in which the circuit device 10 and the oscillators XTAL1 and XTAL2 are accommodated. The package 410 includes a base part 412 and a lid part 414, for example. The base portion 412 is a member such as a box made of an insulating material such as ceramic, and the lid portion 414 is a member such as a flat plate joined to the base portion 412. For example, an external connection terminal (external electrode) for connecting to an external device is provided on the bottom surface of the base portion 412. The circuit device 10 and the resonators XTAL1 and XTAL2 are accommodated in an internal space (cavity) formed by the base portion 412 and the lid portion 414. The circuit device 10 and the resonators XTAL1 and XTAL2 are hermetically sealed in the package 410 by sealing with the lid portion 414.

  The circuit device 10 and the resonators XTAL1 and XTAL2 are mounted in the package 410. The terminals of the oscillators XTAL 1 and XTAL 2 and the terminals (pads) of the circuit device 10 (IC) are electrically connected by the internal wiring of the package 410. The circuit device 10 is provided with oscillation circuits 101 and 102 for causing the oscillators XTAL1 and XTAL2 to oscillate. The oscillation circuits 101 and 102 cause the oscillators XTAL1 and XTAL2 to oscillate, whereby the clock signals CK1 and CK2 are generated. Generated.

  For example, in the conventional method described in Patent Document 4, the first and second oscillation circuits are provided in the first and second crystal oscillators, and the circuit device does not include the first and second oscillation circuits. . For this reason, phase synchronization of the first and second clock signals by the synchronization circuit 110 cannot be realized. Further, there is a disadvantage that control processing common to the first and second oscillation circuits cannot be executed in the circuit device.

  Various modifications can be made to the configuration of the physical quantity measuring device 400. For example, the base portion 412 may have a flat plate shape, and the lid portion 414 may have a shape in which a concave portion is formed inside thereof. Various modifications can be made to the mounting form and wiring connection of the circuit device 10 and the resonators XTAL1 and XTAL2 in the package 410. Further, the oscillators XTAL1 and XTAL2 do not need to be configured separately, and may be the first and second oscillation regions formed in one member. Three or more oscillators may be provided in the physical quantity measuring device 400 (package 410). In this case, the circuit device 10 may be provided with three or more oscillation circuits corresponding thereto.

  FIG. 27 shows a configuration example of an electronic apparatus 500 including the circuit device 10 of the present embodiment. The electronic device 500 includes the circuit device 10 according to the present embodiment, the oscillators XTAL1, XTAL2, and a processing unit 520. Further, the communication unit 510, the operation unit 530, the display unit 540, the storage unit 550, and the antenna ANT can be included. The physical quantity measuring device 400 is configured by the circuit device 10 and the resonators XTAL1 and XTAL2. Note that the electronic apparatus 500 is not limited to the configuration shown in FIG. 27, and various modifications such as omitting some of these components or adding other components are possible.

  As the electronic device 500, for example, a measuring device that measures a physical quantity such as distance, time, flow rate, or flow rate, a biological information measuring device that measures biological information (an ultrasonic measuring device, a pulse wave meter, a blood pressure measuring device, etc.), an in-vehicle device (Devices for automatic operation, etc.), network-related devices such as base stations or routers can be assumed. It also distributes wearable devices such as head-mounted display devices and clock-related devices, printing devices, projection devices, robots, portable information terminals (smartphones, mobile phones, portable game devices, notebook PCs, tablet PCs, etc.), and content. A content providing device or a video device such as a digital camera or a video camera can be assumed.

  The communication unit 510 (wireless circuit) performs processing of receiving data from the outside via the antenna ANT and transmitting data to the outside. The processing unit 520 performs control processing of the electronic device 500, various digital processing of data transmitted / received via the communication unit 510, and the like. The processing unit 520 performs various processes using the physical quantity information measured by the physical quantity measuring device 400. The function of the processing unit 520 can be realized by a processor such as a microcomputer.

  The operation unit 530 is for a user to perform an input operation, and can be realized by an operation button, a touch panel display, or the like. The display unit 540 displays various types of information and can be realized by a display such as a liquid crystal or an organic EL. When a touch panel display is used as the operation unit 530, the touch panel display also functions as the operation unit 530 and the display unit 540. The storage unit 550 stores data, and the function can be realized by a semiconductor memory such as a RAM or a ROM, an HDD (hard disk drive), or the like.

  FIG. 28 shows an example of a moving object including the circuit device of this embodiment. The circuit device 10 (oscillator) of this embodiment can be incorporated into various moving bodies such as a car, an airplane, a motorcycle, a bicycle, a robot, or a ship. The moving body is, for example, a device / device that moves on the ground, in the sky, or on the sea, including a drive mechanism such as an engine or motor, a steering mechanism such as a steering wheel or rudder, and various electronic devices (on-vehicle devices). FIG. 28 schematically shows an automobile 206 as a specific example of the moving object. The automobile 206 (moving body) incorporates the circuit device 10 of the present embodiment and a physical quantity measurement device (not shown) having an oscillator. The control device 208 performs various control processes based on the physical quantity information measured by the physical quantity measuring device. For example, when distance information of an object around the automobile 206 is measured as physical quantity information, the control device 208 performs various control processes for automatic driving using the measured distance information. The control device 208 controls the hardness of the suspension, for example, according to the posture of the vehicle body 207, and controls the brakes of the individual wheels 209. The device in which the circuit device 10 and the physical quantity measuring device of this embodiment are incorporated is not limited to such a control device 208, and may be incorporated in various devices (on-vehicle devices) provided in a moving body such as the automobile 206. Is possible.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term (such as a clock cycle designation value) written together with a different term having a broader meaning or the same meaning (such as a clock cycle designation information) at least once in the specification or the drawing, Can be replaced with a different term. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. In addition, the configuration and operation of the circuit device, the physical quantity measuring device, the electronic device, and the moving body, the time digital conversion processing, the first and second signal generation processing, the phase comparison processing, the phase synchronization processing, and the like have been described in this embodiment. The present invention is not limited to this, and various modifications can be made.

STA, STP ... first and second signals, CK1, CK2 ... first and second clock signals,
XTAL1, XTAL2, XTAL3 ... 1st, 2nd, 3rd oscillator,
f1, f2 ... first and second clock frequencies, Δt ... resolution,
CIN: Clock cycle specification value (clock cycle specification information),
CCT ... clock cycle value, DQ ... digital value, TDF ... time difference,
TR: time difference between clocks, TCNT: count value, TS: measurement period,
TM, TMA, TMB ... phase synchronization timing,
TP, TP1 to TP4 ... update period, N ... number of clocks,
OS1, OS2 ... oscillation signal, LP1, LP2 ... oscillation loop,
DESCRIPTION OF SYMBOLS 10 ... Circuit apparatus, 20 ... Time digital conversion circuit, 21, 22 ... Phase detector, 30 ... Processing part, 32 ... Signal output part, 44 ... Counter,
101, 102, 103 ... oscillation circuit, 110 ... synchronization circuit,
112 ... Counter, 120 ... PLL circuit, 122, 124 ... Frequency divider,
126 ... Phase detector, 128 ... Charge pump circuit, 130 ... PLL circuit,
132, 134 ... frequency divider circuit, 136 ... phase detector, 138 ... charge pump circuit,
206 ... Automobile (moving body), 207 ... Car body, 208 ... Control device, 209 ... Wheel,
400 ... Physical quantity measuring device, 410 ... Package, 412 ... Base part, 414 ... Lid part, 500 ... Electronic device, 510 ... Communication part, 520 ... Processing part, 530 ... Operation part,
540 ... display unit, 550 ... storage unit

Claims (19)

A first clock signal having a first clock frequency and a second clock signal having a second clock frequency different from the first clock frequency are input, and transition timings of the first signal and the second signal are input. A time digital conversion circuit that converts the time difference between the two into a digital value;
A synchronization circuit for synchronizing the phases of the first clock signal and the second clock signal;
Including
The time digital conversion circuit includes:
After the phase synchronization timing of the first clock signal and the second clock signal, the signal level of the first signal is changed based on the first clock signal, and the first signal corresponds to the first signal. A circuit device characterized in that the digital value corresponding to the time difference is obtained by performing phase comparison between the second signal whose signal level transitions and the second clock signal. The circuit device according to claim 1,
The time digital conversion circuit includes:
After the phase synchronization timing, the circuit device shifts the signal level of the first signal every clock cycle of the first clock signal. The circuit device according to claim 2,
The time digital conversion circuit includes:
The phase difference between the second signal whose signal level transitions corresponding to the first signal and the second clock signal is compared at each clock cycle of the first clock signal, so that the time difference is obtained. A circuit device characterized in that the digital value corresponding to is obtained. The circuit device according to any one of claims 1 to 3,
The synchronization circuit includes:
A circuit device, wherein the first clock signal and the second clock signal are phase-synchronized at each phase synchronization timing. In the circuit device according to any one of claims 1 to 4,
The time digital conversion circuit includes:
After the phase synchronization timing, when the signal level of the first signal transits based on the first clock signal, and the signal level of the second signal transits corresponding to the first signal The circuit device is characterized in that the digital value corresponding to the time difference is obtained by specifying the timing at which the phase relationship between the second signal and the second clock signal is switched. The circuit device according to any one of claims 1 to 5,
The time digital conversion circuit includes:
A circuit device characterized in that time digital conversion is performed at a resolution corresponding to a frequency difference between the first clock frequency and the second clock frequency. The circuit device according to any one of claims 1 to 6,
The time digital conversion circuit includes:
After the phase synchronization timing, when the time difference between the transition timings of the first clock signal and the second clock signal in the i-th clock cycle is the time difference between clocks TR = i × Δt, the time with the resolution Δt A circuit device characterized by performing digital conversion. The circuit device according to claim 7, wherein
The time digital conversion circuit includes:
A digital value corresponding to the time difference between clocks TR = j × Δt when the phase relationship between the second signal and the second clock signal is switched in the jth clock cycle after the phase synchronization timing. Is obtained as the digital value corresponding to the time difference. The circuit device according to any one of claims 1 to 8,
The time digital conversion circuit includes:
The first clock signal is a clock signal generated using a first oscillator, and the second clock signal is a clock signal generated using a second oscillator. A circuit device. The circuit device according to any one of claims 1 to 9,
The time digital conversion circuit includes:
A circuit device comprising: a signal output unit that outputs the first signal every clock cycle of the first clock signal based on the first clock signal. The circuit device according to any one of claims 1 to 10,
The time digital conversion circuit includes:
When the phase comparison result signal between the second signal and the second clock signal is at the first voltage level, the count value is not updated, and the phase comparison result signal is at the second voltage level. In some cases, the circuit device includes a counter in which the count value is updated, and the digital value corresponding to the time difference is obtained based on the count value of the counter. The circuit device according to any one of claims 1 to 11,
The time digital conversion circuit includes:
A phase comparison between the second signal and the second clock signal is performed by sampling the other signal based on one of the second signal and the second clock signal. Circuit device. The circuit device according to any one of claims 1 to 12,
As the synchronization circuit, a first PLL circuit that performs phase synchronization between the first clock signal and a reference clock signal, and a second PLL that performs phase synchronization between the second clock signal and the reference clock signal. A circuit device comprising: a circuit; The circuit device according to any one of claims 1 to 13,
A circuit device, wherein J ≦ Δt, where J is a jitter amount per clock cycle of the first clock signal and the second clock signal and Δt is a resolution of time digital conversion. The circuit device according to claim 14, wherein
The one of the first clock signal and the second clock signal in a period between the timing of phase synchronization with respect to the other clock signal or the reference clock signal and the timing of phase synchronization with the next clock signal. A circuit device, wherein J ≧ Δt / K, where K is the number of clocks of the clock signal. The circuit device according to claim 14 or 15,
The one clock in a period between the timing when one of the first clock signal and the second clock signal is phase-synchronized with the other clock signal or the reference clock signal and the next phase-synchronizing timing 1. A circuit device, wherein the number of clocks of a signal is K, (1/10) × (Δt / K ^1/2 ) ≦ J ≦ 10 × (Δt / K ^1/2 ). A circuit device according to any one of claims 1 to 16,
A first oscillator for generating the first clock signal;
A second oscillator for generating the second clock signal;
A physical quantity measuring device comprising:   An electronic apparatus comprising the circuit device according to claim 1.   A moving body comprising the circuit device according to claim 1.