JP2018056531A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including an insulated gate bipolar transistor which inhibits current concentration caused by local breakdown.SOLUTION: A semiconductor device comprises a crystal defect region in a drift region 10; and in working power-supply voltage, the crystal defect region 100 lies below an end of a depletion layer extending from an interface between the drift region 10 and a base region 20 into the drift region 10; and in power-supply voltage to cause breakdown, a lower limit of the crystal defect region 100 lies above an end of the depletion layer extending from the interface between the drift region 10 and the base region 20 into the drift region 10.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device having an insulated gate bipolar transistor.

An insulated gate bipolar transistor (IGBT) is used as a switching element (power semiconductor element) that performs a switching operation of a large current such as a motor drive circuit. The IGBT can reduce the on-voltage using the conductivity modulation of the drift region. However, when the IGBT is turned off, a tail current due to holes (residual carriers) remaining in the drift region flows, and the turn-off loss of the IGBT is increased. Therefore, when a predetermined potential is applied between the collector and the emitter of the IGBT, the drift region of the semiconductor region portion (for example, the interface between the drift region and the buffer layer) outside the end of the depletion layer where the depletion layer does not extend. It is disclosed that a crystal defect is formed inside (see, for example, Patent Document 1). According to the semiconductor device provided with the crystal defect region, since at least a part of the remaining carriers are captured in the crystal defect region, the lifetime of the holes can be lowered, and the tail current generated when the semiconductor device is turned off can be reduced. Can be shortened. As a result, the IGBT turn-off loss can be reduced.

JP 9-121052 A

However, if a breakdown voltage higher than a steep breakdown voltage higher than the voltage used for the power supply of the semiconductor device is applied, the extension of the depletion layer in the drift region is likely to be non-uniform in the plane, causing local breakdown. Sometimes. As a result, burning due to current concentration may occur.
Therefore, an object of the present invention is to provide a semiconductor device including an insulated gate bipolar transistor that suppresses current concentration due to local breakdown.

  According to one aspect of the present invention, the first conductive type first semiconductor region, the second conductive type second semiconductor region disposed on the first semiconductor region, and the second semiconductor region are disposed. A third semiconductor region of the first conductivity type, a control electrode disposed extending from the third semiconductor region to the second semiconductor region, a fourth semiconductor region disposed below the first semiconductor region, A fifth semiconductor region of a first conductivity type disposed between the first semiconductor region and the fourth semiconductor region and having an impurity concentration higher than that of the first semiconductor region; a crystal defect region in the first semiconductor region; In the power supply voltage where the crystal defect region exists below the edge of the depletion layer extending from the interface between the first semiconductor region and the second semiconductor region to the first semiconductor region and breakdown occurs, First from the interface between the first semiconductor region and the second semiconductor region There is provided a semiconductor device having a lower limit of a crystal defect region above an end portion of a depletion layer extending in a semiconductor region.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device containing the insulated gate bipolar transistor which suppressed current concentration by local breakdown can be provided.

It is a typical sectional view showing the structure of the semiconductor device concerning the embodiment of the present invention. It is a schematic diagram showing the number of crystal defects in the depth direction in the crystal defect region of the semiconductor device according to the embodiment of the present invention. It is a schematic diagram showing the number of crystal defects in the depth direction in a modification of the crystal defect region of the semiconductor device according to the embodiment of the present invention. It is a schematic diagram showing the number of crystal defects in the depth direction in another modification of the crystal defect region of the semiconductor device according to the embodiment of the present invention.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the lengths of the respective parts, and the like are different from the actual ones. Therefore, specific dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention includes the shape, structure, arrangement, etc. of components. It is not specified to the following. The embodiment of the present invention can be variously modified within the scope of the claims.

As shown in FIG. 1, the semiconductor device according to the embodiment of the present invention includes a first conductivity type first semiconductor region (drift region 10) and a second conductivity type second semiconductor disposed on the first semiconductor region. 2 semiconductor regions (base region 20) and a first conductivity type third semiconductor region (emitter region 30) disposed on the second semiconductor region. A groove extending from the upper surface of the third semiconductor region and extending through the third semiconductor region and the second semiconductor region to reach the first semiconductor region is formed, and an inner wall insulating film 40 is disposed on the inner wall of the groove.
The first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is n-type, the second conductivity type is p-type. If the first conductivity type is p-type, the second conductivity type is n-type. Hereinafter, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

Drift region 10 is arranged on one main surface of p-type collector region 60. An n-type field stop region 65 having an impurity concentration higher than that of the drift region 10 is arranged between the drift region 10 and the collector region 60. The field stop region 65 limits the amount of holes reaching the drift region 10 from the collector region 60 in the on state of the semiconductor device. Further, the end of the depletion layer extending from the upper surface of the drift region 10 in the off state of the semiconductor device is suppressed from reaching the collector region 60. A collector electrode 80 electrically connected to the collector region 60 is disposed on the other main surface of the collector region 60.

The semiconductor device shown in FIG. 1 is a trench gate type IGBT having a control electrode (gate electrode 50) disposed on the inner wall insulating film 40 on the side surface of the groove facing the side surface of the base region 20. .
As shown in FIG. 1, an interlayer insulating film 70 is provided between the gate electrode 50 and the emitter electrode 90. A gate electrode 50 is disposed in a region facing the base region 20 with the inner wall insulating film 40 interposed therebetween. An emitter region 30 is selectively disposed on the base region 20. The emitter electrode 90 is disposed on the interlayer insulating film 70, and the emitter electrode 90 is connected to the emitter region 30 or both the base region 20 and the emitter region 30. The gate electrode 50 and the emitter electrode 90 are electrically insulated by the interlayer insulating film 70.
In the semiconductor device shown in FIG. 1, the surface of the base region 20 facing the gate electrode 50 with the inner wall insulating film 40 interposed therebetween is a channel region where a channel is formed. That is, the region between the gate electrode 50 and the base region 20 of the inner wall insulating film 40 functions as a gate insulating film. The gate electrode 50 is disposed so as to face at least the base region 20 so that a channel is formed in the base region 20 along the groove from the emitter region 30 to the drift region 10. Furthermore, the end of the gate electrode 50 on the corner side (end on the side surface side of the groove) extends to a position lower than the position where the interface between the base region 20 and the drift region 10 intersects the side surface of the groove, that is, above the drift region 10. It is desirable that Thus, a channel is reliably formed in the base region 20 along the groove from the emitter region 30 to the drift region 10, and the semiconductor device can be reliably turned on.

As shown in FIG. 1, a crystal defect region 100 serving as a lifetime control unit is provided by irradiating light ions such as neon, proton, and helium into the drift region 10 in order to shorten the lifetime in the device. Yes. The crystal defect region 100 is formed in the drift region 10, and the upper limit and the lower limit in the depth direction of the crystal defect region 100 are in the drift region 10. Thereby, a region of the drift region 10 having no crystal defect exists under the crystal defect region 100. As shown in FIG. 2, in the crystal defect region 100, the closer to the collector region 60, the greater the number of crystal defects. The upper limit in the depth direction of the crystal defect region 100 is on the outer side (lower side in the depth direction of the semiconductor device) than the end position (h1) of the depletion layer during actual operation of the IGBT. The lower limit in the depth direction of 100 is on the inner side (upper side in the depth direction of the semiconductor device) than the end position (h2) of the depletion layer at the time of breakdown of the IGBT. In other words, when viewed in the depth direction of the semiconductor device, the crystal defect region 100 has a depletion layer end position (h1) during actual IGBT operation and a depletion layer end position (h2) during IGBT breakdown. between.

Here, the operation of the semiconductor device illustrated in FIG. 1 will be described. A predetermined collector voltage is applied between the emitter electrode 90 and the collector electrode 80, and a predetermined gate voltage is applied between the emitter electrode 90 and the gate electrode 50. For example, the collector voltage is about 300V to 1600V, and the gate voltage is about 10V to 20V. When the semiconductor device is turned on in this manner, the channel region is inverted from the p-type to the n-type to form a channel. Electrons are injected from the emitter electrode 90 into the drift region 10 through the formed channel. A forward bias is applied between the collector region 60 and the drift region 10, and holes move from the collector electrode 80 through the collector region 60 in the order of the drift region 10 and the base region 20. When the current flowing through the semiconductor device is further increased, holes from the collector region 60 are increased, and holes are accumulated below the base region 20. As a result, the ON voltage decreases due to conductivity modulation.

  When the semiconductor device is changed from the on state to the off state, the gate voltage is controlled to be lower than the threshold voltage. For example, the gate voltage is set to the same potential as the emitter voltage or a negative potential. As a result, the channel of the base region 20 disappears, and the injection of electrons from the emitter electrode 90 to the drift region 10 stops. Since the potential of the collector electrode 80 is higher than that of the emitter electrode 90, the depletion layer spreads from the interface between the base region 20 and the drift region 10, and some of the holes accumulated in the drift region 10 are transferred to the emitter electrode 90. As a result, some of the holes move into the drift region 10 outside the edge of the depletion layer. Holes remaining in the drift region 10 when the semiconductor device is turned on from off become residual carriers.

  Here, the semiconductor device shown in FIG. 1 has a crystal defect region 100 in the drift region 10. The region of the drift region 10 having the crystal defect region 100 has a leakage current larger than that of the region 10 of the drift region not having the crystal defect region 100. When the end of the depletion layer reaches the crystal defect region 100 in the drift region 10, the carrier region in the drift region 10 having the crystal defect region 100 becomes active, the space charge is distorted, and the extension of the depletion layer is Be gentle. By providing the crystal defect region 100 in the drift region 10 inside the end of the depletion layer where breakdown occurs (that is, above the depth h2 in FIG. 2), local breakdown is suppressed, and current concentration The semiconductor device is also prevented from burning out.

In FIG. 1, the lower limit of the crystal defect region 100 and the interface between the drift region 10 and the field stop region 65 are larger than the upper limit of the crystal defect region 100 and the distance (d1) to the interface between the drift region 10 and the base region 20. It is desirable that the distance (d2) is short. Thereby, the effect of the present invention can be obtained more effectively without increasing the thickness of the semiconductor device.

Further, the depletion layer in the crystal defect region 100 extends more slowly than the region in which the crystal defect region 100 in the vicinity thereof is not provided. When the crystal defect region 100 is provided in the drift region 10, a large difference occurs between the depth of the end of the depletion layer that has passed through the crystal defect region 100 and the depth of the end of the depletion layer that has not passed through the crystal defect region 100, Local breakdown may occur in the semiconductor device. Particularly, when the lower limit of the crystal defect region 100 is formed to reach the field stop region 65, local breakdown is likely to occur.
Therefore, according to the semiconductor device of FIG. 1, the region of the drift region 10 where the crystal defect region 100 is not provided is provided below the lower limit of the crystal defect region 100. As a result, even if a voltage is applied so that the end of the depletion layer exceeds the lower limit of the crystal defect region 100 and passes through the region of the drift region 10 where the crystal defect region 100 is not provided, it passes through the crystal defect region 100. Thus, the difference between the end depth of the depletion layer that extends without passing through and the end depth of the depletion layer that extends through the crystal defect region 100 can be reduced, and the extension of the depletion layer can be made relatively uniform. As a result, local breakdown can be suppressed.

(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

In the semiconductor device of FIG. 1, the example in which the number of crystal defects in the crystal defect region 100 is provided so as to gradually increase in the depth direction as shown in FIG. May be formed so as to increase stepwise in the depth direction. Even in this case, it is clear that the effect of the present invention can be obtained.
In the semiconductor device of FIG. 1, the example in which the number of crystal defects in the crystal defect region 100 is gradually increased in the depth direction as shown in FIG. 2 has been described. A region having a large number of defects (mountain region) may exist, and a region having a small number of crystal defects (valley region) may be formed so as to be sandwiched therebetween. Even in this case, it is clear that the effect of the present invention can be obtained.
In the semiconductor device of FIG. 1, as shown in FIG. 2, the upper surface of the crystal defect region 100 is outside the end of the depletion layer during actual operation of the IGBT, and the position of the end of the depletion layer during actual operation of the IGBT. As described in the example below (h1), it is desirable that the upper surface of the crystal defect region 100 is the same as the end position (h1) of the depletion layer during the actual operation of the IGBT. However, as shown in FIG. 3, the upper surface of the crystal defect region 100 is in the drift region 10 inside the end of the depletion layer during actual operation of the IGBT, and the position (h1) of the end of the depletion layer during actual operation of the IGBT ). Even in this case, it is clear that the effect of the present invention can be obtained.
In the semiconductor device of FIG. 1, the example in which one crystal defect region 100 is provided in the depth direction has been described, but a plurality of crystal defect regions 100 may be provided in the depth direction as shown in FIG. At this time, the crystal defect region 100 closer to the collector region 60 may be provided so as to increase the maximum value of the number of crystal defects. Even in this case, it is clear that the effect of the present invention can be obtained.
Further, the formation method of the crystal defect region 100 may be changed in the depth direction. For example, the region above the crystal defect region 100 may be formed by implanting gold or platinum into the drift region 10, and the region below the crystal defect region 100 may be formed by implanting ion irradiation into the drift region 10. good. Even in this case, it is clear that the effect of the present invention can be obtained.
In the semiconductor device of FIG. 1, an example of being applicable to a trench gate type IGBT has been shown, but may be applied to a well-known planar gate type IGBT. Even in this case, it is clear that the effect of the present invention can be obtained.

  Note that although the case where the semiconductor device is an n-channel type has been described as an example, it is apparent that the effects of the present invention can be obtained even if the semiconductor device is a p-channel type.

As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

DESCRIPTION OF SYMBOLS 10 ... Drift region 20 ... Base region 30 ... Emitter region 40 ... Inner wall insulating film 50 ... Gate electrode 60 ... Collector region 65 ... Field stop region 70 ... Interlayer insulating film 100 ... Crystal defect region

Claims (6)

A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type disposed on the first semiconductor region;
A third semiconductor region of a first conductivity type disposed on the second semiconductor region;
A control electrode disposed extending from the third semiconductor region to the second semiconductor region;
A fourth semiconductor region disposed below the first semiconductor region;
A fifth semiconductor region of a first conductivity type disposed between the first semiconductor region and the fourth semiconductor region and having an impurity concentration higher than that of the first semiconductor region;
A crystal defect region in the first semiconductor region;
In the power supply voltage to be used, the crystal defect region is below the end of the depletion layer extending from the interface between the first semiconductor region and the second semiconductor region to the first semiconductor region,
In the power supply voltage at which breakdown occurs, the lower limit of the crystal defect region is above the end of the depletion layer extending from the interface between the first semiconductor region and the second semiconductor region to the first semiconductor region. A semiconductor device.
In the power supply voltage used by the upper limit of the crystal defect region, the upper limit of the crystal defect region is located inside the end of the depletion layer extending from the junction between the first semiconductor region and the second semiconductor region to the first semiconductor region. The semiconductor device according to claim 1, wherein the semiconductor device is provided.
The lower limit of the crystal defect region and the interface between the first semiconductor region and the fifth semiconductor region are larger than the upper limit of the crystal defect region and the distance to the interface between the first semiconductor region and the second semiconductor region. The semiconductor device according to claim 1, wherein the distance is short.
The semiconductor device according to claim 1, wherein crystal defects increase in the crystal defect region downward.
5. A plurality of crystal defect regions that are spaced apart from each other in the thickness direction of the first semiconductor region are provided in a range from an upper limit to a lower limit of the crystal defect region. The semiconductor device according to item.
In the range from the upper limit to the lower limit of the crystal defect region, a plurality of the crystal defect regions are provided,
The crystal defect region on the upper side is a crystal defect region generated by introducing gold or platinum,
The semiconductor device according to claim 1, wherein the lower crystal defect region is a crystal defect region caused by ion irradiation.

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