JP2018050057A - Imaging element, imaging device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform image processing at high speed.SOLUTION: An imaging element according to an embodiment comprises: first and second pixel cells; second wiring branched from first wiring at a first branch point and electrically connected with the first pixel cell; third wiring branched from the first wiring at a second branch point and electrically connected with the second pixel cell; a first variable resistive element provided on the second wiring; a second variable resistive element provided on the third wiring; a third variable resistive element provided on the first wiring, between the first branch point and the second branch point; a plurality of first memory elements connected in parallel to the first branch point; and a plurality of second memory elements connected in parallel to the second branch point. Each of the first to third variable resistive elements may include a plurality of resistive elements connected in parallel to each other.SELECTED DRAWING: Figure 15

Description

  Embodiments described herein relate generally to an imaging element, an imaging apparatus, and a semiconductor device.

  Conventionally, in image recognition technology, as basic processing, image smoothing processing, difference processing for images with different smoothness, minimum / maximum value extraction (feature point extraction) processing after difference processing, light intensity gradient near the feature point Image processing such as feature amount calculation processing for calculating information and the like is performed.

  As a technique for performing these processes at high speed, there is a silicon retinal chip technique that mimics the retinal nerve of a living body. In this technique, pixels formed on a semiconductor substrate are connected via a variable resistance circuit composed of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and smoothing processing between the pixels is performed at high speed. However, in the silicon retina chip, the smoothing process can be speeded up. However, since the variable resistance circuit is provided in the pixel region of the semiconductor substrate, the pixel area is increased and the number of pixels is reduced as compared with a normal image sensor. There is a case.

Keisuke Inoue, Seiji Kameda, Tetsuya Yagi: “Real-time parallel image processing using silicon retina and FPGA”, Journal of Information Media Society, Vol. 61, no. 3 (2007)

  An object of the following embodiments is to provide an imaging device, an imaging device, and a semiconductor device that enable high-speed image processing. In addition, at least a part of the following embodiments aims to enable high-speed image smoothing without increasing the pixel area as compared with the case of using the silicon retina chip technology. To do.

  The imaging device according to the embodiment is electrically connected to the first wiring via a first wiring and a second wiring that branches from the first wiring at a first branch point. The first pixel cell having a light receiving element and a first scanning circuit, and the first wiring through a third wiring that branches from the first wiring at a second branch point different from the first branch point. A second pixel cell electrically connected to the second wiring and having a second light receiving element and a second scanning circuit; and on the second wiring, the first branch point and the first A first variable resistance element electrically connected to the pixel cell; and electrically connected to the third wiring and between the second branch point and the second pixel cell. An electrically connected second variable resistance element and the first wiring on the first wiring and between the first branch point and the second branch point. A plurality of first memory elements connected in parallel to the first branch point and storing the potential of the first branch point according to different trigger signals, A plurality of second memory elements that are connected in parallel to the second branch point and store the potential of the second branch point according to different trigger signals, respectively, and the first to third variable resistors Each element may include a plurality of resistance elements connected in parallel to each other.

FIG. 1 is an overhead view showing a schematic configuration of the imaging apparatus according to the first embodiment. FIG. 2 is a circuit diagram illustrating a schematic configuration example of the image sensor according to the first embodiment. FIG. 3 is a circuit diagram illustrating a schematic configuration example of an imaging element using a MOS transistor as a variable resistance element in the first embodiment. FIG. 4 is a diagram illustrating a cross-sectional structure example of the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment (No. 1). FIG. 6 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment (No. 2). FIG. 7 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment (No. 3). FIG. 8 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment (No. 4). FIG. 9 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment (No. 5). FIG. 10 is a circuit diagram illustrating a schematic configuration example of the imaging element according to the second embodiment. FIG. 11 is a diagram illustrating a cross-sectional structure example of the semiconductor device according to the second embodiment. FIG. 12 is a circuit diagram illustrating a schematic configuration example of the imaging element according to the third embodiment. FIG. 13 is a diagram illustrating an example of a cross-sectional structure of the semiconductor device according to the third embodiment. FIG. 14 is a diagram illustrating a cross-sectional structure example of the semiconductor device according to the fourth embodiment. FIG. 15 is a circuit diagram illustrating a schematic configuration example of an imaging element according to the fifth embodiment. FIG. 16 is a circuit diagram illustrating a first example of the memory element according to Embodiment 5. FIG. 17 is a cross-sectional view showing a structural example of the memory element shown in FIG. FIG. 18 is a circuit diagram illustrating a second example of the memory element according to Embodiment 5. FIG. 19 is a cross-sectional view showing a structural example of the memory element shown in FIG. FIG. 20 is a circuit diagram illustrating a schematic configuration example of an image sensor according to the sixth embodiment. FIG. 21 is a circuit block diagram illustrating a first example of an imaging apparatus according to the seventh embodiment. FIG. 22 is a circuit block diagram illustrating a second example of the imaging apparatus according to the seventh embodiment. FIG. 23 is a circuit block diagram illustrating a third example of the imaging apparatus according to the seventh embodiment. FIG. 24 is a bird's-eye view showing a structural example of a CMOS image sensor chip according to the eighth embodiment. FIG. 25 is an overhead view showing a schematic configuration of an imaging apparatus according to the ninth embodiment. FIG. 26 is a circuit block diagram illustrating a schematic configuration of a CMOS image sensor as the imaging apparatus according to the ninth embodiment. FIG. 27 is a circuit diagram illustrating an example of a variable resistance element according to the ninth embodiment. FIG. 28 is a diagram illustrating an example of a cross-sectional structure of a semiconductor device for realizing the circuit configuration illustrated in FIG. FIG. 29 is a circuit diagram illustrating an example of a resistance element including the resistance change memory according to the tenth embodiment. FIG. 30 is a circuit diagram illustrating another example of the resistance element including the resistance change memory according to the tenth embodiment. FIG. 31 is a circuit diagram illustrating still another example of the resistance element including the resistance change memory according to the tenth embodiment. FIG. 32 is a circuit block diagram illustrating a schematic configuration of a CMOS image sensor as the imaging apparatus according to the tenth embodiment. FIG. 33 is a diagram illustrating a structure example of a resistance element according to the tenth embodiment. FIG. 34 is a diagram illustrating another structure example of the resistance element according to the tenth embodiment. FIG. 35 is a diagram illustrating still another structural example of the resistance element according to the tenth embodiment. FIG. 36 is a diagram illustrating a structure example of a three-terminal variable resistance memory according to the eleventh embodiment. FIG. 37 is a diagram illustrating another structure example of the three-terminal variable resistance memory according to the eleventh embodiment. FIG. 38 is a diagram illustrating still another example of the structure of the three-terminal variable resistance memory according to the eleventh embodiment. FIG. 39 is a diagram illustrating still another example of the structure of the three-terminal variable resistance memory according to the eleventh embodiment. FIG. 40 is a circuit diagram illustrating an example of a variable resistance element configured using the three-terminal resistance change memory according to the eleventh embodiment. FIG. 41 is a circuit diagram illustrating a configuration example of a resistance element according to the thirteenth embodiment. FIG. 42 is a diagram illustrating the relationship between the write bias voltage and the number of sets according to the thirteenth embodiment. FIG. 43 is a circuit diagram illustrating a configuration example of a resistance element according to Modification 1 of Embodiment 13. FIG. 44 is a layout diagram illustrating a configuration example of a resistance element according to Modification 1 of Embodiment 13. FIG. 45 is a circuit diagram illustrating a configuration example of a resistance element according to Modification 2 of Embodiment 13. FIG. 46 is a diagram illustrating a structure example of a resistance element according to the second modification of the thirteenth embodiment.

  Hereinafter, an imaging device, an imaging apparatus, and a semiconductor device according to exemplary embodiments will be described in detail with reference to the accompanying drawings.

(Embodiment 1)
First, an imaging device, an imaging device, and a semiconductor device according to Embodiment 1 will be described in detail with reference to the drawings. FIG. 1 is an overhead view showing a schematic configuration of the imaging apparatus according to the first embodiment. As shown in FIG. 1, the imaging apparatus 1 includes a pixel array 11 as an imaging element, a register 12, a timing generation circuit 13, an ADC (Analog-to-Digital Converter) 14, and a DSP (Digital Signal Processor) 15. And an I / O (Input / Output) 16.

  The pixel array 11 is an image sensor in which a plurality of pixels (hereinafter referred to as pixel cells) each including a light receiving element are two-dimensionally arranged. FIG. 2 is a circuit diagram illustrating a schematic configuration example of the image sensor according to the first embodiment. 2 illustrates a configuration in which two pixel cells 11A and 11B are connected to one first wiring L2, but the pixel array 11 in FIG. 1 includes a plurality of pixel cells in each of a plurality of wirings. It may have a connected configuration.

  As shown in FIG. 2, the pixel cell 11A includes a light receiving portion 11a and a scanning circuit 11b. The light receiving unit 11a includes a photodiode PD1 and a transfer gate TG1. Scan circuit 11b includes a reset transistor Q1 and an amplifier circuit 11c. The amplifier circuit 11c is a source follower circuit composed of two MOSFETs (hereinafter referred to as MOS transistors) Q2 and Q3 connected to each other. Of the two MOS transistors Q2 and Q3, the MOS transistor Q2 is an amplifier transistor that amplifies a potential corresponding to the charge accumulated in the light receiving portion 11a with a predetermined gain, and the MOS transistor Q3 selects a pixel cell to be read. Switching transistor. Hereinafter, the MOS transistor Q2 is referred to as an amplifier transistor Q2, and the MOS transistor Q3 is referred to as a switching transistor Q3. The MOS transistor Q3 may be connected to the source side of the MOS transistor Q2, which is an amplifier transistor, or may be omitted from the pixel portion including the light receiving portion 11a and the scanning circuit 11b.

  The cathode of the photodiode PD1 in the light receiving unit 11a is connected to the gate of the amplifier transistor Q2 in the amplifier circuit 11c of the scanning circuit 11b via the transfer gate TG1. The photodiode PD1 receives incident light and converts it into electrons. The transfer gate TG1 transfers electrons generated in the photodiode PD1 to a charge accumulation region called floating diffusion (FD). As a result, charges corresponding to the intensity of incident light are accumulated in the charge accumulation region.

  The power supply line Vdd is also connected to the gate of the amplifier transistor Q2 via the reset transistor Q1. A reset signal Reset for resetting the charges accumulated in the charge accumulation region is applied to the gate of the reset transistor Q1. That is, the reset transistor Q1 has a role of resetting the potential of the charge accumulation region before reading a signal from the light receiving unit 11a (pixel).

  An address signal Address for controlling charge reading from the light receiving portion 11a is input to the gate of the switching transistor Q3 in the amplifier circuit 11c. The source of the amplifier transistor Q2 in the amplifier circuit 11c is connected to the node N1 of the first wiring L2 via the second wiring L1 including the variable resistance element VR1. Therefore, a gate potential corresponding to the charge accumulated in the charge accumulation region via the transfer gate TG1 is generated at the gate of the amplifier transistor Q2. Since the amplifier circuit 11c is the source follower circuit 11c, the gate potential generated at the gate of the amplifier transistor Q2 is converted into the source potential of the amplifier transistor Q2. As a result, the source potential of the amplifier transistor Q2 becomes a potential corresponding to the amount of light received by the photodiode PD1. This source potential is applied to the node N1 via the variable resistance element VR1 on the second wiring L1.

  The configuration of the pixel cell 11A as described above is the same for the pixel cell 11B and other pixel cells (not shown). Therefore, for example, in the case of the pixel cell 11B, when the address signal Address is applied to the gate of the switching transistor Q3 while the selection signal is applied to the transfer gate TG1, the amplifier corresponding to the charge accumulated in the charge accumulation region The gate potential of the transistor Q2 is converted into the source potential and applied to the node N2 via the variable resistance element VR1 on the second wiring L1.

  In addition, a variable resistance element VR2 is provided on the first wiring L2 between adjacent pixel cells (for example, the pixel cells 11A and 11B) among the plurality of pixel cells connected to the same first wiring L2. For example, the variable resistance element VR2 is provided between the nodes N1 and N2 where the adjacent pixel cells 11A and 11B are connected to the first wiring L2. Therefore, the voltage value (light quantity value) output from each node N1 and N2 to the peripheral circuit is the resistance value R1 of the variable resistance element VR1 provided on each second wiring L1 and the variable resistance on the first wiring L2. The value is smoothed according to the ratio R1 / R2 with the resistance value R2 of the element VR2. Note that smoothing means smoothing an edge in an image by reducing a difference in luminance value between adjacent pixels.

  If the ratio R1 / R2 is large, the smoothness is large, and if R1 / R2 is small, the smoothness is small. For example, when the resistance value R2 is very large with respect to the resistance value R1, voltage values (light quantity values) output from the nodes N1 and N2 are hardly smoothed, so that substantially raw image data is converted into a pixel array. 11 is read out. On the other hand, when the resistance value R2 is made smaller than the resistance value R1, the voltage values (light quantity values) output from the nodes N1 and N2 are relatively strongly smoothed. Read from array 11. In this way, it is possible to generate image data with different smoothness by changing the ratio R1 / R2. Thereby, analog smoothing of pixels and creation of a Gaussian pyramid composed of image information having a plurality of different smoothness levels can be performed while suppressing an increase in pixel area in the pixel array 11 as much as possible. Further, by performing differential processing of images with different smoothness, feature point extraction, and feature amount extraction in the peripheral circuit unit, it is possible to perform basic processing necessary for image recognition processing at high speed. For example, by performing difference processing on two pieces of image data read from the pixel array 11 as image data with different smoothness, a so-called edge image in which edges in the image are extracted can be generated at high speed. is there. Note that difference processing, feature point extraction processing, and feature amount extraction processing for images with different smoothness levels are performed not only by peripheral circuits but also by application software executed in an information processing apparatus such as a CPU (Central Processing Unit). May be.

  In FIG. 2, pixel cells adjacent in the one-dimensional direction are connected via variable resistance element VR2. However, pixel cells adjacent in the vertical and horizontal directions may be connected via variable resistance element VR2. Good. When the variable resistance element VR <b> 2 is interposed between pixel cells adjacent in the one-dimensional direction, one-dimensionally smoothed image data can be extracted from the pixel array 11. On the other hand, when the variable resistance element VR2 is interposed between pixel cells adjacent vertically and horizontally, two-dimensionally smoothed image data can be extracted from the pixel array 11.

  For example, MOS transistors can be used for the variable resistance elements VR1 and VR2. However, the present invention is not limited to the MOS transistor, and can be modified in any manner as long as it is a resistance element capable of changing the resistance value. For example, a two-terminal variable resistance element such as ReRAM, MRAM, PRAM, ion memory, amorphous silicon memory, or polysilicon memory can be used as at least one of the variable resistance elements VR1 and VR2. Further, instead of each of the variable resistance elements VR1 and VR2, a variable resistance circuit including a plurality of transistors may be provided in the wiring layer 11L. Further, it is possible to change the resistance value by switching a plurality of resistance element arrays having different resistance values.

  FIG. 3 is a circuit diagram showing a schematic configuration example of an imaging element in which a MOS transistor is used as a variable resistance element. As shown in FIG. 3, MOS transistors QR1 and QR2 used as variable resistance elements VR1 and VR2 are provided in wiring layer 11L that connects adjacent pixels (for example, between pixel cells 11A and 11B). FIG. 4 shows an example of a cross-sectional structure of a semiconductor device for realizing the circuit configuration shown in FIG. In FIG. 4, for convenience of explanation, the reset transistor Q1 and the switching transistor Q3 in the amplifier circuit 11c are omitted. 4 illustrates a back-illuminated semiconductor device, the present invention is not limited to this, and a front-illuminated semiconductor device may be used.

  As shown in the semiconductor device of FIG. 4, in one pixel cell 11A, a photodiode PD1, a transfer gate TG1, and an amplifier transistor Q2 arranged in a matrix are formed on the first surface (this is the upper surface). A semiconductor substrate 113 is included. The color filter 112 is bonded to the second surface of the semiconductor substrate 113 (this is the back surface). In addition, a micro lens 111 aligned with the photodiode PD1 is provided on the surface of the color filter 112 opposite to the bonding surface with the semiconductor substrate 113. Note that light having a specific wavelength corresponding to the color filter 112 can pass from the microlens 111 to the photodiode PD1. For example, a through hole may be formed in the semiconductor substrate 113 between the microlens 111 and the photodiode PD1, or a transparent substrate may be used as the semiconductor substrate 113.

  A contact layer 114 is formed on the upper surface of the semiconductor substrate 113. In the contact layer 114, a via for electrically extracting the source of the amplifier transistor Q2 is formed. A pad for facilitating alignment with the upper layer may be formed on the upper portion of the via. Further, a diffusion preventing film 115 for preventing atomic diffusion between layers is formed on the contact layer 114.

  On the diffusion prevention film 115, a wiring layer 11L composed of interlayer insulating films 116 and 118 and a passivation 120 is formed. Specifically, interlayer insulating films 116 and 118 are formed on diffusion preventing film 115. A gate insulating film 117 is formed between the interlayer insulating films 116 and 118, and a MOS transistor QR1 (see FIG. 3) is formed with the gate insulating film 117 interposed therebetween. The diffusion prevention film 115, the interlayer insulating film 116, the gate insulating film 117, and the interlayer insulating film 118 are provided with vias that are electrically drawn up to the top of the contact layer 114 as a part of the second wiring L1, in the MOS transistor QR1. Vias and wiring layers are formed for electrical connection to the drains.

  The source of the MOS transistor QR1 is electrically drawn up to the top of the interlayer insulating film 118 through a via formed in the interlayer insulating film 118. A pad for facilitating alignment with the upper layer may be formed on the upper portion of the via. A gate insulating film 119 and a passivation 120 are formed on the interlayer insulating film 118.

  The first wiring L2 in FIG. 3 is formed in the passivation 120, and the MOS transistor QR2 is formed with the gate insulating film 119 interposed therebetween. The source of the MOS transistor QR1, which is electrically drawn up to the top of the interlayer insulating film 118, is electrically connected to the first wiring L2 through the gate insulating film 119 and the passivation 120 through a via formed as part of the second wiring L2. Connected to. Further, the node N1 of the first wiring L2 is electrically drawn out to the surface of the passivation 120 through a via formed in the passivation 120. A pad for facilitating alignment at the time of bonding to another substrate (for example, a circuit substrate) may be formed on the via.

The semiconductor layer used for the MOS transistors QR1 and QR2 may be an oxide semiconductor such as InGaZnO or ZnO, or may be Poly-Si, amorphous Si, SiGe, or the like. The semiconductor layer may be a laminated film composed of a plurality of different types of films. As the laminated film, for example, InGaZnO / Al ₂ O ₃ / InGaZnO / Al ₂ O ₃ can be used. For the vias and wiring layers formed in the interlayer insulating films 116 and 118 and the passivation 120, various conductive layers such as a metal wiring or a semiconductor layer doped with impurities can be used.

  As described above, by providing the MOS transistors QR1 and QR2 as the variable resistance elements VR1 and VR2 in the wiring layer 11L formed on the semiconductor substrate 113, the smoothing process of the image data is performed without increasing the pixel area. Can be performed at high speed.

  Note that the cross-sectional structure shown in FIG. 4 is merely an example, and the structures of the MOS transistors QR1 and QR2 formed in the wiring layer 11L, for example, are not limited to this. For example, MOS transistors QR1 and QR2 may have a double gate structure in which gate electrodes are provided above and below a semiconductor layer. Further, the cross-sectional arrangement of each wiring is not limited to the position shown in FIG. For example, the gate width direction of the MOS transistor QR1 located in the lower layer and the gate width direction of the MOS transistor QR2 located in the upper layer may be arranged to be orthogonal to each other. Furthermore, the arrangement of the transistors (including the photodiode PD1) formed on the semiconductor substrate 113 is not limited to the arrangement shown in FIG.

  Next, a method for manufacturing a semiconductor device according to the first embodiment will be described in detail with reference to the drawings. 5 to 9 are process cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 4, for example. 5 to 9 show an example of a method for manufacturing the semiconductor device shown in FIG. 4 and are not limited to these processes.

  First, as shown in FIG. 5, similarly to the conventional CMOS image sensor, the element isolation layer 131 is formed on the upper surface of the semiconductor substrate 113, and the gate insulating film 136 and the gate electrode 135 are sequentially formed. Subsequently, an n-type dopant and a p-type dopant are implanted into a predetermined region on the upper surface of the semiconductor substrate 113 by ion implantation using a mask or self-alignment, whereby an n + type doped region 132 and a p + type doped region 133 are implanted. And form. Subsequently, a contact layer 114a, which is an insulating layer, is formed on the semiconductor substrate 113, and a via 137 for electrically extracting the source of the MOS transistor Q2 is formed in the contact layer 114a. Subsequently, a pad 138 is formed on the contact layer 114a in which the via 137 is formed, and a contact layer 114b is formed on the contact layer 114a in which the pad 138 is formed, and then the upper surface of the pad 138 is exposed by, for example, CMP. . Thereafter, a diffusion prevention film 115 is formed on the planarized contact layer 114b.

  Next, as shown in FIG. 6, an interlayer insulating film 116 is formed on the diffusion prevention film 115, and a via 139 is formed in the interlayer insulating film 116 to electrically draw the pad 138. Next, the pad 140 is formed on the via 139 and the gate electrode 141 of the MOS transistor QR1 is formed. For pad 140 and gate electrode 141, for example, a metal such as copper (Cu) may be used. Subsequently, a gate insulating film 117 is formed on the gate electrode 141 by a plasma CVD method or the like.

  Next, as shown in FIG. 7, a semiconductor layer 142a is formed on the gate insulating film 117 and selectively removed by etching. At this time, in the case where the semiconductor layer 142a is an oxide semiconductor such as InGaZnO, it can be formed by, for example, a sputtering method. When the semiconductor layer 142a is polysilicon, amorphous silicon, or the like, it can be formed by, for example, a plasma CVD method.

  Next, as shown in FIG. 8, a mask pattern 142b is formed on the semiconductor layer 142a and a dopant is implanted into the semiconductor layer 142a by an ion implantation method, thereby forming a channel region 141 and a source in the semiconductor layer 142a. Region 143 and drain region 143 are formed. At this time, in the case where the semiconductor layer 142a is an oxide semiconductor, the source region 143 and the source region 143 are formed by a method of forming an oxygen defect region using a reducing plasma such as hydrogen plasma or a method of introducing nitrogen using a nitrogen-containing plasma such as ammonia. A drain region 143 can be formed. In the case where the semiconductor layer 142a is Poly-Si, amorphous Si, or SiGe, the source region 143 and the drain region 143 can be formed by impurity implantation such as phosphorus, arsenic, or boron.

  Next, as shown in FIG. 9, after removing the mask pattern 142b, vias 144 and 145 and a wiring layer 146 are formed so as to overlap the source region 143, the drain region 143, and the pad 140, respectively.

  Next, an upper layer MOS transistor QR2 is formed by performing the same steps as those in FIGS. 6 to 9 described above, and these MOS transistors QR2 are connected by a wiring layer L2 such as a metal layer, so that FIG. A semiconductor device having a cross-sectional structure as shown in FIG.

  As described above, according to the first embodiment, since the adjacent pixels (for example, the pixel cells 11A and 11B) are connected by the variable resistance element VR2, the smoothing process of the image data without increasing the pixel area is performed. Can be performed at high speed by analog processing.

  In addition, when the silicon retina chip is used, there is a possibility that the pixel layout needs to be changed exclusively. However, since the first embodiment has a configuration in which the variable resistance element VR2 is formed in the wiring layer 11L. An image sensor having a basic processing function necessary for image recognition can be realized without substantially changing the pixel layout of the pixel array 11.

  Image processing such as difference processing for images with different smoothness, minimum / maximum value extraction (feature point extraction) processing after difference processing, feature amount calculation processing for calculating light amount value gradient information in the vicinity of feature points, etc. Since it may be performed outside the peripheral circuit unit or the imaging device, detailed description is omitted here.

(Embodiment 2)
Next, an imaging device, an imaging apparatus, and a semiconductor device according to Embodiment 2 will be described in detail with reference to the drawings.

  As described above, the smoothness of the image data read from the pixel array 11 is determined by the resistance ratio R1 / R2 of the variable resistance elements VR1 and VR2. The resistance ratio R1 / R2 can be adjusted by changing at least one of the resistance values R1 and R2. In other words, one of the resistance values R1 and R2 can be a fixed value. Therefore, in the second embodiment, a non-variable resistance element having a non-variable resistance value is used instead of the variable resistance element VR1 on the second wiring L1. However, the present invention is not limited to this, and a non-variable resistive element may be used instead of the variable resistive element VR2 on the first wiring L2.

  FIG. 10 is a circuit diagram illustrating a schematic configuration example of the imaging element according to the second embodiment. As is clear from comparison between FIG. 10 and FIG. 3, in the second embodiment, the MOS transistor QR1 on the second wiring L1 connecting the pixel cells 11A and 11B and the first wiring L2 is replaced with a non-variable resistive element RR1. It has been. Other configurations may be the same as those of the image sensor shown in FIG.

  FIG. 11 shows an example of a cross-sectional structure of a semiconductor device for realizing the circuit configuration shown in FIG. Also in FIG. 11, the reset transistor Q1 and the switching transistor Q3 in the amplifier circuit 11c are omitted as in FIG. In FIG. 11, a back-illuminated semiconductor device is shown. However, the present invention is not limited to this, and a front-illuminated semiconductor device may be used.

  As is clear from comparison between FIG. 11 and FIG. 4, in the second embodiment, the lower gate insulating film 117 in the wiring layer 11L is omitted, and a non-variable resistor is provided on the interlayer insulating film 116 instead of the MOS transistor QR1. The element RR1 is formed. Non-variable resistance element RR1 may be, for example, a semiconductor layer. This semiconductor layer may be an oxide semiconductor such as InGaZnO, or may be Poly-Si, amorphous Si, SiGe, or the like. Further, an oxygen defect region or an impurity region may be provided in the entire semiconductor layer.

  As described above, according to the second embodiment, similarly to the above-described embodiments, it is possible to perform smoothing processing of image data at high speed by analog processing without increasing the pixel area. Even when a silicon retina chip is used, an image sensor having a basic processing function necessary for image recognition can be realized without substantially changing the pixel layout of the pixel array 11.

  Furthermore, in the second embodiment, since a non-variable resistive element having a simple structure is used for either of the variable resistive elements VR1 and VR2, the number of manufacturing steps can be reduced.

  The configurations, manufacturing methods, and effects of other imaging elements, imaging devices, and semiconductor devices are the same as those in the above-described embodiment, and thus detailed description thereof is omitted here.

(Embodiment 3)
Next, an imaging device, an imaging apparatus, and a semiconductor device according to Embodiment 3 will be described in detail with reference to the drawings.

  FIG. 12 is a circuit diagram illustrating a schematic configuration example of the imaging element according to the third embodiment. As is clear from a comparison between FIG. 12 and FIG. 3, the third embodiment has a circuit configuration similar to that of the first embodiment. However, in the third embodiment, the amplifier transistor Q2 in the amplifier circuit 11c is provided in the wiring layer 31L corresponding to the wiring layer 11L.

  FIG. 13 shows an example of a cross-sectional structure of a semiconductor device for realizing the circuit configuration shown in FIG. In FIG. 13, as in FIG. 4, the reset transistor Q1 and the switching transistor Q3 in the amplifier circuit 11c are omitted. Although FIG. 13 illustrates a back-illuminated semiconductor device, the present invention is not limited to this, and a front-illuminated semiconductor device may be used.

  As is clear from comparison between FIG. 13 and FIG. 4, in the third embodiment, a gate insulating film 317 and an interlayer insulating film 318 are provided between the interlayer insulating film 116 and the gate insulating film 117. An amplifier transistor Q2 is formed across 317. In the contact layer 114, the diffusion preventing film 115, the interlayer insulating film 116, the gate insulating film 317, and the interlayer insulating film 318, a connection wiring L3 that connects the transfer gate TG1 and the amplifier transistor Q2 is formed. Other structures may be the same as those of the semiconductor device shown in FIG.

  As described above, according to the third embodiment, similarly to the above-described embodiment, it is possible to perform smoothing processing of image data at high speed by analog processing without increasing the pixel area. Even when a silicon retina chip is used, an image sensor having a basic processing function necessary for image recognition can be realized without substantially changing the pixel layout of the pixel array 11.

  Furthermore, in the third embodiment, since the amplifier transistor Q2 is provided in the wiring layer 31L, the pixel area can be reduced. Alternatively, the light receiving area of the photodiode PD1 can be increased while maintaining the pixel area, and the pixel sensitivity and the number of saturated electrons can be improved.

  Note that the configurations, manufacturing methods, and effects of other imaging elements, imaging devices, and semiconductor devices are the same as those in the above-described embodiment, and thus detailed description thereof is omitted here.

(Embodiment 4)
Next, an imaging device, an imaging apparatus, and a semiconductor device according to Embodiment 4 will be described in detail with reference to the drawings.

  In the first embodiment described above, the MOS transistors Q2 and Q3 are used as the variable resistance elements VR1 and VR2. However, the present invention is not limited to this. For example, as the variable resistance elements VR1 and VR2, a ReRAM (Resistance Random Access Memory), a PRAM (Phase change RAM), an MRAM (Magnetic Resistive RAM), amorphous Si, Poly-Si, or a stacked structure of these materials and metals is used. Is also possible.

  FIG. 14 shows an example of a cross-sectional structure of a semiconductor device for realizing the circuit configuration of the image sensor according to the fourth embodiment. In FIG. 14, as in FIG. 4, the reset transistor Q1 and the switching transistor Q3 in the amplifier circuit 11c are omitted. 14 illustrates a back-illuminated semiconductor device, the present invention is not limited to this, and a front-illuminated semiconductor device may be used.

  As apparent from comparison between FIG. 14 and FIG. 4, in the second embodiment, the gate insulating films 117 and 119 in the wiring layer 41L corresponding to the wiring layer 11L are omitted, and the variable resistance elements VR1 and VR2 are provided in the interlayer insulating film 118. Is formed.

  As described above, according to the fourth embodiment, similarly to the above-described embodiment, it is possible to perform smoothing processing of image data at high speed by analog processing without increasing the pixel area. Even when a silicon retina chip is used, an image sensor having a basic processing function necessary for image recognition can be realized without substantially changing the pixel layout of the pixel array 11.

  The configurations, manufacturing methods, and effects of other imaging elements, imaging devices, and semiconductor devices are the same as those in the above-described embodiment, and thus detailed description thereof is omitted here.

(Embodiment 5)
Next, an imaging device, an imaging apparatus, and a semiconductor device according to Embodiment 5 will be described in detail with reference to the drawings.

  FIG. 15 is a circuit diagram illustrating a schematic configuration example of an imaging element according to the fifth embodiment. As is clear when FIG. 15 is compared with FIG. 3, the pixel cells 11 </ b> A and 11 </ b> B according to the fifth embodiment may have a circuit configuration similar to that of the first embodiment. However, in the fifth embodiment, one or more (five in FIG. 15) memory elements M1 to M5 are connected to the first wiring L5 connected to the nodes N1 and N2 via the second wiring L6, respectively. . The configuration of the pixel cell is not limited to the circuit configuration according to the first embodiment illustrated in FIG. 3, and may be a circuit configuration according to another embodiment.

  Pixels read out from the pixel cell 11A while being smoothed with different resistance ratios R1 / R2 (that is, with different smoothness) from each of the memory elements M1 to M5 connected to a certain node (referred to as a node N1). Information (for example, pixel values) is stored as analog data. For example, the pixel information smoothed with the lowest smoothness is stored in the memory element M1, and the pixel information smoothed with a higher smoothness than the pixel information stored in the memory element M1 is stored in the memory element M2. The memory element M3 stores pixel information smoothed with higher smoothness than the pixel information stored in the memory element M2, and the memory element M4 stores higher smoothness than the pixel information stored in the memory element M3. Pixel information smoothed at a degree is stored, and pixel information smoothed at the highest degree of smoothness is stored in the memory element M5. Accordingly, the image data smoothed with different smoothness can be read by sequentially reading the pixel information sequentially from the memory elements M1 to M5 connected to all the nodes. However, the correspondence between the smoothness and the memory elements M1 to M5 is not limited to the order described above.

  Each of the memory elements M1 to M5 has a configuration in which, for example, a MOS transistor Q4 and a capacitor C1 are connected in series. However, the present invention is not limited to this. For example, a variable resistance memory such as ReRAM or a SONOS (Silicon / Oxide / Nitride / Oxide / Silicon) memory may be used.

  Subsequently, the operation of the image sensor according to the fifth embodiment will be described. Charge corresponding to the light amount value of incident light at a certain time t is transferred from the photodiode PD1 to the charge accumulation region, and as a result, the source potential of the amplifier transistor Q2 becomes a value corresponding to the light amount value. Therefore, at time t, R1 / R2 << 1, and image information with very low smoothness (substantially no smoothing) is stored in the first-stage memory element M1. Here, assuming that the frame rate is about 30 to 60 FPS (Frame Par Second), each frame interval is 10 msec or more. Therefore, by changing the resistance values of the variable resistance elements VR1 and VR2 between the frames, image information having different smoothness is stored in the memory elements M2 to M5 in the second and subsequent stages. This makes it possible to acquire a large number of pixel information having different smoothness levels in a short time. Note that a memory trigger signal for writing pixel information from the photodiode PD1 is input to the gate of the MOS transistor Q4 in each of the memory elements M1 to M5 at different timings according to the respective writing timings.

  Note that the pixel value with the reset transistor Q1 turned on may be stored in any of the memory elements M1 to M5. In that case, it is possible to remove the low frequency noise component of the image data by executing the difference process based on the image data acquired in the reset state.

  16 to 19 show specific examples of the memory elements M1 to M5 according to the fifth embodiment. FIG. 16 is a circuit diagram illustrating a first example of the memory element, and FIG. 17 is a cross-sectional view illustrating a structure example of the memory element illustrated in FIG. FIG. 18 is a circuit diagram showing a second example of the memory element, and FIG. 19 is a cross-sectional view showing a structure example of the memory element shown in FIG. Note that the memory element M10 illustrated in FIGS. 16 to 19 may have a structure common to the memory elements M1 to M5.

  As shown in FIGS. 16 and 17, the structure of the MOS transistor Q4 in the memory element M10 according to the first example is the same as that of the wiring layer transistors such as the MOS transistors QR1 and QR2 described above. In the capacitor C1, one electrode 151 may be formed of a semiconductor layer, and the other electrode 152 may be formed of a metal wiring. Further, in the cross-sectional structure of the memory element M10 at each stage, for example, an interlayer insulating film 121, a gate insulating film 122, and an interlayer insulating film 123 are sequentially stacked on a passivation 120 (or an interlayer insulating film 123 described later), The MOS transistor Q4 and the capacitor C1 are formed so as to sandwich the gate insulating film 122 therebetween. Therefore, when the memory element M10 has five stages (memory elements M1 to M5), the semiconductor device has a cross-sectional structure in which the structure of the wiring layer 51L in FIG. 17 is repeated five times in the stacking direction. Note that it is preferable to use a transistor having a small off-leakage current as the MOS transistor Q4 in order to improve memory retention characteristics. For example, a MOS transistor using InGaZnO may be used as the semiconductor layer.

  In the first example, one electrode 151 of the capacitor C1 is a semiconductor layer, but the present invention is not limited to this. For example, like the memory element M11 according to the second example shown in FIGS. 18 and 19, both electrodes 161 and 162 of the capacitor C2 may be metal wiring. In this case as well, when the memory element M11 has five stages (memory elements M1 to M5), the semiconductor device has a cross-sectional structure in which the structure of the wiring layer 51L in FIG. 19 is repeated five times in the stacking direction.

  In the first example described above, the gate insulating film 122 is used between the electrodes 151 and 152 of the capacitor C1, and the electrode 161 and 162 of the capacitor C2 is used as a part of the interlayer insulating film 123 in the second example. It is not something that can be done. For example, the capacitance of the capacitor C1 or C2 may be adjusted (increased or decreased) by using a dielectric film or the like between the electrodes 151 and 152.

  As described above, according to the fifth embodiment, similarly to the above-described embodiments, it is possible to perform smoothing processing of image data at high speed by analog processing without increasing the pixel area. Even when a silicon retina chip is used, an image sensor having a basic processing function necessary for image recognition can be realized without substantially changing the pixel layout of the pixel array 11.

  Furthermore, according to the fifth embodiment, the memory element is provided in the wiring layer, and the image data smoothed with different smoothness is stored in the memory array formed thereby, so that a large number of images with different smoothness can be stored in a short time. Can be obtained.

  The configurations, manufacturing methods, and effects of other imaging elements, imaging devices, and semiconductor devices are the same as those in the above-described embodiment, and thus detailed description thereof is omitted here.

(Embodiment 6)
Next, an imaging device, an imaging apparatus, and a semiconductor device according to Embodiment 6 will be described in detail with reference to the drawings.

  In the fifth embodiment described above, a memory trigger signal for writing pixel information is input to the gate of the MOS transistor Q4 at different timings according to the writing timing to each of the memory elements M1 to M5. However, as described above, the frame rate for determining the timing of writing pixel information into the memory elements M1 to M5 is constant. Therefore, the sixth embodiment is configured such that writing to each of the memory elements M1 to M5 is performed at different timings by delaying one memory trigger signal.

  FIG. 20 is a circuit diagram illustrating a schematic configuration example of an image sensor according to the sixth embodiment. As is clear from comparison between FIG. 20 and FIG. 15, in the sixth embodiment, a memory trigger signal is commonly input to the gates of the MOS transistors Q <b> 4 in the memory elements M <b> 1 to M <b> 5. However, in the wiring L7 through which the memory trigger signal propagates, a delay capacitor C11 for delaying the memory trigger signal at each stage is connected immediately before the gate of the MOS transistor Q4 in each of the memory elements M1 to M5. Thereby, since the memory trigger signal is delayed by a certain interval, the on / off operation of the MOS transistor Q4 in each of the memory elements M1 to M5 is deviated by a certain interval. Therefore, by controlling so that the resistance ratio R1 / R2 is changed in accordance with the delay interval, it is possible to store pixel information with different smoothness in the memory elements M1 to M5 by outputting one memory trigger signal. Become. Similarly, when reading out pixel information, it is possible to read out image information held in each of the memory elements M1 to M5 by outputting a memory trigger signal once.

  A buffer or the like can be used instead of the delay capacitor C11. However, the delay capacitor C11 is usually preferable because it is advantageous in terms of area.

  As described above, according to the sixth embodiment, similarly to the above-described embodiments, it is possible to perform smoothing processing of image data at high speed by analog processing without increasing the pixel area. Even when a silicon retina chip is used, an image sensor having a basic processing function necessary for image recognition can be realized without substantially changing the pixel layout of the pixel array 11.

  Furthermore, according to the sixth embodiment, as in the fifth embodiment, it is possible to acquire a large number of images with different smoothness in a short time. Furthermore, according to the sixth embodiment, writing / reading to / from each of the memory elements M1 to M5 can be performed with one output of the memory trigger signal.

  Note that the configurations, manufacturing methods, and effects of other imaging elements, imaging devices, and semiconductor devices are the same as those in the above-described embodiment, and thus detailed description thereof is omitted here.

(Embodiment 7)
Next, some examples of the image pickup apparatus including the image pickup device according to each embodiment described above will be described in detail with reference to the drawings.

First Example First, a case where pixel cells arranged in the horizontal direction are connected via a variable resistance element will be described as a first example. FIG. 21 is a circuit block diagram illustrating a schematic configuration of a CMOS image sensor as the imaging device according to the first example in the seventh embodiment. FIG. 21 shows the imaging apparatus 1 shown in FIG. 1 more specifically.

  As illustrated in FIG. 21, the imaging device 1 according to the first example includes a pixel array 11, an ADC 14, a peripheral circuit 17 including a DSP 15, an I / O 16, and a control unit 20.

  The pixel array 11 has a configuration in which a plurality of pixel cells 11A to 11N are two-dimensionally arranged. The pixel cells 11A to 11N are connected through variable resistance elements VR2 provided in the wiring layer 11L. In the example shown in FIG. 21, variable resistance elements VR2 are provided between the pixel cells 11A to 11N arranged in the row direction.

  The control unit 20 includes a row selection circuit (register) 12, a timing generation circuit 13, a bias generation circuit 23, a voltage control unit 24, and a control circuit 21. The control circuit 21 controls operations of the bias generation circuit 23, the voltage control unit 24, the row selection circuit 12, and the timing generation circuit 13. The row selection circuit 12 selects a row (horizontal line) of the pixel cells 11A to 11N to be read and controls reading of pixel signals from the plurality of pixel cells 11A to 11N in one horizontal line. The voltage control unit 24 controls the voltage of the vertical output signal line and also controls the gate voltage applied to the variable resistance element VR2 for smoothing. However, the gate voltage control for smoothing may be performed by the row selection circuit 12 or may be performed by a voltage control circuit provided exclusively for the variable resistance element VR2.

  The ADC 14 includes ADC blocks 14a to 14n for each vertical output signal line. Each of the ADC blocks 14a to 14n performs AD conversion on the voltage value (pixel signal) read from the corresponding vertical output signal line. The AD-converted pixel signal is subjected to digital signal processing, for example, by the DSP 15 in the peripheral circuit 17. For example, the DSP 15 executes difference processing of images with different smoothness, extraction processing of maximum and minimum values, and the like. The DSP 15 may also perform a feature amount extraction process such as gradient information of image values around feature points. Thereafter, the image signal processed in the peripheral circuit 17 is output from the I / O 16.

Second Example Next, a case where pixel cells arranged in a two-dimensional direction in the horizontal direction and the vertical direction are connected via variable resistance elements will be described as a second example. FIG. 22 is a circuit block diagram illustrating a schematic configuration of a CMOS image sensor as the imaging device according to the second example in the seventh embodiment. As shown in FIG. 22, the imaging device 2 according to the second example has the same configuration as the imaging device 1 shown in FIG. 21, but in the pixel array 11, pixel cells arranged in a two-dimensional direction in the horizontal direction and the vertical direction. 11A to 11N are connected via variable resistance elements VR2a or VR2b, respectively. The gate voltage applied to the variable resistance elements VR2a and VR2b for smoothing is controlled by the voltage control unit 24. However, the present invention is not limited to this, and may be performed by the row selection circuit 12 or may be performed by a voltage control circuit provided exclusively for each of the variable resistance elements VR2a and VR2b.

Third Example Next, a case where pixel cells arranged in the vertical direction are connected via variable resistance elements will be described as a third example. FIG. 23 is a circuit block diagram illustrating a schematic configuration of a CMOS image sensor serving as an imaging apparatus according to a third example of the seventh embodiment. As shown in FIG. 23, the imaging device 3 according to the third example has the same configuration as that of the imaging device 1 shown in FIG. It is connected via a resistance element VR2. The gate voltage applied to the variable resistance element VR2 for smoothing is controlled by the voltage control unit 24. However, the present invention is not limited to this, and may be performed by the row selection circuit 12 or may be performed by a voltage control circuit provided exclusively for the variable resistance element VR2.

(Embodiment 8)
Further, the structure of the CMOS image sensor chip exemplified in the above-described embodiment may have a stacked structure in which two chips 30A and 30B are bonded together as shown in FIG. At this time, the area of the peripheral circuit 17 can be increased by adopting a laminated structure of TSVs (Through Silicon Vias) 31 to 34 and a layout in which the peripheral circuit 17 is arranged on the pixel array 11. As a result, a large-scale peripheral circuit 17 can be mounted, and processing such as feature point extraction and feature amount extraction can be performed at higher speed.

(Embodiment 9)
Next, as the variable resistance element VR1, a drawing in the case of using the variable resistance element VR11 configured to change the resistance value by switching a multi-stage resistance element array having different resistance values in each stage will be described. The details will be described. In the following embodiments, the variable resistance element VR11 may be applied to the variable resistance element VR2, or the variable resistance element VR11 may be applied to both the variable resistance elements VR1 and VR2.

  FIG. 25 is an overhead view showing a schematic configuration of an imaging apparatus according to the ninth embodiment. In FIG. 25, the same components as those in FIG. 1 are denoted by the same reference numerals, and redundant description thereof is omitted. In the configuration shown in FIG. 25, the variable resistance element VR1 in FIG. 1 is replaced with the variable resistance element VR11, and is connected in series to the variable resistance element VR1 on each second wiring L1 branched from the first wiring L2. A switching transistor SW11 is provided. Each switching transistor SW11 is a transistor for switching the pixel cell 11A to be written / read. The switching transistor SW11 may be provided so as to be electrically interposed between the variable resistance element VR1 and the node N1 (N2), or may be electrically connected between the variable resistance element VR1 and the pixel cell 11A (11B). It may be provided so as to intervene.

  FIG. 26 is a circuit block diagram illustrating a schematic configuration of a CMOS image sensor as the imaging apparatus according to the ninth embodiment. As shown in FIG. 26, the imaging device 4 has a configuration similar to that of the imaging device 1 shown in FIG. 21, in which the variable resistance element VR1 is replaced with the variable resistance element VR11, and each variable resistance element VR11 and each pixel cell 11A to 11A. The switching transistor SW11 is connected to 11N. In FIG. 21, the variable resistance element VR1 is omitted. A switching signal supplied to the switching transistor SW11 is supplied from the row selection circuit 12, for example. However, the present invention is not limited to this, and a switching signal may be input from the voltage control unit 24 to the switching transistor SW11.

  FIG. 27 is a circuit diagram illustrating an example of a variable resistance element according to the ninth embodiment. As shown in FIG. 27, the variable resistance element VR11 includes a plurality of resistance elements R1 to R10 connected in parallel between the nodes n1 and n2 in FIG. 25 and a selection transistor T1 for selecting each of the resistance elements R1 to R10. To T10.

  Each of the resistance elements R1 to R10 is composed of a resistance element such as a polysilicon resistance, for example. When the resistance elements R1 to R10 are formed of the same layer of polysilicon resistance, the resistance value of each element is determined by the length in the wiring direction and the area of the cross section perpendicular to the wiring direction. However, the present invention is not limited to this, and the resistance values may be changed by changing the impurity concentration of each of the resistance elements R1 to R10 so that the shape is uniform. Further, when both of the variable resistance elements VR1 and VR2 are replaced with the variable resistance element VR11, the number of parallel stages may be different from each other.

  Each selection transistor T1 to T10 is connected in series to the corresponding resistance element R1 to R10, and a selection signal output from the selection circuit is applied to its gate. The selection circuit may be the row selection circuit 12 in FIG. 26, the voltage control unit 24, or a selection circuit (not shown). The resistance value R1 (or R2) of the variable resistance element VR11 is determined by the resistance values of one or more resistance elements R1 to R10 connected to the selection transistors T1 to T10 that are turned on by the selection signal.

  The selection transistors T1 to T10 are preferably provided in the wiring layer in order to suppress an increase in the area of the pixel cell 11A. FIG. 28 shows an example of a cross-sectional structure of a semiconductor device for realizing the circuit configuration shown in FIG.

  As shown in FIG. 28, in the ninth embodiment, a gate insulating film 201 and interlayer insulating films 202 to 204 are added on the interlayer insulating film 118 in the wiring layer 21L in the same configuration as that shown in FIG. In addition, a switching transistor SW11 is formed in place of the MOS transistor QR1 which is the variable resistance element VR1 formed in the interlayer insulating film 118. In addition, the selection transistor T1 in the variable resistance element VR11 is formed in the interlayer insulating film 202, and the interlayer insulating film 204 that is higher than the selection transistor T1 is variable via the second wiring L1 formed in the interlayer insulating film 203. A resistance element R1 in the resistance element VR11 is formed. For convenience of explanation, FIG. 28 shows the resistance element R1 in the variable resistance element VR11 and the selection transistor T1 connected in series thereto, but the other resistance elements R2 to R10 and the selection transistors T2 to T10 are also shown in FIG. The resistor element R1 and the select transistor T1 may be formed in the same layer.

  As described above, when a resistance element such as a polysilicon resistor is used as the variable resistance element VR1 (VR2), a resistance that is less changed with respect to a bias change between the resistance elements than when a transistor resistance is used. A value can be obtained. In addition, a desired resistance value can be obtained by adjusting the cross-sectional area and length of the polysilicon resistor, and a desired number of smoothness steps can be obtained according to the number of resistor element rows.

  The resistance elements R1 to R10 may be an insulating film, a dielectric film, a metal, or the like other than the polysilicon resistance. In FIG. 27, the resistance elements are 10 rows, but may be 10 rows or more, or 10 rows or less. Further, in the configuration shown in FIG. 25, the switching transistor SW11 may be omitted depending on the configuration of the variable resistance element VR11. For example, when the variable resistance element VR11 having the configuration shown in FIG. 27 is employed, the selection transistors T1 to T10 can be substituted.

(Embodiment 10)
In addition, each of the resistance elements R1 to R10 in the ninth embodiment can be configured by a resistance change memory such as ReRAM, MRAM, PRAM, ion memory, amorphous silicon memory, and polysilicon memory. 29 to 31 are circuit diagrams illustrating an example in which the resistance elements R1 to R3 are configured by a resistance change memory. 29 shows the resistance element R1, FIG. 30 shows the resistance element R2, and FIG. 31 shows the resistance element R3.

  As shown in FIG. 29, for example, the resistance element R1 includes a single resistance change memory R11. Also, the resistance elements R2 and R3 and the resistance elements R4 to R10 shown in FIG. 30 and FIG. 31 are configured by resistance change memories R20 to R24, R30 to R39,. Thus, the parallel number of the resistance change memories constituting the resistance elements R1 to R10 may be changed according to the target resistance value.

  FIG. 32 is a circuit block diagram illustrating a schematic configuration of a CMOS image sensor as the imaging apparatus according to the tenth embodiment. As shown in FIG. 32, the imaging device 5 has a configuration similar to that of the imaging device 4 shown in FIG. 26, with respect to a variable resistance element VR11 configured by resistance change memories R11, R20 to R24, R30 to R39,. Write wiring for writing the resistance value is added. Other configurations may be the same as those of the imaging device 4 shown in FIG.

  FIG. 33 and FIG. 34 are diagrams showing structural examples of the resistance elements R1 to R10. FIG. 33 shows a structural example of the resistive element R1, and FIG. 34 shows a structural example of the resistive element R2. As shown in FIGS. 33 and 34, the resistance element R1 includes two electrodes E11 and E12 arranged above and below, and a resistance change memory R10 provided between the electrodes E11 and E12. Similarly, the resistance element R2 includes electrodes E21 and E22 and resistance change memories R20 to R24 provided between the electrodes E21 and E22. Similarly, the other resistance elements R3 to R10 include two electrodes and a plurality of resistance change memories provided on the electrodes.

  Regarding the resistance elements R2 to R10 including a plurality of resistance change memories, the resistance change memories do not have to be arranged in a line between the electrodes, and may be two-dimensionally arranged, for example, as shown in FIG. Furthermore, in FIGS. 33 to 34, the resistance elements R <b> 1 to R <b> 10 having a single layer structure are illustrated, but a multi-layer structure can also be used. In that case, a rectifying element such as a diode may be provided between the resistance change memory and the electrode. Even when the variable resistance element VR11 has such a configuration, by arranging it in the wiring layer 21L, it is possible to increase the number of smoothness steps while suppressing an increase in area.

  Writing resistance values to each of the resistance elements R1 to R10 includes both the switching transistor SW11 connected to the variable resistance element VR11 to be written and the selection transistor connected to the resistance element to be written in the variable resistance element VR11. This is executed by applying a write voltage to both ends of the resistance element constituted by the resistance change memory in the ON state. For example, when a resistance value is written to the resistance element R3 shown in FIG. 31, both the switching transistor SW11 connected to the variable resistance element VR11 including the resistance value and the selection transistor T3 connected to the resistance element R3ni are turned on. By applying a desired write voltage to both ends of the resistance element R3, a desired resistance value is written to the resistance element R3.

  The verification for verifying the write state may be performed not on the individual variable resistance memories constituting the resistance element but on the entire resistance element to be written. This is because even when the variable resistance memory constituting the resistance element includes element variations and some defects, the desired resistance value is written with high accuracy by invalidating the element variations and some defects when writing the resistance value. It is guiding you to be able to.

  Moreover, the writing of the resistance value to each of the resistance elements R1 to R10 may be performed at the time of factory shipment, when the apparatus is on standby (such as a standby period or an idle period), or when the power is turned off. Since the resistance values written in the resistance elements R1 to R10 are maintained even when the power is turned off, it is not necessary to sequentially write the resistance values. This leads to the effects that the resistance elements R1 to R10 can have a long life and that the resistance value can be switched at high speed during operation. However, this does not exclude the sequential writing of the resistance value from the embodiment.

  Other configurations, effects, and operations are the same as those of the ninth embodiment and other embodiments, and thus detailed description thereof is omitted here.

(Embodiment 11)
In the tenth embodiment, a case where a resistance change memory having two terminals is used as the resistance element is illustrated, but instead of this, a three-terminal having one terminal for writing resistance values in addition to two terminals for reading resistance values is used. It is also possible to use a resistance change memory. By using a three-terminal resistance change memory, a selection transistor for selecting an element is not required when writing a resistance value, so that the number of parallel stages of the variable resistance memory can be increased. As a result, it is possible to increase the rate of change in resistance value and increase the number of smoothness steps.

  36 to 38 are diagrams illustrating a structure example of the three-terminal variable resistance memory according to the eleventh embodiment. The resistance change memory R200a shown in FIG. 36 has a configuration in which a resistance value writing electrode E202 and two variable resistance materials C201 and C202 are provided so as to bridge the resistance value reading electrodes E201 and E203. Prepare. At the time of writing the resistance value, a desired bias voltage is applied between the electrodes E202 and E201 and between the electrodes E202 and E203. At this time, the electrodes E201 and E202 are set to the same potential. Thereby, a desired resistance value is written in the resistance change memory R200a. Further, when reading the resistance value, a current corresponding to the resistance value flows between the electrodes E201 and E203. In the structure shown in FIG. 36, since the electrode E201 and the electrode E203 are target structures, there is an effect that the characteristics as a resistance element with respect to both positive and negative polarities are also improved.

  Further, as in a variable resistance memory R200b shown in FIG. 37, it is possible to arrange electrodes E201, 202 and 203 vertically and connect them with variable resistance materials C201 and C202. Further, as in the variable resistance memory R200c shown in FIG. 38, it is possible to adopt a lateral structure in which one variable resistance material C203 is sandwiched between three electrodes E201 to E203. In this case, the read current may flow from the electrode E201 to the electrode E203 via the variable resistance material C203 and the electrode E202, or may flow through an interface portion between the variable resistance material C203 and the insulator D201. For example, when the electrodes E201 and E203 are made of a metal such as copper (Cu), metal ions diffuse into the interface portion between the variable resistance material C203 and the insulator D201, thereby forming a current path having a desired resistance value. . Furthermore, the structure shown in FIG. 38 may be a vertical structure like the variable resistance memory R200d shown in FIG.

  Note that the structure shown in FIG. 36 or FIG. 37 has an advantage in that it is easy to manufacture. Further, the structure shown in FIG. 38 or FIG. 39 has an advantage in that the exclusive area can be reduced.

  Since other configurations, effects, and operations are the same as those of the other embodiments, detailed description thereof is omitted here. For example, the imaging apparatus according to the eleventh embodiment may be the same as the imaging apparatus 5 illustrated in FIG.

Embodiment 12
Moreover, although Embodiment 9-11 illustrated the case where the resistance value of resistance element R1-R10 was preset, it is not limited to this. For example, it is possible to configure so that the resistance value of the variable resistance element VR11 is set every time a value is read from the scanning circuit 11A or 11B for each layer. In this embodiment, a case where a three-terminal resistance change memory is used is exemplified, but a configuration in which a two-terminal resistance change memory and a selection transistor are combined may be used.

  FIG. 40 is a circuit diagram illustrating an example of a variable resistance element configured using the three-terminal resistance change memory according to the twelfth embodiment. As shown in FIG. 40, the variable resistance element VR21 has a configuration in which resistance change memories R201 to R20n (n is a positive integer, for example, about 400) are connected in parallel in multiple stages. When both the variable resistance elements VR1 and VR2 are replaced with the variable resistance element VR11, the number of parallel stages may be different from each other.

  The resistance change memories R201 to R20n connected in parallel in multiple stages are not partitioned like the resistance elements R1 to R10, and operate as one resistance element as a whole. Therefore, in the writing of the resistance value, the number of resistance change memories corresponding to the target resistance value is selected by the selection circuit. However, the resistance value is written not to the individual variable resistance memories R201 to R20n constituting the variable resistance element VR21, but to the entire resistance element selected as the write target, as in the tenth embodiment. Good. Also, “Verify” in the written state may be executed or omitted.

  Since other configurations, effects, and operations are the same as those of the other embodiments, detailed description thereof is omitted here. For example, the imaging apparatus according to the twelfth embodiment may be the same as the imaging apparatus 5 illustrated in FIG.

(Embodiment 13)
In the thirteenth embodiment, a configuration example of the variable resistance memory exemplified in the tenth to twelfth embodiments will be described in detail with reference to the drawings. In the following description, the variable resistance element R201 exemplified in the twelfth embodiment will be described. However, the present invention can be applied to any of the other resistance elements R202 to R20n, R1 to R10, R20 to R24, and R30 to R39. It is.

  FIG. 41 is a circuit diagram illustrating a configuration example of a resistance element according to the thirteenth embodiment. As shown in FIG. 41, the resistance element R201 is not limited to a configuration using a single variable resistance memory, but may be configured using a plurality of variable resistance memories R50a to R59n.

  In the example shown in FIG. 41, a plurality of variable resistance memories R50a to R59n are connected in series and parallel. In such a configuration, it is possible to control the change of the resistance value for each array connected in series stochastically. This will be described with reference to FIG. FIG. 42 is a diagram showing the relationship between the write bias voltage and the number of sets. The term “set” means that the resistance value is switched. Note that the write bias voltage in FIG. 42 can be replaced with a write current or a write count.

  As shown by the one-dot broken line in FIG. 42, in one variable resistance memory element, when a pulsed write voltage makes a transition from a low resistance state corresponding to information “0” to a high resistance state corresponding to information “1”. In the vicinity of the threshold voltage, the write success probability changes sharply. Therefore, the number of cells whose resistance value is switched (set) in the vicinity of the threshold voltage (hereinafter referred to as the set number) increases rapidly. On the other hand, as shown by the solid line in FIG. 42, in this embodiment in which a plurality of variable resistance memories are connected in series and parallel, the resistance change with respect to the write bias voltage is almost linear. This indicates that the control of the resistance value is higher in the present embodiment. Therefore, the number of sets of the variable resistance memories R50a to R59n can be controlled by controlling the write bias voltage applied between the nodes n341 and n351 in FIG. As a result, the resistance values of the variable resistance memories R50a to R59n can be set in multiple stages. In addition, by designing a resistance change memory array in consideration of manufacturing variations, the relationship between the write bias voltage and the number of sets can be made more linear.

  Further, in the thirteenth embodiment, since the selection transistor for each of the variable resistance memories R50a to R59n is not necessary, it is possible to increase the parallel number of the variable resistance memories R50a to R59n. Furthermore, since the resistance values of the variable resistance memories R50a to R59n can be changed at once, the resistance values can be switched at high speed.

  Since other configurations, effects, and operations are the same as those of the other embodiments, detailed description thereof is omitted here.

(Modification 1 of Embodiment 13)
In the thirteenth embodiment, the case where the variable resistance memories R50a to R59n are connected in series and parallel is illustrated, but the present invention is not limited to this arrangement. For example, it is possible to control the change of the resistance value for each array in a probabilistic manner by adopting a configuration in which the variable resistance memories R50a to R59n are connected in parallel like a resistance element R201A shown in FIG.

  In addition, the variable resistance memories R50a to R59n connected in parallel can have a layout in which the variable resistance memories R50a to R59n are two-dimensionally arranged between the electrodes E50 and E51 arranged above and below, for example, as shown in FIG. It is. With the layout shown in FIG. 44, since the wiring layer in which the variable resistance memories R50a to R59n are arranged can be a single layer, the number of manufacturing steps can be reduced.

  In the configuration in which the variable resistance memories R50a to R59n are connected in parallel, it is possible to use a variable resistance memory whose resistance value is switched by a current. However, in consideration of controllability of the resistance value, the resistance value is switched depending on the voltage value. It is desirable to use a variable resistance memory.

(Modification 2 of Embodiment 13)
Further, it is possible to control the change of the resistance value for each array in a probabilistic manner by adopting a configuration in which the variable resistance memories R50a to R59n are connected in series as in the resistance element R201B shown in FIGS. is there.

  When a plurality of variable resistance memories R50a to R59n are connected in series, the resistance value of the entire resistance element R201B directly corresponds to how many resistance values of the variable resistance memories R50a to R59n have changed. This means that the controllability of the resistance value is high. In addition, since it is easy to design a peripheral circuit that performs write control with high controllability, it is possible to reduce the circuit area and the control processing time.

  In the configuration in which the variable resistance memories R50a to R59n are connected in series, it is possible to use a variable resistance memory whose resistance value is switched depending on the voltage value. However, in view of controllability of the resistance value, the resistance value is switched depending on the current. It is desirable to use a variable resistance memory.

  For example, the resistance value when the information amount “0” of all N variable resistance memories connected in series is R1, the resistance value when the information amount is “1” is R2, and R2 = k × R1. When in the relationship, the resistance value of the entire variable resistance memory can be changed between N × R1 and N × k × R1. Specifically, when N is 100, R1 is 1 kΩ, and R2 is 2 kΩ, k = 2 and the resistance value can be changed between 100 kΩ and 200 kΩ.

  For example, a resistance value is set to 100 kΩ, and a pulse (write bias voltage) whose resistance value changes from information “0” (low resistance) to information “1” (high resistance) with a probability of 1% is applied. Since one piece of information may be rewritten, the resistance value can be expected to be 101 kΩ. When a resistance value of 150 kΩ is required, a pulse (writing bias voltage) whose resistance value changes with a probability of 50% may be applied.

  Furthermore, when the resistance value becomes too large, a pulse (write bias voltage) for rewriting information “1” (high resistance) to information “0” (low resistance) is applied as a method of correcting the error. Then, you can lower the resistance value little by little. In error correction, the read current may be converted into a digital value by an analog-digital converter, or the read analog current value may be directly compared with the current flowing through the reference resistor.

  The above-described embodiment and its modifications are merely examples for carrying out the present invention, and the present invention is not limited thereto, and various modifications according to specifications and the like are within the scope of the present invention. Furthermore, it is obvious from the above description that various other embodiments are possible within the scope of the present invention. For example, it is needless to say that the modification examples illustrated as appropriate for the embodiments can be combined with other embodiments.

  DESCRIPTION OF SYMBOLS 1, 2, 3, 4, 5 ... Image pick-up device, 11 ... Pixel array, 12 ... Row selection circuit (register), 13 ... Timing generation circuit, 14 ... ADC, 15 ... DSP, 16 ... I / O, 17 ... Peripheral Circuit 20, control unit 21, control circuit 23, bias generation circuit 24 voltage control circuit 11 a light receiving unit 11 b scanning circuit 11 c amplifier circuit 11 A to 11 N pixel cells VR 1, VR 2 VR11, VR21... Variable resistance element, M1 to M5, M10, M11... Memory element, C201, C202, C203. E59 (n-1) ... electrodes, R1 to R10 ... resistance elements, R11, R20 to R24, R30 to R39, R2a, R200a, R200b, R200c R200d, R201~R20n, R201A, R201B, R50a~R59n ... the resistance change memory, SW11 ... switching transistor, T ... selection transistor

Claims (7)

A first wiring;
A first pixel electrically connected to the first wiring through a second wiring branched from the first wiring at a first branch point and having a first light receiving element and a first scanning circuit Cell,
The second light receiving element and the second light receiving element are electrically connected to the first wiring through a third wiring that branches from the first wiring at a second branch point different from the first branch point. A second pixel cell having a scanning circuit of
A first variable resistance element on the second wiring and electrically connected between the first branch point and the first pixel cell;
A second variable resistance element on the third wiring and electrically connected between the second branch point and the second pixel cell;
A third variable resistance element on the first wiring and electrically connected between the first branch point and the second branch point;
A plurality of first memory elements connected in parallel to the first branch point and storing the potential of the first branch point according to different trigger signals;
A plurality of second memory elements connected in parallel to the second branch point and storing the potential of the second branch point according to different trigger signals;
With
Each of the first to third variable resistance elements includes a plurality of resistance elements connected in parallel to each other.
Image sensor.   The imaging device according to claim 1, wherein at least one of the plurality of resistance elements is a three-terminal element including a resistance value reading two terminal and a resistance value writing one terminal.   The imaging element according to claim 1, wherein at least one of the plurality of resistance elements includes a plurality of resistance change memories connected in series, parallel, or series-parallel.   The imaging device according to claim 3, wherein the resistance change memory includes at least one of ReRAM, MRAM, PRAM, ion memory, amorphous silicon memory, and polysilicon memory. The imaging device according to any one of claims 1 to 4,
A control unit that controls to read out an image signal from the imaging element while controlling at least one resistance value of the first to third variable resistance elements;
With
The control unit reads the first image signal from the imaging element using at least one of the first to third variable resistance elements as a first resistance value, and then reads the first to third variable resistance elements. An image pickup apparatus that controls to read out a second image signal from the image pickup element by setting the at least one resistance value of the variable resistance elements as a second resistance value different from the first resistance value. The third memory element of the plurality of first memory elements connected in parallel to the first branch point is at least one of the first to third variable resistance elements by the control unit. Storing the potential at the first branch point when the two resistance values are the first resistance values as pixel information constituting the first image signal;
Of the plurality of second memory elements connected in parallel to the second branch point, the fourth memory element has at least one of the first to third variable resistance elements controlled by the control unit. Storing the potential of the second branch point when one resistance value is the first resistance value as pixel information constituting the first image signal;
A fifth memory element different from the third memory element among the plurality of first memory elements connected in parallel to the first branch point is configured such that the control unit includes the first to first elements. A potential of the first branch point when at least one resistance value among the three variable resistance elements is set as the second resistance value is stored as pixel information constituting the second image signal;
A sixth memory element different from the fourth memory element among the plurality of second memory elements connected in parallel to the second branch point is configured such that the control unit includes the first to first elements. A potential of the second branch point when at least one resistance value of the three variable resistance elements is set as the second resistance value is stored as pixel information constituting the second image signal;
The first image signal is read by reading the pixel information from the third memory element connected to the first branch point and the fourth memory element connected to the second branch point. Issued,
What is the first image signal by reading the pixel information from the fifth memory element connected to the first branch point and the sixth memory element connected to the second branch point? The imaging apparatus according to claim 5, wherein the second image signal having different smoothness is read out. A semiconductor substrate;
First and second light receiving elements provided on a surface parallel to the upper surface of the upper surface of the semiconductor substrate;
A first scanning circuit connected to the first light receiving element;
A second scanning circuit connected to the second light receiving element;
A wiring layer located on the upper surface of the semiconductor substrate;
A first wiring included in the wiring layer;
A second wiring included in the wiring layer, branched from the first wiring at a first branch point, and connected to the first scanning circuit;
A third wiring included in the wiring layer, branched from the first wiring at a second branch point, and connected to the second scanning circuit;
A first variable resistance element provided in the wiring layer and on the second wiring and electrically connected between the first branch point and the first scanning circuit;
A second variable resistance element provided in the wiring layer, on the third wiring and electrically connected between the second branch point and the second scanning circuit;
With
Each of the first and second variable resistance elements includes a plurality of resistance elements connected in parallel to each other.

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