JP2010153591A - Nonvolatile variable resistor element and method of driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile variable resistor element that is reliable and is easy to read data from. <P>SOLUTION: There is provided a three-terminal nonvolatile variable resistor element that comprises a first electrode 12, a second electrode 14, a variable resistor 13 electrically connected to both the first and second electrodes 12 and 14, and a control electrode 16 opposite to the variable resistor 12 with a dielectric layer 15 in between. The variable resistor 13 is formed of a material that changes resistive characteristics of the nonvolatile variable resistor element in one resistive state after transition when an electric field is induced inside the variable resistor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a non-volatile variable resistance element whose resistance characteristics vary with voltage application. The present invention also relates to a method for reading out such a nonvolatile variable resistance element.

  A non-volatile memory that can retain recorded information even when the power is turned off, such as a flash memory, FeRAM, or MRAM, can be used as a recording medium for music, moving images, and sentences. In recent years, the resistance value can be reduced by applying voltage or current such as PCRAM using chalcogenide (see Patent Documents 1 and 2), RRAM using metal oxide (see Non-Patent Document 1), CBRAM using metal sulfide, etc. Development of variable resistance elements using variable resistance bodies that are changing is underway.

  These elements are characterized in that both rewriting and reading are performed by applying a voltage pulse between the electrodes of the element. For example, rewriting is performed by changing the resistance state with a pulse of 2 V to 4 V, and reading is performed by detecting a magnitude of current at the time of application by applying a pulse of about 1 V.

U.S. Pat.No. 3,271,591 U.S. Pat.No. 3,530,441 JP 2006-245589 A JP 2006-319342 A W. W. Zhuang et al., “Novel Collaborative Magnetically Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, IEDM Technical Digest, pp. 193-196, December 2002

  However, the above-described writing and reading methods have problems in reading accuracy and reliability. That is, when reading is repeatedly performed using a relatively large voltage pulse close to the absolute value of the rewrite voltage during reading, the resistance value of the variable resistance element is rewritten, that is, there is a problem of read disturb. In order to avoid read disturb, the applied voltage must be changed several times or more during rewrite and read, but the upper limit of the rewrite current is limited due to restrictions on circuit elements such as a load circuit and a decoder circuit connected in series to the memory cell. Since it is determined, it is necessary to reduce the read voltage.

  However, when the read voltage is set to be small, the output current value becomes small, so that a sufficient sense margin cannot be obtained, and it is necessary to lengthen the read time, resulting in a problem that the read operation performance is deteriorated.

  The present invention has been made in view of the above-described problems in reading information of variable resistance elements whose resistance characteristics change due to voltage application. The object of the present invention is to overcome the above-described problems and to provide high reliability and read-out. It is an object of the present invention to provide a non-volatile variable resistance element that is easy to handle.

  A nonvolatile variable resistance element according to the present invention includes a first electrode, a second electrode, and a variable resistor electrically connected to both the first electrode and the second electrode, and applies a voltage. A non-volatile variable resistance element in which a resistance state between the first electrode and the second electrode transitions between two or more different resistance states, and one resistance state after the transition is held in a non-volatile manner. A control electrode facing the variable resistor via a layer, and applying a voltage to the control electrode temporarily modulates a resistance characteristic in one resistance state after the transition; And

  Furthermore, in addition to the first feature, the nonvolatile variable resistance element according to the present invention includes the first electrode formed on an insulating film, the variable resistor on the upper surface of the first electrode, and the variable resistance. The second electrode is formed on the upper surface of the body, the dielectric layer covering the side wall of the variable resistor is formed, and the control electrode facing the side wall of the variable resistor is formed through the dielectric layer. This is a second feature.

  Furthermore, in addition to the first feature, the nonvolatile variable resistance element according to the present invention includes the dielectric layer that covers the control electrode formed on the control electrode, and the variable resistor is formed on the dielectric layer. Is formed across the dielectric layer, and the first electrode and the second electrode are formed on the variable resistor so as to be separated from each other in a direction parallel to the upper surface of the control electrode. And

  Furthermore, in addition to the first feature, the nonvolatile variable resistance element according to the present invention is configured such that the dielectric layer covering the control electrode is formed on the control electrode, and the first dielectric layer is formed on the dielectric layer. The electrode and the second electrode are formed apart from each other in a direction parallel to the upper surface of the control electrode, and are exposed on the first electrode, on the second electrode, and between the first electrode and the second electrode. A fourth feature is that the variable resistor is formed on a dielectric layer.

  Furthermore, the nonvolatile variable resistance element according to the present invention has a fifth feature that, in addition to any of the third to fourth features, the control electrode is formed on an insulator.

  Furthermore, the nonvolatile variable resistance element according to the present invention has, in addition to any one of the first to fifth features, a sixth feature that the variable resistor is made of a transition metal oxide. .

  The memory cell array according to the present invention includes a plurality of nonvolatile variable resistance elements having the above second characteristics arranged in a matrix, and the first electrodes of the nonvolatile variable resistance elements belonging to the same row are connected to each other. The first feature is that the second electrodes of the nonvolatile variable resistance elements belonging to a column are interconnected, and the control electrodes of the nonvolatile variable resistance elements belonging to the same column are interconnected.

  A nonvolatile semiconductor memory device according to the present invention includes the nonvolatile variable resistance element having any one of the first to sixth characteristics, and the first electrode and the second electrode of the nonvolatile variable resistance element to be read. When a predetermined read voltage is applied during this period, the resistance characteristic of the variable resistor is temporarily reduced by applying a predetermined control voltage to the control electrode of the nonvolatile variable resistance element to be read. First, the information stored as the resistance state of the nonvolatile variable resistance element is read.

  In addition to the first feature, the nonvolatile semiconductor memory device according to the present invention includes a plurality of nonvolatile variable resistance elements having any one of the first to sixth features, and the nonvolatile variable resistance element includes: Any one of the first electrode and the second electrode is interconnected, and the predetermined read voltage is applied between the first electrode and the second electrode. A second feature is that the predetermined control voltage is not applied to the control electrode and the resistance is not temporarily reduced.

  Furthermore, in the nonvolatile semiconductor memory device according to the present invention, in addition to any one of the first to second features, the variable resistor is formed of a p-type semiconductor, and the first electrode and the second electrode A third feature is that the resistance characteristic of the variable resistor to be read is temporarily reduced by applying the predetermined control voltage, which is lower than both of the applied voltages, to the control electrode. .

  Furthermore, in the nonvolatile semiconductor memory device according to the present invention, in addition to any of the first to second features, the variable resistor is formed of an n-type semiconductor, and the first electrode and the second electrode A fourth feature is that the resistance characteristic of the variable resistor to be read is temporarily reduced by applying the predetermined control voltage higher than both of the applied voltages to the control electrode. .

  A method for reading a resistance state of a nonvolatile variable resistance element according to the present invention is a method for reading one resistance state after the transition of the nonvolatile variable resistance element according to any one of the first to sixth features, When a predetermined read voltage is applied between the first electrode and the second electrode, a predetermined control voltage is applied to the control electrode to reduce the resistance characteristics of the variable resistor, and the variable resistor The first feature is to read one resistance state after the transition of the body.

  Furthermore, in addition to the first feature, the method for reading the resistance state of the nonvolatile variable resistance element according to the present invention is such that the variable resistor is a p-type semiconductor, and when the predetermined read voltage is applied, A second feature is that the predetermined control voltage, which is lower than both voltages applied to one electrode and the second electrode, is applied to the control electrode.

  Furthermore, in addition to the first feature, the method for reading the resistance state of the nonvolatile variable resistance element according to the present invention is such that the variable resistor is an n-type semiconductor, and when the predetermined read voltage is applied, A third feature is that the predetermined control voltage, which is higher than both voltages applied to one electrode and the second electrode, is applied to the control electrode.

  Here, before describing the effect of the present invention, the resistance change phenomenon of the variable resistance element newly discovered by the present inventor will be described.

  The inventor of the present application produces a nonvolatile variable resistance element in which a transition metal oxide (for example, cobalt oxide), which is a variable resistor, is sandwiched between a first electrode and a second electrode, and the first electrode and the second electrode At the same time, a portion of the variable resistor on the current path is covered with a dielectric layer, and a voltage is applied via first and second electrodes provided at both ends of the variable resistor to flow current. When a voltage is applied via the dielectric layer, an electric field acts on a part of the variable resistor, whereby the resistance value of the variable resistor is temporarily modulated, and the voltage is applied via the dielectric layer. It was discovered that when the electric field is stopped, the original resistance value is restored.

  The details of the above-described resistance change mechanism are currently being elucidated, but a plurality of mechanisms are listed by the inventors' original research. First, it is conceivable that a voltage is applied to the variable resistor via a dielectric layer, an electric field acts inside the variable resistance region, and the resistance value changes due to the formation of a storage layer. On the other hand, when the variable resistor is a filament type variable resistor subjected to forming processing, the filament portion forms a normal conductive path, but an electric field mainly acts on a region other than the filament portion, and the filament portion It is considered that the resistance is lowered by generating another conductive path in a region other than the above.

  It has been found that whether the above-described mechanism for lowering resistance becomes the former storage layer forming type or the latter filament type strongly depends not only on the material of the variable resistor but also on the structure and manufacturing method of the variable resistor. However, details are still unclear.

  The present invention has been made based on the original idea of the inventor with this new resistance change phenomenon as a technical idea, and there is a problem in reading information of variable resistance elements using the new resistance change phenomenon. Is a solution.

  As a similar element structure, a physical property conversion layer (a layer having a metal-semiconductor transition) is formed between source and drain electrodes formed on an insulator, and a dielectric film stacked on the physical property conversion layer is formed. Patent Documents 3 and 4 disclose that a control electrode is provided and a transistor is operated by applying a voltage to the control electrode, but the element is a nonvolatile memory in which two or more resistance states are stored as information. The technical idea is completely different from that of the present invention used for the variable resistance element.

  The nonvolatile variable resistance element of the present invention is formed by sandwiching a variable resistor between a first electrode and a second electrode, and a resistance state is two or more by applying a voltage between the first electrode and the second electrode. A control electrode facing a variable resistor via a dielectric layer in a conventional two-terminal non-volatile variable resistance element that transitions between different resistance states and in which one resistance state after the transition is held in a nonvolatile manner Is a non-volatile variable resistance element having a three-terminal structure. Here, the variable resistor may be made of a material whose resistance characteristic in one resistance state of the variable resistor changes when an electric field is induced inside the variable resistor. It is an oxide. By applying a read voltage between the first electrode and the second electrode and measuring the amount of current, the resistance characteristic of the nonvolatile variable resistance element is calculated, and the resistance state held by the nonvolatile variable resistance element is read. . At this time, by simultaneously applying a voltage to the control electrode and causing an electric field to act on the current path of the variable resistor via the dielectric layer, the resistance characteristic of the variable resistor is temporarily modulated to reduce the resistance. be able to.

  In the case where the resistance modulation mechanism is the above-described storage layer formation type, the first and second cases are used when the variable resistor is a p-type semiconductor so that the storage layer is formed in a resistance change region near the dielectric layer. A voltage lower than both voltages applied directly to the two electrodes or indirectly through the load circuit or the like, in the case of an n-type semiconductor, directly to the first and second electrodes or a load circuit or the like A voltage higher than both of the voltages applied indirectly via the control electrode may be applied via the control electrode.

  Note that when the voltage application to the control electrode is stopped, the nonvolatile variable resistance element described above retains the resistance characteristics defined by the original resistance state before the voltage application, and the memory state of the nonvolatile variable resistance element is rewritten. It will never be done.

  As a result, at the time of reading the resistance state of the non-volatile variable resistance element, a voltage for reading is simultaneously applied between the first electrode and the second electrode, and a voltage is also applied to the control electrode, so that the resistance characteristics of the non-volatile variable resistance element can be improved. By modulating and lowering the resistance, a large read current can be obtained even at a low read voltage. Therefore, the memory cells having the nonvolatile variable resistance elements of the present invention are arranged in a matrix to form a nonvolatile semiconductor memory By configuring the device, it is possible to provide a highly reliable nonvolatile semiconductor memory device that has a large power supply voltage margin in a read operation, a high access speed, suppressed read disturb, and high reliability.

<First Embodiment>
Hereinafter, a first embodiment of a nonvolatile variable resistance element according to the present invention (hereinafter, referred to as “present element 1” as appropriate) will be described with reference to the drawings. In the following drawings, the dimensional ratio of each part of the element and the actual dimensional ratio do not always coincide with each other, and the main part may be emphasized as appropriate.

  FIG. 1 is a cross-sectional view showing the element structure of the element 1 of the present invention. An interlayer insulating film 11 (for example, a silicon dioxide film) is formed on the silicon substrate 10. A lower electrode 12 serving as a first electrode is formed on the interlayer insulating film 11, a variable resistor 13 is formed on the upper surface of the lower electrode 12, and an upper electrode 14 serving as a second electrode is formed on the upper surface of the variable resistor 13. A dielectric layer 15 covering the side wall of the variable resistor 13 is formed, and a control electrode 16 is formed on the dielectric layer 15. That is, the element 1 of the present invention is a three-terminal nonvolatile variable resistance element in which the lower electrode 12, the upper electrode 14, and the control electrode 16 are disposed on the variable resistor 13 via the dielectric layer 15.

  The lower electrode 12 and the upper electrode 14 are electrically connected to the variable resistor 13, and the resistance state of the nonvolatile variable resistance element can be changed by applying a voltage higher than a threshold value between the electrodes and causing a current to flow. it can.

  The variable resistor 13 is made of a material whose resistance characteristics are temporarily modulated by the action of the electric field inside the variable resistor, and is made of, for example, a transition metal oxide.

  The control electrode 16 opposes the side wall of the variable resistor 13 through the dielectric layer 15 and modulates the resistance characteristic in the resistance state of the nonvolatile variable resistance element by applying an electric field in the variable resistor 13 to reduce the resistance characteristic. It can be made resistant.

  The results of actual trial manufacture of the element 1 of the present invention having the above structure and evaluation of resistance characteristics are shown below.

  First, as shown in FIG. 2A, a silicon dioxide film is formed as an interlayer insulating film 100 on the silicon substrate 10 by thermal oxidation, and then, the lower electrode 12 is formed of Ti (30 nm) and TiN (100 nm). ) Was formed. Subsequently, a cobalt oxide film having a thickness of 10 nm was formed as the variable resistor 13 by sputtering. Further, an aluminum film having a thickness of 70 nm was formed on the variable resistor 13 as the upper electrode 14.

  Subsequently, the upper electrode 14 and the variable resistor 13 are collectively processed using a resist patterned by a photolithography technique, and the lower electrode 12 is similarly processed using a different resist, so that FIG. ). The dimension of the element used for the evaluation is a square of 50 μm, but it can be miniaturized to a size of about 1 to 0.5 μm.

  Further, alumina was deposited as a dielectric layer 15 by 8 nm by sputtering, and aluminum was deposited as a control electrode 16 by 70 nm on the dielectric layer 15 by sputtering. Subsequently, the control electrode 16 and the dielectric layer 15 were collectively processed by a photolithography technique, and the element 1 of the present invention shown in FIG. 1 was produced.

  The manufactured element is contacted with each of the lower electrode 12, the upper electrode 14, and the control electrode 16, and the electrical characteristics are evaluated using a commercially available semiconductor parameter analyzer (Agilent 4156B) and a commercially available pulse generator. went. The method and the result are shown below.

  First, a voltage of 0 V was applied to the control electrode 16 and a writing voltage pulse of +2.6 V was applied between the lower electrode 12 and the upper electrode 14 to make the resistance state of the element 1 of the present invention low. Subsequently, FIG. 3 shows a result of applying IV measurement between the lower electrode 12 and the upper electrode 14 of the element 1 of the present invention, that is, reading, by applying 0 V to the control electrode. In the following description, when the resistance value of the element is measured, the lower electrode 12 is grounded, and when a positive voltage is applied to the upper electrode 14 side, + is indicated, and the reverse voltage is applied. Make a notation. As shown in FIG. 3A, a current of about 7 μA was output by applying a voltage of + 1V.

  Then, the result of having applied the voltage of -2.5V to the control electrode 16 and performed IV measurement is shown in FIG.3 (b). When a voltage of +1 V was applied, a current of about 130 μA was output.

  Subsequently, a voltage of 0 V is applied to the control electrode 16 and an erase voltage pulse of -3 V is applied between the lower electrode 12 and the upper electrode 14 to change the resistance state of the element 1 of the present invention to the high resistance state, and then reading is performed. The results of performing are shown in FIG. When measurement was performed with 0 V applied to the control electrode 16, a current of about 0.1 μA was output when a voltage of +1 V was applied, as shown in FIG. Then, the result of having applied the voltage of -2.5V to the control electrode 16 and performed the IV measurement is shown in FIG.4 (b). When a voltage of +1 V was applied, a current of about 6 μA was output. In each of the cases where a voltage of +1 V is applied as a read voltage and a voltage of −2.5 V or 0 V is applied to the control electrode 16, the relationship between the high resistance state and the low resistance state is maintained. The resistance value in the high resistance state was never lower than that in the low resistance state.

  As a result, by applying a voltage to the control electrode 16, a large read current can be output while the voltage applied between the lower electrode 12 and the upper electrode 14 is kept sufficiently low. Since the read speed can be increased as the read current increases, high-speed reading can be performed by using the present invention.

Next, FIG. 5 shows the result of investigating whether the resistance value fluctuates by applying a read voltage pulse of +1 V 30 nanoseconds 10 ¹² times while applying a voltage of −2.5 V to the control electrode 16. . The measurement was performed for each of a high resistance state and a low resistance state. Even after 10 ¹² read operations, there was almost no resistance fluctuation, and good read disturb was shown.

  The above results are thought to be based on the following mechanism. That is, by applying a negative voltage to the control electrode through a dielectric layer with respect to cobalt oxide, which is a variable resistor having p-type semiconductor properties, an accumulation layer is formed inside the resistance change region in the cobalt oxide. It is considered that the resistance is reduced and a large read current can flow with respect to a relatively low read voltage applied between the lower electrode and the upper electrode. However, since the voltage applied at the time of reading is sufficiently smaller than the rewriting voltage, the resistance state of the element 1 of the present invention did not transition to another state.

Second Embodiment
By arranging the above-described element 1 of the present invention in a matrix and forming a memory cell array, a non-volatile semiconductor having a high power supply voltage margin in a read operation, high access speed, suppressed read disturb, and high reliability A storage device can be provided. FIG. 6 is a structural cross-sectional view of the memory cell array, FIG. 7 is an equivalent circuit diagram, and FIG. 8 is a circuit block diagram of the nonvolatile semiconductor memory device in the rewrite / read. In the equivalent circuit diagram of FIG. 7, a symbol indicating a two-terminal variable resistance element is given the same symbol as the gate terminal of the MOSFET, and is a three-terminal nonvolatile variable resistance element having a control terminal. It is shown that.

  The memory cell array according to the present embodiment (hereinafter referred to as “the present memory cell array 2” as appropriate) is configured by arranging a plurality of memory cells composed of the above-described element 1 of the present invention in a matrix in the row direction and the column direction. A cross-point type memory cell array having the structure shown in FIG.

  An insulating film 11 (for example, silicon dioxide film) is formed on the silicon substrate 10, a row-direction groove is formed on the insulating film, and the lower electrode 12 is formed by filling the groove with an electrode material. The lower electrodes 12 belonging to a row are interconnected to form a word line (WL). A variable resistor 13 extending in the column direction is formed on the insulating film 11 and the word line, an upper electrode 14 is formed on the variable resistor 13, and the upper electrodes 14 belonging to the same column are interconnected to form a bit line. (BL) is formed. In parallel with the bit lines, a dielectric layer 15 covering the side wall of the variable resistor 13 is formed, and an electrode material is formed on the dielectric layer 15 to form a control electrode 16, and the control electrodes 16 belonging to the same column are connected to each other. Are interconnected to form a control gate line (CGL).

  The present memory cell array 2 can be manufactured, for example, as follows. (1) As the insulating film 11, for example, silicon dioxide is deposited to 200 nm on the silicon substrate. (2) After depositing an electrode material (for example, a laminated film of titanium and titanium nitride) and forming a striped resist pattern in the row direction, the electrode material in a region where the resist pattern is not formed is removed by dry etching. Thereby, the first electrode 12 is formed, and the first electrode 12 extends in the row direction to form a word line. (3) After removing the resist pattern, the silicon dioxide film 11 is deposited again until the first electrode 12 is filled, and is polished by CMP until the upper surface of the first electrode 12 is exposed. As a result, a row-direction groove is formed on the silicon dioxide film 11 by filling the groove with the first electrode 12. The size of the groove may be about 100 nm deep and 600 nm wide, for example. (4) The variable resistor 13 and the second electrode 14 are formed using a resist patterned by a photolithography technique after forming the variable resistor 13 (for example, cobalt oxide 10 nm) and an electrode material (for example, aluminum 70 nm). Are processed at once. The second electrode 14 extends in the column direction to form a bit line. (5) After depositing a dielectric film (for example, 8 nm of alumina) and a control electrode material (for example, 70 nm of aluminum) using different resist patterns, the resist pattern is removed and the control gate lines 16 are formed. Note that the materials and film thicknesses of the electrode material, variable resistor, and dielectric film mentioned here are merely examples, and a combination of preferable materials and film thicknesses may be selected as appropriate.

  Each memory operation of rewriting and reading of the memory cell array 2 is controlled by a control circuit (not shown) based on an external address input signal, and information is electrically transferred to a memory cell specified by external address input. In addition, the information stored in the memory cell designated by the address input can be read out.

  Specifically, as shown in FIG. 8, in each memory operation, a selected word line connected to the selected memory cell to be the target of the operation, a non-selected word line other than the selected word line, and a selection connected to the selected memory cell Bit lines, non-selected bit lines other than the selected bit line, selection control gate lines connected to the selected memory cell, and non-selection control gate lines other than the selection control gate line are determined in accordance with each memory operation. Is applied to the voltage generation circuit 101, the word line decoder 102, the bit line decoder 103, the control gate line decoder 104, and the like. The voltage generation circuit 101 supplies voltages necessary for the operation of the memory cell array 2 to each of a selected word line, a non-selected word line, a selected bit line, a non-selected bit line, a selected control gate line, and a non-selected gate line. Apply to.

  During the rewriting operation, the selected word line is supplied with a rewriting voltage Vpp (for example, via the load circuit 105 and the word line decoder 102 for controlling the voltage divided by the element 1 of the present invention in the selected memory cell. 2.6V), the voltage Vpp / 2 through the word line decoder 102 for the unselected word line, the ground voltage Vss through the bit line decoder 103 for the selected bit line, and the bit line for the unselected bit line. A voltage Vpp / 2 is applied through the decoder 103 to perform a rewrite operation of the memory cell array. Note that no voltage is applied to the selected and unselected control gate lines. That is, the memory cell array 2 has the same rewrite operation as that of a conventional two-terminal memory cell. Therefore, it is also possible to employ bias conditions in which Vpp / 3 and 2Vpp / 3 are applied to the unselected word line and the unselected bit line, respectively.

  During the read operation, the selected word line is supplied with the ground voltage Vss through the word line decoder 102, and the selected bit line is supplied with a predetermined read voltage Vr (for example, 1 V) through the bit line decoder 103. A read voltage Vr is selected via the word line decoder 102 for the selected word line, a read voltage Vr is selected via the bit line decoder 103 for the non-selected bit line, and a predetermined voltage is supplied via the control gate decoder 104 to the selected control gate line. A control voltage Vg (for example, −2.5 V) is applied to the unselected control gate line via the control gate decoder 104, and only the amount of current flowing through the selected bit line is selectively detected. The read circuit 106 determines the data state from the read current amount of the selected bit line output via the bit line decoder, and sends the result to an output circuit (not shown).

  At this time, when the memory cell is read, a control voltage Vg is applied to the control electrode of the selected memory cell via the selection control gate line 16, and an electric field acts inside the variable resistor via the dielectric layer 15. Since the resistance characteristic of the variable resistor is low, a large read current can be obtained with a small read voltage Vr, and the resistance state of the nonvolatile variable resistance element can be identified at high speed without read disturb.

  Further, at the time of reading the memory cell, the read voltage Vr is also applied between the first electrode and the second electrode of the non-selected read-out memory cell connected to the selected word line. Since the control voltage Vg is not applied to the control electrode and the ground voltage Vss is applied, the resistance is not temporarily reduced and the resistance is higher than that of the selected memory cell. The influence of the sneak current can be greatly reduced, and the deterioration of the read margin due to the sneak current can be significantly suppressed as compared with the conventional cross-point type memory cell array.

<Third Embodiment>
Hereinafter, a third embodiment of the nonvolatile variable resistance element according to the present invention (hereinafter referred to as “the present invention element 3” as appropriate) will be described with reference to the drawings. FIG. 9 is a sectional view showing the element structure of the element 3 of the present invention.

  In the element 3 of the present invention, the control electrode 16 is formed on the insulator 17, the dielectric layer 15 is formed on the control electrode 16, and the variable resistor 13 is formed on the dielectric layer 15 across the dielectric layer 15. 13 is a non-volatile variable resistance element having a three-terminal structure in which a first electrode 12 and a second electrode 14 are formed on a base plate 13 apart from each other in a direction parallel to the upper surface of the control electrode 16.

  The first electrode 12 and the second electrode 14 are electrically connected to the variable resistor 13, and the resistance state of the non-volatile variable resistance element is transitioned by applying a voltage higher than a threshold value between the electrodes and causing a current to flow. be able to.

  As in the first embodiment, the variable resistor 13 is made of a material whose resistance characteristics are temporarily modulated by the action of an electric field inside the variable resistor, and is made of, for example, a transition metal oxide.

  The control electrode 16 is disposed on the current path of the variable resistor 13 between the first electrode 12 and the second electrode 14 so as to face each other with the dielectric layer 15 therebetween, so that an electric field acts on the variable resistor. Thus, the resistance characteristic of the nonvolatile variable resistance element in the resistance state can be temporarily modulated to reduce the resistance.

  The element 3 of the present invention is only required to be formed on an insulator (for example, silicon dioxide). However, when the element 3 is formed on a glass substrate, a TFT (which is often used in liquid crystal panel manufacturing as shown below) is used. (Thin Film Transistor) process. The results obtained by actually making a prototype of the element 3 of the present invention having the above structure and evaluating the resistance characteristics are shown below. In addition, although the dimension of the element used for evaluation is a 50-micrometer square, it can be refined | miniaturized to the magnitude | size of about 1-0.5 micrometer.

  First, as shown in FIG. 10A, a laminated film of tantalum (150 nm) and tantalum nitride (50 nm) is formed on a glass substrate 17 by a sputtering method, and processed using a photolithography technique and etching. The control electrode 16 was formed. Subsequently, the surface of tantalum was oxidized by an anodic oxidation method to form a tantalum oxide layer 18 having a thickness of 50 nm.

  Further, as shown in FIG. 10B, a silicon nitride film 19 was formed thereon as a dielectric layer by 150 nm by a CVD method. Since the laminated film of tantalum oxide and silicon nitride has high insulation and a high dielectric constant, a good dielectric layer 15 is thereby formed. Subsequently, a titanium oxide film having a thickness of 5 nm was formed as the variable resistor 13 having n-type semiconductor properties by sputtering. Subsequently, as shown in FIG. 10C, the titanium oxide 13 and the silicon nitride film 19 were patterned by photolithography and etching.

  Next, as shown in FIG. 10 (d), an amorphous silicon film 20 doped with carriers by a plasma CVD method was formed to a thickness of 50 nm, and an aluminum 21 as an electrode was formed to a thickness of 200 nm by a vacuum evaporation method. Finally, as shown in FIG. 10E, the aluminum 21 and the amorphous silicon film 20 were processed using a photolithography technique and etching to form the first electrode 12 and the second electrode 14 separately.

  A read circuit that senses a current value determined according to the resistance value of the variable resistance element at the time of reading to the second electrode by connecting a voltage pulse applying circuit for rewriting and reading to the first electrode 12, the second electrode 14, and the control electrode 16, respectively. Were connected and the readout evaluation was performed. Note that a sense amplifier is used for the readout circuit, and the readout potential that varies according to the readout current that is output is compared with a reference potential that can be set arbitrarily, and the variable resistance element is in a high resistance state or low resistance. It is determined whether it is in a state.

  The present invention element 3 applies a + 4V, 30 ns rewrite voltage pulse through the first electrode 12 to a low resistance state, and applies a +4 V, 30 ns rewrite voltage pulse through the second electrode 14. It changed to the high resistance state. FIG. 11 shows a variable resistance element written in a low resistance state and a high resistance state, each of 100 bits being rewritten before reading, and a 2 V read voltage pulse is applied, and read times are 20 ns, 50 ns, 100 ns, and 400 ns. Indicates the bit rate at which the data was read out correctly 10 times in succession. As a result, when the applied voltage of the control electrode 16 is 0V, a read time of 400 nanoseconds or more is required to read out the high resistance state and the low resistance state without fail 10 times in succession. On the other hand, when a similar readout test was performed by applying a voltage of +2 V to the control electrode, it was confirmed that the readout could be performed without any problem even when the readout time was 20 nanoseconds.

<Fourth embodiment>
Hereinafter, a fourth embodiment of the nonvolatile variable resistance element according to the present invention (hereinafter referred to as “the present invention element 4” as appropriate) will be described with reference to the drawings. FIG. 12 is a diagram showing an element structure of the element 4 of the present invention. The element 4 of the present invention has a variable resistor formed on the first electrode 12, the second electrode 14, and the dielectric layer 15 exposed between the first electrode 12 and the second electrode 14, The structure is similar to the element 3 of the present invention.

  The element 4 of the present invention is only required to be formed on an insulator (for example, silicon dioxide). However, when the element 4 is formed on a glass substrate, a TFT process often used in manufacturing a liquid crystal panel as shown below. Can be produced. The results of actual trial manufacture and evaluation of resistance characteristics of the present invention element 4 having the above structure are shown below. In addition, although the dimension of the element used for evaluation is a 50-micrometer square, it can be refined | miniaturized to the magnitude | size of about 1-0.5 micrometer.

  First, as shown in FIG. 13A, a laminated film of tantalum (150 nm) and tantalum nitride (50 nm) is formed on a glass substrate 17 by a sputtering method, and processed using a photolithography technique and etching. The control electrode 16 was formed. Subsequently, the surface of tantalum was oxidized by an anodic oxidation method to form a tantalum oxide layer 18 having a thickness of 50 nm.

  Further, as shown in FIG. 13B, a silicon nitride film 19 was formed thereon as a dielectric layer by a CVD method at a thickness of 150 nm. Since the laminated film of tantalum oxide and silicon nitride has high insulation and a high dielectric constant, a good dielectric layer 15 is thereby formed. Next, a 150 nm thick amorphous silicon film 20 doped with carriers was formed by plasma CVD.

  Subsequently, the amorphous silicon film 20 and the silicon nitride film 19 were patterned by photolithography and etching, and processed as shown in FIG. Further, as shown in FIG. 13D, an ITO (Indium Tin Oxide) film 22 and a laminated film 23 of tantalum (100 nm) and tantalum nitride (50 nm) are formed by sputtering, and subsequently, FIG. As shown in (e), the amorphous silicon film 20, the ITO film 22, and the laminated film 23 are processed using a photolithography technique and etching, and patterned to separate and form the first electrode 12 and the second electrode 14, The surface of the silicon nitride film 19 between the first electrode 12 and the second electrode 14 was exposed.

  Next, for example, a tantalum oxide layer having a thickness of 40 nm was formed as the variable resistor 13 by a reactive sputtering method, and was patterned using a photolithography technique and etching as shown in FIG. The tantalum oxide layer 13 is an insulator in the state of film formation, but a current path is formed by applying a relatively strong voltage, and the resistance value of the current path changes according to the history of the applied voltage. It operates as a variable resistor having n-type semiconductor properties.

  When the first electrode 12, the second electrode 14, and the control electrode 16 were rewritten and a voltage pulse application circuit for reading was connected, and reading evaluation similar to that of the third embodiment was performed, good reading characteristics were shown. FIG. 14 shows the result.

  The element 4 of the present invention applies a + 4V, 30 ns rewrite voltage pulse through the first electrode 12 to a low resistance state, and applies a +4 V, 30 ns rewrite voltage pulse through the second electrode 14. It changed to the high resistance state. FIG. 11 shows a variable resistance element written in a low resistance state and a high resistance state, each of 100 bits being rewritten before reading, and a 2 V read voltage pulse is applied, and read times are 20 ns, 50 ns, 100 ns, and 400 ns. Indicates the bit rate at which the data was read out correctly 10 times in succession. As a result, when the applied voltage of the control electrode 16 is 0V, a read time of 400 nanoseconds or more is required to read out the high resistance state and the low resistance state without fail 10 times in succession. On the other hand, when a similar readout test was performed by applying a voltage of +2 V to the control electrode, it was confirmed that the readout could be performed without any problem even when the readout time was 20 nanoseconds.

  Although the ITO film 22 is formed in the manufacturing process of the element 4 of the present invention, this process can be omitted when it is not necessary to form the ITO film in the peripheral circuit manufacturing process.

<Another embodiment>
<1> As described above, the first to fourth embodiments described above are examples of preferred embodiments of the present invention. The embodiment of the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention. For example, in the first, third, fourth, and other embodiments, a plurality of desirable element structures of the nonvolatile variable resistance element of the present invention have been exemplified, but the present invention is not limited to this configuration.
<2> Similarly, in the second embodiment, a nonvolatile semiconductor memory device having a large read margin is disclosed in which a plurality of nonvolatile variable resistance elements according to the first embodiment are arranged in a matrix to form a memory cell array. The element structure of the memory cell array according to the nonvolatile semiconductor memory device of the present invention is not limited to this structure. The memory cell array can be configured by adopting the third and fourth embodiments or other memory cell structures, and can be used as a nonvolatile semiconductor memory device having a large read margin.
<3> In the examples shown in the first to fourth embodiments and the other embodiments, the transition metal oxide is exemplified as the variable resistor. However, the present invention is not limited to this, and the same It is also possible to use other materials that exhibit these properties. For example, even for materials used for phase change memory such as aluminum oxide and polymer, GeSbTe, the resistance value is modulated by applying an electric field through a dielectric layer, and the electric conduction has a semiconducting property. Needless to say, the same effect can be obtained. Further, the electrode material, the dielectric film material, the element structure (including the element dimensions and the film thickness of each material), and the applied voltage are not limited, and the effects described above are based on the concept of the present invention. Needless to say, it can be selected as appropriate.
<4> Further, in the above-described embodiment, the configuration in which the non-volatile variable resistance element exhibits bipolar switching characteristics has been exemplified, but the present invention can also be applied to reading of a variable resistance element exhibiting monopolar switching characteristics. It is.
<5> In the second embodiment, at the time of reading the selected memory cell, the selected word line is grounded (applied voltage Vss), a predetermined voltage Vr is applied to the selected bit line, and a predetermined voltage is applied via the selection control gate line. Is applied to the control electrode to read the resistance state of the selected memory cell. However, the selected bit line is grounded and a predetermined voltage Vr is applied via the selected word line to select the resistance of the selected memory cell. The state may be read out. In addition, it is assumed that the ground voltage is applied to the non-selected control gate line at the time of reading. However, a small bias voltage may be applied as a reference voltage, and if noise countermeasures are taken, no voltage is applied to the control electrode. It does not matter if it is floating.

  The present invention can be applied to a nonvolatile variable resistance element, and is particularly applicable to a nonvolatile semiconductor memory device that uses the resistance state of the nonvolatile variable resistance element for storing information.

Sectional drawing which shows the element structure of this invention element. FIG. 6 is a view showing a method for manufacturing the element 1 of the present invention. The figure which shows the read-out current characteristic of this invention element 1. FIG. The figure which shows the read-out current characteristic of this invention element 1. FIG. FIG. 5 is a diagram showing read disturb characteristics of the element 1 of the present invention. FIG. 3 is a structural cross-sectional view of the memory cell array 2. 3 is an equivalent circuit diagram of the memory cell array 2. FIG. 4 is a circuit block diagram of a nonvolatile semiconductor memory device using the present memory cell array 2. FIG. Sectional drawing which shows the element structure of this invention element 3. FIG. FIG. 6 is a view showing a method for producing the element 3 of the present invention. The figure which shows the read-out characteristic of this invention element 3. FIG. Sectional drawing which shows the element structure of this invention element. The figure which shows the preparation methods of this invention element 4. FIG. The figure which shows the read-out characteristic of this invention element 4. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 3, 4: This invention element 2: This memory cell array 10: Silicon substrate 11: Interlayer insulation film 12: 1st electrode (word line)
13: Variable resistor 14: Second electrode (bit line)
15: Dielectric layer 16: Control electrode (control gate line)
17: Insulator (glass substrate)
18: Tantalum oxide layer 19: Silicon nitride film 20: Amorphous silicon film 21: Metal electrode (aluminum)
22: ITO film 23: Metal electrode (tantalum / tantalum nitride laminated film)
101: Voltage generation circuit 102: Word line decoder (row decoder)
103: Bit line decoder 104: Control gate line decoder 105: Load circuit 106: Read circuit 107: Column decoder

Claims (14)

A first electrode, a second electrode,
A variable resistor electrically connected to both the first electrode and the second electrode;
A nonvolatile variable resistor in which a resistance state between the first electrode and the second electrode is changed between two or more different resistance states by applying a voltage, and one resistance state after the transition is held in a nonvolatile manner An element,
A control electrode facing the variable resistor via a dielectric layer;
The nonvolatile variable resistance element, wherein a resistance characteristic in one resistance state after the transition is temporarily modulated by applying a voltage to the control electrode. The first electrode is formed on an insulating film;
The variable resistor is formed on an upper surface of the first electrode, and the second electrode is formed on an upper surface of the variable resistor;
The dielectric layer covering the sidewall of the variable resistor is formed;
The nonvolatile variable resistance element according to claim 1, wherein the control electrode facing the side wall of the variable resistor is formed through the dielectric layer. The dielectric layer covering the control electrode is formed on the control electrode,
The variable resistor is formed across the dielectric layer on the dielectric layer,
2. The nonvolatile variable resistance element according to claim 1, wherein the first electrode and the second electrode are formed on the variable resistor so as to be separated from each other in a direction parallel to the upper surface of the control electrode. . The dielectric layer covering the control electrode is formed on the control electrode,
On the dielectric layer, the first electrode and the second electrode are formed apart from each other in a direction parallel to the upper surface of the control electrode,
2. The variable resistor is formed on the first electrode, the second electrode, and the dielectric layer exposed between the first electrode and the second electrode. The nonvolatile variable resistance element described.   The nonvolatile variable resistance element according to claim 3, wherein the control electrode is formed on an insulator.   The nonvolatile variable resistance element according to claim 1, wherein the variable resistor is made of a transition metal oxide. A plurality of nonvolatile variable resistance elements according to claim 2 are arranged in a matrix,
The first electrodes of the nonvolatile variable resistance elements belonging to the same row are interconnected;
The second electrodes of the nonvolatile variable resistance elements belonging to the same column are interconnected;
A memory cell array, wherein the control electrodes of the nonvolatile variable resistance elements belonging to the same column are interconnected. A non-volatile variable resistance element according to any one of claims 1 to 6,
When a predetermined read voltage is applied between the first electrode and the second electrode of the nonvolatile variable resistance element to be read, a predetermined control voltage is applied to the control electrode of the nonvolatile variable resistance element to be read A nonvolatile semiconductor memory device, wherein the resistance characteristic of the variable resistor is temporarily lowered by applying the voltage, and information stored as a resistance state of the nonvolatile variable resistance element is read. A plurality of the nonvolatile variable resistance elements according to any one of claims 1 to 6,
One of the first electrode and the second electrode of the nonvolatile variable resistance element is interconnected,
The predetermined read voltage is applied between the first electrode and the second electrode. The predetermined control voltage is not applied to the control electrode of the nonvolatile variable resistance element that is not a read target, and temporarily has a low resistance. 9. The non-volatile semiconductor memory device according to claim 8, wherein the non-volatile semiconductor memory device is not formed. The variable resistor is made of a p-type semiconductor;
By applying the predetermined control voltage, which is lower than both voltages applied to the first electrode and the second electrode, to the control electrode, the resistance characteristic of the variable resistor to be read is temporarily reduced in resistance. 10. The nonvolatile semiconductor memory device according to claim 8, wherein The variable resistor is formed of an n-type semiconductor;
By applying the predetermined control voltage higher than both of the voltages applied to the first electrode and the second electrode to the control electrode, the resistance characteristic of the variable resistor to be read is temporarily reduced to a low resistance 10. The nonvolatile semiconductor memory device according to claim 8, wherein A method of reading one resistance state after the transition of the nonvolatile variable resistance element according to any one of claims 1 to 6,
When a predetermined read voltage is applied between the first electrode and the second electrode, a predetermined control voltage is applied to the control electrode to reduce the resistance characteristics of the variable resistor, and the variable resistor A method for reading a resistance state of a nonvolatile variable resistance element, comprising: reading one resistance state after the transition of the body. The variable resistor is a p-type semiconductor;
13. The predetermined control voltage, which is lower than both voltages applied to the first electrode and the second electrode, is applied to the control electrode when the predetermined read voltage is applied. A method for reading the resistance state of the nonvolatile variable resistance element. The variable resistor is an n-type semiconductor;
13. The predetermined control voltage higher than both voltages applied to the first electrode and the second electrode is applied to the control electrode when the predetermined read voltage is applied. A method for reading the resistance state of the nonvolatile variable resistance element.

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