JP2018049925A - Component built-in substrate and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement a component built-in substrate made by connecting two substrates using a relay element before the relay element being built in the substrates that are brought into contact with each other and integrated, the component built-in substrate, therefore, having no load applied to connection part between the two substrate, having strong connection causing no apprehension of bending and the like, and having the high degree of freedom of rearrangement enabling freely rearranging both substrates.SOLUTION: A component built-in substrate comprises: a substrates 1a(1b) including electronic components 11, 12(21, 22) encapsulated using resin and a recess 15 (25) formed on at least one side surface 14(24) of the substrate; and a relay element 2 detachable attached to the substrate 1a(1b). A set of the substrates 1a, 1b are in contact with each other so that the side surfaces 14, 24 are opposite to each other. The relay element 2 is fitted into a region formed by a set of the recesses 15, 25. Using the relay element 2, the substrates are connected electrically and mechanically.SELECTED DRAWING: Figure 1

Description

  The present embodiment relates to a component built-in substrate and a manufacturing method thereof.

  In recent years, SiP (System in Package) technology for mounting a plurality of functional elements in a small semiconductor package has attracted attention. In particular, FO-WLP (Fan-out wafer level package) technology is being studied. In the FO-WLP technique, after each semiconductor chip is sealed with a mold resin, the chips are connected by a redistribution layer (RDL) technique. With this technology, the interval between each semiconductor chip can be narrowed, and a plurality of semiconductor chips can be sealed in one semiconductor package, so that it is expected to be applied to multifunctional and small semiconductor packages. Has been.

JP 2010-98097 A JP 2010-199172 A JP 2002-280690 A Japanese Patent Laid-Open No. 10-308474 JP 2007-234525 A

  By applying the FO-WLP technology, an electronic device constructed by combining a plurality of small semiconductor packages, for example, is realized. In this electronic apparatus, each semiconductor package is designed so as to realize a single function such as communication or sensor, and the semiconductor package can be easily replaced or added. As a result, the burden on the system designer can be greatly reduced, and functions desired by the end user can be added.

  In order to realize such a small semiconductor package rearrangement, the connection structure is very important. For example, a structure in which a connector is mounted on a semiconductor package and a plurality of semiconductor packages are connected to each other can be considered. In a connector using a jack and a plug, the jack and the plug must be combined, and the degree of freedom of connection is low. When connecting each semiconductor package using a flexible substrate or the like in order to improve the degree of freedom in design, the distance between the semiconductor packages is extremely short, so that there is a high possibility that a large load is applied to the connection portion. Further, when the connector is mounted on the surface of each semiconductor package, the strength of the joint portion of the connector is low, and the strength is insufficient for the user to attach and detach the connector multiple times.

  The present invention has been made in view of the above problems, and when connecting the substrates with the relay element, the relay elements are in contact with each other and integrated into both the substrates, A component-embedded substrate having a high degree of freedom of recombination and a method of manufacturing the same, in which a high-strength connection can be obtained without applying a load to the connection portion of both substrates and without concern about bending, etc. The purpose is to provide.

  One aspect of the component-embedded substrate includes a substrate in which an electronic component is sealed with a resin and a recess is formed on at least one side surface, and a relay element that is detachable from the substrate. The side surfaces are opposed to and in contact with each other, and the relay element is fitted in a region formed by a set of the recesses, and is electrically and mechanically connected by the relay element.

  One aspect of a method for producing a component-embedded substrate includes a step of sealing an electronic component with resin and forming a recess by forming a recess on at least one side surface, and a relay element that is detachable from the recess of the substrate A pair of the substrates are brought into contact with each other via the relay element, and the relay element is fitted into a region formed by the two recesses, and the relay element is used to form the substrate. Forming a component-embedded substrate that electrically and mechanically connects each other.

  According to the above aspects, when the substrates are connected to each other by the relay element, the relay elements are in contact with each other so as to be integrated in both the substrates, so that a load is applied to the connecting portion of both the substrates. Accordingly, a high-strength connection without concern about bending or the like can be obtained, and a component-embedded substrate having a high degree of freedom of recombination that enables the substrates to be freely recombined can be realized.

It is a schematic sectional drawing which shows the structure of the component built-in board | substrate by 1st Embodiment. It is a schematic sectional drawing which shows the manufacturing method of the component built-in board | substrate by 1st Embodiment in order of a process. FIG. 3 is a schematic cross-sectional view illustrating the method of manufacturing the component-embedded substrate according to the first embodiment in the order of steps, following FIG. 2. FIG. 4 is a schematic cross-sectional view illustrating the method of manufacturing the component-embedded substrate according to the first embodiment in the order of steps, following FIG. 3. FIG. 5 is a schematic cross-sectional view subsequent to FIG. 4, illustrating the method for manufacturing the component-embedded substrate according to the first embodiment in the order of steps. FIG. 6 is a schematic cross-sectional view subsequent to FIG. 5, illustrating the method for manufacturing the component-embedded substrate according to the first embodiment in the order of steps. FIG. 7 is a schematic cross-sectional view subsequent to FIG. 6, illustrating the method for manufacturing the component-embedded substrate according to the first embodiment in the order of steps. FIG. 8 is a schematic cross-sectional view illustrating the method of manufacturing the component-embedded substrate according to the first embodiment in order of processes following FIG. 7. It is a schematic sectional drawing which shows the structure of the component built-in board | substrate by 2nd Embodiment. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the component built-in board | substrate by 2nd Embodiment.

  Hereinafter, embodiments of a component-embedded substrate and a manufacturing method thereof will be described in detail with reference to the drawings.

[First Embodiment]
(Configuration of component built-in board)
FIG. 1 is a schematic cross-sectional view showing a configuration of a component-embedded substrate according to the first embodiment. (A) shows each component which has not been mounted, and (b) shows a state where each component has been mounted to form a component-embedded substrate.
This component built-in substrate has a plurality of resin substrates, and in the illustrated example, a pair of resin substrates 1a and 1b and a relay element 2 connecting them are shown.

  As shown in FIG. 1A, the resin substrate 1a includes, as electronic components, for example, an IC semiconductor chip 11 and a chip component 12 such as a resistor, a capacitor, and an inductor sealed with a mold resin 13, and at least one side surface 14 is formed. A recess 15 serving as a female connector is formed. Wiring layers 16 and 17 are formed on the IC semiconductor chip 11 and the chip component 12 and the inner wall surface of the recess 15 by a rewiring technique used in the pseudo SoC technique or the like. On the surface of the wiring layer 17, connection terminals 17 a that are exposed on the inner wall surface of the recess 15 are formed. The wirings of the wiring layers 16 and 17 are electrically connected by a TMV (Through Mold Via) 18 embedded in the molding resin 13.

  As shown in FIG. 1A, the resin substrate 1b includes, for example, an IC semiconductor chip 21 and chip components 22 such as resistors, capacitors, and inductors as electronic components sealed with a mold resin 23, and at least one side surface 24 is provided. A recess 25 serving as a female connector is formed. Wiring layers 26 and 27 are formed on the IC semiconductor chip 21 and the chip component 22 and the inner wall surface of the recess 25 by a rewiring technique used in the pseudo SoC technique or the like. On the surface of the wiring layer 27, connection terminals 27 a that are exposed on the inner wall surface of the recess 25 are formed. The wirings of the wiring layers 26 and 27 are electrically connected by a TMV 28 embedded in the mold resin 23.

  Here, the resin substrates 1a and 1b have, for example, the same shape and size, but may have different shapes or sizes. The IC semiconductor chips 11 and 21 have different functions, for example, but may have the same functions. Similarly, the chip components 12 and 22 have different functions, for example, but may have the same function. The mold resins 13 and 23 are, for example, the same material, but may be different materials. The recesses 15 and 25 have the same shape and size.

  As shown in FIG. 1A, the relay element 2 is formed by a mold resin 31 in a shape and size suitable for the recesses 15 and 25, and a wiring layer 32 is formed on the back surface. Connection terminals 32 a are formed on the surface of the wiring layer 32. The relay element 2 is detachable from the resin substrates 1a and 1b. Similarly to the resin substrates 1a and 1b, the relay element 2 may include electronic components such as an IC semiconductor chip and a chip component.

  In this embodiment, as shown in FIG. 1B, the resin substrates 1 a and 1 b are in contact with each other at the side surfaces 14 and 24, and the relay element 2 is located in the region 10 formed by the recesses 15 and 25. The component-embedded board is configured by being fitted and fixed. The relay element 2 has a shape built in a component built-in substrate. By fitting and fixing in the region 10 of the relay element 2, the connection terminals 15a and 25a of the resin substrates 1a and 1b and the connection terminal 32a of the relay element 2 come into contact with each other, and the IC semiconductor chips 11 and 21 and the chip components 12 and 22 are brought into contact. It is electrically connected as appropriate. At the same time, the resin substrates 1 a and 1 b are mechanically connected by fitting and fixing in the region 10 of the relay element 2.

  As described above, in the present embodiment, when the resin substrates 1a and 1b are connected by the relay element 2, the relay element 2 is in contact with each other and integrated in the resin substrates 1a and 1b. take. Therefore, no load is applied to the connecting portions of the resin substrates 1a and 1b, and there is no concern about bending or the like, and a high strength connection is obtained.

  Further, for example, a plurality of resin substrates having different functions incorporating different electronic components can be connected by a relay element by appropriately combining a set of resin substrates. Thus, a component-embedded substrate having a high degree of freedom of recombination that enables the resin substrates to be freely recombined can be realized.

(Manufacturing method of component built-in board)
2 to 8 are schematic cross-sectional views illustrating the method of manufacturing the component-embedded substrate according to the first embodiment in the order of steps. In the present embodiment, a rewiring technique used for the pseudo SoC technique or the like is used.

First, as shown in FIG. 2A, a pin 42 serving as a TMV is erected on a support substrate 41.
Subsequently, as illustrated in FIG. 2B, a mold resin 43 is formed on the support substrate 41 so as to cover the pins 42. Thereby, a pseudo wafer in which the pins 42 are sealed with the mold resin 43 on the support substrate 41 is formed. The pseudo wafer is peeled from the support substrate 41.

Subsequently, as shown in FIG. 2C, the surface of the mold resin 43 is ground.
Specifically, the mold resin 43 on the upper surface of the pseudo wafer is removed by grinding, and the upper surfaces of the pins 42 are exposed.

Subsequently, as shown in FIG. 2D, an insulating film 44 is formed.
Specifically, for example, a photosensitive phenol-based resin, which is an insulating material, is applied to the upper surface of the pseudo wafer to a thickness of about 10 μm. The photosensitive phenolic resin is exposed and developed with, for example, tetramethylammonium hydroxide (TMAH), and then cured (cured) at about 200 ° C. to 250 ° C. (for example, 230 ° C.). An opening 44a for exposing a part of the upper surface of the pin 42 is formed in the photosensitive phenol resin. Thus, the insulating film 44 having the opening 44a is formed.

Subsequently, as shown in FIG. 3A, a plating seed layer 45 is formed.
Specifically, Ti (thickness of about 30 nm) and Cu (thickness of about 100 nm) are sequentially formed on the insulating film 44 including the upper surface of the pin 42 exposed from the opening 44a by, for example, sputtering. As described above, the plating seed layer 45 is formed on the insulating film 44 including the upper surface of the pin 42.

Subsequently, as shown in FIG. 3B, a resist pattern 46 is formed.
Specifically, a resist is applied on the plating seed layer 45 to a thickness of about 8 μm, for example. The resist is developed by exposure, for example, TMAH. Thus, a resist pattern 46 having an opening 46a is formed.

Subsequently, as shown in FIG. 3C, a wiring 47 is formed.
Specifically, Cu is deposited to a thickness of, for example, about 5 μm so as to fill the opening 46a by electrolytic plating using the plating seed layer 45 as a power feeding layer. Thereby, the wiring 47 is formed.

Subsequently, as shown in FIG. 3D, the resist pattern 46 and the plating seed layer 45 thereunder are removed.
Specifically, the resist pattern 46 is removed using acetone or the like. Next, the Cu layer of the plating seed layer 45 exposed by removing the resist pattern 46 is removed by wet etching using, for example, potassium sulfate as an etching solution. Next, the Ti layer of the plating seed layer 45 exposed by removing the Cu layer is removed by dry etching using, for example, a mixed gas of CF ₄ (carbon tetrafluoride) and O ₂ (oxygen).

Subsequently, as shown in FIG. 4A, a sacrificial layer 48 to be a recess forming layer is formed.
Specifically, a resist material made of, for example, a photosensitive epoxy resin is applied on the wiring 47 to a thickness of about 300 μm. Thereby, the sacrificial layer 48 is formed.

  Subsequently, as shown in FIG. 4B, dicing is performed using, for example, a normal diamond blade, and individual pieces having a desired size are cut out. In this way, a connector part 49 for embedding as shown in FIG. 4C is obtained.

Subsequently, as shown in FIG. 5A, the connector component 49 is disposed on the support substrate 51 together with the IC semiconductor chip 52 and the chip component 53.
Subsequently, as illustrated in FIG. 5B, a mold resin 54 is formed on the support substrate 51 so as to cover the connector component 49, the IC semiconductor chip 52, and the chip component 53. As a result, a pseudo wafer in which the connector component 49, the IC semiconductor chip 52, and the chip component 53 are sealed with the mold resin 54 on the support substrate 51 is formed. The pseudo wafer is peeled from the support substrate 51. In order to adjust the thickness of the pseudo wafer, grinding may be performed by, for example, back grinding.

Subsequently, as shown in FIG. 5C, an insulating film 55 is formed.
Specifically, for example, a photosensitive phenol-based resin, which is an insulating material, is applied to the upper surface of the pseudo wafer to a thickness of about 10 μm. The photosensitive phenolic resin is exposed and developed with, for example, TMAH, and then cured at about 200 ° C. to 250 ° C. (for example, 230 ° C.). Openings 55a, 55b, and 55c that expose a part of the lower surface of the pin 42 of the connector part 49, a part of the electrode of the IC semiconductor chip 52, and a part of the electrode of the chip part 53 are formed in the photosensitive phenol resin. The Thus, the insulating film 55 having the openings 55a, 55b, and 55c is formed.

Subsequently, as shown in FIG. 5D, a plating seed layer 56 is formed.
Specifically, Ti (thickness of about 30 nm) and Cu (thickness of about 100 nm) are sequentially formed by sputtering, for example. Ti and Cu are an insulating film 55 including the lower surface of the pin 42 of the connector part 49 exposed from the openings 55a, 55b, and 55c, the part of the electrode of the IC semiconductor chip 52, and the part of the electrode of the chip part 53. Deposited on top. As described above, the plating seed layer 56 is formed on the insulating film 55 including the lower surface of the pin 42 of the connector component 49, a part of the electrode of the IC semiconductor chip 52, and a part of the electrode of the chip component 53.

Subsequently, as shown in FIG. 6A, a resist pattern 57 is formed.
Specifically, a resist is applied on the plating seed layer 56 to a thickness of about 8 μm, for example. The resist is developed by exposure, for example, TMAH. Thus, a resist pattern 57 having openings 57a, 57b, and 57c is formed.

Subsequently, as shown in FIG. 6B, wirings 58a, 58b, and 58c are formed.
Specifically, Cu is deposited to a thickness of, for example, about 5 μm so as to fill the openings 57a, 57b, and 57c by electrolytic plating using the plating seed layer 56 as a power feeding layer. Thereby, wirings 58a, 58b, and 58c are formed. The wirings 58a, 58b, and 58c electrically connect the connector component 49 and the IC semiconductor chip 52, the IC semiconductor chip 52 and the chip component 53, and the chip component 53 and the connector component 49, respectively.

Subsequently, as shown in FIG. 6C, the resist pattern 57 and the plating seed layer 56 thereunder are removed.
Specifically, the resist pattern 57 is removed using acetone or the like. Next, the Cu layer of the plating seed layer 56 exposed by removing the resist pattern 57 is removed by wet etching using, for example, potassium sulfate as an etching solution. Next, the Ti layer of the plating seed layer 56 exposed by removing the Cu layer is removed by dry etching using, for example, a mixed gas of CF ₄ and O ₂ .

Subsequently, as shown in FIG. 6D, an insulating film 59 is formed.
Specifically, for example, a photosensitive phenolic resin as an insulating material is applied to the thickness of about 10 μm on the insulating film 55 so as to embed between the wirings 58a and 58b, between the wirings 58b and 58c, and between the wirings 58c and 58a. . The photosensitive phenolic resin is exposed and developed with, for example, TMAH, and then cured at about 200 ° C. to 250 ° C. (for example, 230 ° C.). As described above, the insulating film 59 for protecting the wirings 58a, 58b, and 58c is formed on the photosensitive phenol resin.

  Subsequently, as shown in FIG. 7A, dicing is performed using, for example, a normal diamond blade, and individual pieces having a desired size are cut out. In this way, an individual piece 61 as shown in FIG. 7B is obtained.

Subsequently, as shown in FIG. 7C, a resin substrate 60 is formed.
Specifically, the sacrificial layer 48 of the connector part 49 of the individual piece 61 is removed using, for example, an N-methylpydroline-based stripping solution. As described above, the resin substrate 60 having the recess 62 on the side surface is formed. The connection terminal 47 a of the wiring 47 is exposed on the inner wall surface of the recess 62.

As shown in FIG. 7D, the relay element 70 is formed.
Specifically, for example, the wiring layer 64 is formed on the rigid mold resin 63 by a rewiring technique, and the relay element 70 is formed by cutting out to a desired size. The connection terminal 64 a is exposed on the surface of the wiring layer 64. Similarly to the resin substrate 60, the relay element 70 may include an electronic component such as an IC semiconductor chip or a chip component.

  Thereafter, as shown in FIG. 8A, a pair of resin substrates 60 are arranged so as to face each other with the relay element 70 therebetween. As shown in FIG. 8B, the side surfaces of the resin substrate 60 are brought into contact with each other so that the relay element 70 is inserted into each recess 62 of the pair of resin substrates 60. At this time, the relay element 70 is fitted and fixed in a region 65 in which the concave portions 62 are integrally formed to constitute a component built-in board. By fitting and fixing in the region 65 of the relay element 70, the connection terminal 47a of the pair of resin substrates 60 and the connection terminal 64a of the relay element 70 come into contact, and the IC semiconductor chip 52 and the chip component 53 are electrically connected as appropriate. Is done. At the same time, the resin substrates 60 are mechanically connected to each other by fitting and fixing in the region 65 of the relay element 70. Thus, the component built-in substrate is formed.

[Second Embodiment]
In the present embodiment, the component built-in substrate and the manufacturing method thereof are disclosed as in the first embodiment, but differ from the first embodiment in that the material of the relay element of the component built-in substrate is different.

(Configuration of component built-in board)
FIG. 9 is a schematic cross-sectional view showing the configuration of the component-embedded substrate according to the second embodiment. (A) shows each component member not mounted, (b) shows a state at a low temperature when each component member is mounted and becomes a component built-in board, and (c) shows each component member mounted and a component built-in substrate. It represents the state at normal temperature.
This component built-in substrate has a plurality of resin substrates, and in the illustrated example, a pair of resin substrates 1a and 1b and a relay element 3 connecting them are shown.

  As shown in FIG. 9A, the resin substrate 1a includes, as electronic components, an IC semiconductor chip 11 and a chip component 12 such as a resistor, a capacitor, and an inductor, which are sealed with a mold resin 13, and at least one side surface 14 is formed. A recess 15 serving as a female connector is formed. Wiring layers 16 and 17 are formed on the IC semiconductor chip 11 and the chip component 12 and the inner wall surface of the recess 15 by a rewiring technique used in the pseudo SoC technique or the like. On the surface of the wiring layer 17, connection terminals 17 a that are exposed on the inner wall surface of the recess 15 are formed. The wirings of the wiring layers 16 and 17 are electrically connected by TMV 18 embedded in the mold resin 13.

  As shown in FIG. 9A, the resin substrate 1b includes, as electronic components, an IC semiconductor chip 21 and a chip component 22 such as a resistor, a capacitor, and an inductor, which are sealed with a mold resin 23, and at least one side surface 24. A recess 25 serving as a female connector is formed. Wiring layers 26 and 27 are formed on the IC semiconductor chip 21 and the chip component 22 and the inner wall surface of the recess 25 by a rewiring technique used in the pseudo SoC technique or the like. On the surface of the wiring layer 27, a connection terminal 25a exposed on the inner wall surface of the recess 25 is formed. The wirings of the wiring layers 26 and 27 are electrically connected by a TMV 28 embedded in the mold resin 23.

  Here, the resin substrates 1a and 1b have, for example, the same shape and size, but may have different shapes or sizes. The IC semiconductor chips 11 and 21 have different functions, for example, but may have the same functions. Similarly, the chip components 12 and 22 have different functions, for example, but may have the same function. The mold resins 13 and 23 are, for example, the same material, but may be different materials. The recesses 15 and 25 have the same shape and size.

  As shown in FIG. 9A, the relay element 3 is made of recesses 15 and 25 made of a material having a higher coefficient of thermal expansion (a larger coefficient of linear thermal expansion) than the mold resins 13 and 23 of the resin substrates 1a and 1b, for example, Cu4. It is formed in a shape and size suitable for A wiring layer 32 (insulating layer and wiring) is formed on the back surface of the relay element 3, and a connection terminal 32 a is formed on the surface of the wiring layer 32. The relay element 2 is detachable from the resin substrates 1a and 1b. Similarly to the resin substrates 1a and 1b, the relay element 3 may include electronic components such as an IC semiconductor chip and a chip component. In this case, for example, it is conceivable to cover the electronic component with a copper plate via a predetermined insulating layer.

  In this embodiment, as shown in FIG. 9B, the resin substrates 1a and 1b are in contact with each other at the side surfaces 14 and 24. For example, the resin substrates 1a and 1b are formed by the recesses 15 and 25 at a temperature lower than room temperature. The relay element 3 is fitted and fixed in the region 10 thus formed to constitute a component built-in board. The relay element 3 is formed in a component built-in board. Since Cu4 of the relay element 3 has a higher coefficient of thermal expansion than the mold resins 13 and 23 of the resin substrates 1a and 1b, the relay element 3 expands in the region 10 as shown in FIG. As a result, the fitting and fixing of the relay element 3 in the region 10 becomes more firm, and the connection terminals 15a and 25a of the resin substrates 1a and 1b and the connection terminal 32a of the relay element 3 are reliably in contact with each other, and the IC semiconductor chip 11 21 and chip parts 12 and 22 are appropriately electrically connected. At the same time, the resin substrates 1 a and 1 b are reliably mechanically connected by a firmer fitting and fixing in the region 10 of the relay element 3.

  As described above, in the present embodiment, when the resin substrates 1a and 1b are connected by the relay element 3, the relay element 3 comes into contact with each other and is integrated into the integrated resin substrate 1a and 1b. take. Therefore, no load is applied to the connecting portions of the resin substrates 1a and 1b, and there is no concern about bending or the like, and a high strength connection is obtained. Furthermore, in this embodiment, since the relay element 3 has a higher coefficient of thermal expansion than the resin substrates 1a and 1b, the resin substrates 1a and 1b are more reliably connected electrically and mechanically.

  Further, for example, a plurality of resin substrates having different functions incorporating different electronic components can be connected by a relay element by appropriately combining a set of resin substrates. Thus, a component-embedded substrate having a high degree of freedom of recombination that enables the resin substrates to be freely recombined can be realized.

(Manufacturing method of component built-in board)
FIG. 10 is a schematic cross-sectional view showing the main steps of the method for manufacturing a component-embedded substrate according to the second embodiment. In the present embodiment, a rewiring technique used for the pseudo SoC technique or the like is used.

  First, similarly to the first embodiment, the steps of FIGS. 2A to 7C are performed to form the resin substrate 60 of FIG. 7C.

Subsequently, as shown in FIG. 10A, the relay element 80 is formed.
More specifically, a wiring layer 82 including an insulating film and wiring is formed on a material having a higher thermal expansion coefficient than the mold resin 54 of the resin substrate 60, for example, a copper plate 81 by a rewiring technique, and is cut out to an intended size. A relay element 80 is formed. The connection terminal 82 a is exposed on the surface of the wiring layer 82. Similarly to the resin substrate 60, the relay element 80 may include an electronic component such as an IC semiconductor chip or a chip component. In this case, for example, it is conceivable to cover the electronic component with a copper plate via a predetermined insulating layer.

  Subsequently, as illustrated in FIG. 10B, the pair of resin substrates 60 are disposed so as to face each other through the relay element 80 at a temperature lower than normal temperature. As shown in FIG. 10C, the side surfaces of the resin substrate 60 are brought into contact with each other so that the relay element 80 is inserted into each recess 62 of the pair of resin substrates 60. At this time, the relay element 80 is fitted and fixed in a region 65 in which the concave portions 62 are integrally formed to constitute a component built-in board. By fitting and fixing in the region 65 of the relay element 80, the connection terminal 47a of the pair of resin substrates 60 and the connection terminal 82a of the relay element 80 come into contact, and the IC semiconductor chip 52 and the chip component 53 are electrically connected as appropriate. Is done. At the same time, the resin substrates 60 are mechanically connected to each other by fitting and fixing in the region 65 of the relay element 80.

As shown in FIG. 10D, in the component-embedded substrate, the relay element 80 expands in the region 65 at room temperature, and the set of resin substrates 60 are more reliably electrically and mechanically connected. Cu has a linear thermal expansion coefficient of about 17 × 10 ⁻⁶ / K. For example, when a copper piece having a size of about 5 mm × 1 mm × 0.3 mm changes in temperature from 0 ° C. to 20 ° C., the expansion amount is about 2 μm. It is. When the relay element 80 having the same size as the copper piece is used, the relay element 80 expands in the region 65 by about 2 μm at room temperature. Therefore, the set of resin substrates 60 is stably and electrically connected and fixed by the relay element 80 without destroying the mold resin 54 of the resin substrate 60.

  Hereinafter, various aspects of the component built-in substrate and the manufacturing method thereof will be collectively described as additional notes.

(Additional remark 1) The board | substrate with which the electronic component was sealed with resin and the recessed part was formed in the at least 1 side surface,
A relay element detachably attached to the substrate;
Including
A set of the substrates are in contact with each other facing the side surfaces, and the relay element is fitted into an area formed by the set of the recesses, and is electrically and mechanically connected by the relay element. A component-embedded board characterized by

  (Supplementary note 2) The component built-in board according to supplementary note 1, wherein the relay element includes a material having a higher coefficient of thermal expansion than the resin.

(Additional remark 3) The said board | substrate has the 1st terminal electrically connected with the said electronic component formed in the inner wall face of the said recessed part,
The component built-in board according to appendix 1 or 2, wherein a second terminal connected to the first terminal is formed on the surface of the relay element.

  (Additional remark 4) The said relay element has an electronic component, The component built-in board | substrate of any one of Additional remarks 1-3 characterized by the above-mentioned.

(Appendix 5) A step of sealing the electronic component with resin and forming a recess on at least one side surface to constitute a substrate;
Forming a detachable relay element with respect to the concave portion of the substrate;
A pair of the substrates are brought into contact with each other via the relay element between the side surfaces, the relay element is fitted into a region formed by the two concave portions, and the substrates are electrically and mechanically connected by the relay element. Forming a component-embedded substrate to be connected
A method of manufacturing a component-embedded substrate, comprising:

  (Additional remark 6) The said relay element has a material with a higher coefficient of thermal expansion than the said resin, The manufacturing method of the component built-in board of Additional remark 5 characterized by the above-mentioned.

  (Additional remark 7) After forming a recessed part formation layer and sealing with the said resin so that the said recessed part formation layer may be covered, the said recessed part formation layer is removed and the said recessed part is formed, It is characterized by the above-mentioned A method for manufacturing a component-embedded board as described in 1.

(Appendix 8) Forming a first terminal electrically connected to the electronic component on the inner wall surface of the recess of the substrate,
The method for manufacturing a component-embedded board according to any one of appendices 5 to 7, wherein a second terminal connected to the first terminal is formed on a surface of the relay element.

  (Additional remark 9) Electronic component is formed in the said relay element, The manufacturing method of the component built-in board of any one of Additional remark 5-8 characterized by the above-mentioned.

1a, 1b, 60 Resin substrates 2, 3, 70, 80 Relay elements 10, 65 Regions 11, 21, 52 IC semiconductor chips 12, 22, 53 Chip components 13, 23, 31, 43, 54, 63 Mold resin 14, 24 Side surface 15, 25, 62 Recess 47, 58a, 58b, 58c Wiring 17a, 27a, 32a, 47a, 64a, 81a Connection terminal 18 TMV
16, 17, 26, 27, 32, 64 Wiring layers 41, 51 Support substrate 42 Pins 44, 59 Insulating films 44a, 46a, 55a, 55b, 55c, 57a, 57b, 57c Openings 45, 56 Plating seed layers 46, 57 Resist pattern 48 Sacrificial layer 49 Connector component 61 Single piece 81 Copper plate

Claims (8)

A substrate in which an electronic component is sealed with resin and a recess is formed on at least one side surface;
A relay element detachably attached to the substrate;
Including
A set of the substrates are in contact with each other facing the side surfaces, and the relay element is fitted into an area formed by the set of the recesses, and is electrically and mechanically connected by the relay element. A component-embedded board characterized by   The component built-in board according to claim 1, wherein the relay element includes a material having a higher thermal expansion coefficient than the resin. In the substrate, a first terminal electrically connected to the electronic component is formed on an inner wall surface of the recess,
The component built-in board according to claim 1, wherein a second terminal connected to the first terminal is formed on a surface of the relay element.   The component built-in substrate according to claim 1, wherein the relay element includes an electronic component. Sealing the electronic component with resin, forming a recess on at least one side surface, and configuring the substrate;
A step of forming a detachable relay element with respect to the concave portion of the substrate; and a pair of the substrates are brought into contact with each other via the relay element between the side surfaces, and the relay element is formed in a region formed by the two concave portions. And forming a component built-in board for electrically and mechanically connecting the boards with the relay element;
A method of manufacturing a component-embedded substrate, comprising:   The method for manufacturing a component-embedded board according to claim 5, wherein the relay element includes a material having a higher thermal expansion coefficient than the resin.   The concave portion forming layer is formed and sealed with the resin so as to cover the concave portion forming layer, and then the concave portion forming layer is removed to form the concave portion. A method for manufacturing a component-embedded substrate.   The method for manufacturing a component-embedded substrate according to claim 5, wherein an electronic component is formed on the relay element.

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