JP6003369B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to the production how the semiconductor device.

  In recent years, with the spread of ubiquitous terminals such as smartphones and tablet terminals, semiconductor devices (LSI: Large Scale Integration) used in these electronic devices are becoming thinner, lighter, more multifunctional, higher performance, and lower. Cost reduction and high-density mounting are required. There is also a need for new mounting technology that can mount devices such as logic, memory, sensors, and passive components used in these electronic devices on a substrate at higher density and lower cost than conventional devices.

  In response to these requirements, a technology called SoC (System on a chip) and a technology called SiP (System in Package) have been developed. In SoC, a plurality of devices having different functions are directly formed on a single wafer. In SiP, devices having different functions are individually formed and mounted on a substrate called an interposer to form one package (semiconductor device).

  However, although SoC has an advantage that device miniaturization is relatively easy, there is a problem that devices that can be manufactured on the same wafer are limited due to differences in design rules and application processes.

  On the other hand, in SiP, since individual devices can be manufactured by an optimized process, there are few restrictions on devices to be integrated. However, since the interposer and each device are connected by bonding wires or bumps, there is a problem that there is a limit to increasing the density and reducing the thickness of the package.

  In recent years, a technique called pseudo SoC has been proposed as a new integration technique that simultaneously realizes the merits of both SoC and SiP. In the pseudo SoC, devices having different functions are individually manufactured, and these devices are integrated with a resin to form a single wafer in a pseudo manner. Then, using existing microfabrication technology, wiring for electrically connecting the devices is formed on the pseudo wafer.

  Hereinafter, a device in which a plurality of devices are integrated with a resin to form a single wafer is called a pseudo wafer. A semiconductor chip formed using a pseudo wafer is referred to as a pseudo SoC chip.

  In the pseudo SoC, there are few restrictions on devices to be integrated, and a new semiconductor device (LSI) can be developed at a low cost. In addition, since the wiring for electrically connecting the devices is formed using the existing microfabrication technology, the wiring can be easily miniaturized and high integration can be achieved. Furthermore, since no interposer is required, the thickness can be reduced.

JP 2004-103955 A JP 2009-170492 A JP2012-15191A

Relates to a manufacturing method of a semiconductor device having a pseudo-SoC chip, it can avoid warping of the placebo wafer, and an object thereof is to provide a manufacturing how the semiconductor device can be manufactured with good yield a semiconductor device.

According to one aspect of the disclosed technology, a step of attaching a soluble film to a wall surface of the opening of a substrate provided with an opening penetrating from one surface side to the other surface side ; placing a plurality of devices in the opening, by injecting resin into the opening, forming a pseudo wafer between the substrate and the device are integrated, the substrate, the soluble film, the Forming a resin and a first insulating layer on the plurality of devices; forming wirings electrically connected to the plurality of devices on the first insulating layer ; and and obtaining a pseudo SoC chip with said wiring, a step of dissolving the soluble membrane water, with an alkaline aqueous solution or an acidic aqueous solution, after the step of dissolving the soluble membrane, separating the pseudo SoC chip from the substrate That production how a semiconductor device having a step is provided.

  According to the semiconductor device manufacturing method and the pseudo wafer according to the above aspect, the amount of resin to be used may be small, so that the warp of the pseudo wafer is suppressed. Further, since the pseudo wafer is less warped, alignment errors and mounting errors are less likely to occur when mounting the pseudo wafer to the semiconductor manufacturing apparatus. Thereby, the semiconductor device provided with the pseudo SoC chip can be manufactured with a good yield.

  Furthermore, since the amount of resin to be used may be small, the stress accumulated when the resin is cured is small. Therefore, since the stress released during dicing is also reduced, the pseudo SoC chip is less likely to be damaged, and the yield of the semiconductor device having the pseudo SoC chip is further improved.

FIG. 1 is a plan view of a substrate used in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a sectional view (No. 5) showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 8 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 9 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIGS. 13A and 13B are diagrams illustrating an example of a method for forming a resin film. 14A to 14C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a modification.

  Hereinafter, before describing the embodiment, a preliminary matter for facilitating understanding of the embodiment will be described.

  As described above, when the pseudo SoC technology is used, there are few restrictions on devices to be integrated, and a high-performance, high-density and thin semiconductor device can be manufactured. However, in the pseudo SoC technique, since the pseudo wafer is formed of resin, a large warp is likely to occur as the resin is cured.

  If there is a large warp in the pseudo wafer, a mounting error may occur when the pseudo wafer is mounted on a semiconductor manufacturing apparatus (for example, a film forming apparatus, an exposure apparatus, a transfer apparatus, etc.), or the focus may not be adjusted during exposure. A problem may occur or an alignment error may occur when aligning with a semiconductor manufacturing apparatus. In addition, the stress accumulated in the resin due to dicing is released, and the wiring on the pseudo wafer may be destroyed.

  In order to correct the warpage of the pseudo wafer, it has been proposed to bond a correction member formed of a material having a small coefficient of thermal expansion and a high Young's modulus under the pseudo wafer. However, this method has a drawback that the thinning of the semiconductor device is hindered due to the correction member.

  In order to reduce warpage, it has also been proposed to form a pseudo wafer by laminating a plurality of resin layers having different Young's moduli. However, in this method, peeling is likely to occur at the interface of the resin layer, and the reliability is not sufficient.

  Furthermore, a support body provided with a plurality of recesses is used, a semiconductor chip is inserted into each recess, the support body and the semiconductor chip are integrated with sealing resin, and then wiring is formed on the sealing resin A method to do this has also been proposed. In this method, the support is polished and removed after the wiring is formed. However, by removing the support, the stress accumulated in the sealing resin is released, and the wiring may be destroyed.

  The following embodiments relate to a method of manufacturing a semiconductor device including a pseudo SoC chip, a method of manufacturing a semiconductor device that can avoid warping of the pseudo wafer and can manufacture the semiconductor device with a high yield, and a pseudo wafer used in the manufacturing method. explain.

(First embodiment)
FIG. 1 is a plan view of a substrate used in the method for manufacturing a semiconductor device according to the first embodiment, and FIGS. 2 to 6 are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment in the order of steps. 2-6 is sectional drawing in the position shown by the II line | wire in FIG.

  First, as shown in FIG. 1 and FIG. 2A, a substrate 11 provided with a plurality of rectangular openings 11a penetrating from one surface side to the other surface side is prepared.

  The substrate 11 is preferably formed of a material having high rigidity such as silicon, ceramics, glass, or quartz. In this embodiment, a silicon wafer having a diameter of 6 inches and a thickness of 650 μm is used as the substrate 11. Then, a predetermined portion of the substrate 11 is cut into a rectangle by ultrasonic processing or the like to form the opening 11a.

  As will be described later, a plurality of devices are arranged in the opening 11a. When these devices are arranged in the opening 11a, the size of the opening 11a is determined so that the gap between the wall surface of the opening 11a and the device is, for example, 2 mm to 3 mm.

  Next, the temporary bonding film 12 is bonded to the lower surface side of the substrate 11 as shown in FIG. Then, using a device such as a chip bonder, the devices 13a and 13b are arranged on the temporary bonding film 12 in the opening 11a with the electrode formation surface facing down.

  The devices 13a and 13b are modular components such as logic, memory, sensors, or passive components manufactured individually by a method optimized for the devices 13a and 13b. In the present embodiment, it is assumed that at least one of the devices 13a and 13b is a semiconductor chip on which a semiconductor element such as a transistor is formed. The devices 13a and 13b are arranged, for example, separated from each other by several hundred μm.

  In the present embodiment, two devices 13a and 13b are arranged in one opening 11a, but the number of devices arranged in the opening 11a is not limited.

  Next, an insulating resin 14 such as an epoxy resin or an acrylic resin is filled in the opening 11a. For example, an additive such as a filler may be added to the resin 14 in order to adjust the viscosity.

  In this embodiment, since the devices 13a and 13b are fixed by the temporary bonding film 12, the devices 13a and 13b are not displaced when the resin 14 is filled.

  Next, the resin 14 is cured. Then, after the curing of the resin 14 is completed, the temporary bonding film 12 is peeled off. In this manner, the pseudo wafer 10 in which the devices 13a and 13b and the substrate 11 are integrated with the resin 14 is formed. In the following steps, a wiring layer is formed on the pseudo wafer 10 using an existing semiconductor manufacturing apparatus.

  That is, as shown in FIG. 3A, the substrate 11 is inverted so that the electrode formation surfaces of the devices 13a and 13b face up. Thereafter, a conductive seed layer 15 is formed on the entire upper surface of the pseudo wafer 10 by a method such as sputtering.

  In the present embodiment, the seed layer 15 has a two-layer structure of a Ti (titanium) layer having a thickness of 20 nm and a Cu (copper) layer having a thickness of 100 nm thereon. The Ti layer has an effect of improving the adhesion between the base, the Cu layer, and pins 17 described later, and an effect of preventing oxidation and diffusion of Cu.

  Next, as shown in FIG. 3B, a photoresist is applied on the seed layer 15 to form a photoresist film 16. The thickness of the photoresist film 16 is about 8 μm, for example.

  Thereafter, the photoresist film 16 is exposed through a predetermined exposure mask, and then developed with, for example, TMAH (tetramethylammonium hydroxide) to form openings 16a through which the electrodes of the devices 13a and 13b are exposed.

  Next, as shown in FIG. 3C, Cu is electroplated to a thickness of, for example, 3 μm using the seed layer 15 as a power feeding layer, and conductive pins 17 made of Cu are formed on the electrodes in the openings 16a. To do.

  Next, as shown in FIG. 3D, the photoresist film 16 is removed using a stripping solution such as acetone. Further, the portion of the seed layer 15 that is not covered with the pins 17 is removed by etching, and each pin 17 is electrically separated.

The Cu layer of the seed layer 15 can be removed by wet etching using, for example, potassium sulfate as an etchant. Further, the Ti layer of the seed layer 15 can be removed by, for example, wet etching using an ammonium fluoride aqueous solution as an etchant or dry etching using a mixed gas of CF ₄ and O ₂ .

  Next, as shown in FIG. 3E, a photosensitive phenol resin is applied to the entire upper surface of the pseudo wafer 10 to a thickness of 4 μm, for example, to form an insulating layer 18. Thereafter, the insulating layer 18 is cured by heat treatment at a temperature of 200 ° C. to 250 ° C. The insulating layer 18 may be formed of an inorganic material such as silicon oxide instead of the photosensitive phenol resin. The same applies to other insulating layers to be described later.

  Next, as shown in FIG. 4A, the upper portion of the insulating layer 18 is removed by a method such as chemical mechanical polishing (CMP) until the upper surface of the pin 17 is exposed.

  Next, as shown in FIG. 4B, on the insulating layer 18, for example, a photosensitive phenol resin is applied to a thickness of 2 μm to form an insulating layer 19. Thereafter, the insulating layer 19 is exposed using a predetermined exposure mask, and then development processing is performed to form grooves 19a in a predetermined pattern. The upper surface of the pin 17 is exposed at the bottom of these grooves 19a. After forming the groove 19a, the insulating layer 19 is cured (post-cured) by heat treatment at a temperature of 250 ° C., for example.

  Next, as shown in FIG. 4C, a seed layer 21 is formed on the entire upper surface of the pseudo wafer 10 by a method such as sputtering. The seed layer 21 has a two-layer structure of a Ti layer and a Cu layer, for example, like the seed layer 15 described above.

  Thereafter, as shown in FIG. 4D, Cu is electroplated to a thickness of, for example, 3 μm using the seed layer 21 as a power feeding layer, and a Cu layer 22 is formed on the seed layer 21. By this electrolytic plating, the groove 19a is filled with Cu.

  Thereafter, for example, heat treatment is performed at a temperature of 120 ° C. to 200 ° C. for 1 minute to 10 minutes to grow the Cu grains of the Cu layer 22 and to stabilize the film quality. In this embodiment, heat treatment is performed at a temperature of 150 ° C. for 2 minutes. The heat treatment after plating is preferably performed in an atmosphere having a low oxygen concentration, but may be performed in the air. Further, if the thickness of the Cu layer 22 is about 3 μm, the film is stabilized by growing Cu grains by leaving it at room temperature (20 ° C. to 25 ° C.) for about 24 hours.

  Next, as shown in FIG. 4E, the Cu layer 22 and the seed layer 21 are subjected to chemical mechanical polishing until the insulating layer 19 is exposed. Thereby, Cu remaining in the groove 19 a becomes the wiring 23.

  Next, as shown in FIG. 5A, a photosensitive phenol resin is applied to the entire upper surface of the pseudo wafer 10 to a thickness of, for example, 5 μm to form an insulating layer 24. Then, the insulating layer 24 is exposed through a predetermined exposure mask, and development processing is performed to form an opening 24a through which a predetermined portion of the wiring 23 is exposed. Thereafter, the insulating layer 24 is cured (post-cured) by heat treatment at a temperature of 250 ° C., for example.

  Next, as shown in FIG. 5B, a seed layer 25 is formed on the entire upper surface of the pseudo wafer 10 by a method such as sputtering. The seed layer 25 also has a two-layer structure of a Ti layer and a Cu layer, for example, like the seed layer 15 described above.

  Next, as shown in FIG. 5C, a photoresist is applied on the seed layer 25 to a thickness of 4 μm, for example, to form a photoresist film 26. Thereafter, the photoresist film 26 is exposed through a predetermined exposure mask, and development processing is performed, thereby forming an opening 26 a where the seed layer 25 is exposed at a position corresponding to the groove 24 a of the insulating layer 24.

  Next, as shown in FIG. 5D, Cu is electroplated to a thickness of 3 μm, for example, on the seed layer 25 in the opening 26a using the seed layer 25 as a power feeding layer. As a result, a wiring 27 made of Cu is formed in the opening 26 a of the photoresist film 26.

  Next, as shown in FIG. 6A, the photoresist film 26 is removed with a stripping solution such as acetone. Further, the portion of the seed layer 25 not covered with the wiring 27 is removed by etching, so that the wirings 27 are electrically separated.

  Next, steps required until a structure shown in FIG.

  After the wirings 27 are electrically separated in the above process, a photosensitive phenol resin is applied to the entire upper surface of the pseudo wafer 10 to form the insulating layer 28. Thereafter, the insulating layer 28 is exposed through a predetermined exposure mask, and development processing is performed to form an opening through which a predetermined portion of the wiring 27 is exposed. Next, heat treatment is performed at a temperature of, for example, 250 ° C. to cure (post-cure) the insulating layer 28.

  Next, after forming a conductive seed layer (not shown) on the entire upper surface of the pseudo wafer 10, a photoresist is applied on the seed layer to form a photoresist film (not shown). Then, the photoresist film is exposed through a predetermined exposure mask, and thereafter development processing is performed to form grooves in a predetermined pattern.

  Thereafter, Cu is electroplated on the seed layer in the groove of the photoresist film using the seed layer as a power feeding layer. In this manner, the wiring 29 that is electrically connected to the predetermined wiring 27 is formed on the insulating layer 28.

  Next, after removing the photoresist film with a stripping solution such as acetone, the portion of the seed layer not covered with the wiring 29 is removed by etching. Then, the insulating layer 30 is formed on the entire upper surface of the pseudo wafer 10 by using, for example, a photosensitive phenol resin.

  Thereafter, the insulating layer 30 is exposed through a predetermined exposure mask, and then development processing is performed to form a contact hole 30a in which a predetermined portion of the wiring 29 is exposed.

  In this way, a plurality of pseudo SoC chips 40 are formed simultaneously using one pseudo wafer 10.

  Next, as shown in FIG. 6C, for example, by laser dicing, a portion of the resin 14 (a portion indicated by a broken line arrow in FIG. 6C) is cut for each opening 11a, and FIG. The pseudo SoC chip 40 is cut out as shown in FIG. Thereafter, the pseudo SoC chip 40 is sealed in a package. In this way, the semiconductor device is completed.

  The substrate 11 after the pseudo SoC chip 40 is cut out can be removed by immersing it in N-methylpyrrolidone or the like or ashing with ozone to remove the resin 14 attached to the wall surface of the opening 11a. Can be used. When it is not necessary to reuse the substrate 11, the pseudo SoC chip 40 may be cut out by cutting the substrate 11 using a diamond blade or the like.

  In the present embodiment, as described above, the substrate 11 having high rigidity is used. After the devices 13a and 13b are arranged in the opening 11a of the substrate 11, the resin 14 is filled in the opening 11a and the pseudo wafer 10 is filled. Form. For this reason, the pseudo wafer 10 is unlikely to be warped, and an alignment error at the time of alignment in a semiconductor manufacturing apparatus (for example, a film forming apparatus, an exposure apparatus, a transfer apparatus, etc.) Installation mistakes when doing so are avoided.

  In the present embodiment, since the amount of the resin 14 used is small, the stress accumulated in the resin 14 when the resin 14 is cured is small. Therefore, even if the stress accumulated in the resin 14 is released when the pseudo SoC chip 40 is cut out from the pseudo wafer 10, the wiring (wirings 23, 29, etc.) formed on the pseudo wafer 10 is not destroyed. Absent.

  For the above reasons, according to the manufacturing method according to the present embodiment, the manufacturing yield of the semiconductor device using the pseudo SoC chip is improved.

  Furthermore, according to the present embodiment, since the amount of the resin 14 used is small and the substrate 11 can be used repeatedly, there is an advantage that the manufacturing cost of the semiconductor device using the pseudo SoC chip can be reduced.

(Second Embodiment)
7 to 12 are cross-sectional views showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps. This embodiment will also be described with reference to FIG. 7 to 12 are cross-sectional views taken along the line II in FIG.

  First, as in the first embodiment, a substrate 11 provided with a plurality of openings 11a is prepared (see FIG. 1).

  Thereafter, as shown in FIG. 7A, a resin film 51 covering the wall surface of the opening 11a is formed. The thickness of the resin film 51 is, for example, about 1 μm to 5 mm. Further, the resin film 51 is formed of a material that dissolves in water or an alkaline aqueous solution in a process described later.

  Such materials include water-soluble resins such as hydroxyethyl cellulose, polyvinyl alcohol, polyvinyl acetal, polyvinyl butyral, and polyvinyl pyrrolidone.

  In addition, carboxylic acid-containing alkali-soluble resins containing methacrylic acid, acrylic acid, or benzoic acid units, styrene-maleic anhydride copolymers, phenolic resins, alkali-soluble resins containing hexafluorocarbinol groups, etc. The resin film 51 may be formed.

  In this embodiment, the resin film 51 is formed from hydroxyethyl cellulose. The resin film 51 is an example of a soluble film.

  13A and 13B are diagrams illustrating an example of a method for forming the resin film 51. FIG. For example, as illustrated in FIG. 13A, a rectangular frame plate 45 is disposed inside the opening 11 a of the substrate 11. Then, as shown in FIG.13 (b), the water-soluble resin or alkali-soluble resin 51a mentioned above is inject | poured into the clearance gap between the wall surface of the opening part 11a, and the frame board 45. FIG. Then, after the resin 51a is cured, the frame plate 45 is removed. Thereby, as shown in FIG. 7A, a resin film 51 covering the wall surface of the opening 11a is obtained.

  However, the formation method of the resin film 51 is not limited to this. For example, after filling the opening 11a with the resin 51a, the resin film 51 may be formed by removing only the resin 51a in the vicinity of the wall surface of the opening 11a with a drill or the like and removing the resin 51a in other portions.

  Alternatively, the resin film 51 may be formed by filling a resin 51a in the opening 11a and then removing a predetermined portion of the resin 51a using a photolithography method.

  In the present embodiment, as described above, the thickness of the resin film 51 is set to about 1 μm to 5 mm. However, the thickness of the resin film 51 may be determined in consideration of ease of dissolution in the liquid, and may be 1 μm or less. The thickness of the resin film 51 may be 5 mm or more, but in that case, the number of pseudo SoC chips that can be manufactured from one pseudo wafer is reduced.

  Next, as illustrated in FIG. 7B, the temporary bonding film 12 is connected to the lower side of the substrate 11. Then, using a device such as a chip bonder, the devices 13 a and 13 b are arranged on the temporary bonding film 12 in the opening 11 with the electrode formation surface facing down.

  Then, after filling the opening 11a with an insulating resin 14 such as an epoxy resin or an acrylic resin, the resin 14 is cured. After the curing of the resin 14 is completed, the substrate 11 is inverted and the temporary bonding film 12 is peeled off.

  In this way, a pseudo wafer 50 in which the devices 13a and 13b and the substrate 11 are integrated with the resin 14 as shown in FIG. 7C is formed.

  Next, as shown in FIG. 7D, a positive photoresist is applied on the pseudo wafer 50 to a thickness of, for example, 1 μm to form an insulating layer 52. Then, after exposing the insulating layer 52 using a predetermined exposure mask, a development process is performed to form an opening 52a through which the electrodes of the devices 13a and 13b are exposed.

  Next, as shown in FIG. 7E, a seed layer 53 is formed on the entire upper surface of the pseudo wafer 50 by a method such as sputtering. Also in this embodiment, the seed layer 53 has a two-layer structure of a Ti layer and a Cu layer, as in the first embodiment.

  Next, as shown in FIG. 8A, a photoresist is applied on the seed layer 53 to a thickness of 8 μm, for example, to form a photoresist film 54. Then, after exposing the photoresist film 54 through a predetermined exposure mask, development processing is performed to form an opening 54a through which the seed layer 53 is exposed at a position corresponding to the electrodes of the devices 13a and 13b.

  Next, as shown in FIG. 8B, using the seed layer 53 as a power feeding layer, Cu is electroplated on the seed layer 53 in the opening 54a to a thickness of 3 μm, for example. Thereby, the pin 55 electrically connected to the electrodes of the devices 13a and 13b is formed inside the opening 54a.

  Next, as shown in FIG. 8C, the photoresist film 54 is removed by a stripping solution such as acetone. Thereafter, the portion of the seed layer 53 that is not covered with the pins 55 is removed by etching, and the pins 55 are electrically separated.

  Next, as shown in FIG. 8D, a photosensitive phenol resin is applied to the entire upper surface of the pseudo wafer 50 to a thickness of 4 μm, for example, to form the insulating layer 56. Then, the insulating layer 56 is exposed through a predetermined exposure mask, and development processing is performed to form a slit 56a through which the insulating layer 52 is exposed. The slit 56a is formed above the resin film 51 and has a rectangular frame shape surrounding the pseudo SoC chip formation region when viewed from above.

  Next, as shown in FIG. 8E, the upper portion of the insulating layer 56 is removed by a method such as chemical mechanical polishing to expose the upper surface of the pin 55.

  Next, as shown in FIG. 9A, for example, a photosensitive phenol resin is applied on the insulating layer 56 to a thickness of 2 μm to form the insulating layer 57. Then, after exposing the insulating layer 57 through a predetermined exposure mask, a development process is performed to form a slit 57a through which the insulating layer 52 above the resin film 51 is exposed, and the groove 57b is formed in a predetermined pattern. Form.

  The groove 57b is for forming a wiring 60 described later, and the upper surface of the pin 55 is exposed by the groove 57b. Thereafter, heat treatment is performed at a temperature of, for example, 250 ° C. to cure (post-cure) the insulating layer 57.

  Next, as shown in FIG. 9B, a seed layer 58 is formed on the entire upper surface of the pseudo wafer 50 by a method such as sputtering. The seed layer 58 also has a two-layer structure of a Ti layer and a Cu layer, for example, similarly to the seed layer 15 described above.

  Next, as shown in FIG. 9C, Cu is electroplated to a thickness of 3 μm, for example, using the seed layer 58 as a power feeding layer, and a Cu layer 59 is formed on the seed layer 58. By this electrolytic plating, the slit 57a and the groove 57b are filled with Cu.

  Thereafter, for example, heat treatment is performed at a temperature of 150 ° C. for 2 minutes to grow Cu grains of the Cu layer 59 and stabilize the film quality.

  Next, as shown in FIG. 9D, the Cu layer 59 and the seed layer 58 are subjected to chemical mechanical polishing until the insulating layer 57 is exposed. Thereby, Cu remaining in the groove 57 b becomes the wiring 60. Further, a part of the seed layer 58 and a part of the Cu layer 59 remain in the slit 57a.

  Next, as shown in FIG. 10A, for example, a photosensitive phenol resin is applied to the entire upper surface of the pseudo wafer 10 to a thickness of 5 μm to form an insulating layer 61. Then, after exposing the insulating layer 61 through a predetermined exposure mask, development processing is performed to form an opening 61a through which a predetermined portion of the wiring 60 is exposed, and the Cu layer 59 and the seed layer in the slit 57a. A slit 61b is formed in which 58 is exposed. Thereafter, the insulating layer 61 is cured (post-cured) by heat treatment at a temperature of, for example, 250 ° C.

  Next, as shown in FIG. 10B, a seed layer 62 is formed on the entire upper surface of the pseudo wafer 50 by a method such as sputtering. The seed layer 62 also has a two-layer structure of a Ti layer and a Cu layer, for example, similar to the seed layer 15 described above.

  Next, as shown in FIG. 10C, for example, a photoresist is applied on the seed layer 62 to a thickness of 4 μm to form a photoresist film 63. Then, after exposing the photoresist film 63 through a predetermined exposure mask, development processing is performed to form an opening 63a at a position corresponding to the opening 61a and a slit 63b at a position corresponding to the slit 61b. Form.

  Next, as shown in FIG. 10D, using the seed layer 62 as a power feeding layer, Cu is electroplated on the seed layer 62 inside the opening 62a to a thickness of 3 μm, for example. As a result, a wiring 64 made of Cu is formed in the opening 63 a of the photoresist film 63. Further, Cu is embedded in the slit 63b.

  Next, as shown in FIG. 11A, the photoresist film 63 is stripped with a stripping solution such as acetone. Then, the portion of the seed layer 62 that is not covered with the wiring 64 is removed by etching, and the upper surface of the insulating layer 61 is exposed. Note that the Cu embedded in the slit 61 b of the insulating layer 61 is exposed by peeling the photoresist film 63.

  Next, as shown in FIG. 11B, a photoresist film 65 is formed on the entire upper surface of the pseudo wafer 50 by applying, for example, a photoresist to a thickness of 4 μm, for example. Then, after exposing the photoresist film 65 through a predetermined exposure mask, development processing is performed to form a slit 65 a above the resin film 51.

Thereafter, as shown in FIG. 11C, Cu and the seed layer in the slit 65a are removed by etching. Cu can be removed, for example, by wet etching using potassium sulfate as an etchant. Further, the Ti layer can be removed by, for example, wet etching using an ammonium fluoride aqueous solution as an etching solution or dry etching using a mixed gas of CF ₄ and O ₂ . By this etching, the insulating layer 52 is exposed at the bottom of the slit 65a.

  Next, steps required until a structure shown in FIG.

  After the Cu and seed layer in the slit 65a are removed by etching in the above process, the photoresist film 65 is removed. Thereafter, for example, a photosensitive phenol resin is applied to the entire upper surface of the pseudo wafer 50 to form the insulating layer 66. Next, the insulating layer 66 is exposed using a predetermined exposure mask, and development processing is performed to form an opening through which a predetermined portion of the wiring 64 is exposed, and the insulating layer 52 is exposed above the resin film 51. A slit is formed. Then, for example, heat treatment is performed at a temperature of 250 ° C. to cure (post-cure) the insulating layer 66.

  Next, after forming a conductive seed layer (not shown) on the entire upper surface of the pseudo wafer 50, a photoresist is applied on the seed layer to form a photoresist film (not shown). Then, the photoresist film is exposed through a predetermined exposure mask, and thereafter development processing is performed to form grooves in a predetermined pattern.

  Next, Cu is electroplated using the seed layer as a power feeding layer. In this manner, the wiring 67 made of Cu and electrically connected to the predetermined wiring 64 is formed on the insulating layer 66. Thereafter, after removing the photoresist film, the seed layer not covered with the wiring 67 is removed.

  Next, an insulating layer 68 is formed on the entire upper surface of the pseudo wafer 50 with a photosensitive phenol resin or the like. Thereafter, the insulating layer 68 is exposed through a predetermined exposure mask, and then development processing is performed, so that a contact hole 68a exposing a predetermined portion of the wiring 67 and a slit exposing the insulating layer 52 above the resin film 51 are exposed. 68b.

  Next, the pseudo wafer 50 is immersed in water, or water is sprayed onto the pseudo wafer 50 to dissolve and remove the resin film 51 as shown in FIG. When the resin film 51 is formed of an alkali-soluble resin, the resin film 51 is dissolved with an alkaline aqueous solution such as TMAH. Thereby, a slit 51b reaching the insulating layer 52 from the bottom surface of the pseudo wafer 50 is formed, and the pseudo SoC chip 70 is supported only by the insulating layer 52 in each opening 11a.

  Next, the pseudo SoC chip 70 is separated from the pseudo wafer 50 by vacuum tweezers or the like. FIG. 12C shows the pseudo SoC chip 70 after separation. Next, the pseudo SoC chip 70 is sealed in a package. In this way, the semiconductor device is completed.

  Instead of dissolving the resin film 51 in the liquid, the pseudo SoC chip 70 may be separated from the pseudo wafer 50 by cooling the pseudo wafer 50 to, for example, −65 ° C. and contracting the resin film 51.

  The substrate 11 after the pseudo SoC chip is separated can be removed by immersing the substrate 11 in N-methylpyrrolidone or the like or by ashing with ozone to remove the resin 14 attached to the wall surface of the opening 11a. Can be used.

  Also in the present embodiment, as in the first embodiment, the substrate 11 having high rigidity is used, and after the devices 13a and 13b are arranged in the opening 11a of the substrate 11, the resin 14 is placed in the opening 11a. The pseudo wafer 50 is formed by filling. For this reason, it is difficult for the pseudo wafer 50 to be warped, and an alignment error at the time of alignment by a semiconductor manufacturing apparatus (for example, a film forming apparatus, an exposure apparatus, a transfer apparatus, etc.) or the pseudo wafer 10 is mounted on the semiconductor manufacturing apparatus. Installation mistakes when doing so are avoided.

  In the present embodiment, since the amount of the resin 14 used is small, the stress accumulated in the resin 14 when the resin 14 is cured is small. For this reason, even if the stress accumulated in the resin 14 is released when the pseudo SoC chip 70 is cut out from the pseudo wafer 50, the wiring formed on the pseudo wafer 50 is not destroyed.

  For the above reasons, according to the manufacturing method according to the present embodiment, the manufacturing yield of the semiconductor device using the pseudo SoC chip is improved.

  Furthermore, according to the present embodiment, since the amount of the resin 14 used is small and the substrate 11 can be used repeatedly, there is an advantage that the manufacturing cost of the semiconductor device using the pseudo SoC chip can be reduced.

  Furthermore, this embodiment has an advantage that the pseudo SoC chip 70 can be easily separated from the pseudo wafer 50 without using laser dicing or a diamond blade.

(Modification)
In the second embodiment described above, the resin film 51 made of a resin that dissolves in water or an alkaline aqueous solution is formed on the wall surface of the opening 11a of the substrate 11. However, as shown in FIG. A metal film 81 may be formed on the wall surface of 11a.

  Although the method of forming the metal film 81 on the wall surface of the opening 11a is not particularly limited, for example, the following method can be used.

  That is, after a photoresist film is applied to both the front and back surfaces of the substrate 11, a predetermined portion of the substrate 11 is cut into a rectangle by ultrasonic processing or the like to form the opening 11a. Thereafter, a Cu layer serving as a seed layer is formed to a thickness of, for example, 100 nm on the wall surface of the opening 11a by a method such as sputtering. Next, the metal film attached on the photoresist film is removed together with the photoresist film. Thereafter, a Cu layer is electrolytically plated on the seed layer to a thickness of 3 mm, for example, to form a metal film 75.

  After the metal film 75 is formed in this way, the devices 13a and 13b are arranged in the opening 11a and fixed with the resin 14 as in the second embodiment to form a pseudo wafer. Then, as in the second embodiment, an insulating layer, wiring, and the like are formed on the pseudo wafer, and a pseudo SoC chip 80 as shown in FIG. 14B is manufactured.

  Next, the metal film 81 is dissolved using an etching solution such as a mixed solution of sulfuric acid and hydrogen peroxide solution, a mixed solution of acetic acid and hydrogen peroxide solution, an aqueous solution of ferric chloride, or an aqueous solution of potassium sulfate. A slit 81a is formed as shown in FIG. In this case, it is preferable to protect the wiring 67 exposed on the upper side of the pseudo SoC chip 80 with a film such as a resist.

  Thereafter, the pseudo SoC chip 80 is separated from the pseudo wafer 50 by vacuum tweezers or the like and sealed in a package. In this way, the semiconductor device is completed.

  In this modification, the slit 81a is formed after removing Cu or the like in the slit 68b. However, the Cu in the slit 68b may be removed when the slit 81a is formed.

  The following additional notes are disclosed with respect to the above embodiments.

(Additional remark 1) The process of arrange | positioning a several device in the said opening part of the board | substrate provided with the opening part penetrated from the one surface side to the other surface side,
Injecting resin into the opening to form a pseudo wafer in which the substrate and the device are integrated;
Forming a wiring electrically connected to the plurality of devices on the pseudo wafer to obtain a pseudo SoC chip having the plurality of devices and the wiring;
Separating the pseudo SoC chip from the substrate. A method for manufacturing a semiconductor device, comprising:

  (Supplementary note 2) The method of manufacturing a semiconductor device according to supplementary note 1, wherein the substrate is formed of any one of silicon, ceramics, glass, and quartz.

(Appendix 3) Before the step of disposing a plurality of devices in the opening, the method includes a step of attaching a soluble film to the wall surface of the opening,
The method for manufacturing a semiconductor device according to appendix 1 or 2, wherein in the step of separating the pseudo SoC chip from the substrate, the soluble film is dissolved with water, an alkaline aqueous solution or an acidic aqueous solution.

  (Supplementary note 4) The semiconductor device according to supplementary note 3, wherein the soluble film is formed of a resin containing polyvinyl pyrrolidone, polyvinyl alcohol, polyvinyl acetal, cellulose, acrylic acid or methacrylic acid, or a derivative thereof. Manufacturing method.

  (Additional remark 5) The manufacturing method of the semiconductor device of Additional remark 3 characterized by the said soluble film | membrane being formed with the metal.

  (Supplementary note 6) The method of manufacturing a semiconductor device according to supplementary note 1 or 2, wherein laser dicing is used in the step of separating the pseudo SoC chip from the substrate.

  (Supplementary note 7) The method of manufacturing a semiconductor device according to any one of supplementary notes 3 to 5, wherein vacuum tweezers are used in the step of separating the pseudo SoC chip from the substrate.

  (Supplementary note 8) The method of manufacturing a semiconductor device according to supplementary note 1 or 2, further comprising a step of removing the resin adhering to the substrate after the step of separating the pseudo SoC chip from the substrate. .

(Supplementary note 9) a substrate provided with an opening penetrating from one surface side to the other surface side;
A plurality of devices disposed in the opening of the substrate;
A pseudo wafer comprising: a resin that fills the opening and integrates the substrate and the plurality of devices.

  (Additional remark 10) The pseudo | simulation wafer of Additional remark 9 characterized by providing the soluble film | membrane which can be melt | dissolved by water, alkaline aqueous solution, or acidic aqueous solution between the wall surface of the said opening part, and the said resin.

  DESCRIPTION OF SYMBOLS 10,50 ... Pseudo wafer, 11 ... Substrate, 11a ... Opening part, 12 ... Temporary joining film, 13a, 13b ... Device, 14 ... Resin, 15, 21, 25, 53, 58, 62 ... Seed layer, 16, 26 , 54, 63, 65 ... photoresist film, 17, 55 ... pin, 18, 19, 24, 28, 30, 52, 56, 57, 61, 66, 68 ... insulating layer, 22, 59 ... Cu layer, 23 , 27, 29, 60, 64, 67 ... wiring, 40, 70, 80 ... pseudo SoC chip, 45 ... frame plate, 51 ... resin film, 81 ... metal film.

Claims (5)

Attaching a soluble film to the wall surface of the opening of the substrate provided with an opening penetrating from one surface side to the other surface side ;
Disposing a plurality of devices in the opening inside the soluble membrane ;
Injecting resin into the opening to form a pseudo wafer in which the substrate and the device are integrated;
Forming a first insulating layer on the substrate, the soluble film, the resin, and the plurality of devices;
Forming a wiring electrically connected to the plurality of devices on the first insulating layer to obtain a pseudo SoC chip having the plurality of devices and the wiring;
Dissolving the soluble membrane with water, an alkaline aqueous solution or an acidic aqueous solution;
And a step of separating the pseudo SoC chip from the substrate after the step of dissolving the soluble film .   The method of manufacturing a semiconductor device according to claim 1, wherein the substrate is formed of any one of silicon, ceramics, glass, and quartz. 3. The method of manufacturing a semiconductor device according to claim 1 , further comprising a step of removing the resin adhering to the substrate after the step of separating the pseudo SoC chip from the substrate . The method of manufacturing a semiconductor device according to claim 1, wherein vacuum tweezers are used in the step of separating the pseudo SoC chip from the substrate. Forming a second insulating layer on the first insulating layer before forming the wiring electrically connected to the plurality of devices; and forming the soluble film of the second insulating layer on the soluble film. 5. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a slit through which the first insulating layer is exposed at a corresponding position.

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