JP2018049922A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent increase in leakage current caused by generation of a parasitic MOSFET in a case where no element isolation region consisting of an insulating film is formed between a plurality of semiconductor regions formed on an upper surface of a semiconductor substrate.SOLUTION: A metal shield film MS is formed between a principal surface of a semiconductor substrate SB between elements of two semiconductor regions PC formed on the principal surface of the semiconductor substrate SB and that configure mutually different semiconductor elements, and an upper surface of an interlayer insulating film IL on the principal surface of the semiconductor substrate SB. A potential is supplied to the metal shield film MS.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used for, for example, a semiconductor device having two or more semiconductor regions formed on the upper surface of a substrate and wiring on the substrate.

  Method of performing isolation without forming an insulating film embedded in a main surface of a semiconductor substrate between the semiconductor elements formed between the semiconductor elements formed on the main surface of the semiconductor substrate and electrically adjacent to each other There is. That is, for example, the main surface of the semiconductor substrate between the semiconductor elements is made into a non-doped state containing no impurities, or the first conductors that constitute the semiconductor elements and are adjacent to each other on the main surface of the semiconductor substrate. There is a method of forming a second conductivity type semiconductor region or a first conductivity type semiconductor region different from the first conductivity type between the semiconductor regions (electrodes) of the type.

  Patent Document 1 (Japanese Patent Laid-Open No. 2007-81041) describes that a shield layer is formed on a wiring layer formed on a substrate via a contact layer, thereby preventing the operation of a parasitic MOS transistor. Has been.

JP 2007-81041 A

  The two semiconductor regions formed on the main surface of the semiconductor substrate serve as source / drain regions of the parasitic MOSFET, and the wiring formed on the semiconductor substrate via the interlayer insulating film serves as the gate electrode of the parasitic MOSFET. There is a problem that an inversion layer is generated between the two source / drain regions, and a leakage current flows.

  On the other hand, if an attempt is made to prevent the generation of the inversion layer by forming the metal shield film at the same height as the wiring, the wiring layout is restricted and it is difficult to miniaturize the semiconductor device. Moreover, even if a metal shield film is formed on the wiring layer as in Patent Document 1, there are problems that the wiring layout is restricted and the manufacturing cost is increased.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In a semiconductor device according to an embodiment, a metal shield film is formed between a main surface of a semiconductor substrate between elements and an upper surface of an interlayer insulating film.

  In another embodiment of the method for manufacturing a semiconductor device, a metal shield film is formed between a main surface of a semiconductor substrate between elements and an upper surface of an interlayer insulating film.

  According to one embodiment, the performance of a semiconductor device can be improved.

It is a top view of the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing in the AA of FIG. It is a top view of the semiconductor device which is Embodiment 1 of this invention. It is the top view and sectional drawing of a semiconductor device which are Embodiment 1 of this invention. It is sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 6 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. 7 is a plan view of the semiconductor device during a manufacturing step following that of FIG. 6; It is sectional drawing in the AA of FIG. FIG. 9 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8; FIG. 10 is a plan view of the semiconductor device during a manufacturing step following that of FIG. 9; It is sectional drawing in the AA of FIG. FIG. 12 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; It is sectional drawing of the semiconductor device which is Embodiment 2 of this invention. It is sectional drawing of the semiconductor device which is a modification of Embodiment 2 of this invention. It is sectional drawing which shows the semiconductor device which is a comparative example. It is sectional drawing which shows the semiconductor device which is a comparative example. It is sectional drawing which shows the semiconductor device which is a comparative example.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the mentioned number, and may be more or less than the mentioned number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
<Structure of semiconductor device>
First, the structure of the semiconductor device of this embodiment will be described. FIG. 1 is a plan view showing a configuration of a semiconductor chip which is a semiconductor device of the present embodiment. FIG. 2 is a cross-sectional view showing the configuration of the semiconductor device of this embodiment. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is a plan view showing the semiconductor device of the present embodiment. FIG. 4 is a diagram showing both a planar layout and a cross section of elements constituting the semiconductor device of the present embodiment. 4, each of the PNP bipolar transistor, the NPN bipolar transistor, and the resistance element shown in FIG. 1 is shown in order from the left.

  As shown in FIG. 1, the semiconductor chip CHP of the present embodiment includes a semiconductor substrate (semiconductor wafer) SB (see FIG. 2), a capacitive element CAP mounted on the semiconductor substrate, a PNP bipolar transistor BT1, and an NPN bipolar. A plurality of transistors BT2 and resistance elements RE are provided. Each of the capacitive element CAP, the PNP-type bipolar transistor BT1, the NPN-type bipolar transistor BT2, and the resistance element RE is a semiconductor element, and a plurality of these various semiconductor elements are arranged side by side on the semiconductor substrate. A plurality of semiconductor elements arranged side by side on the semiconductor substrate are separated from each other and insulated from each other.

  In FIG. 2, the connection region CR1, the inter-element region SR, the connection region CR2, and the power feeding region SE are shown in order from the left side. Each of the connection regions CR1 and CR2 is a region that connects a contact plug (connection portion) CP1 that supplies a collector potential to the semiconductor region (diffusion region) PC formed on the main surface of the semiconductor substrate SB to the upper surface of the semiconductor region PC. It is. The inter-element region SR is a region between the semiconductor regions PC adjacent to each other, that is, a region between the semiconductor devices adjacent to each other (for example, the PNP bipolar transistor BT1) and electrically isolates the semiconductor devices from each other. It is. The power supply region SE is a region for connecting the contact plug CP2 to the metal shield film MS in order to supply a voltage to the metal shield film (metal film, conductive film) MS formed on the semiconductor substrate SB.

  As shown in FIG. 2, the semiconductor device of the present embodiment has a semiconductor substrate SB. The semiconductor substrate SB is, for example, a non-doped (undoped) single crystal silicon substrate into which almost no impurities are introduced. The semiconductor substrate SB may be a substrate including a single crystal silicon substrate and an epitaxial growth layer formed on the single crystal silicon layer. In this case, for example, the single crystal silicon substrate is a p-type substrate into which boron is introduced, and the epitaxial growth layer thereon is a layer containing no impurities. Regardless of the presence or absence of the epitaxial growth layer, the plane orientation (crystal orientation) of the main surface of the semiconductor substrate SB is (100).

  The non-doped silicon substrate means an intrinsic silicon substrate that exhibits neither n-type conductivity nor p-type conductivity. That is, the semiconductor substrate SB is neither n-type nor p-type. That is, the semiconductor substrate SB is neither an n-type semiconductor nor a p-type semiconductor. When an epitaxial growth layer is formed on a substrate, the epitaxial growth layer is a layer grown without intentional doping, for example.

  Here, “semiconductor exhibits n-type conductivity”, “semiconductor conductivity type is n-type” and “n-type semiconductor” means that majority carriers in the semiconductor are electrons. To do. In addition, “a semiconductor exhibits p-type conductivity”, “a semiconductor has a p-type conductivity” and “a p-type semiconductor” means that majority carriers in the semiconductor are holes. To do. The intrinsic state refers to a state where the electron concentration and the hole concentration are substantially equal, or a state where electrons or holes as carriers are not generated.

  The semiconductor substrate SB is not limited to a non-doped silicon substrate, and may be a p-type or n-type silicon substrate having an impurity concentration lower than that of each of the following semiconductor regions. Further, when the semiconductor substrate SB has a p-type or n-type conductivity type, the conductivity type of a semiconductor region SR1 described later is the same as the conductivity type of the semiconductor substrate SB.

  On the main surface of the semiconductor substrate SB in the connection region CR1, a p-type semiconductor region PC that constitutes a collector electrode of a PNP-type bipolar transistor BT1 that is a semiconductor element is formed. Similarly, on the main surface of the semiconductor substrate SB in the connection region CR2, a p-type semiconductor region PC that constitutes a collector electrode of the PNP-type bipolar transistor BT1 that is a semiconductor element is formed. That is, each of the connection regions CR1 and CR2 is a region for forming a semiconductor element. The PNP bipolar transistor BT1 including the semiconductor region PC in the connection region CR1 and the PNP bipolar transistor BT1 including the semiconductor region PC in the connection region CR2 are separate semiconductor elements and are separated from each other by the inter-element region SR. ing. That is, each of the connection regions CR1 and CR2 is also a region where a semiconductor element is formed.

  The inter-element region SR is a region between the connection regions CR1 and CR2, and the main surface of the semiconductor substrate SB in the inter-element region SR is a non-doped semiconductor layer. That is, the adjacent semiconductor regions PC are electrically separated by the non-doped semiconductor substrate SB in the inter-element region SR between them. A p-type semiconductor region (diffusion region) SR1 is formed on the main surface of the semiconductor substrate SB in the power feeding region SE.

  Here, in the inter-element region SR, an element isolation region made of an insulating film for isolating elements is not formed. That is, an element isolation region having an STI (Shallow Trench Isolation) structure or a LOCOS (Local Oxidation of Silicon) structure is not formed in the vicinity of the main surface of the semiconductor substrate.

  In other words, the upper surface of each of the two semiconductor regions PC formed across the inter-element region SR and the main surface of the semiconductor substrate SB in the inter-element region SR are located in substantially the same plane, Of the two semiconductor regions PC, the main surface of the semiconductor substrate SB is flat from the upper surface of one semiconductor region PC to the upper surface of the other semiconductor region PC. A silicon oxide film is not formed between the two semiconductor regions PC, and even if a silicon oxide film is formed, the position of the bottom surface of the silicon oxide film is the position of the lower surface of each semiconductor region PC. Higher than. For example, a p-type semiconductor region may be formed on the main surface of the semiconductor substrate SB in the inter-element region SR to have a deep formation depth in order to separate the semiconductor elements from each other.

  On the main surface of the semiconductor substrate SB, an interlayer insulating film IL is formed. The interlayer insulating film IL includes an interlayer insulating film IL1 and an interlayer insulating film IL2 that are sequentially formed on the main surface of the semiconductor substrate SB. Here, the metal shield film MS is interposed in a partial region between the interlayer insulating film IL1 and the interlayer insulating film IL2. The main feature of the present embodiment is that the metal shield film MS is formed in the interlayer insulating film IL as described above, thereby preventing the occurrence of a leakage current due to a parasitic MOSFET (Metal Oxide Semiconductor Field Effect Transistor). It is in. The film thickness of the interlayer insulating film IL1 is, for example, 1 μm, and the film thickness of the interlayer insulating film IL2 is smaller than the film thickness of the interlayer insulating film IL1. The film thickness of the interlayer insulating film IL2 here refers to the distance from the upper surface of the interlayer insulating film IL1 to the upper surface of the interlayer insulating film IL2.

  The interlayer insulating films IL1 and IL2 are each made of, for example, a silicon oxide film. The material of the metal shield film MS is, for example, Ti (titanium), TiN (titanium nitride), W (tungsten), or Al (aluminum). In addition, the metal shield film MS may be formed of a film in which a plurality of conductive films made of different materials are stacked among these materials. For example, the metal shield film MS may be composed of a laminated film composed of a titanium film and a tungsten film that are sequentially formed on the interlayer insulating film IL1. The film thickness of the metal shield film MS is, for example, 10 nm or more and 100 nm or less. Specifically, the metal shield film MS is, for example, 20 nm or 30 nm.

  The interlayer insulating film IL is a layer through which the contact plugs CP1 and CP2 penetrate from the upper surface to the lower surface, and the interlayer insulating film IL, the metal shield film MS, the plurality of contact plugs CP1 and the contact plug CP2 constitute a contact layer. To do. The contact plug CP1 in the connection region CR1 is embedded in a contact hole (connection hole) CH1 penetrating from the upper surface to the lower surface of the interlayer insulating film IL. The contact plug CP1 in the connection region CR2 is buried in a contact hole (connection hole) CH1 penetrating from the upper surface to the lower surface of the interlayer insulating film IL. The contact plug CP2 is embedded in a contact hole (connection hole) CH2 penetrating from the upper surface to the lower surface of the interlayer insulating film IL in the power feeding region SE.

  The contact plug CP1 in the connection region CR1 is connected to the upper surface of the semiconductor region PC. Similarly, the contact plug CP1 of the connection region CR2 is connected to the upper surface of the semiconductor region PC. Further, the contact plug CP2 in the power supply region SE is connected to the upper surface of the semiconductor region PC. Each of the contact plugs CP1 and CP2 has a width of several μm or more, for example, 20 μm.

  Contact plugs CP1, CP2 and contact holes CH1, CH2 all penetrate interlayer insulating film IL1, metal shield film MS, and interlayer insulating film IL2. The contact plug CP1 penetrates the opening OP1 of the metal shield film MS, and the contact plug CP2 penetrates the opening OP2 of the metal shield film MS. The contact plug CP1 is not in contact with the metal shield film MS, but the contact plug CP2 is in contact with the metal shield film MS. That is, the surface of the metal shield film MS does not exist on the side wall of the contact hole CH1, and the surface of the metal shield film MS exists on the side wall of the contact hole CH2. An interlayer insulating film IL2 is interposed between the contact plug CP1 and the metal shield film MS.

  On the interlayer insulating film IL, wirings M1 and M2 made of a metal film are formed. The wiring M1 and the contact plug CP1 are connected to each other and integrated. That is, the wiring M1 and the contact plug CP1 immediately below it are made of one metal film. Further, the wiring M2 and the contact plug CP2 are connected to each other and integrated. That is, the wiring M2 and the contact plug CP2 immediately below it are made of one metal film. All or part of the wiring M1 is formed in each of the connection regions CR1 and CR2, and all or part of the wiring M2 is formed in the power feeding region SE. The wiring M1 and the contact plug CP1 are made of, for example, a conductive film mainly made of an AL (aluminum) film.

  Each of the wirings M1 and M2 and the contact plugs CP1 and CP2 is composed of, for example, a laminated film in which a thin barrier conductive film and a main conductive film made of an aluminum film are sequentially laminated. The barrier conductive film is made of, for example, a Ti (titanium) film, a Ta (tantalum) film, or a nitride film thereof. The film thickness of each of the wirings M1 and M2 is, for example, 1 μm.

  Since the wiring M1 in the connection region CR1 and the wiring M1 in the connection region CR2 are conductive films that supply voltages to different semiconductor elements, they are separated from each other. The distance between the wiring M1 in the connection region CR1 and the wiring M1 in the connection region CR2 is greater than 1 μm, for example. Further, the distance between the wirings M1 and M2 is also larger than 1 μm, for example. It is conceivable that another wiring electrically connected to the semiconductor substrate SB is formed between the adjacent wirings M1, but is not electrically connected to the semiconductor substrate SB like the wiring M2. The wiring is not disposed between the adjacent wirings M1.

  FIG. 3 shows a planar layout of the interlayer insulating film IL2, the metal shield film MS, and the contact holes CH1 and CH2. In FIG. 3, the illustration of the semiconductor substrate, the contact plug, and the wiring is omitted, and only the interlayer insulating film IL2 and the metal shield film MS are shown. Here, the outline of the metal shield film MS covered with the interlayer insulating film IL2 is indicated by a broken line. FIG. 2 shows a cross section including the contact holes CH1 and CH2 of FIG.

  As shown in FIG. 3, the contact holes CH1, CH2 and the openings OP1, OP2 all have a circular planar layout. In plan view, the opening OP1 is located outside the contact hole CH1, and the opening OP2 is located inside the contact hole CH2. Therefore, a part of the upper surface of the metal shield film MS, a side wall of the metal shield film MS that is the side wall of the opening OP2, and a part of the lower surface of the metal shield film MS are exposed in the contact hole CH2. That is, the diameter of the opening OP2 is smaller than any of the diameters of the opening OP1 and the contact holes CH1 and CH2.

  As shown in FIG. 2, when the contact plug CP2 is in contact with the metal shield film MS exposed in the contact hole CH2, a voltage can be supplied to the metal shield film MS via the wiring M2 and the contact plug CP2. For example, 0 V is applied to the metal shield film MS. Here, the semiconductor substrate SB and the metal shield film MS are at the same potential via the contact plug CP2 and the semiconductor region SR1.

  Here, if the potential of the metal shield film MS can be fixed, the generation of the inversion layer and the operation (energization) of the parasitic MOSFET can be prevented, and the value of the voltage applied to the metal shield film MS is 0V. It is not necessary and can be changed as appropriate. Further, as described in the second embodiment, the metal shield film MS and the semiconductor substrate SB need not have the same potential.

  In the semiconductor device according to the present embodiment, the formation of the inversion layer caused by the change in the charge on the main surface of the semiconductor substrate SB according to the usage state of the semiconductor device is prevented by forming the metal shield film MS. . For this reason, it is desirable that the voltage applied to the metal shield film MS is fixed at 0 V so that neither the n-type inversion layer nor the p-type inversion layer is biased. However, when either the n-type inversion layer or the p-type inversion layer can be separately formed on the main surface of the semiconductor substrate SB, a voltage advantageous for preventing the occurrence of each inversion layer is applied to the metal shield film MS. As a result, the effect of preventing the occurrence of leakage current can be enhanced.

  Further, a plurality of metal shield films MS may be formed, and different voltages may be applied to each metal shield film MS. That is, it is possible to apply different voltages to the metal shield film MS in each of the regions where the n-type inversion layer is easily formed and the regions where the p-type inversion layer is easily formed.

  Note that the opening width of the contact hole CH2 at the same height as the interlayer insulating film IL1 may be smaller than the opening width of the contact hole CH2 at the same height as the interlayer insulating film IL2.

  Further, the planar layout of each of the contact holes CH1 and CH2 and the openings OP1 and OP2 is not limited to a circle, and may be an ellipse, a square, a rectangle, or the like. In FIG. 4 used in the following description, a contact plug having a rectangular or square planar shape is shown. Each of the circular contact holes CH1 and CH2 shown in FIG. 3 has a diameter of several μm or more. Specifically, the diameter of each of the contact holes CH1 and CH2 is, for example, 20 μm, and the diameter of the opening OP2 is, for example, 5 μm to 10 μm. The shortest distance (distance a in FIG. 2) from the end of the contact hole CH1 to the opening OP1 is, for example, 200 nm or more.

  As shown in FIG. 2, the distance a between the end portion of the metal shield film MS and the end portion of the contact plug CP1 in the direction along the main surface of the semiconductor substrate SB (hereinafter sometimes simply referred to as a lateral direction) is The distance b is smaller than the distance b between the end of the contact plug CP1 and the end of the semiconductor region PC in this direction. That is, in the lateral direction, the metal shield film MS is terminated at a position closer to the contact plug CP1 than the end of the semiconductor region PC. That is, the sidewall of the metal shield film MS, that is, the sidewall of the opening OP1 is located immediately above the semiconductor region PC connected to the contact plug CP1 surrounded by the opening OP1, and the sidewall is the semiconductor. It is not located directly above the end of the area PC. Therefore, the inequality of b> a> 0 holds. The size of the distance b is, for example, 1 μm.

  In other words, in the lateral direction, the sidewall of the opening OP1 directly above the predetermined semiconductor region PC is located on the center side of the semiconductor region PC with respect to the end of the semiconductor region PC, and the semiconductor region PC It is not located on the other semiconductor region PC side adjacent to.

  The lateral distance a is smaller than the distance c between the end of the contact plug CP1 and the end of the wiring M1 in the direction. That is, in the lateral direction, the metal shield film MS terminates at a position closer to the contact plug CP1 than the end portion of the wiring M1. That is, the side wall of the metal shield film MS, that is, the side wall of the opening OP1 is located immediately below the wiring M1 connected to the contact plug CP1 surrounded by the opening OP1, and the side wall is the wiring M1. It is not located directly under the edge of the. For this reason, the inequality of c> a> 0 holds. The distance a is smaller than both the distance between the wirings M1 and the distance between the wirings M1 and M2. Here, distances a to c are distances in the same direction measured at overlapping positions in plan view, but distances a to c may be distances at different positions in plan view. The distances may be in different directions in plan view.

  The magnitude of the distance a is preferably less than or equal to ½ of the distance b. In other words, the size of the distance a is desirably 500 nm or less, for example. This is because, as will be described later, the metal shield film MS is a conductive film provided to prevent the inversion layer of the parasitic MOSFET from being formed on the main surface of the semiconductor substrate SB in the inter-element region SR. This is because it is possible to effectively prevent the occurrence of a leakage current due to the parasitic MOSFET by covering it more largely.

  The magnitude of the distance a is, for example, 200 nm or more. The distance a is preferably as small as possible, but the lower limit of the distance a is mainly determined by the accuracy of a semiconductor device manufacturing apparatus such as an exposure apparatus used for forming a photoresist pattern. That is, if the accuracy of aligning the exposure position by the exposure apparatus is high, the distance a can be reduced, thereby effectively preventing the occurrence of leakage current.

  However, when the thickness of the metal shield film MS is large, it is difficult to reduce the distance a, and conversely, it is necessary to increase the distance a. This is because when the thickness of the metal shield film MS is, for example, 1 μm or more, the processing accuracy of the metal shield film MS is lowered, and the side wall of the opening OP1 of the metal shield film MS is tapered. For these reasons, it is difficult to bring the end portion of the metal shield film MS close to the contact plug CP1.

  On the other hand, if the thickness of the metal shield film MS is 100 nm or less, the end portion of the metal shield film MS can be brought close to the contact plug CP1 without being substantially affected by the processing accuracy and the presence of the taper. That is, if the thickness of the metal shield film MS is 100 nm or less, the distance a is substantially constant regardless of the thickness of the metal shield film MS. Therefore, here, from the viewpoint of suppressing the occurrence of leakage current, the thickness of the metal shield film MS is set to less than 1 μm, that is, smaller than the wirings M1 and M2. Desirably, the thickness of the metal shield film MS is set to 100 nm or less.

  Moreover, there are two main reasons for setting the distance a smaller than the distance c as follows. The first reason is that the effect of preventing the occurrence of leakage current as described above can be obtained by bringing the metal shield film MS closer to the contact plug CP1 as the metal shield film MS partially overlaps the wiring M1. is there. The second reason is that the degree of freedom of the wiring layout is improved as compared with the case where the metal shield film MS is formed at the same height as the wirings M1 and M2, that is, on the interlayer insulating film IL2. Thereby, the semiconductor device can be miniaturized.

  Further, by forming the opening OP1 so as to surround the contact plug CP1 (see FIG. 2) at a constant interval in plan view, the area covering the main surface of the semiconductor substrate SB with the metal shield film MS can be expanded. Therefore, the generation of the inversion layer can be prevented more efficiently.

  FIG. 4 shows a plan view and a cross-sectional view of a PNP bipolar transistor BT1, an NPN bipolar transistor BT2, and a resistance element RE, which are examples of semiconductor elements formed near the upper surface of the semiconductor substrate SB. Each sectional view shown on the lower side of the figure is a sectional view taken along line BB of the plan view shown on the upper side of the figure. However, in FIG. 4, in order to make the drawing easier to understand, there are places where the dimensions of each part are shown as different from the actual semiconductor device. Therefore, the relationship between the dimensions of the respective parts shown in FIG. 4 may conflict with the description given above with reference to FIG. 1 includes a lower electrode made of a semiconductor region formed on the main surface of the semiconductor substrate SB and an upper electrode made of a metal film formed on the semiconductor substrate via an insulating film. Although it is an element, description by illustration is abbreviate | omitted.

  As shown in FIG. 4, the PNP bipolar transistor BT1 is an n-type semiconductor region NB, which is a base electrode formed on the main surface of the semiconductor substrate SB, and a collector electrode formed on the main surface of the semiconductor substrate SB. The semiconductor device includes a p-type semiconductor region PC and a p-type semiconductor region PE that is an emitter electrode formed on the main surface of the semiconductor substrate SB. In addition, an n-type semiconductor region NW having a formation depth deeper than any of the semiconductor regions NB, PC, and PE and having an impurity concentration lower than that of the semiconductor region NB is formed on the main surface of the semiconductor substrate SB. And PE. The semiconductor region NW is electrically connected to the semiconductor region NB, and a part of the semiconductor region NW is located between the semiconductor region PC and the semiconductor region PE on the main surface of the semiconductor substrate SB.

  The NPN bipolar transistor BT2 includes an n-type semiconductor region NC that is a collector electrode formed on the main surface of the semiconductor substrate SB and a p-type semiconductor region that is a base electrode formed on the main surface of the semiconductor substrate SB. PB and an n-type semiconductor region NE that is an emitter electrode formed on the main surface of the semiconductor substrate SB. In the semiconductor substrate SB, the semiconductor region NE is covered with the semiconductor region PB, and a part of the semiconductor region PB is located between the semiconductor region NC and the semiconductor region NE on the main surface of the semiconductor substrate SB.

  Although not shown, an n-type semiconductor region having a low impurity concentration covering the semiconductor regions PB, NE and NC is also formed on the main surface of the semiconductor substrate SB on which the NPN-type bipolar transistor BT2 is formed, similar to the semiconductor region NW. It may be formed.

  The resistance element RE is configured by a p-type semiconductor region PR formed on the main surface of the semiconductor substrate SB. The semiconductor region PR extends in a direction along the main surface of the semiconductor substrate SB, and contact plugs CP1 are connected to the upper surfaces of both ends thereof. Each of the above-described n-type semiconductor regions is a region in which an n-type impurity (for example, P (phosphorus)) is introduced into the main surface of the semiconductor substrate SB, and any of the above-described p-type semiconductor regions is the semiconductor substrate SB. This is a region where a p-type impurity (for example, B (boron)) is introduced into the main surface.

  Immediately above the semiconductor substrate SB on which the PNP-type bipolar transistor BT1, the NPN-type bipolar transistor BT2, and the resistance element RE are formed, interlayer insulating films IL1 and IL2 are formed in order on the main surface of the semiconductor substrate SB. An interlayer insulating film IL is formed. A plurality of contact plugs CP1 penetrating the interlayer insulating film IL are formed on the semiconductor substrate SB, and a wiring M1 is formed on each contact plug CP1.

  The wiring M1 and the contact plug CP1 are integrated, for example, mainly made of an AL (aluminum) film. A contact plug CP1 is connected to each upper surface of the semiconductor regions NC, NE, NB, PC, PB and PE. A silicide layer made of, for example, CoSi (cobalt silicide) may be formed between the upper surfaces of the semiconductor regions NC, NE, NB, PB, PC, PR, and PE and the contact plug CP1. Similarly, a silicide layer may be formed between the semiconductor region SR1 and the contact plug CP2 shown in FIG. In this case, each semiconductor region and the contact plug are not in direct contact, but are connected via a silicide layer. Thereby, each semiconductor region and the contact plug are electrically connected.

  Here, a metal shield film MS is formed in the interlayer insulating film IL on each of the PNP type bipolar transistor BT1, the NPN type bipolar transistor BT2 and the resistance element RE except for the vicinity of the contact plug CP1. That is, the metal shield film MS is formed so as to spread over the entire semiconductor chip CHP (see FIG. 1) in a plan view except for the vicinity of the contact plug CP1. By forming the metal shield film MS in such a wide area, it is possible to prevent leakage current from occurring in the entire semiconductor chip CHP without leakage.

<Effect of semiconductor device>
Below, the effect of the semiconductor device of this Embodiment is demonstrated using the comparative example shown in FIGS. Each of FIGS. 16 to 18 is a cross-sectional view of a semiconductor device of a comparative example. 16 to 18 show the connection region CR1, the inter-element region SR, and the connection region CR2.

  The structure of the connection region CR1, the element region SR, and the connection region CR2 shown in FIGS. 16 to 18 is such that the interlayer insulating film IL3 on the semiconductor substrate SB is formed by stacking two interlayer insulating films IL1 and IL2 as shown in FIG. This is different from the semiconductor device of the present embodiment in that it does not have the above structure and in that it does not have the metal shield film MS in the interlayer insulating film IL3.

  As shown in FIG. 16, when a plurality of semiconductor elements (PNP bipolar transistors BT1) are formed on the main surface of the semiconductor substrate SB or the main surface of the epitaxial growth layer and no element isolation region made of an insulating film is formed between the elements, The wiring M1 on the insulating film IL3 works as a gate electrode, and a parasitic MOSFET may be generated. That is, for example, two semiconductor regions PC formed on the main surface of the semiconductor substrate SB and constituting different elements function as source / drain regions of the parasitic MOSFET.

  That is, if the semiconductor elements adjacent on the main surface of the semiconductor substrate SB are to be electrically separated without forming the insulating film embedded in the main surface of the semiconductor substrate SB, the wiring M1 on the interlayer insulating film IL3 is gated. By functioning as an electrode and the interlayer insulating film IL3 as a gate insulating film, an inversion layer is formed on the main surface of the semiconductor substrate between the semiconductor regions PC constituting each of these semiconductor elements. Thereby, a leak current flows. Note that the inversion layer is generated when the charge on the main surface of the semiconductor substrate SB fluctuates in accordance with the usage state of the semiconductor device. In this manner, the parasitic MOSFET operates and a leak current flows, so that an abnormality occurs in the operation of the semiconductor device.

  Further, in order to separate the elements, it is conceivable to form a semiconductor region for separation (not shown) on the main surface of the semiconductor substrate between the elements. Also in this case, the isolation semiconductor region and the semiconductor region PC constituting the element function as source / drain regions, and a leakage current may flow in the parasitic MOSFET.

  Even when the wiring M1 is not formed in the inter-element region SR, that is, when the wiring M1 is not formed immediately above the region between the two semiconductor regions PC, it is adjacent to the inter-element region SR. When a voltage is applied to the wiring M1 in the matching region, a current can flow through the parasitic MOSFET.

  In these cases, there arises a problem that the semiconductor element does not operate normally or a problem that power consumption for flowing a desired current through the semiconductor element increases. Such a problem becomes more conspicuous when the plane orientation is (100) than when the plane orientation (crystal orientation) of the main surface of the semiconductor substrate SB is (111). This is because the interface state of the substrate main surface is lower when the surface orientation is (100) than when the surface orientation is (111), and this causes the main surface of the semiconductor substrate SB. This is because the threshold voltage of the parasitic MOSFET having the channel region as the channel region decreases.

  When the diameter of the semiconductor wafer is, for example, 8 inches and is relatively large, it is the mainstream to manufacture a wafer whose surface orientation of the main surface of the semiconductor substrate SB is (100), compared to a wafer whose surface orientation is (111). A wafer having a plane orientation of (100) can be manufactured at a lower cost. For this reason, when a cheap wafer with a large diameter is used, it is considered that the plane orientation of the semiconductor substrate SB is (100). In this case, it is particularly important to prevent the occurrence of parasitic MOSFETs.

  As a method for preventing the occurrence of the parasitic MOSFET, there is a method of controlling the electric field by forming a metal shield film and applying a voltage to the metal shield film. That is, by fixing a predetermined voltage applied to the metal shield film on the semiconductor substrate, it is possible to prevent the charge on the main surface of the semiconductor substrate SB from fluctuating in accordance with the usage state of the semiconductor device. As a result, it is possible to prevent the threshold voltage of the parasitic MOSFET from being lowered, and thus it is possible to prevent an inversion layer from being generated on the main surface of the semiconductor substrate in the inter-element region that becomes the channel region of the parasitic MOSFET. By preventing the generation of the inversion layer in this way, it is possible to prevent leakage current from flowing between the source region and the drain region of the parasitic MOSFET, that is, the main surface of the semiconductor substrate in the inter-element region.

  Here, as in the semiconductor device of the comparative example shown in FIG. 17, it is conceivable to form the metal shield film MS1 on the interlayer insulating film IL3 so as to be aligned with the wiring M1. The metal shield film MS1 shown in FIG. 17 is formed in contact with the upper surface of the interlayer insulating film IL3 constituting the contact layer, like the wiring M1. In this case, the metal shield film MS1 may be a film in the same layer as the wiring M1, for example. That is, in the manufacturing process of the semiconductor device of the comparative example, one conductive film is formed on the semiconductor substrate SB after the contact hole CH1 is formed, and the conductive film is processed to thereby process the wiring M1, the contact plug CP1, and the metal shield film MS1. Can be considered. Since the metal shield film MS1 is a conductive film to which a voltage different from that of each semiconductor element is applied, it is separated from the wiring M1.

  In this case, since it is necessary to dispose the wiring M1 extending in various directions on the interlayer insulating film IL3, the metal shield film MS1 is disposed so as to cover a portion where a leakage current due to the parasitic MOSFET can flow. Difficult to do. That is, the area of the metal shield film MS1 in a plan view cannot be increased, and the occurrence of a leakage current cannot be effectively prevented in the comparative example. Further, in order to dispose the metal shield film MS1, it is necessary to increase the interval between the adjacent wirings M1, so that the layout of the wiring M1 is restricted. As a result, it becomes necessary to widen the interval between the semiconductor elements formed via the contact plug CP1 immediately below the wiring M1, which causes a problem that miniaturization of the semiconductor device is hindered.

  Further, as in the semiconductor device of the comparative example shown in FIG. 18, it is conceivable that the interlayer insulating film IL4 is formed on the interlayer insulating film IL3 and the wiring M1, and the metal shield film MS2 is formed on the interlayer insulating film IL4. . The interlayer insulating film IL4 is made of, for example, a silicon oxide film. In this case, the layout of the wiring M1 is not restricted, and adjacent wirings M1 can be brought close to each other at the shortest distance, so that the layout of the wiring M1 and the semiconductor element as described above with reference to FIG. 17 is prevented from being restricted. be able to. Further, since the metal shield film MS2 is formed in the region where the wiring M1 does not exist, it seems that the metal shield film MS2 can be formed evenly over the entire semiconductor chip.

  However, the region on the first wiring layer including the wiring M1 and the interlayer insulating film IL4 is a region for forming the second wiring layer including the wiring electrically connected to the wiring M1 through the via, and the metal shield film If the MS is formed side by side with the wiring of the second wiring layer, the layout of the wiring is restricted. Therefore, it becomes difficult to miniaturize the semiconductor device, and furthermore, since the metal shield film MS2 cannot be formed so as to be spread over the entire semiconductor chip, the generation of leakage current cannot be effectively prevented.

  In addition, since the metal shield film MS2 is located above the wiring M1 functioning as the gate electrode of the parasitic MOSFET, even if a predetermined voltage is applied to the metal shield film MS2, the electric field is effectively controlled, and the inversion layer It is difficult to prevent formation.

  Therefore, in the semiconductor device of the present embodiment, as shown in FIG. 2, the metal shield film MS is formed in the interlayer insulating film IL that constitutes the contact layer including the contact plug CP1 connected to the semiconductor substrate SB. Yes. That is, the metal shield film MS is formed between the wiring M1 functioning as the gate electrode of the parasitic MOSFET and the main surface of the semiconductor substrate SB in the inter-element region SR where the inversion layer of the parasitic MOSFET can be formed. For this reason, compared with the case where the metal shield film is formed at the same height as the wiring M1 (see FIG. 17) and the case where the metal shield film is formed above the wiring M1 (see FIG. 18), the metal shield film MS. Is fixed at a predetermined value, the electric field can be controlled, and an inversion layer can be easily prevented from being formed on the main surface of the semiconductor substrate SB in the inter-element region SR.

  Here, as shown in FIG. 2, the metal shield film MS is formed close to the contact plug CP1 so that the distance a is smaller than the distance b and the distance c, whereby the semiconductor substrate SB is formed by the metal shield film MS. The area covering the main surface can be enlarged. Therefore, the generation of the inversion layer can be prevented more effectively, and the generation of leakage current can be suppressed. Here, in plan view, the metal shield film MS covers the entire main surface of the semiconductor substrate SB in the inter-element region SR, that is, the entire main surface of the semiconductor substrate SB between two adjacent semiconductor regions PC. Covering. Thereby, generation | occurrence | production of an inversion layer can be prevented effectively.

  In the present embodiment, unlike the comparative example shown in FIG. 17, the metal shield film MS is formed at a height where the wirings M1 and M2 do not exist, so that the contact plugs CP1 and CP2 are formed. The metal shield film MS can be formed so as to be evenly spread over the entire semiconductor chip except in the vicinity of the region in which it is present.

  Although the contact plug CP1 may have a rectangular layout in plan view, it does not extend long in the horizontal direction like the wiring on the contact layer. In many cases, the wiring M1 is disposed so as to straddle over the inter-element region SR, but the predetermined contact plug CP1 is disposed so as to straddle over each of the plurality of semiconductor elements electrically isolated from each other. There are few things.

  For this reason, due to the presence of the contact plug CP1, the coverage of the main surface of the semiconductor substrate SB in the inter-element region SR is reduced by the metal shield film MS formed at the same height as the contact plug CP1. Compared to the case where the metal shield film MS1 is formed side by side with the wiring M1 as in the comparative example of FIG. Therefore, by forming the metal shield film MS between the main surface of the semiconductor substrate SB and the wiring M1, the metal shield film MS can be formed over a wide area of the entire semiconductor chip. Generation of leakage current can be prevented without leakage.

  In the present embodiment, the metal shield film MS is not formed at the same height as the wiring M1 on the interlayer insulating film IL or other wirings on the wiring M1, but the metal shield film MS is formed in the contact layer. Therefore, it is possible to prevent the layout of the wiring M1 on the contact layer from being restricted. Therefore, compared to the comparative example shown in FIGS. 17 and 18, each wiring and the semiconductor element can be formed densely, so that the semiconductor device can be easily miniaturized. Therefore, the performance of the semiconductor device is improved.

  Since the leakage current generated by the operation of the parasitic MOSFET is larger when the surface orientation of the main surface of the semiconductor substrate SB is (100) than when (111), the effect of the semiconductor device of the present embodiment is that surface This is more effectively obtained when the orientation is (100).

  By preventing the occurrence of leak current, that is, increasing the leak margin between elements, for example, the voltage supplied to the element can be increased, and the breakdown voltage of the semiconductor device can be increased. Further, by increasing the leak margin between elements, the semiconductor device can be miniaturized by reducing the interval between the semiconductor regions PC, that is, the interval between the semiconductor elements. Therefore, the performance of the semiconductor device is improved.

  Here, the metal shield film MS is formed using a conductive film different from the film constituting the wiring, and the metal shield film MS can be formed thinner than the wirings M1 and M2. For this reason, it is possible to prevent a step (unevenness) from being generated on the upper surface of the interlayer insulating film IL2 and the like formed on the metal shield film MS, so that the reliability of the semiconductor device can be improved.

<Method for Manufacturing Semiconductor Device>
A method for manufacturing the semiconductor device of the present embodiment will be described below with reference to FIGS. 5, 6, 8, 9, and 11 to 13 are cross-sectional views of the semiconductor device according to the present embodiment during the manufacturing process. 7 and 10 are plan views of the semiconductor device of the present embodiment during the manufacturing process. 8 is a cross-sectional view taken along line AA in FIG. 11 is a cross-sectional view taken along line AA in FIG. 5, 6, 8, 9, and 11 to 13, similarly to FIG. 2, the connection region CR <b> 1, the inter-element region SR, the connection region CR <b> 2, and the power feeding region SE are illustrated in order from the left side.

  First, as shown in FIG. 5, a semiconductor substrate SB made of single crystal silicon is prepared. The semiconductor substrate SB has a main surface and a back surface opposite to the main surface, and the surface orientation of the main surface is (100). The semiconductor substrate SB is made of non-doped single crystal silicon.

  Subsequently, a p-type impurity (for example, B (boron)) is implanted into the main surface of each semiconductor substrate SB in each of the connection regions CR1 and CR2 by using a photolithography technique and an ion implantation method, whereby a p-type semiconductor region is obtained. A plurality of semiconductor regions PC are formed. Further, a p-type semiconductor region SR1 is formed by implanting a p-type impurity (for example, B (boron)) into the main surface of the semiconductor substrate SB in the power supply region SE by using a photolithography technique and an ion implantation method. Further, here, the semiconductor regions NC, NE, NB, PB, PE, PR, and NW shown in FIG. 4 are formed by selectively implanting ions in other regions. As a result, the PNP bipolar transistor BT1, and the NPN bipolar transistor BT2 and the resistor element RE shown in FIG. 4 are formed.

  Next, as shown in FIG. 6, an interlayer insulating film IL1 made of, for example, a silicon oxide film is formed on the main surface of the main surface of the semiconductor substrate SB. Thereafter, the upper surface of the interlayer insulating film IL1 is planarized by using, for example, a CMP (Chemical Mechanical Polishing) method. Subsequently, a metal shield film (metal film, conductive film) MS is formed on the interlayer insulating film IL1. The interlayer insulating film IL1 can be formed using, for example, a CVD (Chemical Vapor Deposition) method, and the film thickness thereof is, for example, 1 μm. The metal shield film MS can be formed by sputtering, for example. The interlayer insulating film IL1 is made of, for example, an LP-PTEOS (Low Pressure-Plasma Tetra Ethyl Ortho Silicate) film.

  The metal shield film MS is made of, for example, Ti (titanium), TiN (titanium nitride), W (tungsten), or Al (aluminum). In addition, the metal shield film MS may be formed of a film in which a plurality of conductive films made of different materials are stacked among these materials. For example, the metal shield film MS may be composed of a laminated film composed of a titanium film and a tungsten film that are sequentially formed on the interlayer insulating film IL1. The film thickness of the metal shield film MS is, for example, 10 nm or more and 100 nm or less. Specifically, the metal shield film MS is, for example, 20 nm or 30 nm.

  Next, as shown in FIGS. 7 and 8, a part of the metal shield film MS is removed by using a photolithography technique and an etching method, and the upper surface of the interlayer insulating film IL1 is exposed. This etching step is performed by a wet etching method. By this etching process, an opening OP1 having a circular shape in plan view is formed in each of the connection regions CR1 and CR2. Further, through this etching process, an opening OP2 having a circular shape in plan view is formed in the power feeding region SE. The diameter of the opening OP1 is, for example, several μm or more. The diameter of the opening OP2 is, for example, 5 μm to 10 μm.

  Here, as shown in FIG. 8, the side wall of the opening OP1, that is, the side wall of the terminal portion of the metal shield film MS in the connection regions CR1 and CR2 is located immediately above the semiconductor region PC. That is, the entire opening OP1 is located immediately above the semiconductor region PC. In other words, in the lateral direction, the sidewall of the opening OP1 directly above the predetermined semiconductor region PC is located on the center side of the semiconductor region PC with respect to the end of the semiconductor region PC, and the semiconductor region PC It is not located on the other semiconductor region PC side adjacent to.

  Next, as shown in FIG. 9, an interlayer insulating film IL2 made of, for example, a silicon oxide film is formed on the interlayer insulating film IL1 and the metal shield film MS so as to cover the upper surface and side walls of the metal shield film MS. Thereafter, the upper surface of the interlayer insulating film IL1 is planarized using, for example, a CMP method. The interlayer insulating film IL1 is made of, for example, an LP-PTEOS film, and the film thickness thereof is smaller than the film thickness of the interlayer insulating film IL1. The laminated film composed of the interlayer insulating films IL1 and IL2 constitutes the interlayer insulating film IL.

  Thereby, the insides of the openings OP1 and OP2 are completely filled with the interlayer insulating film IL2.

  Next, as shown in FIGS. 10 and 11, a contact hole CH1 penetrating the interlayer insulating film IL is formed in each of the connection regions CR1 and CR2 by using a photolithography technique and an etching method, and in the power supply region SE. Then, a contact hole CH2 penetrating the interlayer insulating film IL is formed.

  The contact holes CH1 of the connection regions CR1 and CR2 are both formed immediately above the semiconductor region PC, and the upper surface of the semiconductor region PC is exposed from the interlayer insulating film IL at the bottom of each contact hole CH1. The contact hole CH2 in the power feeding region SE is formed immediately above the semiconductor region SR1, and the upper surface of the semiconductor region SR1 is exposed from the interlayer insulating film IL at the bottom of the contact hole CH2. The diameters of the contact holes CH1 and CH2 at the same height as the upper surface of the interlayer insulating film IL2, that is, the diameters of the uppermost portions of the contact holes CH1 and CH2, are the same.

  Here, in plan view, the contact hole CH1 is formed inside the opening OP1, and the contact hole CH1 is formed completely away from the side wall of the opening OP1. The diameter of the contact hole CH1 is several μm or more, but the diameter is smaller than the diameter of the opening OP1. The diameter of the contact hole CH1 is, for example, 400 nm or less smaller than the diameter of the opening OP1. Therefore, the metal shield film MS is not exposed on the side wall of the contact hole CH1. That is, the contact hole CH1 and the metal shield film MS are separated from each other, and the interlayer insulating film IL2 is interposed between the contact hole CH1 and the metal shield film MS. When the contact hole CH1 has a shape extending in a plan view, the opening OP1 is also extended accordingly.

  Further, the contact hole CH2 is formed so as to overlap the entire opening OP2 in plan view. Since the diameter of the contact hole CH2 is larger than the diameter of the opening OP2, the entire opening OP2 is located inside the contact hole CH2 in plan view. Therefore, the upper surface, the side wall, and the lower surface of the end portion of the metal shield film MS adjacent to the opening OP2 are exposed in the contact hole CH2. That is, the end portion of the metal shield film MS protrudes in a bowl shape from the side wall of the interlayer insulating film IL in the contact hole CH2.

  Next, as shown in FIG. 12, a metal film (conductive film) MF is formed on the entire main surface of the semiconductor substrate SB using, for example, a sputtering method. The metal film MF is mainly made of an Al (aluminum) film, for example. The metal film MF is composed of, for example, a laminated film in which a thin barrier conductive film and a main conductive film made of an aluminum film are sequentially stacked. The main conductor film is made of, for example, an aluminum film. The metal film MF completely fills the insides of the contact holes CH1, CH2 and the opening OP2. The metal film MF covers the upper surface of the interlayer insulating film IL.

  Next, as shown in FIG. 13, the metal film MF is processed by using a photolithography technique and a dry etching method, whereby a contact plug (connection portion) CP1 made of the metal film MF in the contact hole CH1; A contact plug (connection portion) CP2 made of the metal film MF in the contact hole CH2 and wirings M1 and M2 made of the metal film MF on the interlayer insulating film IL are formed. Here, a part of the metal film MF is removed to expose the upper surface of the interlayer insulating film IL, thereby forming a plurality of wirings M1 and wirings M2 that are separated from each other. The contact plug CP1 and the wiring M1 are connected to each other, and the contact plug CP2 and the wiring M2 are connected to each other.

  The contact plug CP1 is connected to the semiconductor region PC. The contact plug CP2 is connected to the semiconductor region SR1. Further, in the connection regions CR1 and CR2, the metal shield film MS is covered with the interlayer insulating film IL2, and is not exposed on the side wall of the contact hole CH1, so that the contact plug CP1 and the metal shield film MS are separated from each other. And insulated from each other through the interlayer insulating film IL2. On the other hand, since the contact plug CP2 is in contact with the top surface, the side wall, and the bottom surface of the metal shield film MS exposed in the contact hole CH2, the contact plug CP2 is electrically connected to the metal shield film MS.

  Here, in the lateral direction, the wiring M1 terminates at a position farther from the contact plug CP1 than the side wall of the opening OP1 facing the side wall of the contact plug CP1 immediately below the wiring M1. That is, the entire opening OP1 is located immediately below the wiring M1 in plan view. Therefore, the entire end portion of the metal shield film MS adjacent to the opening OP1 and adjacent to the opening OP1 overlaps the wiring M1 and the semiconductor region PC immediately below the wiring M1 in plan view.

  Further, in plan view, the entire opening OP2 is located directly below the wiring M2. Therefore, the entire end portion of the metal shield film MS adjacent to the opening OP2 and adjacent to the opening OP2 overlaps with the wiring M2 and the semiconductor region SR1 directly below the wiring M2 in plan view. The contact plugs CP1, CP2, the metal shield film MS, and the interlayer insulating film IL constitute a contact layer.

  Through the above steps, the semiconductor device of this embodiment is substantially completed.

<Effects of semiconductor device manufacturing method>
The effects of the method for manufacturing the semiconductor device of the present embodiment will be described below.

  In the manufacturing method of the semiconductor device of the present embodiment, the semiconductor device described with reference to FIGS. 1 to 4 can be manufactured. Therefore, the book described above using the semiconductor device of the comparative example shown in FIGS. The same effects as those of the semiconductor device of the embodiment can be obtained.

  That is, the metal shield film MS is formed in the interlayer insulating film IL constituting the contact layer including the contact plug CP1 connected to the semiconductor substrate SB. For this reason, compared with the case where the metal shield film is formed at the same height as the wiring M1 (see FIG. 17) and the case where the metal shield film is formed above the wiring M1 (see FIG. 18), the metal shield film MS. Is fixed at a predetermined value, the electric field can be controlled, and an inversion layer can be easily prevented from being formed on the main surface of the semiconductor substrate SB in the inter-element region SR.

  In the present embodiment, unlike the comparative example shown in FIG. 17, the metal shield film MS is formed at a height position where the wirings M1 and M2 do not exist. Therefore, the metal shield film MS can be uniformly extended over the entire semiconductor chip except for the vicinity of the region where the contact plugs CP1 and CP2 are formed without restricting the layout of the wiring M1 and the like. Therefore, compared to the comparative example shown in FIGS. 17 and 18, since each wiring and semiconductor element can be formed densely, generation of a leakage current can be prevented without preventing miniaturization of the semiconductor device. Therefore, the performance of the semiconductor device is improved.

  Since the leakage current generated by the operation of the parasitic MOSFET is larger when the surface orientation of the main surface of the semiconductor substrate SB is (100) than when (111), the effect of the semiconductor device of the present embodiment is that surface This is more effectively obtained when the orientation is (100).

  By preventing the occurrence of leak current, that is, increasing the leak margin between elements, for example, the voltage supplied to the element can be increased, and the breakdown voltage of the semiconductor device can be increased. Further, by increasing the leak margin between elements, the semiconductor device can be miniaturized by reducing the interval between the semiconductor regions PC, that is, the interval between the semiconductor elements. Therefore, the performance of the semiconductor device is improved.

  Here, the metal shield film MS is formed using a conductive film different from the film constituting the wiring, and the metal shield film MS can be formed thinner than the wirings M1 and M2. For this reason, for example, since the metal shield film MS is easier to process than the comparative example described with reference to FIG. 18, the manufacturing cost of the semiconductor device can be suppressed. Since it is possible to prevent a step (unevenness) from occurring on the upper surface of the interlayer insulating film IL2 and the like formed on the metal shield film MS, the reliability of the semiconductor device can be improved.

  In the comparative example shown in FIGS. 17 and 18, since the metal shield film is formed at the same height as the wiring, the design is changed for the semiconductor device not provided with the metal shield film, and the metal When a new semiconductor device having a shield film is newly designed, it is necessary to change the layout of wiring significantly, resulting in an increase in manufacturing cost of the semiconductor device. On the other hand, in the present embodiment, the metal shield film MS is formed between the adjacent contact plugs CP1 and CP2 in the interlayer insulating film IL constituting the contact layer. For this reason, it is not necessary to change the layout of the wiring M1 and the like, and when designing a new semiconductor device provided with the metal shield film MS, the conventional wiring layout can be used almost as it is. Can be prevented.

(Embodiment 2)
In the first embodiment, the semiconductor device in the case where the wiring M2 reaches the main surface of the semiconductor substrate SB has been described with reference to FIGS. 1 to 13. However, the bottom of the wiring M2 is a halfway depth of the interlayer insulating film IL1. Alternatively, it may terminate at the upper surface of the metal shield film MS.

  The semiconductor device and the manufacturing method thereof according to the second embodiment will be described below with reference to FIG. FIG. 14 is a cross-sectional view showing the semiconductor device of the present embodiment. FIG. 14 shows a cross section at the same position as in FIG.

  As shown in FIG. 14, in the semiconductor device of the present embodiment, the opening OP2 is not formed in the metal shield film MS, and the contact plug CP2 does not penetrate the metal shield film MS and the interlayer insulating film IL1. Thus, it is different from the first embodiment. Further, the semiconductor region SR1 is not formed on the upper surface of the semiconductor substrate SB in the power feeding region SE.

  The contact plug CP2 penetrates the interlayer insulating film IL2, and the entire bottom surface of the contact plug CP2 is connected to the top surface of the metal shield film MS. Thus, even if the contact plug CP2 does not penetrate the metal shield film MS, a voltage can be supplied to the metal shield film MS via the wiring M2 and the contact plug CP2. By fixing the potential of the metal shield film MS, the occurrence of leak current can be prevented, and the same effect as in the above embodiment can be obtained.

  In the case of manufacturing such a semiconductor device, it is not necessary to provide the opening OP2 in the manufacturing process described with reference to FIGS. Accordingly, in the process described with reference to FIG. 11, the etching for forming the contact hole CH2 stops at the upper surface of the metal shield film MS, so that the connection penetrating the metal shield film MS and the interlayer insulating film IL1 in the power supply region SE. No holes are formed.

<Modification>
Next, a modification of the second embodiment will be described with reference to FIG. FIG. 15 is a cross-sectional view of a semiconductor device which is a modification of the present embodiment. FIG. 15 shows a cross section at the same position as in FIG.

  In the semiconductor device of this modification example, as shown in FIG. 15, the metal shield film MS has the opening OP2, but unlike the first embodiment, the contact hole CH2 and the contact plug CP2 have interlayer insulation. It does not penetrate the membrane IL1. That is, the contact hole CH2 and the contact plug CP2 reach the intermediate depth of the interlayer insulating film IL1 from the upper surface of the interlayer insulating film IL2, but do not reach the main surface of the semiconductor substrate SB. Although FIG. 15 shows the semiconductor region SR1, the semiconductor region SR1 may not be formed.

  That is, the only difference between the present modification and the first embodiment is that the bottom surfaces of the contact hole CH2 and the contact plug CP2 are located at an intermediate depth of the interlayer insulating film IL1. As described above, even if the contact plug CP2 is not connected to the semiconductor substrate SB, the potential of the metal shield film MS can be fixed through the contact plug CP2. Similar effects can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

BT1 PNP type bipolar transistor CP1, CP2 Contact plug CR1, CR2 Connection region IL, IL1-IL4 Interlayer insulating film M1 Wiring MS Metal shield film PC, SR1 Semiconductor region SB Semiconductor substrate SE Feed region SR Inter-element region

Claims (15)

A semiconductor substrate having a first region, a second region, a third region, and a fourth region on a main surface;
A first semiconductor region of a first conductivity type formed on the main surface of the semiconductor substrate of the first region;
A second semiconductor region of the first conductivity type formed on the main surface of the semiconductor substrate of the second region;
An interlayer insulating film formed on the main surface of the semiconductor substrate;
A first wiring, a second wiring, and a third wiring formed on the interlayer insulating film;
A conductive film formed between the main surface of the semiconductor substrate and the upper surface of the interlayer insulating film in the fourth region and the third region between the first region and the second region;
A first connection portion that penetrates the interlayer insulating film and electrically connects the first semiconductor region and the first wiring;
A second connection portion that penetrates the interlayer insulating film and electrically connects the second semiconductor region and the second wiring;
A third connection portion formed from the upper surface of the interlayer insulating film to the upper surface of the conductive film, and electrically connecting the conductive film and the third wiring;
Have
The semiconductor device, wherein the conductive film is insulated from the first connection portion and the second connection portion. The semiconductor device according to claim 1,
The semiconductor device, wherein the conductive film terminates at a position closer to the first connection portion than an end portion of the first semiconductor region in a direction along the main surface of the semiconductor substrate. The semiconductor device according to claim 1,
The semiconductor device, wherein the conductive film terminates at a position closer to the first connection portion than an end portion of the first wiring in a direction along the main surface of the semiconductor substrate. The semiconductor device according to claim 1,
The interlayer insulating film includes a first insulating film and a second insulating film formed on the first insulating film and covering an upper surface of the conductive film, and the interlayer insulating film is interposed between the conductive film and the first connection portion. Is a semiconductor device in which the second insulating film is interposed. The semiconductor device according to claim 1,
The semiconductor device, wherein a plane orientation of the main surface of the semiconductor substrate is (100). The semiconductor device according to claim 1,
A semiconductor device in which a constant voltage is applied to the conductive film. The semiconductor device according to claim 1,
The semiconductor device, wherein the main surface of the semiconductor substrate in the fourth region is covered with the conductive film from the upper surface of the first semiconductor region to the upper surface of the second semiconductor region. The semiconductor device according to claim 1,
The semiconductor device, wherein the film thickness of the conductive film is smaller than the film thickness of the first wiring. The semiconductor device according to claim 1,
The third connection portion passes through the conductive film,
The third connection portion is a semiconductor device in contact with the conductive film in a connection hole formed in the interlayer insulating film in the third region. The semiconductor device according to claim 9.
The semiconductor device, wherein the third connection portion is connected to the main surface of the semiconductor substrate. (A) providing a semiconductor substrate having a first region, a second region, a third region, and a fourth region on a main surface;
(B) forming a first conductive type first semiconductor region on the main surface of the semiconductor substrate in the first region, and forming the first conductive type second on the main surface of the semiconductor substrate in the second region; Forming a semiconductor region;
(C) After the step (b), a step of sequentially forming a first insulating film and a conductive film on the main surface of the semiconductor substrate;
(D) By processing the conductive film, a first opening that exposes the first insulating film in the first region and a second opening that exposes the first insulating film in the second region. Forming step,
(E) forming an interlayer insulating film including the first insulating film and the second insulating film by forming a second insulating film covering the conductive film on the first insulating film;
(F) a first connection hole penetrating the interlayer insulating film in the first opening, a second connection hole penetrating the interlayer insulating film in the second opening, and the second insulation in the third region. Forming a third connection hole penetrating the film and exposing the conductive film;
(G) a first connection portion embedded in the first connection hole and connected to the first semiconductor region; a second connection portion embedded in the second connection hole and connected to the second semiconductor region; A third connection portion embedded in the third connection hole and connected to the conductive film, a first wiring disposed on the interlayer insulating film and connected to the first connection portion, and the interlayer insulating film Forming a second wiring connected to the second connection portion and a third wiring connected to the third connection portion disposed on the interlayer insulating film;
Have
The method for manufacturing a semiconductor device, wherein the conductive film is insulated from the first connection portion and the second connection portion. The method of manufacturing a semiconductor device according to claim 11.
The method of manufacturing a semiconductor device, wherein the conductive film terminates at a position closer to the first connection portion than an end portion of the first semiconductor region in a direction along the main surface of the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 11.
The method of manufacturing a semiconductor device, wherein the conductive film terminates at a position closer to the first connection portion than an end portion of the first wiring in a direction along the main surface of the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 11.
In the step (d), the first opening, the second opening, and a third opening having a smaller diameter in plan view than any of the first opening and the second opening are formed. ,
In the step (f), the first connection hole, the second connection hole, and the third connection hole that overlaps the entire third opening in a plan view are formed. The method of manufacturing a semiconductor device according to claim 11.
The method of manufacturing a semiconductor device, wherein a plane orientation of the main surface of the semiconductor substrate is (100).

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